tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-13-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson ed96df3d 38d40dd3

+61 -61
+61 -61
drivers/clk/qcom/gcc-msm8996.c
··· 290 290 .clkr.hw.init = &(struct clk_init_data){ 291 291 .name = "system_noc_clk_src", 292 292 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, 293 - .num_parents = 7, 293 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), 294 294 .ops = &clk_rcg2_ops, 295 295 }, 296 296 }; ··· 310 310 .clkr.hw.init = &(struct clk_init_data){ 311 311 .name = "config_noc_clk_src", 312 312 .parent_names = gcc_xo_gpll0, 313 - .num_parents = 2, 313 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 314 314 .ops = &clk_rcg2_ops, 315 315 }, 316 316 }; ··· 332 332 .clkr.hw.init = &(struct clk_init_data){ 333 333 .name = "periph_noc_clk_src", 334 334 .parent_names = gcc_xo_gpll0, 335 - .num_parents = 2, 335 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 336 336 .ops = &clk_rcg2_ops, 337 337 }, 338 338 }; ··· 353 353 .clkr.hw.init = &(struct clk_init_data){ 354 354 .name = "usb30_master_clk_src", 355 355 .parent_names = gcc_xo_gpll0_gpll0_early_div, 356 - .num_parents = 3, 356 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 357 357 .ops = &clk_rcg2_ops, 358 358 }, 359 359 }; ··· 371 371 .clkr.hw.init = &(struct clk_init_data){ 372 372 .name = "usb30_mock_utmi_clk_src", 373 373 .parent_names = gcc_xo_gpll0_gpll0_early_div, 374 - .num_parents = 3, 374 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 375 375 .ops = &clk_rcg2_ops, 376 376 }, 377 377 }; ··· 389 389 .clkr.hw.init = &(struct clk_init_data){ 390 390 .name = "usb3_phy_aux_clk_src", 391 391 .parent_names = gcc_xo_sleep_clk, 392 - .num_parents = 2, 392 + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), 393 393 .ops = &clk_rcg2_ops, 394 394 }, 395 395 }; ··· 408 408 .clkr.hw.init = &(struct clk_init_data){ 409 409 .name = "usb20_master_clk_src", 410 410 .parent_names = gcc_xo_gpll0_gpll0_early_div, 411 - .num_parents = 3, 411 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 412 412 .ops = &clk_rcg2_ops, 413 413 }, 414 414 }; ··· 421 421 .clkr.hw.init = &(struct clk_init_data){ 422 422 .name = "usb20_mock_utmi_clk_src", 423 423 .parent_names = gcc_xo_gpll0_gpll0_early_div, 424 - .num_parents = 3, 424 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 425 425 .ops = &clk_rcg2_ops, 426 426 }, 427 427 }; ··· 447 447 .clkr.hw.init = &(struct clk_init_data){ 448 448 .name = "sdcc1_apps_clk_src", 449 449 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, 450 - .num_parents = 4, 450 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), 451 451 .ops = &clk_rcg2_floor_ops, 452 452 }, 453 453 }; ··· 467 467 .clkr.hw.init = &(struct clk_init_data){ 468 468 .name = "sdcc1_ice_core_clk_src", 469 469 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, 470 - .num_parents = 4, 470 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), 471 471 .ops = &clk_rcg2_ops, 472 472 }, 473 473 }; ··· 492 492 .clkr.hw.init = &(struct clk_init_data){ 493 493 .name = "sdcc2_apps_clk_src", 494 494 .parent_names = gcc_xo_gpll0_gpll4, 495 - .num_parents = 3, 495 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 496 496 .ops = &clk_rcg2_floor_ops, 497 497 }, 498 498 }; ··· 506 506 .clkr.hw.init = &(struct clk_init_data){ 507 507 .name = "sdcc3_apps_clk_src", 508 508 .parent_names = gcc_xo_gpll0_gpll4, 509 - .num_parents = 3, 509 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 510 510 .ops = &clk_rcg2_floor_ops, 511 511 }, 512 512 }; ··· 530 530 .clkr.hw.init = &(struct clk_init_data){ 531 531 .name = "sdcc4_apps_clk_src", 532 532 .parent_names = gcc_xo_gpll0, 533 - .num_parents = 2, 533 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 534 534 .ops = &clk_rcg2_floor_ops, 535 535 }, 536 536 }; ··· 555 555 .clkr.hw.init = &(struct clk_init_data){ 556 556 .name = "blsp1_qup1_spi_apps_clk_src", 557 557 .parent_names = gcc_xo_gpll0, 558 - .num_parents = 2, 558 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 559 559 .ops = &clk_rcg2_ops, 560 560 }, 561 561 }; ··· 574 574 .clkr.hw.init = &(struct clk_init_data){ 575 575 .name = "blsp1_qup1_i2c_apps_clk_src", 576 576 .parent_names = gcc_xo_gpll0, 577 - .num_parents = 2, 577 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 578 578 .ops = &clk_rcg2_ops, 579 579 }, 580 580 }; ··· 607 607 .clkr.hw.init = &(struct clk_init_data){ 608 608 .name = "blsp1_uart1_apps_clk_src", 609 609 .parent_names = gcc_xo_gpll0, 610 - .num_parents = 2, 610 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 611 611 .ops = &clk_rcg2_ops, 612 612 }, 613 613 }; ··· 621 621 .clkr.hw.init = &(struct clk_init_data){ 622 622 .name = "blsp1_qup2_spi_apps_clk_src", 623 623 .parent_names = gcc_xo_gpll0, 624 - .num_parents = 2, 624 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 625 625 .ops = &clk_rcg2_ops, 626 626 }, 627 627 }; ··· 634 634 .clkr.hw.init = &(struct clk_init_data){ 635 635 .name = "blsp1_qup2_i2c_apps_clk_src", 636 636 .parent_names = gcc_xo_gpll0, 637 - .num_parents = 2, 637 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 638 638 .ops = &clk_rcg2_ops, 639 639 }, 640 640 }; ··· 648 648 .clkr.hw.init = &(struct clk_init_data){ 649 649 .name = "blsp1_uart2_apps_clk_src", 650 650 .parent_names = gcc_xo_gpll0, 651 - .num_parents = 2, 651 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 652 652 .ops = &clk_rcg2_ops, 653 653 }, 654 654 }; ··· 662 662 .clkr.hw.init = &(struct clk_init_data){ 663 663 .name = "blsp1_qup3_spi_apps_clk_src", 664 664 .parent_names = gcc_xo_gpll0, 665 - .num_parents = 2, 665 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 666 666 .ops = &clk_rcg2_ops, 667 667 }, 668 668 }; ··· 675 675 .clkr.hw.init = &(struct clk_init_data){ 676 676 .name = "blsp1_qup3_i2c_apps_clk_src", 677 677 .parent_names = gcc_xo_gpll0, 678 - .num_parents = 2, 678 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 679 679 .ops = &clk_rcg2_ops, 680 680 }, 681 681 }; ··· 689 689 .clkr.hw.init = &(struct clk_init_data){ 690 690 .name = "blsp1_uart3_apps_clk_src", 691 691 .parent_names = gcc_xo_gpll0, 692 - .num_parents = 2, 692 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 693 693 .ops = &clk_rcg2_ops, 694 694 }, 695 695 }; ··· 703 703 .clkr.hw.init = &(struct clk_init_data){ 704 704 .name = "blsp1_qup4_spi_apps_clk_src", 705 705 .parent_names = gcc_xo_gpll0, 706 - .num_parents = 2, 706 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 707 707 .ops = &clk_rcg2_ops, 708 708 }, 709 709 }; ··· 716 716 .clkr.hw.init = &(struct clk_init_data){ 717 717 .name = "blsp1_qup4_i2c_apps_clk_src", 718 718 .parent_names = gcc_xo_gpll0, 719 - .num_parents = 2, 719 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 720 720 .ops = &clk_rcg2_ops, 721 721 }, 722 722 }; ··· 730 730 .clkr.hw.init = &(struct clk_init_data){ 731 731 .name = "blsp1_uart4_apps_clk_src", 732 732 .parent_names = gcc_xo_gpll0, 733 - .num_parents = 2, 733 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 734 734 .ops = &clk_rcg2_ops, 735 735 }, 736 736 }; ··· 744 744 .clkr.hw.init = &(struct clk_init_data){ 745 745 .name = "blsp1_qup5_spi_apps_clk_src", 746 746 .parent_names = gcc_xo_gpll0, 747 - .num_parents = 2, 747 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 748 748 .ops = &clk_rcg2_ops, 749 749 }, 750 750 }; ··· 757 757 .clkr.hw.init = &(struct clk_init_data){ 758 758 .name = "blsp1_qup5_i2c_apps_clk_src", 759 759 .parent_names = gcc_xo_gpll0, 760 - .num_parents = 2, 760 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 761 761 .ops = &clk_rcg2_ops, 762 762 }, 763 763 }; ··· 771 771 .clkr.hw.init = &(struct clk_init_data){ 772 772 .name = "blsp1_uart5_apps_clk_src", 773 773 .parent_names = gcc_xo_gpll0, 774 - .num_parents = 2, 774 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 775 775 .ops = &clk_rcg2_ops, 776 776 }, 777 777 }; ··· 785 785 .clkr.hw.init = &(struct clk_init_data){ 786 786 .name = "blsp1_qup6_spi_apps_clk_src", 787 787 .parent_names = gcc_xo_gpll0, 788 - .num_parents = 2, 788 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 789 789 .ops = &clk_rcg2_ops, 790 790 }, 791 791 }; ··· 798 798 .clkr.hw.init = &(struct clk_init_data){ 799 799 .name = "blsp1_qup6_i2c_apps_clk_src", 800 800 .parent_names = gcc_xo_gpll0, 801 - .num_parents = 2, 801 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 802 802 .ops = &clk_rcg2_ops, 803 803 }, 804 804 }; ··· 812 812 .clkr.hw.init = &(struct clk_init_data){ 813 813 .name = "blsp1_uart6_apps_clk_src", 814 814 .parent_names = gcc_xo_gpll0, 815 - .num_parents = 2, 815 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 816 816 .ops = &clk_rcg2_ops, 817 817 }, 818 818 }; ··· 826 826 .clkr.hw.init = &(struct clk_init_data){ 827 827 .name = "blsp2_qup1_spi_apps_clk_src", 828 828 .parent_names = gcc_xo_gpll0, 829 - .num_parents = 2, 829 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 830 830 .ops = &clk_rcg2_ops, 831 831 }, 832 832 }; ··· 839 839 .clkr.hw.init = &(struct clk_init_data){ 840 840 .name = "blsp2_qup1_i2c_apps_clk_src", 841 841 .parent_names = gcc_xo_gpll0, 842 - .num_parents = 2, 842 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 843 843 .ops = &clk_rcg2_ops, 844 844 }, 845 845 }; ··· 853 853 .clkr.hw.init = &(struct clk_init_data){ 854 854 .name = "blsp2_uart1_apps_clk_src", 855 855 .parent_names = gcc_xo_gpll0, 856 - .num_parents = 2, 856 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 857 857 .ops = &clk_rcg2_ops, 858 858 }, 859 859 }; ··· 867 867 .clkr.hw.init = &(struct clk_init_data){ 868 868 .name = "blsp2_qup2_spi_apps_clk_src", 869 869 .parent_names = gcc_xo_gpll0, 870 - .num_parents = 2, 870 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 871 871 .ops = &clk_rcg2_ops, 872 872 }, 873 873 }; ··· 880 880 .clkr.hw.init = &(struct clk_init_data){ 881 881 .name = "blsp2_qup2_i2c_apps_clk_src", 882 882 .parent_names = gcc_xo_gpll0, 883 - .num_parents = 2, 883 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 884 884 .ops = &clk_rcg2_ops, 885 885 }, 886 886 }; ··· 894 894 .clkr.hw.init = &(struct clk_init_data){ 895 895 .name = "blsp2_uart2_apps_clk_src", 896 896 .parent_names = gcc_xo_gpll0, 897 - .num_parents = 2, 897 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 898 898 .ops = &clk_rcg2_ops, 899 899 }, 900 900 }; ··· 908 908 .clkr.hw.init = &(struct clk_init_data){ 909 909 .name = "blsp2_qup3_spi_apps_clk_src", 910 910 .parent_names = gcc_xo_gpll0, 911 - .num_parents = 2, 911 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 912 912 .ops = &clk_rcg2_ops, 913 913 }, 914 914 }; ··· 921 921 .clkr.hw.init = &(struct clk_init_data){ 922 922 .name = "blsp2_qup3_i2c_apps_clk_src", 923 923 .parent_names = gcc_xo_gpll0, 924 - .num_parents = 2, 924 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 925 925 .ops = &clk_rcg2_ops, 926 926 }, 927 927 }; ··· 935 935 .clkr.hw.init = &(struct clk_init_data){ 936 936 .name = "blsp2_uart3_apps_clk_src", 937 937 .parent_names = gcc_xo_gpll0, 938 - .num_parents = 2, 938 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 939 939 .ops = &clk_rcg2_ops, 940 940 }, 941 941 }; ··· 949 949 .clkr.hw.init = &(struct clk_init_data){ 950 950 .name = "blsp2_qup4_spi_apps_clk_src", 951 951 .parent_names = gcc_xo_gpll0, 952 - .num_parents = 2, 952 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 953 953 .ops = &clk_rcg2_ops, 954 954 }, 955 955 }; ··· 962 962 .clkr.hw.init = &(struct clk_init_data){ 963 963 .name = "blsp2_qup4_i2c_apps_clk_src", 964 964 .parent_names = gcc_xo_gpll0, 965 - .num_parents = 2, 965 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 966 966 .ops = &clk_rcg2_ops, 967 967 }, 968 968 }; ··· 976 976 .clkr.hw.init = &(struct clk_init_data){ 977 977 .name = "blsp2_uart4_apps_clk_src", 978 978 .parent_names = gcc_xo_gpll0, 979 - .num_parents = 2, 979 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 980 980 .ops = &clk_rcg2_ops, 981 981 }, 982 982 }; ··· 990 990 .clkr.hw.init = &(struct clk_init_data){ 991 991 .name = "blsp2_qup5_spi_apps_clk_src", 992 992 .parent_names = gcc_xo_gpll0, 993 - .num_parents = 2, 993 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 994 994 .ops = &clk_rcg2_ops, 995 995 }, 996 996 }; ··· 1003 1003 .clkr.hw.init = &(struct clk_init_data){ 1004 1004 .name = "blsp2_qup5_i2c_apps_clk_src", 1005 1005 .parent_names = gcc_xo_gpll0, 1006 - .num_parents = 2, 1006 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1007 1007 .ops = &clk_rcg2_ops, 1008 1008 }, 1009 1009 }; ··· 1017 1017 .clkr.hw.init = &(struct clk_init_data){ 1018 1018 .name = "blsp2_uart5_apps_clk_src", 1019 1019 .parent_names = gcc_xo_gpll0, 1020 - .num_parents = 2, 1020 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1021 1021 .ops = &clk_rcg2_ops, 1022 1022 }, 1023 1023 }; ··· 1031 1031 .clkr.hw.init = &(struct clk_init_data){ 1032 1032 .name = "blsp2_qup6_spi_apps_clk_src", 1033 1033 .parent_names = gcc_xo_gpll0, 1034 - .num_parents = 2, 1034 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1035 1035 .ops = &clk_rcg2_ops, 1036 1036 }, 1037 1037 }; ··· 1044 1044 .clkr.hw.init = &(struct clk_init_data){ 1045 1045 .name = "blsp2_qup6_i2c_apps_clk_src", 1046 1046 .parent_names = gcc_xo_gpll0, 1047 - .num_parents = 2, 1047 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1048 1048 .ops = &clk_rcg2_ops, 1049 1049 }, 1050 1050 }; ··· 1058 1058 .clkr.hw.init = &(struct clk_init_data){ 1059 1059 .name = "blsp2_uart6_apps_clk_src", 1060 1060 .parent_names = gcc_xo_gpll0, 1061 - .num_parents = 2, 1061 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1062 1062 .ops = &clk_rcg2_ops, 1063 1063 }, 1064 1064 }; ··· 1076 1076 .clkr.hw.init = &(struct clk_init_data){ 1077 1077 .name = "pdm2_clk_src", 1078 1078 .parent_names = gcc_xo_gpll0, 1079 - .num_parents = 2, 1079 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1080 1080 .ops = &clk_rcg2_ops, 1081 1081 }, 1082 1082 }; ··· 1095 1095 .clkr.hw.init = &(struct clk_init_data){ 1096 1096 .name = "tsif_ref_clk_src", 1097 1097 .parent_names = gcc_xo_gpll0_aud_ref_clk, 1098 - .num_parents = 3, 1098 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), 1099 1099 .ops = &clk_rcg2_ops, 1100 1100 }, 1101 1101 }; ··· 1107 1107 .clkr.hw.init = &(struct clk_init_data){ 1108 1108 .name = "gcc_sleep_clk_src", 1109 1109 .parent_names = gcc_sleep_clk, 1110 - .num_parents = 1, 1110 + .num_parents = ARRAY_SIZE(gcc_sleep_clk), 1111 1111 .ops = &clk_rcg2_ops, 1112 1112 }, 1113 1113 }; ··· 1120 1120 .clkr.hw.init = &(struct clk_init_data){ 1121 1121 .name = "hmss_rbcpr_clk_src", 1122 1122 .parent_names = gcc_xo_gpll0, 1123 - .num_parents = 2, 1123 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1124 1124 .ops = &clk_rcg2_ops, 1125 1125 }, 1126 1126 }; ··· 1132 1132 .clkr.hw.init = &(struct clk_init_data){ 1133 1133 .name = "hmss_gpll0_clk_src", 1134 1134 .parent_names = gcc_xo_gpll0, 1135 - .num_parents = 2, 1135 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1136 1136 .ops = &clk_rcg2_ops, 1137 1137 }, 1138 1138 }; ··· 1153 1153 .clkr.hw.init = &(struct clk_init_data){ 1154 1154 .name = "gp1_clk_src", 1155 1155 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1156 - .num_parents = 4, 1156 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), 1157 1157 .ops = &clk_rcg2_ops, 1158 1158 }, 1159 1159 }; ··· 1167 1167 .clkr.hw.init = &(struct clk_init_data){ 1168 1168 .name = "gp2_clk_src", 1169 1169 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1170 - .num_parents = 4, 1170 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), 1171 1171 .ops = &clk_rcg2_ops, 1172 1172 }, 1173 1173 }; ··· 1181 1181 .clkr.hw.init = &(struct clk_init_data){ 1182 1182 .name = "gp3_clk_src", 1183 1183 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1184 - .num_parents = 4, 1184 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), 1185 1185 .ops = &clk_rcg2_ops, 1186 1186 }, 1187 1187 }; ··· 1200 1200 .clkr.hw.init = &(struct clk_init_data){ 1201 1201 .name = "pcie_aux_clk_src", 1202 1202 .parent_names = gcc_xo_sleep_clk, 1203 - .num_parents = 2, 1203 + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), 1204 1204 .ops = &clk_rcg2_ops, 1205 1205 }, 1206 1206 }; ··· 1221 1221 .clkr.hw.init = &(struct clk_init_data){ 1222 1222 .name = "ufs_axi_clk_src", 1223 1223 .parent_names = gcc_xo_gpll0, 1224 - .num_parents = 2, 1224 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1225 1225 .ops = &clk_rcg2_ops, 1226 1226 }, 1227 1227 }; ··· 1241 1241 .clkr.hw.init = &(struct clk_init_data){ 1242 1242 .name = "ufs_ice_core_clk_src", 1243 1243 .parent_names = gcc_xo_gpll0, 1244 - .num_parents = 2, 1244 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1245 1245 .ops = &clk_rcg2_ops, 1246 1246 }, 1247 1247 }; ··· 1262 1262 .clkr.hw.init = &(struct clk_init_data){ 1263 1263 .name = "qspi_ser_clk_src", 1264 1264 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, 1265 - .num_parents = 6, 1265 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), 1266 1266 .ops = &clk_rcg2_ops, 1267 1267 }, 1268 1268 };