Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rtc-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Pull RTC updates from Alexandre Belloni:
"A quiet cycle this time.
- ds1307: properly handle oscillator failure flags
- imx-sc: alarm support
- pcf2123: alarm support, correct offset handling
- sun6i: add R40 support
- simplify getting the adapter of an i2c client"
* tag 'rtc-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (37 commits)
rtc: wm831x: Add IRQF_ONESHOT flag
rtc: stm32: remove one condition check in stm32_rtc_set_alarm()
rtc: pcf2123: Fix build error
rtc: interface: Change type of 'count' from int to u64
rtc: pcf8563: Clear event flags and disable interrupts before requesting irq
rtc: pcf8563: Fix interrupt trigger method
rtc: pcf2123: fix negative offset rounding
rtc: pcf2123: add alarm support
rtc: pcf2123: use %ptR
rtc: pcf2123: port to regmap
rtc: pcf2123: remove sysfs register view
rtc: rx8025: simplify getting the adapter of a client
rtc: rx8010: simplify getting the adapter of a client
rtc: rv8803: simplify getting the adapter of a client
rtc: m41t80: simplify getting the adapter of a client
rtc: fm3130: simplify getting the adapter of a client
rtc: tegra: Drop MODULE_ALIAS
rtc: sun6i: Add R40 compatible
dt-bindings: rtc: sun6i: Add the R40 RTC compatible
dt-bindings: rtc: Convert Allwinner A31 RTC to a schema
...
+822
-569
+43
Documentation/devicetree/bindings/rtc/allwinner,sun4i-a10-rtc.yaml
+43
Documentation/devicetree/bindings/rtc/allwinner,sun4i-a10-rtc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/allwinner,sun4i-a10-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A10 RTC Device Tree Bindings
8
+
9
+
allOf:
10
+
- $ref: "rtc.yaml#"
11
+
12
+
maintainers:
13
+
- Chen-Yu Tsai <wens@csie.org>
14
+
- Maxime Ripard <maxime.ripard@bootlin.com>
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- allwinner,sun4i-a10-rtc
20
+
- allwinner,sun7i-a20-rtc
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
required:
29
+
- compatible
30
+
- reg
31
+
- interrupts
32
+
33
+
additionalProperties: false
34
+
35
+
examples:
36
+
- |
37
+
rtc: rtc@1c20d00 {
38
+
compatible = "allwinner,sun4i-a10-rtc";
39
+
reg = <0x01c20d00 0x20>;
40
+
interrupts = <24>;
41
+
};
42
+
43
+
...
+134
Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+134
Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A31 RTC Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <maxime.ripard@bootlin.com>
12
+
13
+
properties:
14
+
"#clock-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
oneOf:
19
+
- const: allwinner,sun6i-a31-rtc
20
+
- const: allwinner,sun8i-a23-rtc
21
+
- const: allwinner,sun8i-h3-rtc
22
+
- const: allwinner,sun8i-r40-rtc
23
+
- const: allwinner,sun8i-v3-rtc
24
+
- const: allwinner,sun50i-h5-rtc
25
+
- items:
26
+
- const: allwinner,sun50i-a64-rtc
27
+
- const: allwinner,sun8i-h3-rtc
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
minItems: 1
34
+
maxItems: 2
35
+
items:
36
+
- description: RTC Alarm 0
37
+
- description: RTC Alarm 1
38
+
39
+
clocks:
40
+
maxItems: 1
41
+
42
+
clock-output-names:
43
+
minItems: 1
44
+
maxItems: 3
45
+
description:
46
+
The RTC provides up to three clocks
47
+
- the Low Frequency Oscillator or LOSC, at index 0,
48
+
- the Low Frequency Oscillator External output (X32KFOUT in
49
+
the datasheet), at index 1,
50
+
- the Internal Oscillator, at index 2.
51
+
52
+
allOf:
53
+
- $ref: "rtc.yaml#"
54
+
- if:
55
+
properties:
56
+
compatible:
57
+
contains:
58
+
const: allwinner,sun6i-a31-rtc
59
+
60
+
then:
61
+
properties:
62
+
clock-output-names:
63
+
minItems: 1
64
+
maxItems: 1
65
+
66
+
- if:
67
+
properties:
68
+
compatible:
69
+
contains:
70
+
enum:
71
+
- allwinner,sun8i-a23-rtc
72
+
- allwinner,sun8i-r40-rtc
73
+
- allwinner,sun8i-v3-rtc
74
+
75
+
then:
76
+
properties:
77
+
clock-output-names:
78
+
minItems: 2
79
+
maxItems: 2
80
+
81
+
- if:
82
+
properties:
83
+
compatible:
84
+
contains:
85
+
enum:
86
+
- allwinner,sun8i-h3-rtc
87
+
- allwinner,sun50i-h5-rtc
88
+
89
+
then:
90
+
properties:
91
+
clock-output-names:
92
+
minItems: 3
93
+
maxItems: 3
94
+
95
+
- if:
96
+
properties:
97
+
compatible:
98
+
contains:
99
+
const: allwinner,sun8i-r40-rtc
100
+
101
+
then:
102
+
properties:
103
+
interrupts:
104
+
minItems: 1
105
+
maxItems: 1
106
+
107
+
else:
108
+
properties:
109
+
interrupts:
110
+
minItems: 2
111
+
maxItems: 2
112
+
113
+
required:
114
+
- "#clock-cells"
115
+
- compatible
116
+
- reg
117
+
- interrupts
118
+
- clocks
119
+
- clock-output-names
120
+
121
+
additionalProperties: false
122
+
123
+
examples:
124
+
- |
125
+
rtc: rtc@1f00000 {
126
+
compatible = "allwinner,sun6i-a31-rtc";
127
+
reg = <0x01f00000 0x400>;
128
+
interrupts = <0 40 4>, <0 41 4>;
129
+
clock-output-names = "osc32k";
130
+
clocks = <&ext_osc32k>;
131
+
#clock-cells = <1>;
132
+
};
133
+
134
+
...
+1
-72
Documentation/devicetree/bindings/rtc/rtc.txt
+1
-72
Documentation/devicetree/bindings/rtc/rtc.txt
···
1
-
Generic device tree bindings for Real Time Clock devices
2
-
========================================================
3
-
4
-
This document describes generic bindings which can be used to describe Real Time
5
-
Clock devices in a device tree.
6
-
7
-
Required properties
8
-
-------------------
9
-
10
-
- compatible : name of RTC device following generic names recommended practice.
11
-
12
-
For other required properties e.g. to describe register sets,
13
-
clocks, etc. check the binding documentation of the specific driver.
14
-
15
-
Optional properties
16
-
-------------------
17
-
18
-
- start-year : if provided, the default hardware range supported by the RTC is
19
-
shifted so the first usable year is the specified one.
20
-
21
-
The following properties may not be supported by all drivers. However, if a
22
-
driver wants to support one of the below features, it should adapt the bindings
23
-
below.
24
-
- trickle-resistor-ohms : Selected resistor for trickle charger. Should be given
25
-
if trickle charger should be enabled
26
-
- trickle-diode-disable : Do not use internal trickle charger diode Should be
27
-
given if internal trickle charger diode should be
28
-
disabled
29
-
- wakeup-source : Enables wake up of host system on alarm
30
-
- quartz-load-femtofarads : The capacitive load of the quartz(x-tal),
31
-
expressed in femto Farad (fF).
32
-
The default value shall be listed (if optional),
33
-
and likewise all valid values.
34
-
35
-
Trivial RTCs
36
-
------------
37
-
38
-
This is a list of trivial RTC devices that have simple device tree
39
-
bindings, consisting only of a compatible field, an address and
40
-
possibly an interrupt line.
41
-
42
-
43
-
Compatible Vendor / Chip
44
-
========== =============
45
-
abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
46
-
abracon,abeoz9 AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
47
-
dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
48
-
dallas,ds1672 Dallas DS1672 Real-time Clock
49
-
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
50
-
epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
51
-
epson,rx8571 I2C-BUS INTERFACE REAL TIME CLOCK MODULE with Battery Backed RAM
52
-
epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
53
-
emmicro,em3027 EM Microelectronic EM3027 Real-time Clock
54
-
isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM
55
-
isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM
56
-
isil,isl12022 Intersil ISL12022 Real-time Clock
57
-
microcrystal,rv3028 Real Time Clock Module with I2C-Bus
58
-
microcrystal,rv3029 Real Time Clock Module with I2C-Bus
59
-
microcrystal,rv8523 Real Time Clock
60
-
nxp,pcf2127 Real-time clock
61
-
nxp,pcf2129 Real-time clock
62
-
nxp,pcf8563 Real-time clock/calendar
63
-
pericom,pt7c4338 Real-time Clock Module
64
-
ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
65
-
ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
66
-
ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
67
-
ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
68
-
ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
69
-
ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
70
-
sii,s35390a 2-wire CMOS real-time clock
71
-
whwave,sd3078 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
72
-
xircom,x1205 Xircom X1205 I2C RTC
1
+
This file has been moved to rtc.yaml.
+50
Documentation/devicetree/bindings/rtc/rtc.yaml
+50
Documentation/devicetree/bindings/rtc/rtc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RTC Generic Binding
8
+
9
+
maintainers:
10
+
- Alexandre Belloni <alexandre.belloni@bootlin.com>
11
+
12
+
description: |
13
+
This document describes generic bindings which can be used to
14
+
describe Real Time Clock devices in a device tree.
15
+
16
+
properties:
17
+
$nodename:
18
+
pattern: "^rtc(@.*|-[0-9a-f])*$"
19
+
20
+
quartz-load-femtofarads:
21
+
$ref: /schemas/types.yaml#/definitions/uint32
22
+
description:
23
+
The capacitive load of the quartz(x-tal), expressed in femto
24
+
Farad (fF). The default value shall be listed (if optional),
25
+
and likewise all valid values.
26
+
27
+
start-year:
28
+
$ref: /schemas/types.yaml#/definitions/uint32
29
+
description:
30
+
If provided, the default hardware range supported by the RTC is
31
+
shifted so the first usable year is the specified one.
32
+
33
+
trickle-diode-disable:
34
+
$ref: /schemas/types.yaml#/definitions/flag
35
+
description:
36
+
Do not use internal trickle charger diode. Should be given if
37
+
internal trickle charger diode should be disabled.
38
+
39
+
trickle-resistor-ohms:
40
+
$ref: /schemas/types.yaml#/definitions/uint32
41
+
description:
42
+
Selected resistor for trickle charger. Should be given
43
+
if trickle charger should be enabled.
44
+
45
+
wakeup-source:
46
+
$ref: /schemas/types.yaml#/definitions/flag
47
+
description:
48
+
Enables wake up of host system on alarm.
49
+
50
+
...
-46
Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
-46
Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
···
1
-
* sun6i Real Time Clock
2
-
3
-
RTC controller for the Allwinner A31
4
-
5
-
Required properties:
6
-
- compatible : Should be one of the following combinations:
7
-
- "allwinner,sun6i-a31-rtc"
8
-
- "allwinner,sun8i-a23-rtc"
9
-
- "allwinner,sun8i-h3-rtc"
10
-
- "allwinner,sun8i-r40-rtc", "allwinner,sun8i-h3-rtc"
11
-
- "allwinner,sun8i-v3-rtc"
12
-
- "allwinner,sun50i-a64-rtc", "allwinner,sun8i-h3-rtc"
13
-
- "allwinner,sun50i-h5-rtc"
14
-
15
-
Where there are two or more compatible strings, this
16
-
denotes the hardware covered by the most specific one
17
-
is backward-compatible with the latter ones, and the
18
-
implementation for the latter ones can be used, albeit
19
-
with reduced functionality.
20
-
21
-
- reg : physical base address of the controller and length of
22
-
memory mapped region.
23
-
- interrupts : IRQ lines for the RTC alarm 0 and alarm 1, in that order.
24
-
25
-
Required properties for new device trees
26
-
- clocks : phandle to the 32kHz external oscillator
27
-
- clock-output-names : names of up to three clock outputs. See below.
28
-
- #clock-cells : must be equal to 1.
29
-
30
-
The RTC provides the following clocks at the given indices:
31
-
- 0: LOSC
32
-
- 1: LOSC external output, known as X32KFOUT in the datasheet.
33
-
This clock is not available on the A31 and is deprecated for old
34
-
device trees still using the "allwinner,sun6i-a31-rtc" compatible.
35
-
- 2: InternalOSC, or internal RC oscillator (A64/H3/H5 only)
36
-
37
-
Example:
38
-
39
-
rtc: rtc@1f00000 {
40
-
compatible = "allwinner,sun6i-a31-rtc";
41
-
reg = <0x01f00000 0x400>;
42
-
interrupts = <0 40 4>, <0 41 4>;
43
-
clock-output-names = "osc32k";
44
-
clocks = <&ext_osc32k>;
45
-
#clock-cells = <1>;
46
-
};
-17
Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
-17
Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
···
1
-
* sun4i/sun7i Real Time Clock
2
-
3
-
RTC controller for the Allwinner A10/A20
4
-
5
-
Required properties:
6
-
- compatible : Should be "allwinner,sun4i-a10-rtc" or "allwinner,sun7i-a20-rtc"
7
-
- reg: physical base address of the controller and length of memory mapped
8
-
region.
9
-
- interrupts: IRQ line for the RTC.
10
-
11
-
Example:
12
-
13
-
rtc: rtc@1c20d00 {
14
-
compatible = "allwinner,sun4i-a10-rtc";
15
-
reg = <0x01c20d00 0x20>;
16
-
interrupts = <24>;
17
-
};
+92
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
+92
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Trivial RTCs
8
+
9
+
maintainers:
10
+
- Alexandre Belloni <alexandre.belloni@bootlin.com>
11
+
12
+
description: |
13
+
This is a list of trivial RTC devices that have simple device tree
14
+
bindings, consisting only of a compatible field, an address and
15
+
possibly an interrupt line.
16
+
17
+
allOf:
18
+
- $ref: "rtc.yaml#"
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
# AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24
+
- abracon,abb5zes3
25
+
# AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
26
+
- abracon,abeoz9
27
+
# I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
28
+
- dallas,ds1374
29
+
# Dallas DS1672 Real-time Clock
30
+
- dallas,ds1672
31
+
# Extremely Accurate I²C RTC with Integrated Crystal and SRAM
32
+
- dallas,ds3232
33
+
# I2C-BUS INTERFACE REAL TIME CLOCK MODULE
34
+
- epson,rx8010
35
+
# I2C-BUS INTERFACE REAL TIME CLOCK MODULE with Battery Backed RAM
36
+
- epson,rx8571
37
+
# I2C-BUS INTERFACE REAL TIME CLOCK MODULE
38
+
- epson,rx8581
39
+
# Intersil ISL1208 Low Power RTC with Battery Backed SRAM
40
+
- isil,isl1208
41
+
# Intersil ISL1218 Low Power RTC with Battery Backed SRAM
42
+
- isil,isl1218
43
+
# Intersil ISL12022 Real-time Clock
44
+
- isil,isl12022
45
+
# Real Time Clock Module with I2C-Bus
46
+
- microcrystal,rv3028
47
+
# Real Time Clock Module with I2C-Bus
48
+
- microcrystal,rv3029
49
+
# Real Time Clock
50
+
- microcrystal,rv8523
51
+
# Real-time clock
52
+
- nxp,pcf2127
53
+
# Real-time clock
54
+
- nxp,pcf2129
55
+
# Real-time clock/calendar
56
+
- nxp,pcf8563
57
+
# Real-time Clock Module
58
+
- pericom,pt7c4338
59
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
60
+
- ricoh,r2025sd
61
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
62
+
- ricoh,r2221tl
63
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
64
+
- ricoh,rs5c372a
65
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
66
+
- ricoh,rs5c372b
67
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
68
+
- ricoh,rv5c386
69
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
70
+
- ricoh,rv5c387a
71
+
# 2-wire CMOS real-time clock
72
+
- sii,s35390a
73
+
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
74
+
- whwave,sd3078
75
+
# Xircom X1205 I2C RTC
76
+
- xircom,x1205
77
+
78
+
reg:
79
+
maxItems: 1
80
+
81
+
interrupts:
82
+
maxItems: 1
83
+
84
+
start-year: true
85
+
86
+
required:
87
+
- compatible
88
+
- reg
89
+
90
+
additionalProperties: false
91
+
92
+
...
+2
-1
drivers/rtc/Kconfig
+2
-1
drivers/rtc/Kconfig
···
562
562
563
563
config RTC_DRV_TPS65910
564
564
tristate "TI TPS65910 RTC driver"
565
-
depends on RTC_CLASS && MFD_TPS65910
565
+
depends on MFD_TPS65910
566
566
help
567
567
If you say yes here you get support for the RTC on the
568
568
TPS65910 chips.
···
820
820
821
821
config RTC_DRV_PCF2123
822
822
tristate "NXP PCF2123"
823
+
select REGMAP_SPI
823
824
help
824
825
If you say yes here you get support for the NXP PCF2123
825
826
RTC chip.
+1
-1
drivers/rtc/interface.c
+1
-1
drivers/rtc/interface.c
+58
-71
drivers/rtc/rtc-ds1307.c
+58
-71
drivers/rtc/rtc-ds1307.c
···
222
222
return -EINVAL;
223
223
}
224
224
225
+
tmp = regs[DS1307_REG_SECS];
226
+
switch (ds1307->type) {
227
+
case ds_1307:
228
+
case m41t0:
229
+
case m41t00:
230
+
case m41t11:
231
+
if (tmp & DS1307_BIT_CH)
232
+
return -EINVAL;
233
+
break;
234
+
case ds_1308:
235
+
case ds_1338:
236
+
if (tmp & DS1307_BIT_CH)
237
+
return -EINVAL;
238
+
239
+
ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
240
+
if (ret)
241
+
return ret;
242
+
if (tmp & DS1338_BIT_OSF)
243
+
return -EINVAL;
244
+
break;
245
+
case ds_1340:
246
+
if (tmp & DS1340_BIT_nEOSC)
247
+
return -EINVAL;
248
+
249
+
ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
250
+
if (ret)
251
+
return ret;
252
+
if (tmp & DS1340_BIT_OSF)
253
+
return -EINVAL;
254
+
break;
255
+
case mcp794xx:
256
+
if (!(tmp & MCP794XX_BIT_ST))
257
+
return -EINVAL;
258
+
259
+
break;
260
+
default:
261
+
break;
262
+
}
263
+
225
264
t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
226
265
t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
227
266
tmp = regs[DS1307_REG_HOUR] & 0x3f;
···
325
286
if (t->tm_year > 199 && chip->century_bit)
326
287
regs[chip->century_reg] |= chip->century_bit;
327
288
328
-
if (ds1307->type == mcp794xx) {
289
+
switch (ds1307->type) {
290
+
case ds_1308:
291
+
case ds_1338:
292
+
regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
293
+
DS1338_BIT_OSF, 0);
294
+
break;
295
+
case ds_1340:
296
+
regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
297
+
DS1340_BIT_OSF, 0);
298
+
break;
299
+
case mcp794xx:
329
300
/*
330
301
* these bits were cleared when preparing the date/time
331
302
* values and need to be set again before writing the
···
343
294
*/
344
295
regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
345
296
regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
297
+
break;
298
+
default:
299
+
break;
346
300
}
347
301
348
302
dev_dbg(dev, "%s: %7ph\n", "write", regs);
···
1754
1702
break;
1755
1703
}
1756
1704
1757
-
read_rtc:
1758
1705
/* read RTC registers */
1759
1706
err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1760
1707
sizeof(regs));
···
1762
1711
goto exit;
1763
1712
}
1764
1713
1765
-
/*
1766
-
* minimal sanity checking; some chips (like DS1340) don't
1767
-
* specify the extra bits as must-be-zero, but there are
1768
-
* still a few values that are clearly out-of-range.
1769
-
*/
1770
-
tmp = regs[DS1307_REG_SECS];
1771
-
switch (ds1307->type) {
1772
-
case ds_1307:
1773
-
case m41t0:
1774
-
case m41t00:
1775
-
case m41t11:
1776
-
/* clock halted? turn it on, so clock can tick. */
1777
-
if (tmp & DS1307_BIT_CH) {
1778
-
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1779
-
dev_warn(ds1307->dev, "SET TIME!\n");
1780
-
goto read_rtc;
1781
-
}
1782
-
break;
1783
-
case ds_1308:
1784
-
case ds_1338:
1785
-
/* clock halted? turn it on, so clock can tick. */
1786
-
if (tmp & DS1307_BIT_CH)
1787
-
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1788
-
1789
-
/* oscillator fault? clear flag, and warn */
1790
-
if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1791
-
regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1792
-
regs[DS1307_REG_CONTROL] &
1793
-
~DS1338_BIT_OSF);
1794
-
dev_warn(ds1307->dev, "SET TIME!\n");
1795
-
goto read_rtc;
1796
-
}
1797
-
break;
1798
-
case ds_1340:
1799
-
/* clock halted? turn it on, so clock can tick. */
1800
-
if (tmp & DS1340_BIT_nEOSC)
1801
-
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1802
-
1803
-
err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1804
-
if (err) {
1805
-
dev_dbg(ds1307->dev, "read error %d\n", err);
1806
-
goto exit;
1807
-
}
1808
-
1809
-
/* oscillator fault? clear flag, and warn */
1810
-
if (tmp & DS1340_BIT_OSF) {
1811
-
regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1812
-
dev_warn(ds1307->dev, "SET TIME!\n");
1813
-
}
1814
-
break;
1815
-
case mcp794xx:
1816
-
/* make sure that the backup battery is enabled */
1817
-
if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1818
-
regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1819
-
regs[DS1307_REG_WDAY] |
1820
-
MCP794XX_BIT_VBATEN);
1821
-
}
1822
-
1823
-
/* clock halted? turn it on, so clock can tick. */
1824
-
if (!(tmp & MCP794XX_BIT_ST)) {
1825
-
regmap_write(ds1307->regmap, DS1307_REG_SECS,
1826
-
MCP794XX_BIT_ST);
1827
-
dev_warn(ds1307->dev, "SET TIME!\n");
1828
-
goto read_rtc;
1829
-
}
1830
-
1831
-
break;
1832
-
default:
1833
-
break;
1714
+
if (ds1307->type == mcp794xx &&
1715
+
!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1716
+
regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1717
+
regs[DS1307_REG_WDAY] |
1718
+
MCP794XX_BIT_VBATEN);
1834
1719
}
1835
1720
1836
1721
tmp = regs[DS1307_REG_HOUR];
+3
-2
drivers/rtc/rtc-ds2404.c
+3
-2
drivers/rtc/rtc-ds2404.c
···
182
182
static int ds2404_read_time(struct device *dev, struct rtc_time *dt)
183
183
{
184
184
unsigned long time = 0;
185
+
__le32 hw_time = 0;
185
186
186
-
ds2404_read_memory(dev, 0x203, 4, (u8 *)&time);
187
-
time = le32_to_cpu(time);
187
+
ds2404_read_memory(dev, 0x203, 4, (u8 *)&hw_time);
188
+
time = le32_to_cpu(hw_time);
188
189
189
190
rtc_time64_to_tm(time, dt);
190
191
return 0;
+3
-5
drivers/rtc/rtc-fm3130.c
+3
-5
drivers/rtc/rtc-fm3130.c
···
104
104
fm3130_rtc_mode(dev, FM3130_MODE_READ);
105
105
106
106
/* read the RTC date and time registers all at once */
107
-
tmp = i2c_transfer(to_i2c_adapter(fm3130->client->dev.parent),
108
-
fm3130->msg, 2);
107
+
tmp = i2c_transfer(fm3130->client->adapter, fm3130->msg, 2);
109
108
if (tmp != 2) {
110
109
dev_err(dev, "%s error %d\n", "read", tmp);
111
110
return -EIO;
···
196
197
}
197
198
198
199
/* read the RTC alarm registers all at once */
199
-
tmp = i2c_transfer(to_i2c_adapter(fm3130->client->dev.parent),
200
-
&fm3130->msg[2], 2);
200
+
tmp = i2c_transfer(fm3130->client->adapter, &fm3130->msg[2], 2);
201
201
if (tmp != 2) {
202
202
dev_err(dev, "%s error %d\n", "read", tmp);
203
203
return -EIO;
···
346
348
struct fm3130 *fm3130;
347
349
int err = -ENODEV;
348
350
int tmp;
349
-
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
351
+
struct i2c_adapter *adapter = client->adapter;
350
352
351
353
if (!i2c_check_functionality(adapter,
352
354
I2C_FUNC_I2C | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
+87
drivers/rtc/rtc-imx-sc.c
+87
drivers/rtc/rtc-imx-sc.c
···
3
3
* Copyright 2018 NXP.
4
4
*/
5
5
6
+
#include <dt-bindings/firmware/imx/rsrc.h>
6
7
#include <linux/arm-smccc.h>
7
8
#include <linux/firmware/imx/sci.h>
8
9
#include <linux/module.h>
···
12
11
#include <linux/rtc.h>
13
12
14
13
#define IMX_SC_TIMER_FUNC_GET_RTC_SEC1970 9
14
+
#define IMX_SC_TIMER_FUNC_SET_RTC_ALARM 8
15
15
#define IMX_SC_TIMER_FUNC_SET_RTC_TIME 6
16
16
17
17
#define IMX_SIP_SRTC 0xC2000002
18
18
#define IMX_SIP_SRTC_SET_TIME 0x0
19
+
20
+
#define SC_IRQ_GROUP_RTC 2
21
+
#define SC_IRQ_RTC 1
19
22
20
23
static struct imx_sc_ipc *rtc_ipc_handle;
21
24
static struct rtc_device *imx_sc_rtc;
···
27
22
struct imx_sc_msg_timer_get_rtc_time {
28
23
struct imx_sc_rpc_msg hdr;
29
24
u32 time;
25
+
} __packed;
26
+
27
+
struct imx_sc_msg_timer_rtc_set_alarm {
28
+
struct imx_sc_rpc_msg hdr;
29
+
u16 year;
30
+
u8 mon;
31
+
u8 day;
32
+
u8 hour;
33
+
u8 min;
34
+
u8 sec;
30
35
} __packed;
31
36
32
37
static int imx_sc_rtc_read_time(struct device *dev, struct rtc_time *tm)
···
75
60
return res.a0;
76
61
}
77
62
63
+
static int imx_sc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
64
+
{
65
+
return imx_scu_irq_group_enable(SC_IRQ_GROUP_RTC, SC_IRQ_RTC, enable);
66
+
}
67
+
68
+
static int imx_sc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
69
+
{
70
+
/*
71
+
* SCU firmware does NOT provide read alarm API, but .read_alarm
72
+
* callback is required by RTC framework to support alarm function,
73
+
* so just return here.
74
+
*/
75
+
return 0;
76
+
}
77
+
78
+
static int imx_sc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
79
+
{
80
+
struct imx_sc_msg_timer_rtc_set_alarm msg;
81
+
struct imx_sc_rpc_msg *hdr = &msg.hdr;
82
+
int ret;
83
+
struct rtc_time *alrm_tm = &alrm->time;
84
+
85
+
hdr->ver = IMX_SC_RPC_VERSION;
86
+
hdr->svc = IMX_SC_RPC_SVC_TIMER;
87
+
hdr->func = IMX_SC_TIMER_FUNC_SET_RTC_ALARM;
88
+
hdr->size = 3;
89
+
90
+
msg.year = alrm_tm->tm_year + 1900;
91
+
msg.mon = alrm_tm->tm_mon + 1;
92
+
msg.day = alrm_tm->tm_mday;
93
+
msg.hour = alrm_tm->tm_hour;
94
+
msg.min = alrm_tm->tm_min;
95
+
msg.sec = alrm_tm->tm_sec;
96
+
97
+
ret = imx_scu_call_rpc(rtc_ipc_handle, &msg, true);
98
+
if (ret) {
99
+
dev_err(dev, "set rtc alarm failed, ret %d\n", ret);
100
+
return ret;
101
+
}
102
+
103
+
ret = imx_sc_rtc_alarm_irq_enable(dev, alrm->enabled);
104
+
if (ret) {
105
+
dev_err(dev, "enable rtc alarm failed, ret %d\n", ret);
106
+
return ret;
107
+
}
108
+
109
+
return 0;
110
+
}
111
+
78
112
static const struct rtc_class_ops imx_sc_rtc_ops = {
79
113
.read_time = imx_sc_rtc_read_time,
80
114
.set_time = imx_sc_rtc_set_time,
115
+
.read_alarm = imx_sc_rtc_read_alarm,
116
+
.set_alarm = imx_sc_rtc_set_alarm,
117
+
.alarm_irq_enable = imx_sc_rtc_alarm_irq_enable,
118
+
};
119
+
120
+
static int imx_sc_rtc_alarm_notify(struct notifier_block *nb,
121
+
unsigned long event, void *group)
122
+
{
123
+
/* ignore non-rtc irq */
124
+
if (!((event & SC_IRQ_RTC) && (*(u8 *)group == SC_IRQ_GROUP_RTC)))
125
+
return 0;
126
+
127
+
rtc_update_irq(imx_sc_rtc, 1, RTC_IRQF | RTC_AF);
128
+
129
+
return 0;
130
+
}
131
+
132
+
static struct notifier_block imx_sc_rtc_alarm_sc_notifier = {
133
+
.notifier_call = imx_sc_rtc_alarm_notify,
81
134
};
82
135
83
136
static int imx_sc_rtc_probe(struct platform_device *pdev)
···
155
72
ret = imx_scu_get_handle(&rtc_ipc_handle);
156
73
if (ret)
157
74
return ret;
75
+
76
+
device_init_wakeup(&pdev->dev, true);
158
77
159
78
imx_sc_rtc = devm_rtc_allocate_device(&pdev->dev);
160
79
if (IS_ERR(imx_sc_rtc))
···
171
86
dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
172
87
return ret;
173
88
}
89
+
90
+
imx_scu_irq_register_notifier(&imx_sc_rtc_alarm_sc_notifier);
174
91
175
92
return 0;
176
93
}
+1
-1
drivers/rtc/rtc-m41t80.c
+1
-1
drivers/rtc/rtc-m41t80.c
···
872
872
static int m41t80_probe(struct i2c_client *client,
873
873
const struct i2c_device_id *id)
874
874
{
875
-
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
875
+
struct i2c_adapter *adapter = client->adapter;
876
876
int rc = 0;
877
877
struct rtc_time tm;
878
878
struct m41t80_data *m41t80_data = NULL;
+176
-180
drivers/rtc/rtc-pcf2123.c
+176
-180
drivers/rtc/rtc-pcf2123.c
···
40
40
#include <linux/rtc.h>
41
41
#include <linux/spi/spi.h>
42
42
#include <linux/module.h>
43
-
#include <linux/sysfs.h>
43
+
#include <linux/regmap.h>
44
44
45
45
/* REGISTERS */
46
46
#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
···
95
95
#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
96
96
#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
97
97
#define OFFSET_STEP (2170) /* Offset step in parts per billion */
98
+
#define OFFSET_MASK GENMASK(6, 0) /* Offset value */
98
99
99
100
/* READ/WRITE ADDRESS BITS */
100
101
#define PCF2123_WRITE BIT(4)
···
104
103
105
104
static struct spi_driver pcf2123_driver;
106
105
107
-
struct pcf2123_sysfs_reg {
108
-
struct device_attribute attr;
109
-
char name[2];
110
-
};
111
-
112
106
struct pcf2123_plat_data {
113
107
struct rtc_device *rtc;
114
-
struct pcf2123_sysfs_reg regs[16];
108
+
struct regmap *map;
115
109
};
116
110
117
-
/*
118
-
* Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
119
-
* is released properly after an SPI write. This function should be
120
-
* called after EVERY read/write call over SPI.
121
-
*/
122
-
static inline void pcf2123_delay_trec(void)
123
-
{
124
-
ndelay(30);
125
-
}
126
-
127
-
static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
128
-
{
129
-
struct spi_device *spi = to_spi_device(dev);
130
-
int ret;
131
-
132
-
reg |= PCF2123_READ;
133
-
ret = spi_write_then_read(spi, ®, 1, rxbuf, size);
134
-
pcf2123_delay_trec();
135
-
136
-
return ret;
137
-
}
138
-
139
-
static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
140
-
{
141
-
struct spi_device *spi = to_spi_device(dev);
142
-
int ret;
143
-
144
-
txbuf[0] |= PCF2123_WRITE;
145
-
ret = spi_write(spi, txbuf, size);
146
-
pcf2123_delay_trec();
147
-
148
-
return ret;
149
-
}
150
-
151
-
static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
152
-
{
153
-
u8 txbuf[2];
154
-
155
-
txbuf[0] = reg;
156
-
txbuf[1] = val;
157
-
return pcf2123_write(dev, txbuf, sizeof(txbuf));
158
-
}
159
-
160
-
static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
161
-
char *buffer)
162
-
{
163
-
struct pcf2123_sysfs_reg *r;
164
-
u8 rxbuf[1];
165
-
unsigned long reg;
166
-
int ret;
167
-
168
-
r = container_of(attr, struct pcf2123_sysfs_reg, attr);
169
-
170
-
ret = kstrtoul(r->name, 16, ®);
171
-
if (ret)
172
-
return ret;
173
-
174
-
ret = pcf2123_read(dev, reg, rxbuf, 1);
175
-
if (ret < 0)
176
-
return -EIO;
177
-
178
-
return sprintf(buffer, "0x%x\n", rxbuf[0]);
179
-
}
180
-
181
-
static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
182
-
const char *buffer, size_t count)
183
-
{
184
-
struct pcf2123_sysfs_reg *r;
185
-
unsigned long reg;
186
-
unsigned long val;
187
-
188
-
int ret;
189
-
190
-
r = container_of(attr, struct pcf2123_sysfs_reg, attr);
191
-
192
-
ret = kstrtoul(r->name, 16, ®);
193
-
if (ret)
194
-
return ret;
195
-
196
-
ret = kstrtoul(buffer, 10, &val);
197
-
if (ret)
198
-
return ret;
199
-
200
-
ret = pcf2123_write_reg(dev, reg, val);
201
-
if (ret < 0)
202
-
return -EIO;
203
-
return count;
204
-
}
111
+
static const struct regmap_config pcf2123_regmap_config = {
112
+
.reg_bits = 8,
113
+
.val_bits = 8,
114
+
.read_flag_mask = PCF2123_READ,
115
+
.write_flag_mask = PCF2123_WRITE,
116
+
.max_register = PCF2123_REG_CTDWN_TMR,
117
+
};
205
118
206
119
static int pcf2123_read_offset(struct device *dev, long *offset)
207
120
{
208
-
int ret;
209
-
s8 reg;
121
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
122
+
int ret, val;
123
+
unsigned int reg;
210
124
211
-
ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1);
212
-
if (ret < 0)
125
+
ret = regmap_read(pdata->map, PCF2123_REG_OFFSET, ®);
126
+
if (ret)
213
127
return ret;
214
128
215
-
if (reg & OFFSET_COARSE)
216
-
reg <<= 1; /* multiply by 2 and sign extend */
217
-
else
218
-
reg = sign_extend32(reg, OFFSET_SIGN_BIT);
129
+
val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
219
130
220
-
*offset = ((long)reg) * OFFSET_STEP;
131
+
if (reg & OFFSET_COARSE)
132
+
val *= 2;
133
+
134
+
*offset = ((long)val) * OFFSET_STEP;
221
135
222
136
return 0;
223
137
}
···
149
233
*/
150
234
static int pcf2123_set_offset(struct device *dev, long offset)
151
235
{
236
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
152
237
s8 reg;
153
238
154
239
if (offset > OFFSET_STEP * 127)
···
157
240
else if (offset < OFFSET_STEP * -128)
158
241
reg = -128;
159
242
else
160
-
reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
243
+
reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
161
244
162
245
/* choose fine offset only for odd values in the normal range */
163
246
if (reg & 1 && reg <= 63 && reg >= -64) {
···
169
252
reg |= OFFSET_COARSE;
170
253
}
171
254
172
-
return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
255
+
return regmap_write(pdata->map, PCF2123_REG_OFFSET, (unsigned int)reg);
173
256
}
174
257
175
258
static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
176
259
{
260
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
177
261
u8 rxbuf[7];
178
262
int ret;
179
263
180
-
ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
181
-
if (ret < 0)
264
+
ret = regmap_bulk_read(pdata->map, PCF2123_REG_SC, rxbuf,
265
+
sizeof(rxbuf));
266
+
if (ret)
182
267
return ret;
183
268
184
269
if (rxbuf[0] & OSC_HAS_STOPPED) {
···
198
279
if (tm->tm_year < 70)
199
280
tm->tm_year += 100; /* assume we are in 1970...2069 */
200
281
201
-
dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
202
-
"mday=%d, mon=%d, year=%d, wday=%d\n",
203
-
__func__,
204
-
tm->tm_sec, tm->tm_min, tm->tm_hour,
205
-
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
282
+
dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
206
283
207
284
return 0;
208
285
}
209
286
210
287
static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
211
288
{
212
-
u8 txbuf[8];
289
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
290
+
u8 txbuf[7];
213
291
int ret;
214
292
215
-
dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
216
-
"mday=%d, mon=%d, year=%d, wday=%d\n",
217
-
__func__,
218
-
tm->tm_sec, tm->tm_min, tm->tm_hour,
219
-
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
293
+
dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
220
294
221
295
/* Stop the counter first */
222
-
ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
223
-
if (ret < 0)
296
+
ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
297
+
if (ret)
224
298
return ret;
225
299
226
300
/* Set the new time */
227
-
txbuf[0] = PCF2123_REG_SC;
228
-
txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
229
-
txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
230
-
txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
231
-
txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
232
-
txbuf[5] = tm->tm_wday & 0x07;
233
-
txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
234
-
txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
301
+
txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
302
+
txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
303
+
txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
304
+
txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
305
+
txbuf[4] = tm->tm_wday & 0x07;
306
+
txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
307
+
txbuf[6] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
235
308
236
-
ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
237
-
if (ret < 0)
309
+
ret = regmap_bulk_write(pdata->map, PCF2123_REG_SC, txbuf,
310
+
sizeof(txbuf));
311
+
if (ret)
238
312
return ret;
239
313
240
314
/* Start the counter */
241
-
ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
242
-
if (ret < 0)
315
+
ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
316
+
if (ret)
243
317
return ret;
244
318
245
319
return 0;
246
320
}
247
321
322
+
static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
323
+
{
324
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
325
+
u8 rxbuf[4];
326
+
int ret;
327
+
unsigned int val = 0;
328
+
329
+
ret = regmap_bulk_read(pdata->map, PCF2123_REG_ALRM_MN, rxbuf,
330
+
sizeof(rxbuf));
331
+
if (ret)
332
+
return ret;
333
+
334
+
alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
335
+
alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
336
+
alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
337
+
alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
338
+
339
+
dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
340
+
341
+
ret = regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
342
+
if (ret)
343
+
return ret;
344
+
345
+
alm->enabled = !!(val & CTRL2_AIE);
346
+
347
+
return 0;
348
+
}
349
+
350
+
static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
351
+
{
352
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
353
+
u8 txbuf[4];
354
+
int ret;
355
+
356
+
dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
357
+
358
+
/* Ensure alarm flag is clear */
359
+
ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
360
+
if (ret)
361
+
return ret;
362
+
363
+
/* Disable alarm interrupt */
364
+
ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
365
+
if (ret)
366
+
return ret;
367
+
368
+
/* Set new alarm */
369
+
txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
370
+
txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
371
+
txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
372
+
txbuf[3] = bin2bcd(alm->time.tm_wday & 0x07);
373
+
374
+
ret = regmap_bulk_write(pdata->map, PCF2123_REG_ALRM_MN, txbuf,
375
+
sizeof(txbuf));
376
+
if (ret)
377
+
return ret;
378
+
379
+
/* Enable alarm interrupt */
380
+
if (alm->enabled) {
381
+
ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2,
382
+
CTRL2_AIE, CTRL2_AIE);
383
+
if (ret)
384
+
return ret;
385
+
}
386
+
387
+
return 0;
388
+
}
389
+
390
+
static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
391
+
{
392
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
393
+
struct mutex *lock = &pdata->rtc->ops_lock;
394
+
unsigned int val = 0;
395
+
int ret = IRQ_NONE;
396
+
397
+
mutex_lock(lock);
398
+
regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
399
+
400
+
/* Alarm? */
401
+
if (val & CTRL2_AF) {
402
+
ret = IRQ_HANDLED;
403
+
404
+
/* Clear alarm flag */
405
+
regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
406
+
407
+
rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
408
+
}
409
+
410
+
mutex_unlock(lock);
411
+
412
+
return ret;
413
+
}
414
+
248
415
static int pcf2123_reset(struct device *dev)
249
416
{
417
+
struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
250
418
int ret;
251
-
u8 rxbuf[2];
419
+
unsigned int val = 0;
252
420
253
-
ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
254
-
if (ret < 0)
421
+
ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
422
+
if (ret)
255
423
return ret;
256
424
257
425
/* Stop the counter */
258
426
dev_dbg(dev, "stopping RTC\n");
259
-
ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
260
-
if (ret < 0)
427
+
ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
428
+
if (ret)
261
429
return ret;
262
430
263
431
/* See if the counter was actually stopped */
264
432
dev_dbg(dev, "checking for presence of RTC\n");
265
-
ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
266
-
if (ret < 0)
433
+
ret = regmap_read(pdata->map, PCF2123_REG_CTRL1, &val);
434
+
if (ret)
267
435
return ret;
268
436
269
-
dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
270
-
rxbuf[0], rxbuf[1]);
271
-
if (!(rxbuf[0] & CTRL1_STOP))
437
+
dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
438
+
if (!(val & CTRL1_STOP))
272
439
return -ENODEV;
273
440
274
441
/* Start the counter */
275
-
ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
276
-
if (ret < 0)
442
+
ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
443
+
if (ret)
277
444
return ret;
278
445
279
446
return 0;
···
370
365
.set_time = pcf2123_rtc_set_time,
371
366
.read_offset = pcf2123_read_offset,
372
367
.set_offset = pcf2123_set_offset,
373
-
368
+
.read_alarm = pcf2123_rtc_read_alarm,
369
+
.set_alarm = pcf2123_rtc_set_alarm,
374
370
};
375
371
376
372
static int pcf2123_probe(struct spi_device *spi)
···
379
373
struct rtc_device *rtc;
380
374
struct rtc_time tm;
381
375
struct pcf2123_plat_data *pdata;
382
-
int ret, i;
376
+
int ret = 0;
383
377
384
378
pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
385
379
GFP_KERNEL);
386
380
if (!pdata)
387
381
return -ENOMEM;
388
382
spi->dev.platform_data = pdata;
383
+
384
+
pdata->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
385
+
386
+
if (IS_ERR(pdata->map)) {
387
+
dev_err(&spi->dev, "regmap init failed.\n");
388
+
goto kfree_exit;
389
+
}
389
390
390
391
ret = pcf2123_rtc_read_time(&spi->dev, &tm);
391
392
if (ret < 0) {
···
418
405
419
406
pdata->rtc = rtc;
420
407
421
-
for (i = 0; i < 16; i++) {
422
-
sysfs_attr_init(&pdata->regs[i].attr.attr);
423
-
sprintf(pdata->regs[i].name, "%1x", i);
424
-
pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
425
-
pdata->regs[i].attr.attr.name = pdata->regs[i].name;
426
-
pdata->regs[i].attr.show = pcf2123_show;
427
-
pdata->regs[i].attr.store = pcf2123_store;
428
-
ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
429
-
if (ret) {
430
-
dev_err(&spi->dev, "Unable to create sysfs %s\n",
431
-
pdata->regs[i].name);
432
-
goto sysfs_exit;
433
-
}
408
+
/* Register alarm irq */
409
+
if (spi->irq > 0) {
410
+
ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
411
+
pcf2123_rtc_irq,
412
+
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
413
+
pcf2123_driver.driver.name, &spi->dev);
414
+
if (!ret)
415
+
device_init_wakeup(&spi->dev, true);
416
+
else
417
+
dev_err(&spi->dev, "could not request irq.\n");
434
418
}
435
419
436
-
return 0;
420
+
/* The PCF2123's alarm only has minute accuracy. Must add timer
421
+
* support to this driver to generate interrupts more than once
422
+
* per minute.
423
+
*/
424
+
pdata->rtc->uie_unsupported = 1;
437
425
438
-
sysfs_exit:
439
-
for (i--; i >= 0; i--)
440
-
device_remove_file(&spi->dev, &pdata->regs[i].attr);
426
+
return 0;
441
427
442
428
kfree_exit:
443
429
spi->dev.platform_data = NULL;
444
430
return ret;
445
-
}
446
-
447
-
static int pcf2123_remove(struct spi_device *spi)
448
-
{
449
-
struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
450
-
int i;
451
-
452
-
if (pdata) {
453
-
for (i = 0; i < 16; i++)
454
-
if (pdata->regs[i].name[0])
455
-
device_remove_file(&spi->dev,
456
-
&pdata->regs[i].attr);
457
-
}
458
-
459
-
return 0;
460
431
}
461
432
462
433
#ifdef CONFIG_OF
···
458
461
.of_match_table = of_match_ptr(pcf2123_dt_ids),
459
462
},
460
463
.probe = pcf2123_probe,
461
-
.remove = pcf2123_remove,
462
464
};
463
465
464
466
module_spi_driver(pcf2123_driver);
+6
-7
drivers/rtc/rtc-pcf8563.c
+6
-7
drivers/rtc/rtc-pcf8563.c
···
560
560
struct pcf8563 *pcf8563;
561
561
int err;
562
562
unsigned char buf;
563
-
unsigned char alm_pending;
564
563
565
564
dev_dbg(&client->dev, "%s\n", __func__);
566
565
···
583
584
return err;
584
585
}
585
586
586
-
err = pcf8563_get_alarm_mode(client, NULL, &alm_pending);
587
-
if (err) {
588
-
dev_err(&client->dev, "%s: read error\n", __func__);
587
+
/* Clear flags and disable interrupts */
588
+
buf = 0;
589
+
err = pcf8563_write_block_data(client, PCF8563_REG_ST2, 1, &buf);
590
+
if (err < 0) {
591
+
dev_err(&client->dev, "%s: write error\n", __func__);
589
592
return err;
590
593
}
591
-
if (alm_pending)
592
-
pcf8563_set_alarm_mode(client, 0);
593
594
594
595
pcf8563->rtc = devm_rtc_device_register(&client->dev,
595
596
pcf8563_driver.driver.name,
···
601
602
if (client->irq > 0) {
602
603
err = devm_request_threaded_irq(&client->dev, client->irq,
603
604
NULL, pcf8563_irq,
604
-
IRQF_SHARED|IRQF_ONESHOT|IRQF_TRIGGER_FALLING,
605
+
IRQF_SHARED | IRQF_ONESHOT | IRQF_TRIGGER_LOW,
605
606
pcf8563_driver.driver.name, client);
606
607
if (err) {
607
608
dev_err(&client->dev, "unable to request IRQ %d\n",
+1
-1
drivers/rtc/rtc-rv8803.c
+1
-1
drivers/rtc/rtc-rv8803.c
···
517
517
static int rv8803_probe(struct i2c_client *client,
518
518
const struct i2c_device_id *id)
519
519
{
520
-
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
520
+
struct i2c_adapter *adapter = client->adapter;
521
521
struct rv8803_data *rv8803;
522
522
int err, flags;
523
523
struct nvmem_config nvmem_cfg = {
+1
-1
drivers/rtc/rtc-rx8010.c
+1
-1
drivers/rtc/rtc-rx8010.c
···
433
433
static int rx8010_probe(struct i2c_client *client,
434
434
const struct i2c_device_id *id)
435
435
{
436
-
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
436
+
struct i2c_adapter *adapter = client->adapter;
437
437
struct rx8010_data *rx8010;
438
438
int err = 0;
439
439
+1
-1
drivers/rtc/rtc-rx8025.c
+1
-1
drivers/rtc/rtc-rx8025.c
···
501
501
static int rx8025_probe(struct i2c_client *client,
502
502
const struct i2c_device_id *id)
503
503
{
504
-
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
504
+
struct i2c_adapter *adapter = client->adapter;
505
505
struct rx8025_data *rx8025;
506
506
int err = 0;
507
507
+29
-26
drivers/rtc/rtc-s35390a.c
+29
-26
drivers/rtc/rtc-s35390a.c
···
32
32
#define S35390A_ALRM_BYTE_MINS 2
33
33
34
34
/* flags for STATUS1 */
35
-
#define S35390A_FLAG_POC 0x01
36
-
#define S35390A_FLAG_BLD 0x02
37
-
#define S35390A_FLAG_INT2 0x04
38
-
#define S35390A_FLAG_24H 0x40
39
-
#define S35390A_FLAG_RESET 0x80
35
+
#define S35390A_FLAG_POC BIT(0)
36
+
#define S35390A_FLAG_BLD BIT(1)
37
+
#define S35390A_FLAG_INT2 BIT(2)
38
+
#define S35390A_FLAG_24H BIT(6)
39
+
#define S35390A_FLAG_RESET BIT(7)
40
40
41
41
/* flag for STATUS2 */
42
-
#define S35390A_FLAG_TEST 0x01
42
+
#define S35390A_FLAG_TEST BIT(0)
43
43
44
-
#define S35390A_INT2_MODE_MASK 0xF0
45
-
44
+
/* INT2 pin output mode */
45
+
#define S35390A_INT2_MODE_MASK 0x0E
46
46
#define S35390A_INT2_MODE_NOINTR 0x00
47
-
#define S35390A_INT2_MODE_FREQ 0x10
48
-
#define S35390A_INT2_MODE_ALARM 0x40
49
-
#define S35390A_INT2_MODE_PMIN_EDG 0x20
47
+
#define S35390A_INT2_MODE_ALARM BIT(1) /* INT2AE */
48
+
#define S35390A_INT2_MODE_PMIN_EDG BIT(2) /* INT2ME */
49
+
#define S35390A_INT2_MODE_FREQ BIT(3) /* INT2FE */
50
+
#define S35390A_INT2_MODE_PMIN (BIT(3) | BIT(2)) /* INT2FE | INT2ME */
50
51
51
52
static const struct i2c_device_id s35390a_id[] = {
52
53
{ "s35390a", 0 },
···
285
284
alm->time.tm_min, alm->time.tm_hour, alm->time.tm_mday,
286
285
alm->time.tm_mon, alm->time.tm_year, alm->time.tm_wday);
287
286
287
+
if (alm->time.tm_sec != 0)
288
+
dev_warn(&client->dev, "Alarms are only supported on a per minute basis!\n");
289
+
288
290
/* disable interrupt (which deasserts the irq line) */
289
291
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
290
292
if (err < 0)
···
302
298
sts = S35390A_INT2_MODE_ALARM;
303
299
else
304
300
sts = S35390A_INT2_MODE_NOINTR;
305
-
306
-
/* This chip expects the bits of each byte to be in reverse order */
307
-
sts = bitrev8(sts);
308
301
309
302
/* set interupt mode*/
310
303
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
···
340
339
if (err < 0)
341
340
return err;
342
341
343
-
if ((bitrev8(sts) & S35390A_INT2_MODE_MASK) != S35390A_INT2_MODE_ALARM) {
342
+
if ((sts & S35390A_INT2_MODE_MASK) != S35390A_INT2_MODE_ALARM) {
344
343
/*
345
344
* When the alarm isn't enabled, the register to configure
346
345
* the alarm time isn't accessible.
···
432
431
unsigned int i;
433
432
struct s35390a *s35390a;
434
433
char buf, status1;
434
+
struct device *dev = &client->dev;
435
435
436
436
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
437
437
err = -ENODEV;
438
438
goto exit;
439
439
}
440
440
441
-
s35390a = devm_kzalloc(&client->dev, sizeof(struct s35390a),
442
-
GFP_KERNEL);
441
+
s35390a = devm_kzalloc(dev, sizeof(struct s35390a), GFP_KERNEL);
443
442
if (!s35390a) {
444
443
err = -ENOMEM;
445
444
goto exit;
···
453
452
s35390a->client[i] = i2c_new_dummy(client->adapter,
454
453
client->addr + i);
455
454
if (!s35390a->client[i]) {
456
-
dev_err(&client->dev, "Address %02x unavailable\n",
457
-
client->addr + i);
455
+
dev_err(dev, "Address %02x unavailable\n",
456
+
client->addr + i);
458
457
err = -EBUSY;
459
458
goto exit_dummy;
460
459
}
···
463
462
err_read = s35390a_read_status(s35390a, &status1);
464
463
if (err_read < 0) {
465
464
err = err_read;
466
-
dev_err(&client->dev, "error resetting chip\n");
465
+
dev_err(dev, "error resetting chip\n");
467
466
goto exit_dummy;
468
467
}
469
468
···
477
476
buf = 0;
478
477
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &buf, 1);
479
478
if (err < 0) {
480
-
dev_err(&client->dev, "error disabling alarm");
479
+
dev_err(dev, "error disabling alarm");
481
480
goto exit_dummy;
482
481
}
483
482
} else {
484
483
err = s35390a_disable_test_mode(s35390a);
485
484
if (err < 0) {
486
-
dev_err(&client->dev, "error disabling test mode\n");
485
+
dev_err(dev, "error disabling test mode\n");
487
486
goto exit_dummy;
488
487
}
489
488
}
490
489
491
-
device_set_wakeup_capable(&client->dev, 1);
490
+
device_set_wakeup_capable(dev, 1);
492
491
493
-
s35390a->rtc = devm_rtc_device_register(&client->dev,
494
-
s35390a_driver.driver.name,
495
-
&s35390a_rtc_ops, THIS_MODULE);
492
+
s35390a->rtc = devm_rtc_device_register(dev, s35390a_driver.driver.name,
493
+
&s35390a_rtc_ops, THIS_MODULE);
496
494
497
495
if (IS_ERR(s35390a->rtc)) {
498
496
err = PTR_ERR(s35390a->rtc);
499
497
goto exit_dummy;
500
498
}
499
+
500
+
/* supports per-minute alarms only, therefore set uie_unsupported */
501
+
s35390a->rtc->uie_unsupported = 1;
501
502
502
503
if (status1 & S35390A_FLAG_INT2)
503
504
rtc_update_irq(s35390a->rtc, 1, RTC_AF);
-4
drivers/rtc/rtc-st-lpc.c
-4
drivers/rtc/rtc-st-lpc.c
+1
-5
drivers/rtc/rtc-stm32.c
+1
-5
drivers/rtc/rtc-stm32.c
···
519
519
/* Write to Alarm register */
520
520
writel_relaxed(alrmar, rtc->base + regs->alrmar);
521
521
522
-
if (alrm->enabled)
523
-
stm32_rtc_alarm_irq_enable(dev, 1);
524
-
else
525
-
stm32_rtc_alarm_irq_enable(dev, 0);
526
-
522
+
stm32_rtc_alarm_irq_enable(dev, alrm->enabled);
527
523
end:
528
524
stm32_rtc_wpr_lock(rtc);
529
525
+1
drivers/rtc/rtc-sun6i.c
+1
drivers/rtc/rtc-sun6i.c
···
672
672
{ .compatible = "allwinner,sun6i-a31-rtc" },
673
673
{ .compatible = "allwinner,sun8i-a23-rtc" },
674
674
{ .compatible = "allwinner,sun8i-h3-rtc" },
675
+
{ .compatible = "allwinner,sun8i-r40-rtc" },
675
676
{ .compatible = "allwinner,sun8i-v3-rtc" },
676
677
{ .compatible = "allwinner,sun50i-h5-rtc" },
677
678
{ /* sentinel */ },
+127
-126
drivers/rtc/rtc-tegra.c
+127
-126
drivers/rtc/rtc-tegra.c
···
2
2
/*
3
3
* An RTC driver for the NVIDIA Tegra 200 series internal RTC.
4
4
*
5
-
* Copyright (c) 2010, NVIDIA Corporation.
5
+
* Copyright (c) 2010-2019, NVIDIA Corporation.
6
6
*/
7
7
8
8
#include <linux/clk.h>
···
18
18
#include <linux/rtc.h>
19
19
#include <linux/slab.h>
20
20
21
-
/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
21
+
/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
22
22
#define TEGRA_RTC_REG_BUSY 0x004
23
23
#define TEGRA_RTC_REG_SECONDS 0x008
24
-
/* when msec is read, the seconds are buffered into shadow seconds. */
24
+
/* When msec is read, the seconds are buffered into shadow seconds. */
25
25
#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
26
26
#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
27
27
#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
···
46
46
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
47
47
48
48
struct tegra_rtc_info {
49
-
struct platform_device *pdev;
50
-
struct rtc_device *rtc_dev;
51
-
void __iomem *rtc_base; /* NULL if not initialized. */
52
-
struct clk *clk;
53
-
int tegra_rtc_irq; /* alarm and periodic irq */
54
-
spinlock_t tegra_rtc_lock;
49
+
struct platform_device *pdev;
50
+
struct rtc_device *rtc;
51
+
void __iomem *base; /* NULL if not initialized */
52
+
struct clk *clk;
53
+
int irq; /* alarm and periodic IRQ */
54
+
spinlock_t lock;
55
55
};
56
56
57
-
/* RTC hardware is busy when it is updating its values over AHB once
58
-
* every eight 32kHz clocks (~250uS).
59
-
* outside of these updates the CPU is free to write.
60
-
* CPU is always free to read.
57
+
/*
58
+
* RTC hardware is busy when it is updating its values over AHB once every
59
+
* eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
60
+
* write. CPU is always free to read.
61
61
*/
62
62
static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
63
63
{
64
-
return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
64
+
return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
65
65
}
66
66
67
-
/* Wait for hardware to be ready for writing.
68
-
* This function tries to maximize the amount of time before the next update.
69
-
* It does this by waiting for the RTC to become busy with its periodic update,
70
-
* then returning once the RTC first becomes not busy.
67
+
/*
68
+
* Wait for hardware to be ready for writing. This function tries to maximize
69
+
* the amount of time before the next update. It does this by waiting for the
70
+
* RTC to become busy with its periodic update, then returning once the RTC
71
+
* first becomes not busy.
72
+
*
71
73
* This periodic update (where the seconds and milliseconds are copied to the
72
-
* AHB side) occurs every eight 32kHz clocks (~250uS).
73
-
* The behavior of this function allows us to make some assumptions without
74
-
* introducing a race, because 250uS is plenty of time to read/write a value.
74
+
* AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
75
+
* function allows us to make some assumptions without introducing a race,
76
+
* because 250 us is plenty of time to read/write a value.
75
77
*/
76
78
static int tegra_rtc_wait_while_busy(struct device *dev)
77
79
{
78
80
struct tegra_rtc_info *info = dev_get_drvdata(dev);
81
+
int retries = 500; /* ~490 us is the worst case, ~250 us is best */
79
82
80
-
int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
81
-
82
-
/* first wait for the RTC to become busy. this is when it
83
-
* posts its updated seconds+msec registers to AHB side. */
83
+
/*
84
+
* First wait for the RTC to become busy. This is when it posts its
85
+
* updated seconds+msec registers to AHB side.
86
+
*/
84
87
while (tegra_rtc_check_busy(info)) {
85
88
if (!retries--)
86
89
goto retry_failed;
90
+
87
91
udelay(1);
88
92
}
89
93
···
95
91
return 0;
96
92
97
93
retry_failed:
98
-
dev_err(dev, "write failed:retry count exceeded.\n");
94
+
dev_err(dev, "write failed: retry count exceeded\n");
99
95
return -ETIMEDOUT;
100
96
}
101
97
102
98
static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
103
99
{
104
100
struct tegra_rtc_info *info = dev_get_drvdata(dev);
105
-
unsigned long sec, msec;
106
-
unsigned long sl_irq_flags;
101
+
unsigned long flags;
102
+
u32 sec, msec;
107
103
108
-
/* RTC hardware copies seconds to shadow seconds when a read
109
-
* of milliseconds occurs. use a lock to keep other threads out. */
110
-
spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
104
+
/*
105
+
* RTC hardware copies seconds to shadow seconds when a read of
106
+
* milliseconds occurs. use a lock to keep other threads out.
107
+
*/
108
+
spin_lock_irqsave(&info->lock, flags);
111
109
112
-
msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
113
-
sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
110
+
msec = readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
111
+
sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
114
112
115
-
spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
113
+
spin_unlock_irqrestore(&info->lock, flags);
116
114
117
115
rtc_time64_to_tm(sec, tm);
118
116
119
-
dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm);
117
+
dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
120
118
121
119
return 0;
122
120
}
···
126
120
static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
127
121
{
128
122
struct tegra_rtc_info *info = dev_get_drvdata(dev);
129
-
unsigned long sec;
123
+
u32 sec;
130
124
int ret;
131
125
132
-
/* convert tm to seconds. */
126
+
/* convert tm to seconds */
133
127
sec = rtc_tm_to_time64(tm);
134
128
135
-
dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm);
129
+
dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
136
130
137
-
/* seconds only written if wait succeeded. */
131
+
/* seconds only written if wait succeeded */
138
132
ret = tegra_rtc_wait_while_busy(dev);
139
133
if (!ret)
140
-
writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
134
+
writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
141
135
142
136
dev_vdbg(dev, "time read back as %d\n",
143
-
readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
137
+
readl(info->base + TEGRA_RTC_REG_SECONDS));
144
138
145
139
return ret;
146
140
}
···
148
142
static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
149
143
{
150
144
struct tegra_rtc_info *info = dev_get_drvdata(dev);
151
-
unsigned long sec;
152
-
unsigned tmp;
145
+
u32 sec, value;
153
146
154
-
sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
147
+
sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
155
148
156
149
if (sec == 0) {
157
-
/* alarm is disabled. */
150
+
/* alarm is disabled */
158
151
alarm->enabled = 0;
159
152
} else {
160
-
/* alarm is enabled. */
153
+
/* alarm is enabled */
161
154
alarm->enabled = 1;
162
155
rtc_time64_to_tm(sec, &alarm->time);
163
156
}
164
157
165
-
tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
166
-
alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
158
+
value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
159
+
alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
167
160
168
161
return 0;
169
162
}
···
170
165
static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
171
166
{
172
167
struct tegra_rtc_info *info = dev_get_drvdata(dev);
173
-
unsigned status;
174
-
unsigned long sl_irq_flags;
168
+
unsigned long flags;
169
+
u32 status;
175
170
176
171
tegra_rtc_wait_while_busy(dev);
177
-
spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
172
+
spin_lock_irqsave(&info->lock, flags);
178
173
179
-
/* read the original value, and OR in the flag. */
180
-
status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
174
+
/* read the original value, and OR in the flag */
175
+
status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
181
176
if (enabled)
182
177
status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
183
178
else
184
179
status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
185
180
186
-
writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
181
+
writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
187
182
188
-
spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
183
+
spin_unlock_irqrestore(&info->lock, flags);
189
184
190
185
return 0;
191
186
}
···
193
188
static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
194
189
{
195
190
struct tegra_rtc_info *info = dev_get_drvdata(dev);
196
-
unsigned long sec;
191
+
u32 sec;
197
192
198
193
if (alarm->enabled)
199
194
sec = rtc_tm_to_time64(&alarm->time);
···
201
196
sec = 0;
202
197
203
198
tegra_rtc_wait_while_busy(dev);
204
-
writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
199
+
writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
205
200
dev_vdbg(dev, "alarm read back as %d\n",
206
-
readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
201
+
readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
207
202
208
203
/* if successfully written and alarm is enabled ... */
209
204
if (sec) {
210
205
tegra_rtc_alarm_irq_enable(dev, 1);
211
-
dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time);
206
+
dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
212
207
} else {
213
-
/* disable alarm if 0 or write error. */
208
+
/* disable alarm if 0 or write error */
214
209
dev_vdbg(dev, "alarm disabled\n");
215
210
tegra_rtc_alarm_irq_enable(dev, 0);
216
211
}
···
232
227
{
233
228
struct device *dev = data;
234
229
struct tegra_rtc_info *info = dev_get_drvdata(dev);
235
-
unsigned long events = 0;
236
-
unsigned status;
237
-
unsigned long sl_irq_flags;
230
+
unsigned long events = 0, flags;
231
+
u32 status;
238
232
239
-
status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
233
+
status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
240
234
if (status) {
241
-
/* clear the interrupt masks and status on any irq. */
235
+
/* clear the interrupt masks and status on any IRQ */
242
236
tegra_rtc_wait_while_busy(dev);
243
-
spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
244
-
writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
245
-
writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
246
-
spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
237
+
238
+
spin_lock_irqsave(&info->lock, flags);
239
+
writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
240
+
writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
241
+
spin_unlock_irqrestore(&info->lock, flags);
247
242
}
248
243
249
-
/* check if Alarm */
250
-
if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
244
+
/* check if alarm */
245
+
if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
251
246
events |= RTC_IRQF | RTC_AF;
252
247
253
-
/* check if Periodic */
254
-
if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
248
+
/* check if periodic */
249
+
if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
255
250
events |= RTC_IRQF | RTC_PF;
256
251
257
-
rtc_update_irq(info->rtc_dev, 1, events);
252
+
rtc_update_irq(info->rtc, 1, events);
258
253
259
254
return IRQ_HANDLED;
260
255
}
261
256
262
257
static const struct rtc_class_ops tegra_rtc_ops = {
263
-
.read_time = tegra_rtc_read_time,
264
-
.set_time = tegra_rtc_set_time,
265
-
.read_alarm = tegra_rtc_read_alarm,
266
-
.set_alarm = tegra_rtc_set_alarm,
267
-
.proc = tegra_rtc_proc,
258
+
.read_time = tegra_rtc_read_time,
259
+
.set_time = tegra_rtc_set_time,
260
+
.read_alarm = tegra_rtc_read_alarm,
261
+
.set_alarm = tegra_rtc_set_alarm,
262
+
.proc = tegra_rtc_proc,
268
263
.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
269
264
};
270
265
···
274
269
};
275
270
MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
276
271
277
-
static int __init tegra_rtc_probe(struct platform_device *pdev)
272
+
static int tegra_rtc_probe(struct platform_device *pdev)
278
273
{
279
274
struct tegra_rtc_info *info;
280
275
struct resource *res;
281
276
int ret;
282
277
283
-
info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
284
-
GFP_KERNEL);
278
+
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
285
279
if (!info)
286
280
return -ENOMEM;
287
281
288
282
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289
-
info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
290
-
if (IS_ERR(info->rtc_base))
291
-
return PTR_ERR(info->rtc_base);
283
+
info->base = devm_ioremap_resource(&pdev->dev, res);
284
+
if (IS_ERR(info->base))
285
+
return PTR_ERR(info->base);
292
286
293
287
ret = platform_get_irq(pdev, 0);
294
288
if (ret <= 0) {
···
295
291
return ret;
296
292
}
297
293
298
-
info->tegra_rtc_irq = ret;
294
+
info->irq = ret;
299
295
300
-
info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
301
-
if (IS_ERR(info->rtc_dev))
302
-
return PTR_ERR(info->rtc_dev);
296
+
info->rtc = devm_rtc_allocate_device(&pdev->dev);
297
+
if (IS_ERR(info->rtc))
298
+
return PTR_ERR(info->rtc);
303
299
304
-
info->rtc_dev->ops = &tegra_rtc_ops;
305
-
info->rtc_dev->range_max = U32_MAX;
300
+
info->rtc->ops = &tegra_rtc_ops;
301
+
info->rtc->range_max = U32_MAX;
306
302
307
303
info->clk = devm_clk_get(&pdev->dev, NULL);
308
304
if (IS_ERR(info->clk))
···
312
308
if (ret < 0)
313
309
return ret;
314
310
315
-
/* set context info. */
311
+
/* set context info */
316
312
info->pdev = pdev;
317
-
spin_lock_init(&info->tegra_rtc_lock);
313
+
spin_lock_init(&info->lock);
318
314
319
315
platform_set_drvdata(pdev, info);
320
316
321
-
/* clear out the hardware. */
322
-
writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
323
-
writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
324
-
writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
317
+
/* clear out the hardware */
318
+
writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
319
+
writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
320
+
writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
325
321
326
322
device_init_wakeup(&pdev->dev, 1);
327
323
328
-
ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
329
-
tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
330
-
dev_name(&pdev->dev), &pdev->dev);
324
+
ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
325
+
IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
326
+
&pdev->dev);
331
327
if (ret) {
332
-
dev_err(&pdev->dev,
333
-
"Unable to request interrupt for device (err=%d).\n",
334
-
ret);
328
+
dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
335
329
goto disable_clk;
336
330
}
337
331
338
-
ret = rtc_register_device(info->rtc_dev);
332
+
ret = rtc_register_device(info->rtc);
339
333
if (ret) {
340
-
dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
341
-
ret);
334
+
dev_err(&pdev->dev, "failed to register device: %d\n", ret);
342
335
goto disable_clk;
343
336
}
344
337
···
364
363
365
364
tegra_rtc_wait_while_busy(dev);
366
365
367
-
/* only use ALARM0 as a wake source. */
368
-
writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
366
+
/* only use ALARM0 as a wake source */
367
+
writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
369
368
writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
370
-
info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
369
+
info->base + TEGRA_RTC_REG_INTR_MASK);
371
370
372
371
dev_vdbg(dev, "alarm sec = %d\n",
373
-
readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
372
+
readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
374
373
375
-
dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
376
-
device_may_wakeup(dev), info->tegra_rtc_irq);
374
+
dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
375
+
device_may_wakeup(dev), info->irq);
377
376
378
-
/* leave the alarms on as a wake source. */
377
+
/* leave the alarms on as a wake source */
379
378
if (device_may_wakeup(dev))
380
-
enable_irq_wake(info->tegra_rtc_irq);
379
+
enable_irq_wake(info->irq);
381
380
382
381
return 0;
383
382
}
···
387
386
struct tegra_rtc_info *info = dev_get_drvdata(dev);
388
387
389
388
dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
390
-
device_may_wakeup(dev));
391
-
/* alarms were left on as a wake source, turn them off. */
389
+
device_may_wakeup(dev));
390
+
391
+
/* alarms were left on as a wake source, turn them off */
392
392
if (device_may_wakeup(dev))
393
-
disable_irq_wake(info->tegra_rtc_irq);
393
+
disable_irq_wake(info->irq);
394
394
395
395
return 0;
396
396
}
···
401
399
402
400
static void tegra_rtc_shutdown(struct platform_device *pdev)
403
401
{
404
-
dev_vdbg(&pdev->dev, "disabling interrupts.\n");
402
+
dev_vdbg(&pdev->dev, "disabling interrupts\n");
405
403
tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
406
404
}
407
405
408
-
MODULE_ALIAS("platform:tegra_rtc");
409
406
static struct platform_driver tegra_rtc_driver = {
410
-
.remove = tegra_rtc_remove,
411
-
.shutdown = tegra_rtc_shutdown,
412
-
.driver = {
413
-
.name = "tegra_rtc",
407
+
.probe = tegra_rtc_probe,
408
+
.remove = tegra_rtc_remove,
409
+
.shutdown = tegra_rtc_shutdown,
410
+
.driver = {
411
+
.name = "tegra_rtc",
414
412
.of_match_table = tegra_rtc_dt_match,
415
-
.pm = &tegra_rtc_pm_ops,
413
+
.pm = &tegra_rtc_pm_ops,
416
414
},
417
415
};
418
-
419
-
module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
416
+
module_platform_driver(tegra_rtc_driver);
420
417
421
418
MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
422
419
MODULE_DESCRIPTION("driver for Tegra internal RTC");
+1
drivers/rtc/rtc-test.c
+1
drivers/rtc/rtc-test.c
+1
-1
drivers/rtc/rtc-tps65910.c
+1
-1
drivers/rtc/rtc-tps65910.c
···
143
143
struct tps65910 *tps = dev_get_drvdata(dev->parent);
144
144
int ret;
145
145
146
-
ret = regmap_bulk_read(tps->regmap, TPS65910_SECONDS, alarm_data,
146
+
ret = regmap_bulk_read(tps->regmap, TPS65910_ALARM_SECONDS, alarm_data,
147
147
NUM_TIME_REGS);
148
148
if (ret < 0) {
149
149
dev_err(dev, "rtc_read_alarm error %d\n", ret);
+2
-1
drivers/rtc/rtc-wm831x.c
+2
-1
drivers/rtc/rtc-wm831x.c
···
435
435
436
436
ret = devm_request_threaded_irq(&pdev->dev, alm_irq, NULL,
437
437
wm831x_alm_irq,
438
-
IRQF_TRIGGER_RISING, "RTC alarm",
438
+
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
439
+
"RTC alarm",
439
440
wm831x_rtc);
440
441
if (ret != 0) {
441
442
dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",