Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
scsi: elx: libefc_sli: SLI-4 register offsets and field definitions
This is the initial patch for the new Emulex target mode SCSI driver.
- Create the new Emulex source level directory drivers/scsi/elx and add
the directory to the MAINTAINERS file.
- Create the first library subdirectory drivers/scsi/elx/libefc_sli. This
library is a SLI-4 interface library.
- Start the population of the libefc_sli library with definitions of SLI-4
hardware register offsets and definitions.
Link: https://lore.kernel.org/r/20210601235512.20104-2-jsmart2021@gmail.com
Reviewed-by: Hannes Reinecke <hare@suse.de>
Reviewed-by: Daniel Wagner <dwagner@suse.de>
Co-developed-by: Ram Vegesna <ram.vegesna@broadcom.com>
Signed-off-by: Ram Vegesna <ram.vegesna@broadcom.com>
Signed-off-by: James Smart <jsmart2021@gmail.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
authored by
James Smart
and committed by
Martin K. Petersen
edba59f3
4ee8c40b
+339
+9
MAINTAINERS
+9
MAINTAINERS
···
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W: http://www.broadcom.com
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F: drivers/scsi/lpfc/
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EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER
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M: James Smart <james.smart@broadcom.com>
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M: Ram Vegesna <ram.vegesna@broadcom.com>
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L: linux-scsi@vger.kernel.org
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L: target-devel@vger.kernel.org
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S: Supported
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W: http://www.broadcom.com
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F: drivers/scsi/elx/
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ENE CB710 FLASH CARD READER DRIVER
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M: Michał Mirosław <mirq-linux@rere.qmqm.pl>
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S: Maintained
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drivers/scsi/elx/libefc_sli/sli4.c
+22
drivers/scsi/elx/libefc_sli/sli4.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Broadcom. All Rights Reserved. The term
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* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
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*/
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/**
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* All common (i.e. transport-independent) SLI-4 functions are implemented
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* in this file.
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*/
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#include "sli4.h"
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static struct sli4_asic_entry_t sli4_asic_table[] = {
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{ SLI4_ASIC_REV_B0, SLI4_ASIC_GEN_5},
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{ SLI4_ASIC_REV_D0, SLI4_ASIC_GEN_5},
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{ SLI4_ASIC_REV_A3, SLI4_ASIC_GEN_6},
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{ SLI4_ASIC_REV_A0, SLI4_ASIC_GEN_6},
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{ SLI4_ASIC_REV_A1, SLI4_ASIC_GEN_6},
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{ SLI4_ASIC_REV_A3, SLI4_ASIC_GEN_6},
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{ SLI4_ASIC_REV_A1, SLI4_ASIC_GEN_7},
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{ SLI4_ASIC_REV_A0, SLI4_ASIC_GEN_7},
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};
+308
drivers/scsi/elx/libefc_sli/sli4.h
+308
drivers/scsi/elx/libefc_sli/sli4.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 Broadcom. All Rights Reserved. The term
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* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
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*
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*/
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/*
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* All common SLI-4 structures and function prototypes.
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*/
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#ifndef _SLI4_H
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#define _SLI4_H
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "scsi/fc/fc_els.h"
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#include "scsi/fc/fc_fs.h"
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#include "../include/efc_common.h"
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/*************************************************************************
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* Common SLI-4 register offsets and field definitions
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*/
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/* SLI_INTF - SLI Interface Definition Register */
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#define SLI4_INTF_REG 0x0058
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enum sli4_intf {
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SLI4_INTF_REV_SHIFT = 4,
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SLI4_INTF_REV_MASK = 0xf0,
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SLI4_INTF_REV_S3 = 0x30,
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SLI4_INTF_REV_S4 = 0x40,
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+
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SLI4_INTF_FAMILY_SHIFT = 8,
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SLI4_INTF_FAMILY_MASK = 0x0f00,
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+
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SLI4_FAMILY_CHECK_ASIC_TYPE = 0x0f00,
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+
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SLI4_INTF_IF_TYPE_SHIFT = 12,
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SLI4_INTF_IF_TYPE_MASK = 0xf000,
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+
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SLI4_INTF_IF_TYPE_2 = 0x2000,
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SLI4_INTF_IF_TYPE_6 = 0x6000,
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+
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SLI4_INTF_VALID_SHIFT = 29,
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SLI4_INTF_VALID_MASK = 0xe0000000,
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+
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SLI4_INTF_VALID_VALUE = 0xc0000000,
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};
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+
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/* ASIC_ID - SLI ASIC Type and Revision Register */
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#define SLI4_ASIC_ID_REG 0x009c
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enum sli4_asic {
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SLI4_ASIC_GEN_SHIFT = 8,
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SLI4_ASIC_GEN_MASK = 0xff00,
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SLI4_ASIC_GEN_5 = 0x0b00,
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SLI4_ASIC_GEN_6 = 0x0c00,
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SLI4_ASIC_GEN_7 = 0x0d00,
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};
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+
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enum sli4_acic_revisions {
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SLI4_ASIC_REV_A0 = 0x00,
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SLI4_ASIC_REV_A1 = 0x01,
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SLI4_ASIC_REV_A2 = 0x02,
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SLI4_ASIC_REV_A3 = 0x03,
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SLI4_ASIC_REV_B0 = 0x10,
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SLI4_ASIC_REV_B1 = 0x11,
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SLI4_ASIC_REV_B2 = 0x12,
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SLI4_ASIC_REV_C0 = 0x20,
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SLI4_ASIC_REV_C1 = 0x21,
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SLI4_ASIC_REV_C2 = 0x22,
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SLI4_ASIC_REV_D0 = 0x30,
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};
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struct sli4_asic_entry_t {
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u32 rev_id;
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u32 family;
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};
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/* BMBX - Bootstrap Mailbox Register */
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#define SLI4_BMBX_REG 0x0160
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enum sli4_bmbx {
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SLI4_BMBX_MASK_HI = 0x3,
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SLI4_BMBX_MASK_LO = 0xf,
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SLI4_BMBX_RDY = 1 << 0,
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SLI4_BMBX_HI = 1 << 1,
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SLI4_BMBX_SIZE = 256,
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};
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static inline u32
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sli_bmbx_write_hi(u64 addr) {
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u32 val;
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val = upper_32_bits(addr) & ~SLI4_BMBX_MASK_HI;
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val |= SLI4_BMBX_HI;
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return val;
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}
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static inline u32
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sli_bmbx_write_lo(u64 addr) {
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u32 val;
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val = (upper_32_bits(addr) & SLI4_BMBX_MASK_HI) << 30;
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val |= ((addr) & ~SLI4_BMBX_MASK_LO) >> 2;
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return val;
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}
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/* SLIPORT_CONTROL - SLI Port Control Register */
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#define SLI4_PORT_CTRL_REG 0x0408
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enum sli4_port_ctrl {
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SLI4_PORT_CTRL_IP = 1u << 27,
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SLI4_PORT_CTRL_IDIS = 1u << 22,
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SLI4_PORT_CTRL_FDD = 1u << 31,
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};
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/* SLI4_SLIPORT_ERROR - SLI Port Error Register */
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#define SLI4_PORT_ERROR1 0x040c
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#define SLI4_PORT_ERROR2 0x0410
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/* EQCQ_DOORBELL - EQ and CQ Doorbell Register */
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#define SLI4_EQCQ_DB_REG 0x120
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enum sli4_eqcq_e {
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SLI4_EQ_ID_LO_MASK = 0x01ff,
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SLI4_CQ_ID_LO_MASK = 0x03ff,
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SLI4_EQCQ_CI_EQ = 0x0200,
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SLI4_EQCQ_QT_EQ = 0x00000400,
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SLI4_EQCQ_QT_CQ = 0x00000000,
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SLI4_EQCQ_ID_HI_SHIFT = 11,
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SLI4_EQCQ_ID_HI_MASK = 0xf800,
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SLI4_EQCQ_NUM_SHIFT = 16,
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SLI4_EQCQ_NUM_MASK = 0x1fff0000,
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SLI4_EQCQ_ARM = 0x20000000,
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SLI4_EQCQ_UNARM = 0x00000000,
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};
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static inline u32
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sli_format_eq_db_data(u16 num_popped, u16 id, u32 arm) {
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u32 reg;
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+
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reg = (id & SLI4_EQ_ID_LO_MASK) | SLI4_EQCQ_QT_EQ;
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reg |= (((id) >> 9) << SLI4_EQCQ_ID_HI_SHIFT) & SLI4_EQCQ_ID_HI_MASK;
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reg |= ((num_popped) << SLI4_EQCQ_NUM_SHIFT) & SLI4_EQCQ_NUM_MASK;
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reg |= arm | SLI4_EQCQ_CI_EQ;
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return reg;
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}
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static inline u32
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sli_format_cq_db_data(u16 num_popped, u16 id, u32 arm) {
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u32 reg;
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reg = ((id) & SLI4_CQ_ID_LO_MASK) | SLI4_EQCQ_QT_CQ;
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reg |= (((id) >> 10) << SLI4_EQCQ_ID_HI_SHIFT) & SLI4_EQCQ_ID_HI_MASK;
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reg |= ((num_popped) << SLI4_EQCQ_NUM_SHIFT) & SLI4_EQCQ_NUM_MASK;
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reg |= arm;
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return reg;
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}
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/* EQ_DOORBELL - EQ Doorbell Register for IF_TYPE = 6*/
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#define SLI4_IF6_EQ_DB_REG 0x120
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enum sli4_eq_e {
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SLI4_IF6_EQ_ID_MASK = 0x0fff,
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SLI4_IF6_EQ_NUM_SHIFT = 16,
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SLI4_IF6_EQ_NUM_MASK = 0x1fff0000,
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};
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static inline u32
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sli_format_if6_eq_db_data(u16 num_popped, u16 id, u32 arm) {
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u32 reg;
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reg = id & SLI4_IF6_EQ_ID_MASK;
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reg |= (num_popped << SLI4_IF6_EQ_NUM_SHIFT) & SLI4_IF6_EQ_NUM_MASK;
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reg |= arm;
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return reg;
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}
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+
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/* CQ_DOORBELL - CQ Doorbell Register for IF_TYPE = 6 */
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#define SLI4_IF6_CQ_DB_REG 0xc0
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enum sli4_cq_e {
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SLI4_IF6_CQ_ID_MASK = 0xffff,
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+
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SLI4_IF6_CQ_NUM_SHIFT = 16,
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SLI4_IF6_CQ_NUM_MASK = 0x1fff0000,
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};
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static inline u32
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sli_format_if6_cq_db_data(u16 num_popped, u16 id, u32 arm) {
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u32 reg;
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reg = id & SLI4_IF6_CQ_ID_MASK;
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reg |= ((num_popped) << SLI4_IF6_CQ_NUM_SHIFT) & SLI4_IF6_CQ_NUM_MASK;
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reg |= arm;
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return reg;
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}
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+
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/* MQ_DOORBELL - MQ Doorbell Register */
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#define SLI4_MQ_DB_REG 0x0140
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#define SLI4_IF6_MQ_DB_REG 0x0160
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enum sli4_mq_e {
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SLI4_MQ_ID_MASK = 0xffff,
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+
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SLI4_MQ_NUM_SHIFT = 16,
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SLI4_MQ_NUM_MASK = 0x3fff0000,
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};
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static inline u32
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sli_format_mq_db_data(u16 id) {
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u32 reg;
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reg = id & SLI4_MQ_ID_MASK;
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reg |= (1 << SLI4_MQ_NUM_SHIFT) & SLI4_MQ_NUM_MASK;
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return reg;
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}
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+
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/* RQ_DOORBELL - RQ Doorbell Register */
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#define SLI4_RQ_DB_REG 0x0a0
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#define SLI4_IF6_RQ_DB_REG 0x0080
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enum sli4_rq_e {
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SLI4_RQ_DB_ID_MASK = 0xffff,
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+
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SLI4_RQ_DB_NUM_SHIFT = 16,
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SLI4_RQ_DB_NUM_MASK = 0x3fff0000,
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};
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static inline u32
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sli_format_rq_db_data(u16 id) {
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u32 reg;
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reg = id & SLI4_RQ_DB_ID_MASK;
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reg |= (1 << SLI4_RQ_DB_NUM_SHIFT) & SLI4_RQ_DB_NUM_MASK;
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+
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return reg;
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}
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+
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/* WQ_DOORBELL - WQ Doorbell Register */
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#define SLI4_IO_WQ_DB_REG 0x040
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#define SLI4_IF6_WQ_DB_REG 0x040
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enum sli4_wq_e {
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SLI4_WQ_ID_MASK = 0xffff,
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+
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SLI4_WQ_IDX_SHIFT = 16,
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SLI4_WQ_IDX_MASK = 0xff0000,
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+
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SLI4_WQ_NUM_SHIFT = 24,
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SLI4_WQ_NUM_MASK = 0x0ff00000,
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};
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static inline u32
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sli_format_wq_db_data(u16 id) {
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u32 reg;
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+
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reg = id & SLI4_WQ_ID_MASK;
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reg |= (1 << SLI4_WQ_NUM_SHIFT) & SLI4_WQ_NUM_MASK;
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+
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return reg;
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+
}
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+
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+
/* SLIPORT_STATUS - SLI Port Status Register */
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+
#define SLI4_PORT_STATUS_REGOFF 0x0404
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+
enum sli4_port_status {
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+
SLI4_PORT_STATUS_FDP = 1u << 21,
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+
SLI4_PORT_STATUS_RDY = 1u << 23,
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+
SLI4_PORT_STATUS_RN = 1u << 24,
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+
SLI4_PORT_STATUS_DIP = 1u << 25,
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+
SLI4_PORT_STATUS_OTI = 1u << 29,
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SLI4_PORT_STATUS_ERR = 1u << 31,
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+
};
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+
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#define SLI4_PHYDEV_CTRL_REG 0x0414
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#define SLI4_PHYDEV_CTRL_FRST (1 << 1)
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#define SLI4_PHYDEV_CTRL_DD (1 << 2)
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+
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+
/* Register name enums */
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+
enum sli4_regname_en {
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SLI4_REG_BMBX,
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+
SLI4_REG_EQ_DOORBELL,
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SLI4_REG_CQ_DOORBELL,
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SLI4_REG_RQ_DOORBELL,
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+
SLI4_REG_IO_WQ_DOORBELL,
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+
SLI4_REG_MQ_DOORBELL,
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+
SLI4_REG_PHYSDEV_CONTROL,
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+
SLI4_REG_PORT_CONTROL,
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+
SLI4_REG_PORT_ERROR1,
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+
SLI4_REG_PORT_ERROR2,
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+
SLI4_REG_PORT_SEMAPHORE,
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+
SLI4_REG_PORT_STATUS,
300
+
SLI4_REG_UNKWOWN /* must be last */
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+
};
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+
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struct sli4_reg {
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u32 rset;
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u32 off;
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+
};
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+
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#endif /* !_SLI4_H */