Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"I'm mostly on vacation but what would vacation be without a few
critical fixes so people can use their gaming laptops when hiding away
from the sun (or rain)?
- Fix a really annoying interrupt storm in the AMD driver affecting
Asus TUF gaming notebooks
- Fix device tree parsing in the Renesas driver"
* tag 'pinctrl-v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: amd: Unify debounce handling into amd_pinconf_set()
pinctrl: amd: Drop pull up select configuration
pinctrl: amd: Use amd_pinconf_set() for all config options
pinctrl: amd: Only use special debounce behavior for GPIO 0
pinctrl: renesas: rzg2l: Handle non-unique subnode names
pinctrl: renesas: rzv2m: Handle non-unique subnode names
+63
-55
+23
-38
drivers/pinctrl/pinctrl-amd.c
+23
-38
drivers/pinctrl/pinctrl-amd.c
···
116
116
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
117
117
}
118
118
119
-
static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
120
-
unsigned debounce)
119
+
static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
120
+
unsigned int debounce)
121
121
{
122
122
u32 time;
123
123
u32 pin_reg;
124
124
int ret = 0;
125
-
unsigned long flags;
126
-
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
127
-
128
-
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
129
125
130
126
/* Use special handling for Pin0 debounce */
131
-
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
132
-
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
133
-
debounce = 0;
127
+
if (offset == 0) {
128
+
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
129
+
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
130
+
debounce = 0;
131
+
}
134
132
135
133
pin_reg = readl(gpio_dev->base + offset * 4);
136
134
···
180
182
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
181
183
}
182
184
writel(pin_reg, gpio_dev->base + offset * 4);
183
-
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
184
185
185
186
return ret;
186
-
}
187
-
188
-
static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
189
-
unsigned long config)
190
-
{
191
-
u32 debounce;
192
-
193
-
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
194
-
return -ENOTSUPP;
195
-
196
-
debounce = pinconf_to_config_argument(config);
197
-
return amd_gpio_set_debounce(gc, offset, debounce);
198
187
}
199
188
200
189
#ifdef CONFIG_DEBUG_FS
···
205
220
char *pin_sts;
206
221
char *interrupt_sts;
207
222
char *wake_sts;
208
-
char *pull_up_sel;
209
223
char *orientation;
210
224
char debounce_value[40];
211
225
char *debounce_enable;
···
312
328
seq_printf(s, " %s|", wake_sts);
313
329
314
330
if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
315
-
if (pin_reg & BIT(PULL_UP_SEL_OFF))
316
-
pull_up_sel = "8k";
317
-
else
318
-
pull_up_sel = "4k";
319
-
seq_printf(s, "%s ↑|",
320
-
pull_up_sel);
331
+
seq_puts(s, " ↑ |");
321
332
} else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
322
-
seq_puts(s, " ↓|");
333
+
seq_puts(s, " ↓ |");
323
334
} else {
324
335
seq_puts(s, " |");
325
336
}
···
740
761
break;
741
762
742
763
case PIN_CONFIG_BIAS_PULL_UP:
743
-
arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
764
+
arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
744
765
break;
745
766
746
767
case PIN_CONFIG_DRIVE_STRENGTH:
···
759
780
}
760
781
761
782
static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
762
-
unsigned long *configs, unsigned num_configs)
783
+
unsigned long *configs, unsigned int num_configs)
763
784
{
764
785
int i;
765
786
u32 arg;
···
777
798
778
799
switch (param) {
779
800
case PIN_CONFIG_INPUT_DEBOUNCE:
780
-
pin_reg &= ~DB_TMR_OUT_MASK;
781
-
pin_reg |= arg & DB_TMR_OUT_MASK;
782
-
break;
801
+
ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
802
+
goto out_unlock;
783
803
784
804
case PIN_CONFIG_BIAS_PULL_DOWN:
785
805
pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
···
786
808
break;
787
809
788
810
case PIN_CONFIG_BIAS_PULL_UP:
789
-
pin_reg &= ~BIT(PULL_UP_SEL_OFF);
790
-
pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
791
811
pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
792
-
pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
812
+
pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
793
813
break;
794
814
795
815
case PIN_CONFIG_DRIVE_STRENGTH:
···
805
829
806
830
writel(pin_reg, gpio_dev->base + pin*4);
807
831
}
832
+
out_unlock:
808
833
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
809
834
810
835
return ret;
···
845
868
return -ENOTSUPP;
846
869
}
847
870
return 0;
871
+
}
872
+
873
+
static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
874
+
unsigned long config)
875
+
{
876
+
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
877
+
878
+
return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
848
879
}
849
880
850
881
static const struct pinconf_ops amd_pinconf_ops = {
-1
drivers/pinctrl/pinctrl-amd.h
-1
drivers/pinctrl/pinctrl-amd.h
+20
-8
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+20
-8
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
249
249
250
250
static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
251
251
struct device_node *np,
252
+
struct device_node *parent,
252
253
struct pinctrl_map **map,
253
254
unsigned int *num_maps,
254
255
unsigned int *index)
···
267
266
struct property *prop;
268
267
int ret, gsel, fsel;
269
268
const char **pin_fn;
269
+
const char *name;
270
270
const char *pin;
271
271
272
272
pinmux = of_find_property(np, "pinmux", NULL);
···
351
349
psel_val[i] = MUX_FUNC(value);
352
350
}
353
351
352
+
if (parent) {
353
+
name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
354
+
parent, np);
355
+
if (!name) {
356
+
ret = -ENOMEM;
357
+
goto done;
358
+
}
359
+
} else {
360
+
name = np->name;
361
+
}
362
+
354
363
/* Register a single pin group listing all the pins we read from DT */
355
-
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
364
+
gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
356
365
if (gsel < 0) {
357
366
ret = gsel;
358
367
goto done;
···
373
360
* Register a single group function where the 'data' is an array PSEL
374
361
* register values read from DT.
375
362
*/
376
-
pin_fn[0] = np->name;
377
-
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
378
-
psel_val);
363
+
pin_fn[0] = name;
364
+
fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
379
365
if (fsel < 0) {
380
366
ret = fsel;
381
367
goto remove_group;
382
368
}
383
369
384
370
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
385
-
maps[idx].data.mux.group = np->name;
386
-
maps[idx].data.mux.function = np->name;
371
+
maps[idx].data.mux.group = name;
372
+
maps[idx].data.mux.function = name;
387
373
idx++;
388
374
389
375
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
···
429
417
index = 0;
430
418
431
419
for_each_child_of_node(np, child) {
432
-
ret = rzg2l_dt_subnode_to_map(pctldev, child, map,
420
+
ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
433
421
num_maps, &index);
434
422
if (ret < 0) {
435
423
of_node_put(child);
···
438
426
}
439
427
440
428
if (*num_maps == 0) {
441
-
ret = rzg2l_dt_subnode_to_map(pctldev, np, map,
429
+
ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
442
430
num_maps, &index);
443
431
if (ret < 0)
444
432
goto done;
+20
-8
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+20
-8
drivers/pinctrl/renesas/pinctrl-rzv2m.c
···
209
209
210
210
static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
211
211
struct device_node *np,
212
+
struct device_node *parent,
212
213
struct pinctrl_map **map,
213
214
unsigned int *num_maps,
214
215
unsigned int *index)
···
227
226
struct property *prop;
228
227
int ret, gsel, fsel;
229
228
const char **pin_fn;
229
+
const char *name;
230
230
const char *pin;
231
231
232
232
pinmux = of_find_property(np, "pinmux", NULL);
···
311
309
psel_val[i] = MUX_FUNC(value);
312
310
}
313
311
312
+
if (parent) {
313
+
name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
314
+
parent, np);
315
+
if (!name) {
316
+
ret = -ENOMEM;
317
+
goto done;
318
+
}
319
+
} else {
320
+
name = np->name;
321
+
}
322
+
314
323
/* Register a single pin group listing all the pins we read from DT */
315
-
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
324
+
gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
316
325
if (gsel < 0) {
317
326
ret = gsel;
318
327
goto done;
···
333
320
* Register a single group function where the 'data' is an array PSEL
334
321
* register values read from DT.
335
322
*/
336
-
pin_fn[0] = np->name;
337
-
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
338
-
psel_val);
323
+
pin_fn[0] = name;
324
+
fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
339
325
if (fsel < 0) {
340
326
ret = fsel;
341
327
goto remove_group;
342
328
}
343
329
344
330
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
345
-
maps[idx].data.mux.group = np->name;
346
-
maps[idx].data.mux.function = np->name;
331
+
maps[idx].data.mux.group = name;
332
+
maps[idx].data.mux.function = name;
347
333
idx++;
348
334
349
335
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
···
389
377
index = 0;
390
378
391
379
for_each_child_of_node(np, child) {
392
-
ret = rzv2m_dt_subnode_to_map(pctldev, child, map,
380
+
ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map,
393
381
num_maps, &index);
394
382
if (ret < 0) {
395
383
of_node_put(child);
···
398
386
}
399
387
400
388
if (*num_maps == 0) {
401
-
ret = rzv2m_dt_subnode_to_map(pctldev, np, map,
389
+
ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map,
402
390
num_maps, &index);
403
391
if (ret < 0)
404
392
goto done;