Merge tag 'staging-5.7-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

+1 -1

Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 - $id: "http://devicetree.org/schemas/bindings/iio/adc/st,stm32-adc.yaml#" 4 + $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#" 5 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 6 7 7 title: STMicroelectronics STM32 ADC bindings

+7 -8

MAINTAINERS

··· 570 570 F: drivers/input/misc/adxl34x.c 571 571 572 572 ADXL372 THREE-AXIS DIGITAL ACCELEROMETER DRIVER 573 - M: Stefan Popa <stefan.popa@analog.com> 573 + M: Michael Hennerich <michael.hennerich@analog.com> 574 574 S: Supported 575 575 W: http://ez.analog.com/community/linux-device-drivers 576 576 F: Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml ··· 922 922 F: drivers/net/ethernet/amd/xgbe/ 923 923 924 924 ANALOG DEVICES INC AD5686 DRIVER 925 - M: Stefan Popa <stefan.popa@analog.com> 925 + M: Michael Hennerich <Michael.Hennerich@analog.com> 926 926 L: linux-pm@vger.kernel.org 927 927 S: Supported 928 928 W: http://ez.analog.com/community/linux-device-drivers ··· 930 930 F: drivers/iio/dac/ad5696* 931 931 932 932 ANALOG DEVICES INC AD5758 DRIVER 933 - M: Stefan Popa <stefan.popa@analog.com> 933 + M: Michael Hennerich <Michael.Hennerich@analog.com> 934 934 L: linux-iio@vger.kernel.org 935 935 S: Supported 936 936 W: http://ez.analog.com/community/linux-device-drivers ··· 946 946 F: drivers/iio/adc/ad7091r5.c 947 947 948 948 ANALOG DEVICES INC AD7124 DRIVER 949 - M: Stefan Popa <stefan.popa@analog.com> 949 + M: Michael Hennerich <Michael.Hennerich@analog.com> 950 950 L: linux-iio@vger.kernel.org 951 951 S: Supported 952 952 W: http://ez.analog.com/community/linux-device-drivers ··· 970 970 F: drivers/iio/adc/ad7292.c 971 971 972 972 ANALOG DEVICES INC AD7606 DRIVER 973 - M: Stefan Popa <stefan.popa@analog.com> 973 + M: Michael Hennerich <Michael.Hennerich@analog.com> 974 974 M: Beniamin Bia <beniamin.bia@analog.com> 975 975 L: linux-iio@vger.kernel.org 976 976 S: Supported ··· 979 979 F: drivers/iio/adc/ad7606.c 980 980 981 981 ANALOG DEVICES INC AD7768-1 DRIVER 982 - M: Stefan Popa <stefan.popa@analog.com> 982 + M: Michael Hennerich <Michael.Hennerich@analog.com> 983 983 L: linux-iio@vger.kernel.org 984 984 S: Supported 985 985 W: http://ez.analog.com/community/linux-device-drivers ··· 1040 1040 F: drivers/hwmon/adm1177.c 1041 1041 1042 1042 ANALOG DEVICES INC ADP5061 DRIVER 1043 - M: Stefan Popa <stefan.popa@analog.com> 1043 + M: Michael Hennerich <Michael.Hennerich@analog.com> 1044 1044 L: linux-pm@vger.kernel.org 1045 1045 S: Supported 1046 1046 W: http://ez.analog.com/community/linux-device-drivers ··· 1109 1109 ANALOG DEVICES INC IIO DRIVERS 1110 1110 M: Lars-Peter Clausen <lars@metafoo.de> 1111 1111 M: Michael Hennerich <Michael.Hennerich@analog.com> 1112 - M: Stefan Popa <stefan.popa@analog.com> 1113 1112 S: Supported 1114 1113 W: http://wiki.analog.com/ 1115 1114 W: http://ez.analog.com/community/linux-device-drivers

+160 -34

drivers/counter/104-quad-8.c

··· 44 44 * @base: base port address of the IIO device 45 45 */ 46 46 struct quad8_iio { 47 + struct mutex lock; 47 48 struct counter_device counter; 48 49 unsigned int fck_prescaler[QUAD8_NUM_COUNTERS]; 49 50 unsigned int preset[QUAD8_NUM_COUNTERS]; ··· 124 123 /* Borrow XOR Carry effectively doubles count range */ 125 124 *val = (borrow ^ carry) << 24; 126 125 126 + mutex_lock(&priv->lock); 127 + 127 128 /* Reset Byte Pointer; transfer Counter to Output Latch */ 128 129 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, 129 130 base_offset + 1); 130 131 131 132 for (i = 0; i < 3; i++) 132 133 *val |= (unsigned int)inb(base_offset) << (8 * i); 134 + 135 + mutex_unlock(&priv->lock); 133 136 134 137 return IIO_VAL_INT; 135 138 case IIO_CHAN_INFO_ENABLE: ··· 165 160 if ((unsigned int)val > 0xFFFFFF) 166 161 return -EINVAL; 167 162 163 + mutex_lock(&priv->lock); 164 + 168 165 /* Reset Byte Pointer */ 169 166 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 170 167 ··· 190 183 /* Reset Error flag */ 191 184 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); 192 185 186 + mutex_unlock(&priv->lock); 187 + 193 188 return 0; 194 189 case IIO_CHAN_INFO_ENABLE: 195 190 /* only boolean values accepted */ 196 191 if (val < 0 || val > 1) 197 192 return -EINVAL; 193 + 194 + mutex_lock(&priv->lock); 198 195 199 196 priv->ab_enable[chan->channel] = val; 200 197 ··· 207 196 /* Load I/O control configuration */ 208 197 outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); 209 198 199 + mutex_unlock(&priv->lock); 200 + 210 201 return 0; 211 202 case IIO_CHAN_INFO_SCALE: 203 + mutex_lock(&priv->lock); 204 + 212 205 /* Quadrature scaling only available in quadrature mode */ 213 - if (!priv->quadrature_mode[chan->channel] && (val2 || val != 1)) 206 + if (!priv->quadrature_mode[chan->channel] && 207 + (val2 || val != 1)) { 208 + mutex_unlock(&priv->lock); 214 209 return -EINVAL; 210 + } 215 211 216 212 /* Only three gain states (1, 0.5, 0.25) */ 217 213 if (val == 1 && !val2) ··· 232 214 priv->quadrature_scale[chan->channel] = 2; 233 215 break; 234 216 default: 217 + mutex_unlock(&priv->lock); 235 218 return -EINVAL; 236 219 } 237 - else 220 + else { 221 + mutex_unlock(&priv->lock); 238 222 return -EINVAL; 223 + } 239 224 225 + mutex_unlock(&priv->lock); 240 226 return 0; 241 227 } 242 228 ··· 277 255 if (preset > 0xFFFFFF) 278 256 return -EINVAL; 279 257 258 + mutex_lock(&priv->lock); 259 + 280 260 priv->preset[chan->channel] = preset; 281 261 282 262 /* Reset Byte Pointer */ ··· 287 263 /* Set Preset Register */ 288 264 for (i = 0; i < 3; i++) 289 265 outb(preset >> (8 * i), base_offset); 266 + 267 + mutex_unlock(&priv->lock); 290 268 291 269 return len; 292 270 } ··· 319 293 /* Preset enable is active low in Input/Output Control register */ 320 294 preset_enable = !preset_enable; 321 295 296 + mutex_lock(&priv->lock); 297 + 322 298 priv->preset_enable[chan->channel] = preset_enable; 323 299 324 300 ior_cfg = priv->ab_enable[chan->channel] | ··· 328 300 329 301 /* Load I/O control configuration to Input / Output Control Register */ 330 302 outb(QUAD8_CTR_IOR | ior_cfg, base_offset); 303 + 304 + mutex_unlock(&priv->lock); 331 305 332 306 return len; 333 307 } ··· 388 358 unsigned int mode_cfg = cnt_mode << 1; 389 359 const int base_offset = priv->base + 2 * chan->channel + 1; 390 360 361 + mutex_lock(&priv->lock); 362 + 391 363 priv->count_mode[chan->channel] = cnt_mode; 392 364 393 365 /* Add quadrature mode configuration */ ··· 398 366 399 367 /* Load mode configuration to Counter Mode Register */ 400 368 outb(QUAD8_CTR_CMR | mode_cfg, base_offset); 369 + 370 + mutex_unlock(&priv->lock); 401 371 402 372 return 0; 403 373 } ··· 428 394 const struct iio_chan_spec *chan, unsigned int synchronous_mode) 429 395 { 430 396 struct quad8_iio *const priv = iio_priv(indio_dev); 431 - const unsigned int idr_cfg = synchronous_mode | 432 - priv->index_polarity[chan->channel] << 1; 433 397 const int base_offset = priv->base + 2 * chan->channel + 1; 398 + unsigned int idr_cfg = synchronous_mode; 399 + 400 + mutex_lock(&priv->lock); 401 + 402 + idr_cfg |= priv->index_polarity[chan->channel] << 1; 434 403 435 404 /* Index function must be non-synchronous in non-quadrature mode */ 436 - if (synchronous_mode && !priv->quadrature_mode[chan->channel]) 405 + if (synchronous_mode && !priv->quadrature_mode[chan->channel]) { 406 + mutex_unlock(&priv->lock); 437 407 return -EINVAL; 408 + } 438 409 439 410 priv->synchronous_mode[chan->channel] = synchronous_mode; 440 411 441 412 /* Load Index Control configuration to Index Control Register */ 442 413 outb(QUAD8_CTR_IDR | idr_cfg, base_offset); 414 + 415 + mutex_unlock(&priv->lock); 443 416 444 417 return 0; 445 418 } ··· 475 434 const struct iio_chan_spec *chan, unsigned int quadrature_mode) 476 435 { 477 436 struct quad8_iio *const priv = iio_priv(indio_dev); 478 - unsigned int mode_cfg = priv->count_mode[chan->channel] << 1; 479 437 const int base_offset = priv->base + 2 * chan->channel + 1; 438 + unsigned int mode_cfg; 439 + 440 + mutex_lock(&priv->lock); 441 + 442 + mode_cfg = priv->count_mode[chan->channel] << 1; 480 443 481 444 if (quadrature_mode) 482 445 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3; ··· 497 452 498 453 /* Load mode configuration to Counter Mode Register */ 499 454 outb(QUAD8_CTR_CMR | mode_cfg, base_offset); 455 + 456 + mutex_unlock(&priv->lock); 500 457 501 458 return 0; 502 459 } ··· 527 480 const struct iio_chan_spec *chan, unsigned int index_polarity) 528 481 { 529 482 struct quad8_iio *const priv = iio_priv(indio_dev); 530 - const unsigned int idr_cfg = priv->synchronous_mode[chan->channel] | 531 - index_polarity << 1; 532 483 const int base_offset = priv->base + 2 * chan->channel + 1; 484 + unsigned int idr_cfg = index_polarity << 1; 485 + 486 + mutex_lock(&priv->lock); 487 + 488 + idr_cfg |= priv->synchronous_mode[chan->channel]; 533 489 534 490 priv->index_polarity[chan->channel] = index_polarity; 535 491 536 492 /* Load Index Control configuration to Index Control Register */ 537 493 outb(QUAD8_CTR_IDR | idr_cfg, base_offset); 494 + 495 + mutex_unlock(&priv->lock); 538 496 539 497 return 0; 540 498 } ··· 641 589 static int quad8_count_read(struct counter_device *counter, 642 590 struct counter_count *count, unsigned long *val) 643 591 { 644 - const struct quad8_iio *const priv = counter->priv; 592 + struct quad8_iio *const priv = counter->priv; 645 593 const int base_offset = priv->base + 2 * count->id; 646 594 unsigned int flags; 647 595 unsigned int borrow; ··· 655 603 /* Borrow XOR Carry effectively doubles count range */ 656 604 *val = (unsigned long)(borrow ^ carry) << 24; 657 605 606 + mutex_lock(&priv->lock); 607 + 658 608 /* Reset Byte Pointer; transfer Counter to Output Latch */ 659 609 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, 660 610 base_offset + 1); ··· 664 610 for (i = 0; i < 3; i++) 665 611 *val |= (unsigned long)inb(base_offset) << (8 * i); 666 612 613 + mutex_unlock(&priv->lock); 614 + 667 615 return 0; 668 616 } 669 617 670 618 static int quad8_count_write(struct counter_device *counter, 671 619 struct counter_count *count, unsigned long val) 672 620 { 673 - const struct quad8_iio *const priv = counter->priv; 621 + struct quad8_iio *const priv = counter->priv; 674 622 const int base_offset = priv->base + 2 * count->id; 675 623 int i; 676 624 677 625 /* Only 24-bit values are supported */ 678 626 if (val > 0xFFFFFF) 679 627 return -EINVAL; 628 + 629 + mutex_lock(&priv->lock); 680 630 681 631 /* Reset Byte Pointer */ 682 632 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); ··· 705 647 /* Reset Error flag */ 706 648 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); 707 649 650 + mutex_unlock(&priv->lock); 651 + 708 652 return 0; 709 653 } 710 654 ··· 727 667 static int quad8_function_get(struct counter_device *counter, 728 668 struct counter_count *count, size_t *function) 729 669 { 730 - const struct quad8_iio *const priv = counter->priv; 670 + struct quad8_iio *const priv = counter->priv; 731 671 const int id = count->id; 732 - const unsigned int quadrature_mode = priv->quadrature_mode[id]; 733 - const unsigned int scale = priv->quadrature_scale[id]; 734 672 735 - if (quadrature_mode) 736 - switch (scale) { 673 + mutex_lock(&priv->lock); 674 + 675 + if (priv->quadrature_mode[id]) 676 + switch (priv->quadrature_scale[id]) { 737 677 case 0: 738 678 *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X1; 739 679 break; ··· 747 687 else 748 688 *function = QUAD8_COUNT_FUNCTION_PULSE_DIRECTION; 749 689 690 + mutex_unlock(&priv->lock); 691 + 750 692 return 0; 751 693 } 752 694 ··· 759 697 const int id = count->id; 760 698 unsigned int *const quadrature_mode = priv->quadrature_mode + id; 761 699 unsigned int *const scale = priv->quadrature_scale + id; 762 - unsigned int mode_cfg = priv->count_mode[id] << 1; 763 700 unsigned int *const synchronous_mode = priv->synchronous_mode + id; 764 - const unsigned int idr_cfg = priv->index_polarity[id] << 1; 765 701 const int base_offset = priv->base + 2 * id + 1; 702 + unsigned int mode_cfg; 703 + unsigned int idr_cfg; 704 + 705 + mutex_lock(&priv->lock); 706 + 707 + mode_cfg = priv->count_mode[id] << 1; 708 + idr_cfg = priv->index_polarity[id] << 1; 766 709 767 710 if (function == QUAD8_COUNT_FUNCTION_PULSE_DIRECTION) { 768 711 *quadrature_mode = 0; ··· 802 735 803 736 /* Load mode configuration to Counter Mode Register */ 804 737 outb(QUAD8_CTR_CMR | mode_cfg, base_offset); 738 + 739 + mutex_unlock(&priv->lock); 805 740 806 741 return 0; 807 742 } ··· 921 852 { 922 853 struct quad8_iio *const priv = counter->priv; 923 854 const size_t channel_id = signal->id - 16; 924 - const unsigned int idr_cfg = priv->synchronous_mode[channel_id] | 925 - index_polarity << 1; 926 855 const int base_offset = priv->base + 2 * channel_id + 1; 856 + unsigned int idr_cfg = index_polarity << 1; 857 + 858 + mutex_lock(&priv->lock); 859 + 860 + idr_cfg |= priv->synchronous_mode[channel_id]; 927 861 928 862 priv->index_polarity[channel_id] = index_polarity; 929 863 930 864 /* Load Index Control configuration to Index Control Register */ 931 865 outb(QUAD8_CTR_IDR | idr_cfg, base_offset); 866 + 867 + mutex_unlock(&priv->lock); 932 868 933 869 return 0; 934 870 } ··· 961 887 { 962 888 struct quad8_iio *const priv = counter->priv; 963 889 const size_t channel_id = signal->id - 16; 964 - const unsigned int idr_cfg = synchronous_mode | 965 - priv->index_polarity[channel_id] << 1; 966 890 const int base_offset = priv->base + 2 * channel_id + 1; 891 + unsigned int idr_cfg = synchronous_mode; 892 + 893 + mutex_lock(&priv->lock); 894 + 895 + idr_cfg |= priv->index_polarity[channel_id] << 1; 967 896 968 897 /* Index function must be non-synchronous in non-quadrature mode */ 969 - if (synchronous_mode && !priv->quadrature_mode[channel_id]) 898 + if (synchronous_mode && !priv->quadrature_mode[channel_id]) { 899 + mutex_unlock(&priv->lock); 970 900 return -EINVAL; 901 + } 971 902 972 903 priv->synchronous_mode[channel_id] = synchronous_mode; 973 904 974 905 /* Load Index Control configuration to Index Control Register */ 975 906 outb(QUAD8_CTR_IDR | idr_cfg, base_offset); 907 + 908 + mutex_unlock(&priv->lock); 976 909 977 910 return 0; 978 911 } ··· 1045 964 break; 1046 965 } 1047 966 967 + mutex_lock(&priv->lock); 968 + 1048 969 priv->count_mode[count->id] = cnt_mode; 1049 970 1050 971 /* Set count mode configuration value */ ··· 1058 975 1059 976 /* Load mode configuration to Counter Mode Register */ 1060 977 outb(QUAD8_CTR_CMR | mode_cfg, base_offset); 978 + 979 + mutex_unlock(&priv->lock); 1061 980 1062 981 return 0; 1063 982 } ··· 1102 1017 if (err) 1103 1018 return err; 1104 1019 1020 + mutex_lock(&priv->lock); 1021 + 1105 1022 priv->ab_enable[count->id] = ab_enable; 1106 1023 1107 1024 ior_cfg = ab_enable | priv->preset_enable[count->id] << 1; 1108 1025 1109 1026 /* Load I/O control configuration */ 1110 1027 outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); 1028 + 1029 + mutex_unlock(&priv->lock); 1111 1030 1112 1031 return len; 1113 1032 } ··· 1141 1052 return sprintf(buf, "%u\n", priv->preset[count->id]); 1142 1053 } 1143 1054 1055 + static void quad8_preset_register_set(struct quad8_iio *quad8iio, int id, 1056 + unsigned int preset) 1057 + { 1058 + const unsigned int base_offset = quad8iio->base + 2 * id; 1059 + int i; 1060 + 1061 + quad8iio->preset[id] = preset; 1062 + 1063 + /* Reset Byte Pointer */ 1064 + outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 1065 + 1066 + /* Set Preset Register */ 1067 + for (i = 0; i < 3; i++) 1068 + outb(preset >> (8 * i), base_offset); 1069 + } 1070 + 1144 1071 static ssize_t quad8_count_preset_write(struct counter_device *counter, 1145 1072 struct counter_count *count, void *private, const char *buf, size_t len) 1146 1073 { 1147 1074 struct quad8_iio *const priv = counter->priv; 1148 - const int base_offset = priv->base + 2 * count->id; 1149 1075 unsigned int preset; 1150 1076 int ret; 1151 - int i; 1152 1077 1153 1078 ret = kstrtouint(buf, 0, &preset); 1154 1079 if (ret) ··· 1172 1069 if (preset > 0xFFFFFF) 1173 1070 return -EINVAL; 1174 1071 1175 - priv->preset[count->id] = preset; 1072 + mutex_lock(&priv->lock); 1176 1073 1177 - /* Reset Byte Pointer */ 1178 - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 1074 + quad8_preset_register_set(priv, count->id, preset); 1179 1075 1180 - /* Set Preset Register */ 1181 - for (i = 0; i < 3; i++) 1182 - outb(preset >> (8 * i), base_offset); 1076 + mutex_unlock(&priv->lock); 1183 1077 1184 1078 return len; 1185 1079 } ··· 1184 1084 static ssize_t quad8_count_ceiling_read(struct counter_device *counter, 1185 1085 struct counter_count *count, void *private, char *buf) 1186 1086 { 1187 - const struct quad8_iio *const priv = counter->priv; 1087 + struct quad8_iio *const priv = counter->priv; 1088 + 1089 + mutex_lock(&priv->lock); 1188 1090 1189 1091 /* Range Limit and Modulo-N count modes use preset value as ceiling */ 1190 1092 switch (priv->count_mode[count->id]) { 1191 1093 case 1: 1192 1094 case 3: 1193 - return quad8_count_preset_read(counter, count, private, buf); 1095 + mutex_unlock(&priv->lock); 1096 + return sprintf(buf, "%u\n", priv->preset[count->id]); 1194 1097 } 1098 + 1099 + mutex_unlock(&priv->lock); 1195 1100 1196 1101 /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */ 1197 1102 return sprintf(buf, "33554431\n"); ··· 1206 1101 struct counter_count *count, void *private, const char *buf, size_t len) 1207 1102 { 1208 1103 struct quad8_iio *const priv = counter->priv; 1104 + unsigned int ceiling; 1105 + int ret; 1106 + 1107 + ret = kstrtouint(buf, 0, &ceiling); 1108 + if (ret) 1109 + return ret; 1110 + 1111 + /* Only 24-bit values are supported */ 1112 + if (ceiling > 0xFFFFFF) 1113 + return -EINVAL; 1114 + 1115 + mutex_lock(&priv->lock); 1209 1116 1210 1117 /* Range Limit and Modulo-N count modes use preset value as ceiling */ 1211 1118 switch (priv->count_mode[count->id]) { 1212 1119 case 1: 1213 1120 case 3: 1214 - return quad8_count_preset_write(counter, count, private, buf, 1215 - len); 1121 + quad8_preset_register_set(priv, count->id, ceiling); 1122 + break; 1216 1123 } 1124 + 1125 + mutex_unlock(&priv->lock); 1217 1126 1218 1127 return len; 1219 1128 } ··· 1256 1137 /* Preset enable is active low in Input/Output Control register */ 1257 1138 preset_enable = !preset_enable; 1258 1139 1140 + mutex_lock(&priv->lock); 1141 + 1259 1142 priv->preset_enable[count->id] = preset_enable; 1260 1143 1261 1144 ior_cfg = priv->ab_enable[count->id] | (unsigned int)preset_enable << 1; 1262 1145 1263 1146 /* Load I/O control configuration to Input / Output Control Register */ 1264 1147 outb(QUAD8_CTR_IOR | ior_cfg, base_offset); 1148 + 1149 + mutex_unlock(&priv->lock); 1265 1150 1266 1151 return len; 1267 1152 } ··· 1551 1428 quad8iio->counter.num_signals = ARRAY_SIZE(quad8_signals); 1552 1429 quad8iio->counter.priv = quad8iio; 1553 1430 quad8iio->base = base[id]; 1431 + 1432 + /* Initialize mutex */ 1433 + mutex_init(&quad8iio->lock); 1554 1434 1555 1435 /* Reset all counters and disable interrupt function */ 1556 1436 outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);

+47 -16

drivers/iio/adc/ad7192.c

··· 125 125 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 126 126 127 127 /* ID Register Bit Designations (AD7192_REG_ID) */ 128 - #define ID_AD7190 0x4 129 - #define ID_AD7192 0x0 130 - #define ID_AD7193 0x2 131 - #define ID_AD7195 0x6 128 + #define CHIPID_AD7190 0x4 129 + #define CHIPID_AD7192 0x0 130 + #define CHIPID_AD7193 0x2 131 + #define CHIPID_AD7195 0x6 132 132 #define AD7192_ID_MASK 0x0F 133 133 134 134 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ ··· 161 161 AD7192_SYSCALIB_FULL_SCALE, 162 162 }; 163 163 164 + enum { 165 + ID_AD7190, 166 + ID_AD7192, 167 + ID_AD7193, 168 + ID_AD7195, 169 + }; 170 + 171 + struct ad7192_chip_info { 172 + unsigned int chip_id; 173 + const char *name; 174 + }; 175 + 164 176 struct ad7192_state { 177 + const struct ad7192_chip_info *chip_info; 165 178 struct regulator *avdd; 166 179 struct regulator *dvdd; 167 180 struct clk *mclk; ··· 185 172 u32 conf; 186 173 u32 scale_avail[8][2]; 187 174 u8 gpocon; 188 - u8 devid; 189 175 u8 clock_sel; 190 176 struct mutex lock; /* protect sensor state */ 191 177 u8 syscalib_mode[8]; ··· 360 348 361 349 id &= AD7192_ID_MASK; 362 350 363 - if (id != st->devid) 351 + if (id != st->chip_info->chip_id) 364 352 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", 365 353 id); 366 354 ··· 375 363 st->mode |= AD7192_MODE_REJ60; 376 364 377 365 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); 378 - if (refin2_en && st->devid != ID_AD7195) 366 + if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 379 367 st->conf |= AD7192_CONF_REFSEL; 380 368 381 369 st->conf &= ~AD7192_CONF_CHOP; ··· 871 859 IIO_CHAN_SOFT_TIMESTAMP(14), 872 860 }; 873 861 862 + static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 863 + [ID_AD7190] = { 864 + .chip_id = CHIPID_AD7190, 865 + .name = "ad7190", 866 + }, 867 + [ID_AD7192] = { 868 + .chip_id = CHIPID_AD7192, 869 + .name = "ad7192", 870 + }, 871 + [ID_AD7193] = { 872 + .chip_id = CHIPID_AD7193, 873 + .name = "ad7193", 874 + }, 875 + [ID_AD7195] = { 876 + .chip_id = CHIPID_AD7195, 877 + .name = "ad7195", 878 + }, 879 + }; 880 + 874 881 static int ad7192_channels_config(struct iio_dev *indio_dev) 875 882 { 876 883 struct ad7192_state *st = iio_priv(indio_dev); 877 884 878 - switch (st->devid) { 879 - case ID_AD7193: 885 + switch (st->chip_info->chip_id) { 886 + case CHIPID_AD7193: 880 887 indio_dev->channels = ad7193_channels; 881 888 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); 882 889 break; ··· 909 878 } 910 879 911 880 static const struct of_device_id ad7192_of_match[] = { 912 - { .compatible = "adi,ad7190", .data = (void *)ID_AD7190 }, 913 - { .compatible = "adi,ad7192", .data = (void *)ID_AD7192 }, 914 - { .compatible = "adi,ad7193", .data = (void *)ID_AD7193 }, 915 - { .compatible = "adi,ad7195", .data = (void *)ID_AD7195 }, 881 + { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 882 + { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 883 + { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 884 + { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 916 885 {} 917 886 }; 918 887 MODULE_DEVICE_TABLE(of, ad7192_of_match); ··· 969 938 } 970 939 971 940 spi_set_drvdata(spi, indio_dev); 972 - st->devid = (unsigned long)of_device_get_match_data(&spi->dev); 941 + st->chip_info = of_device_get_match_data(&spi->dev); 973 942 indio_dev->dev.parent = &spi->dev; 974 - indio_dev->name = spi_get_device_id(spi)->name; 943 + indio_dev->name = st->chip_info->name; 975 944 indio_dev->modes = INDIO_DIRECT_MODE; 976 945 977 946 ret = ad7192_channels_config(indio_dev); 978 947 if (ret < 0) 979 948 goto error_disable_dvdd; 980 949 981 - if (st->devid == ID_AD7195) 950 + if (st->chip_info->chip_id == CHIPID_AD7195) 982 951 indio_dev->info = &ad7195_info; 983 952 else 984 953 indio_dev->info = &ad7192_info;

+1 -1

drivers/iio/adc/ad7793.c

··· 542 542 .read_raw = &ad7793_read_raw, 543 543 .write_raw = &ad7793_write_raw, 544 544 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 545 - .attrs = &ad7793_attribute_group, 545 + .attrs = &ad7797_attribute_group, 546 546 .validate_trigger = ad_sd_validate_trigger, 547 547 }; 548 548

+28 -3

drivers/iio/adc/stm32-adc.c

··· 1418 1418 static void stm32_adc_dma_buffer_done(void *data) 1419 1419 { 1420 1420 struct iio_dev *indio_dev = data; 1421 + struct stm32_adc *adc = iio_priv(indio_dev); 1422 + int residue = stm32_adc_dma_residue(adc); 1421 1423 1422 - iio_trigger_poll_chained(indio_dev->trig); 1424 + /* 1425 + * In DMA mode the trigger services of IIO are not used 1426 + * (e.g. no call to iio_trigger_poll). 1427 + * Calling irq handler associated to the hardware trigger is not 1428 + * relevant as the conversions have already been done. Data 1429 + * transfers are performed directly in DMA callback instead. 1430 + * This implementation avoids to call trigger irq handler that 1431 + * may sleep, in an atomic context (DMA irq handler context). 1432 + */ 1433 + dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1434 + 1435 + while (residue >= indio_dev->scan_bytes) { 1436 + u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1437 + 1438 + iio_push_to_buffers(indio_dev, buffer); 1439 + 1440 + residue -= indio_dev->scan_bytes; 1441 + adc->bufi += indio_dev->scan_bytes; 1442 + if (adc->bufi >= adc->rx_buf_sz) 1443 + adc->bufi = 0; 1444 + } 1423 1445 } 1424 1446 1425 1447 static int stm32_adc_dma_start(struct iio_dev *indio_dev) ··· 1867 1845 { 1868 1846 struct iio_dev *indio_dev; 1869 1847 struct device *dev = &pdev->dev; 1848 + irqreturn_t (*handler)(int irq, void *p) = NULL; 1870 1849 struct stm32_adc *adc; 1871 1850 int ret; 1872 1851 ··· 1934 1911 if (ret < 0) 1935 1912 return ret; 1936 1913 1914 + if (!adc->dma_chan) 1915 + handler = &stm32_adc_trigger_handler; 1916 + 1937 1917 ret = iio_triggered_buffer_setup(indio_dev, 1938 - &iio_pollfunc_store_time, 1939 - &stm32_adc_trigger_handler, 1918 + &iio_pollfunc_store_time, handler, 1940 1919 &stm32_adc_buffer_setup_ops); 1941 1920 if (ret) { 1942 1921 dev_err(&pdev->dev, "buffer setup failed\n");

+3 -3

drivers/iio/adc/ti-ads8344.c

··· 29 29 struct mutex lock; 30 30 31 31 u8 tx_buf ____cacheline_aligned; 32 - u16 rx_buf; 32 + u8 rx_buf[3]; 33 33 }; 34 34 35 35 #define ADS8344_VOLTAGE_CHANNEL(chan, si) \ ··· 89 89 90 90 udelay(9); 91 91 92 - ret = spi_read(spi, &adc->rx_buf, 2); 92 + ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf)); 93 93 if (ret) 94 94 return ret; 95 95 96 - return adc->rx_buf; 96 + return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7; 97 97 } 98 98 99 99 static int ads8344_read_raw(struct iio_dev *iio,

+74 -21

drivers/iio/adc/xilinx-xadc-core.c

··· 102 102 103 103 #define XADC_FLAGS_BUFFERED BIT(0) 104 104 105 + /* 106 + * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does 107 + * not have a hardware FIFO. Which means an interrupt is generated for each 108 + * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely 109 + * overloaded by the interrupts that it soft-lockups. For this reason the driver 110 + * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy, 111 + * but still responsive. 112 + */ 113 + #define XADC_MAX_SAMPLERATE 150000 114 + 105 115 static void xadc_write_reg(struct xadc *xadc, unsigned int reg, 106 116 uint32_t val) 107 117 { ··· 684 674 685 675 spin_lock_irqsave(&xadc->lock, flags); 686 676 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); 687 - xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS); 677 + xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS); 688 678 if (state) 689 679 val |= XADC_AXI_INT_EOS; 690 680 else ··· 732 722 { 733 723 uint16_t val; 734 724 725 + /* Powerdown the ADC-B when it is not needed. */ 735 726 switch (seq_mode) { 736 727 case XADC_CONF1_SEQ_SIMULTANEOUS: 737 728 case XADC_CONF1_SEQ_INDEPENDENT: 738 - val = XADC_CONF2_PD_ADC_B; 729 + val = 0; 739 730 break; 740 731 default: 741 - val = 0; 732 + val = XADC_CONF2_PD_ADC_B; 742 733 break; 743 734 } 744 735 ··· 808 797 if (ret) 809 798 goto err; 810 799 800 + /* 801 + * In simultaneous mode the upper and lower aux channels are samples at 802 + * the same time. In this mode the upper 8 bits in the sequencer 803 + * register are don't care and the lower 8 bits control two channels 804 + * each. As such we must set the bit if either the channel in the lower 805 + * group or the upper group is enabled. 806 + */ 807 + if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS) 808 + scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000; 809 + 811 810 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); 812 811 if (ret) 813 812 goto err; ··· 844 823 .postdisable = &xadc_postdisable, 845 824 }; 846 825 826 + static int xadc_read_samplerate(struct xadc *xadc) 827 + { 828 + unsigned int div; 829 + uint16_t val16; 830 + int ret; 831 + 832 + ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16); 833 + if (ret) 834 + return ret; 835 + 836 + div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; 837 + if (div < 2) 838 + div = 2; 839 + 840 + return xadc_get_dclk_rate(xadc) / div / 26; 841 + } 842 + 847 843 static int xadc_read_raw(struct iio_dev *indio_dev, 848 844 struct iio_chan_spec const *chan, int *val, int *val2, long info) 849 845 { 850 846 struct xadc *xadc = iio_priv(indio_dev); 851 - unsigned int div; 852 847 uint16_t val16; 853 848 int ret; 854 849 ··· 917 880 *val = -((273150 << 12) / 503975); 918 881 return IIO_VAL_INT; 919 882 case IIO_CHAN_INFO_SAMP_FREQ: 920 - ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16); 921 - if (ret) 883 + ret = xadc_read_samplerate(xadc); 884 + if (ret < 0) 922 885 return ret; 923 886 924 - div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; 925 - if (div < 2) 926 - div = 2; 927 - 928 - *val = xadc_get_dclk_rate(xadc) / div / 26; 929 - 887 + *val = ret; 930 888 return IIO_VAL_INT; 931 889 default: 932 890 return -EINVAL; 933 891 } 934 892 } 935 893 936 - static int xadc_write_raw(struct iio_dev *indio_dev, 937 - struct iio_chan_spec const *chan, int val, int val2, long info) 894 + static int xadc_write_samplerate(struct xadc *xadc, int val) 938 895 { 939 - struct xadc *xadc = iio_priv(indio_dev); 940 896 unsigned long clk_rate = xadc_get_dclk_rate(xadc); 941 897 unsigned int div; 942 898 943 899 if (!clk_rate) 944 900 return -EINVAL; 945 901 946 - if (info != IIO_CHAN_INFO_SAMP_FREQ) 947 - return -EINVAL; 948 - 949 902 if (val <= 0) 950 903 return -EINVAL; 951 904 952 905 /* Max. 150 kSPS */ 953 - if (val > 150000) 954 - val = 150000; 906 + if (val > XADC_MAX_SAMPLERATE) 907 + val = XADC_MAX_SAMPLERATE; 955 908 956 909 val *= 26; 957 910 ··· 954 927 * limit. 955 928 */ 956 929 div = clk_rate / val; 957 - if (clk_rate / div / 26 > 150000) 930 + if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE) 958 931 div++; 959 932 if (div < 2) 960 933 div = 2; ··· 963 936 964 937 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK, 965 938 div << XADC_CONF2_DIV_OFFSET); 939 + } 940 + 941 + static int xadc_write_raw(struct iio_dev *indio_dev, 942 + struct iio_chan_spec const *chan, int val, int val2, long info) 943 + { 944 + struct xadc *xadc = iio_priv(indio_dev); 945 + 946 + if (info != IIO_CHAN_INFO_SAMP_FREQ) 947 + return -EINVAL; 948 + 949 + return xadc_write_samplerate(xadc, val); 966 950 } 967 951 968 952 static const struct iio_event_spec xadc_temp_events[] = { ··· 1260 1222 ret = clk_prepare_enable(xadc->clk); 1261 1223 if (ret) 1262 1224 goto err_free_samplerate_trigger; 1225 + 1226 + /* 1227 + * Make sure not to exceed the maximum samplerate since otherwise the 1228 + * resulting interrupt storm will soft-lock the system. 1229 + */ 1230 + if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { 1231 + ret = xadc_read_samplerate(xadc); 1232 + if (ret < 0) 1233 + goto err_free_samplerate_trigger; 1234 + if (ret > XADC_MAX_SAMPLERATE) { 1235 + ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE); 1236 + if (ret < 0) 1237 + goto err_free_samplerate_trigger; 1238 + } 1239 + } 1263 1240 1264 1241 ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0, 1265 1242 dev_name(&pdev->dev), indio_dev);

+1 -1

drivers/iio/common/st_sensors/st_sensors_core.c

··· 79 79 struct st_sensor_odr_avl odr_out = {0, 0}; 80 80 struct st_sensor_data *sdata = iio_priv(indio_dev); 81 81 82 - if (!sdata->sensor_settings->odr.addr) 82 + if (!sdata->sensor_settings->odr.mask) 83 83 return 0; 84 84 85 85 err = st_sensors_match_odr(sdata->sensor_settings, odr, &odr_out);

+1 -1

drivers/iio/dac/ad5770r.c

··· 525 525 ret = fwnode_property_read_u32(child, "num", &num); 526 526 if (ret) 527 527 return ret; 528 - if (num > AD5770R_MAX_CHANNELS) 528 + if (num >= AD5770R_MAX_CHANNELS) 529 529 return -EINVAL; 530 530 531 531 ret = fwnode_property_read_u32_array(child,

+10 -1

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

··· 1617 1617 if (result) 1618 1618 goto out_unlock; 1619 1619 1620 + pm_runtime_disable(dev); 1621 + pm_runtime_set_active(dev); 1622 + pm_runtime_enable(dev); 1623 + 1620 1624 result = inv_mpu6050_switch_engine(st, true, st->suspended_sensors); 1621 1625 if (result) 1622 1626 goto out_unlock; ··· 1642 1638 1643 1639 mutex_lock(&st->lock); 1644 1640 1641 + st->suspended_sensors = 0; 1642 + if (pm_runtime_suspended(dev)) { 1643 + result = 0; 1644 + goto out_unlock; 1645 + } 1646 + 1645 1647 if (iio_buffer_enabled(indio_dev)) { 1646 1648 result = inv_mpu6050_prepare_fifo(st, false); 1647 1649 if (result) 1648 1650 goto out_unlock; 1649 1651 } 1650 1652 1651 - st->suspended_sensors = 0; 1652 1653 if (st->chip_config.accl_en) 1653 1654 st->suspended_sensors |= INV_MPU6050_SENSOR_ACCL; 1654 1655 if (st->chip_config.gyro_en)

+3

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h

··· 337 337 * @gain: Configured sensor sensitivity. 338 338 * @odr: Output data rate of the sensor [Hz]. 339 339 * @watermark: Sensor watermark level. 340 + * @decimator: Sensor decimation factor. 340 341 * @sip: Number of samples in a given pattern. 341 342 * @ts_ref: Sensor timestamp reference for hw one. 342 343 * @ext_info: Sensor settings if it is connected to i2c controller ··· 351 350 u32 odr; 352 351 353 352 u16 watermark; 353 + u8 decimator; 354 354 u8 sip; 355 355 s64 ts_ref; 356 356 357 357 struct { 358 358 const struct st_lsm6dsx_ext_dev_settings *settings; 359 + u32 slv_odr; 359 360 u8 addr; 360 361 } ext_info; 361 362 };

+16 -7

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c

··· 93 93 break; 94 94 } 95 95 96 + sensor->decimator = decimator; 96 97 return i == max_size ? 0 : st_lsm6dsx_decimator_table[i].val; 97 98 } 98 99 ··· 338 337 int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw) 339 338 { 340 339 struct st_lsm6dsx_sensor *acc_sensor, *gyro_sensor, *ext_sensor = NULL; 341 - int err, acc_sip, gyro_sip, ts_sip, ext_sip, read_len, offset; 340 + int err, sip, acc_sip, gyro_sip, ts_sip, ext_sip, read_len, offset; 342 341 u16 fifo_len, pattern_len = hw->sip * ST_LSM6DSX_SAMPLE_SIZE; 343 342 u16 fifo_diff_mask = hw->settings->fifo_ops.fifo_diff.mask; 344 343 u8 gyro_buff[ST_LSM6DSX_IIO_BUFF_SIZE]; ··· 400 399 acc_sip = acc_sensor->sip; 401 400 ts_sip = hw->ts_sip; 402 401 offset = 0; 402 + sip = 0; 403 403 404 404 while (acc_sip > 0 || gyro_sip > 0 || ext_sip > 0) { 405 - if (gyro_sip > 0) { 405 + if (gyro_sip > 0 && !(sip % gyro_sensor->decimator)) { 406 406 memcpy(gyro_buff, &hw->buff[offset], 407 407 ST_LSM6DSX_SAMPLE_SIZE); 408 408 offset += ST_LSM6DSX_SAMPLE_SIZE; 409 409 } 410 - if (acc_sip > 0) { 410 + if (acc_sip > 0 && !(sip % acc_sensor->decimator)) { 411 411 memcpy(acc_buff, &hw->buff[offset], 412 412 ST_LSM6DSX_SAMPLE_SIZE); 413 413 offset += ST_LSM6DSX_SAMPLE_SIZE; 414 414 } 415 - if (ext_sip > 0) { 415 + if (ext_sip > 0 && !(sip % ext_sensor->decimator)) { 416 416 memcpy(ext_buff, &hw->buff[offset], 417 417 ST_LSM6DSX_SAMPLE_SIZE); 418 418 offset += ST_LSM6DSX_SAMPLE_SIZE; ··· 443 441 offset += ST_LSM6DSX_SAMPLE_SIZE; 444 442 } 445 443 446 - if (gyro_sip-- > 0) 444 + if (gyro_sip > 0 && !(sip % gyro_sensor->decimator)) { 447 445 iio_push_to_buffers_with_timestamp( 448 446 hw->iio_devs[ST_LSM6DSX_ID_GYRO], 449 447 gyro_buff, gyro_sensor->ts_ref + ts); 450 - if (acc_sip-- > 0) 448 + gyro_sip--; 449 + } 450 + if (acc_sip > 0 && !(sip % acc_sensor->decimator)) { 451 451 iio_push_to_buffers_with_timestamp( 452 452 hw->iio_devs[ST_LSM6DSX_ID_ACC], 453 453 acc_buff, acc_sensor->ts_ref + ts); 454 - if (ext_sip-- > 0) 454 + acc_sip--; 455 + } 456 + if (ext_sip > 0 && !(sip % ext_sensor->decimator)) { 455 457 iio_push_to_buffers_with_timestamp( 456 458 hw->iio_devs[ST_LSM6DSX_ID_EXT0], 457 459 ext_buff, ext_sensor->ts_ref + ts); 460 + ext_sip--; 461 + } 462 + sip++; 458 463 } 459 464 } 460 465

+23 -1

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

··· 2036 2036 return 0; 2037 2037 } 2038 2038 2039 - static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 2039 + static int st_lsm6dsx_reset_device(struct st_lsm6dsx_hw *hw) 2040 2040 { 2041 2041 const struct st_lsm6dsx_reg *reg; 2042 2042 int err; 2043 + 2044 + /* 2045 + * flush hw FIFO before device reset in order to avoid 2046 + * possible races on interrupt line 1. If the first interrupt 2047 + * line is asserted during hw reset the device will work in 2048 + * I3C-only mode (if it is supported) 2049 + */ 2050 + err = st_lsm6dsx_flush_fifo(hw); 2051 + if (err < 0 && err != -ENOTSUPP) 2052 + return err; 2043 2053 2044 2054 /* device sw reset */ 2045 2055 reg = &hw->settings->reset; ··· 2068 2058 return err; 2069 2059 2070 2060 msleep(50); 2061 + 2062 + return 0; 2063 + } 2064 + 2065 + static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 2066 + { 2067 + const struct st_lsm6dsx_reg *reg; 2068 + int err; 2069 + 2070 + err = st_lsm6dsx_reset_device(hw); 2071 + if (err < 0) 2072 + return err; 2071 2073 2072 2074 /* enable Block Data Update */ 2073 2075 reg = &hw->settings->bdu;

+22 -7

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

··· 421 421 422 422 settings = sensor->ext_info.settings; 423 423 if (enable) { 424 - err = st_lsm6dsx_shub_set_odr(sensor, sensor->odr); 424 + err = st_lsm6dsx_shub_set_odr(sensor, 425 + sensor->ext_info.slv_odr); 425 426 if (err < 0) 426 427 return err; 427 428 } else { ··· 460 459 if (err < 0) 461 460 return err; 462 461 463 - delay = 1000000000 / sensor->odr; 462 + delay = 1000000000 / sensor->ext_info.slv_odr; 464 463 usleep_range(delay, 2 * delay); 465 464 466 465 len = min_t(int, sizeof(data), ch->scan_type.realbits >> 3); ··· 501 500 iio_device_release_direct_mode(iio_dev); 502 501 break; 503 502 case IIO_CHAN_INFO_SAMP_FREQ: 504 - *val = sensor->odr / 1000; 505 - *val2 = (sensor->odr % 1000) * 1000; 503 + *val = sensor->ext_info.slv_odr / 1000; 504 + *val2 = (sensor->ext_info.slv_odr % 1000) * 1000; 506 505 ret = IIO_VAL_INT_PLUS_MICRO; 507 506 break; 508 507 case IIO_CHAN_INFO_SCALE: ··· 536 535 537 536 val = val * 1000 + val2 / 1000; 538 537 err = st_lsm6dsx_shub_get_odr_val(sensor, val, &data); 539 - if (!err) 540 - sensor->odr = val; 538 + if (!err) { 539 + struct st_lsm6dsx_hw *hw = sensor->hw; 540 + struct st_lsm6dsx_sensor *ref_sensor; 541 + u8 odr_val; 542 + int odr; 543 + 544 + ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 545 + odr = st_lsm6dsx_check_odr(ref_sensor, val, &odr_val); 546 + if (odr < 0) 547 + return odr; 548 + 549 + sensor->ext_info.slv_odr = val; 550 + sensor->odr = odr; 551 + } 541 552 break; 542 553 } 543 554 default: ··· 626 613 const struct st_lsm6dsx_ext_dev_settings *info, 627 614 u8 i2c_addr, const char *name) 628 615 { 616 + enum st_lsm6dsx_sensor_id ref_id = ST_LSM6DSX_ID_ACC; 629 617 struct iio_chan_spec *ext_channels; 630 618 struct st_lsm6dsx_sensor *sensor; 631 619 struct iio_dev *iio_dev; ··· 642 628 sensor = iio_priv(iio_dev); 643 629 sensor->id = id; 644 630 sensor->hw = hw; 645 - sensor->odr = info->odr_table.odr_avl[0].milli_hz; 631 + sensor->odr = hw->settings->odr_table[ref_id].odr_avl[0].milli_hz; 632 + sensor->ext_info.slv_odr = info->odr_table.odr_avl[0].milli_hz; 646 633 sensor->gain = info->fs_table.fs_avl[0].gain; 647 634 sensor->ext_info.settings = info; 648 635 sensor->ext_info.addr = i2c_addr;

+2 -5

drivers/iio/industrialio-core.c

··· 915 915 return -EINVAL; 916 916 integer = ch; 917 917 } else { 918 - ret = iio_str_to_fixpoint(buf, fract_mult, &integer, &fract); 918 + ret = __iio_str_to_fixpoint(buf, fract_mult, &integer, &fract, 919 + scale_db); 919 920 if (ret) 920 921 return ret; 921 922 } 922 - ret = __iio_str_to_fixpoint(buf, fract_mult, &integer, &fract, 923 - scale_db); 924 - if (ret) 925 - return ret; 926 923 927 924 ret = indio_dev->info->write_raw(indio_dev, this_attr->c, 928 925 integer, fract, this_attr->address);

+3 -1

drivers/staging/comedi/comedi_fops.c

··· 2725 2725 } 2726 2726 2727 2727 cfp = kzalloc(sizeof(*cfp), GFP_KERNEL); 2728 - if (!cfp) 2728 + if (!cfp) { 2729 + comedi_dev_put(dev); 2729 2730 return -ENOMEM; 2731 + } 2730 2732 2731 2733 cfp->dev = dev; 2732 2734

+3

drivers/staging/comedi/drivers/dt2815.c

··· 92 92 int ret; 93 93 94 94 for (i = 0; i < insn->n; i++) { 95 + /* FIXME: lo bit 0 chooses voltage output or current output */ 95 96 lo = ((data[i] & 0x0f) << 4) | (chan << 1) | 0x01; 96 97 hi = (data[i] & 0xff0) >> 4; 97 98 ··· 105 104 ret = comedi_timeout(dev, s, insn, dt2815_ao_status, 0x10); 106 105 if (ret) 107 106 return ret; 107 + 108 + outb(hi, dev->iobase + DT2815_DATA); 108 109 109 110 devpriv->ao_readback[chan] = data[i]; 110 111 }

+1 -2

drivers/staging/gasket/gasket_sysfs.c

··· 228 228 } 229 229 230 230 mutex_lock(&mapping->mutex); 231 - for (i = 0; strcmp(attrs[i].attr.attr.name, GASKET_ARRAY_END_MARKER); 232 - i++) { 231 + for (i = 0; attrs[i].attr.attr.name != NULL; i++) { 233 232 if (mapping->attribute_count == GASKET_SYSFS_MAX_NODES) { 234 233 dev_err(device, 235 234 "Maximum number of sysfs nodes reached for device\n");

-4

drivers/staging/gasket/gasket_sysfs.h

··· 30 30 */ 31 31 #define GASKET_SYSFS_MAX_NODES 196 32 32 33 - /* End markers for sysfs struct arrays. */ 34 - #define GASKET_ARRAY_END_TOKEN GASKET_RESERVED_ARRAY_END 35 - #define GASKET_ARRAY_END_MARKER __stringify(GASKET_ARRAY_END_TOKEN) 36 - 37 33 /* 38 34 * Terminator struct for a gasket_sysfs_attr array. Must be at the end of 39 35 * all gasket_sysfs_attribute arrays.

+3 -11

drivers/staging/vt6656/key.c

··· 83 83 case VNT_KEY_PAIRWISE: 84 84 key_mode |= mode; 85 85 key_inx = 4; 86 - /* Don't save entry for pairwise key for station mode */ 87 - if (priv->op_mode == NL80211_IFTYPE_STATION) 88 - clear_bit(entry, &priv->key_entry_inuse); 89 86 break; 90 87 default: 91 88 return -EINVAL; ··· 106 109 int vnt_set_keys(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 107 110 struct ieee80211_vif *vif, struct ieee80211_key_conf *key) 108 111 { 109 - struct ieee80211_bss_conf *conf = &vif->bss_conf; 110 112 struct vnt_private *priv = hw->priv; 111 113 u8 *mac_addr = NULL; 112 114 u8 key_dec_mode = 0; ··· 150 154 return -EOPNOTSUPP; 151 155 } 152 156 153 - if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 157 + if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) 154 158 vnt_set_keymode(hw, mac_addr, key, VNT_KEY_PAIRWISE, 155 159 key_dec_mode, true); 156 - } else { 157 - vnt_set_keymode(hw, mac_addr, key, VNT_KEY_DEFAULTKEY, 160 + else 161 + vnt_set_keymode(hw, mac_addr, key, VNT_KEY_GROUP_ADDRESS, 158 162 key_dec_mode, true); 159 - 160 - vnt_set_keymode(hw, (u8 *)conf->bssid, key, 161 - VNT_KEY_GROUP_ADDRESS, key_dec_mode, true); 162 - } 163 163 164 164 return 0; 165 165 }

+17 -14

drivers/staging/vt6656/main_usb.c

··· 625 625 626 626 priv->op_mode = vif->type; 627 627 628 - vnt_set_bss_mode(priv); 629 - 630 628 /* LED blink on TX */ 631 629 vnt_mac_set_led(priv, LEDSTS_STS, LEDSTS_INTER); 632 630 ··· 711 713 priv->basic_rates = conf->basic_rates; 712 714 713 715 vnt_update_top_rates(priv); 714 - vnt_set_bss_mode(priv); 715 716 716 717 dev_dbg(&priv->usb->dev, "basic rates %x\n", conf->basic_rates); 717 718 } ··· 739 742 priv->short_slot_time = false; 740 743 741 744 vnt_set_short_slot_time(priv); 742 - vnt_update_ifs(priv); 743 745 vnt_set_vga_gain_offset(priv, priv->bb_vga[0]); 744 746 vnt_update_pre_ed_threshold(priv, false); 745 747 } 748 + 749 + if (changed & (BSS_CHANGED_BASIC_RATES | BSS_CHANGED_ERP_PREAMBLE | 750 + BSS_CHANGED_ERP_SLOT)) 751 + vnt_set_bss_mode(priv); 746 752 747 753 if (changed & BSS_CHANGED_TXPOWER) 748 754 vnt_rf_setpower(priv, priv->current_rate, ··· 770 770 vnt_mac_reg_bits_on(priv, MAC_REG_TFTCTL, 771 771 TFTCTL_TSFCNTREN); 772 772 773 - vnt_adjust_tsf(priv, conf->beacon_rate->hw_value, 774 - conf->sync_tsf, priv->current_tsf); 775 - 776 773 vnt_mac_set_beacon_interval(priv, conf->beacon_int); 777 774 778 775 vnt_reset_next_tbtt(priv, conf->beacon_int); 776 + 777 + vnt_adjust_tsf(priv, conf->beacon_rate->hw_value, 778 + conf->sync_tsf, priv->current_tsf); 779 + 780 + vnt_update_next_tbtt(priv, 781 + conf->sync_tsf, conf->beacon_int); 779 782 } else { 780 783 vnt_clear_current_tsf(priv); 781 784 ··· 812 809 { 813 810 struct vnt_private *priv = hw->priv; 814 811 u8 rx_mode = 0; 815 - int rc; 816 812 817 813 *total_flags &= FIF_ALLMULTI | FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC; 818 814 819 - rc = vnt_control_in(priv, MESSAGE_TYPE_READ, MAC_REG_RCR, 820 - MESSAGE_REQUEST_MACREG, sizeof(u8), &rx_mode); 821 - 822 - if (!rc) 823 - rx_mode = RCR_MULTICAST | RCR_BROADCAST; 815 + vnt_control_in(priv, MESSAGE_TYPE_READ, MAC_REG_RCR, 816 + MESSAGE_REQUEST_MACREG, sizeof(u8), &rx_mode); 824 817 825 818 dev_dbg(&priv->usb->dev, "rx mode in = %x\n", rx_mode); 826 819 ··· 855 856 case SET_KEY: 856 857 return vnt_set_keys(hw, sta, vif, key); 857 858 case DISABLE_KEY: 858 - if (test_bit(key->hw_key_idx, &priv->key_entry_inuse)) 859 + if (test_bit(key->hw_key_idx, &priv->key_entry_inuse)) { 859 860 clear_bit(key->hw_key_idx, &priv->key_entry_inuse); 861 + 862 + vnt_mac_disable_keyentry(priv, key->hw_key_idx); 863 + } 864 + 860 865 default: 861 866 break; 862 867 }

+2 -1

drivers/staging/vt6656/usbpipe.c

··· 207 207 priv->wake_up_count = 208 208 priv->hw->conf.listen_interval; 209 209 210 - --priv->wake_up_count; 210 + if (priv->wake_up_count) 211 + --priv->wake_up_count; 211 212 212 213 /* Turn on wake up to listen next beacon */ 213 214 if (priv->wake_up_count == 1)

+1 -1

include/linux/iio/iio.h

··· 600 600 * 0 on success, negative error number on failure. 601 601 */ 602 602 #define devm_iio_device_register(dev, indio_dev) \ 603 - __devm_iio_device_register((dev), (indio_dev), THIS_MODULE); 603 + __devm_iio_device_register((dev), (indio_dev), THIS_MODULE) 604 604 int __devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev, 605 605 struct module *this_mod); 606 606 void devm_iio_device_unregister(struct device *dev, struct iio_dev *indio_dev);

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