Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: Support ROHM BD79112 ADC/GPIO
The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can
be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O
voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with
daisy-chain configuration) and maximum sampling rate is 1MSPS.
The IC does also support CRC but it is not implemented in the driver.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Matti Vaittinen
and committed by
Jonathan Cameron
edf2fc7b
d021fb3a
+567
+10
drivers/iio/adc/Kconfig
+10
drivers/iio/adc/Kconfig
···
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This driver can also be built as a module. If so, the module
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will be called rn5t618-adc.
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config ROHM_BD79112
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tristate "Rohm BD79112 ADC driver"
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depends on SPI && GPIOLIB
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select REGMAP_SPI
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select IIO_ADC_HELPER
1350
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help
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Say yes here to build support for the ROHM BD79112 ADC. The
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ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. Analog inputs
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can also be used for GPIO.
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+
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config ROHM_BD79124
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tristate "Rohm BD79124 ADC driver"
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depends on I2C && GPIOLIB
+1
drivers/iio/adc/Makefile
+1
drivers/iio/adc/Makefile
···
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obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o
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obj-$(CONFIG_RICHTEK_RTQ6056) += rtq6056.o
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obj-$(CONFIG_RN5T618_ADC) += rn5t618-adc.o
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+
obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o
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obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o
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obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
+556
drivers/iio/adc/rohm-bd79112.c
+556
drivers/iio/adc/rohm-bd79112.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
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+
/*
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+
* ROHM ADC driver for BD79112 signal monitoring hub.
4
+
* Copyright (C) 2025, ROHM Semiconductor.
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+
*
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* SPI communication derived from ad7923.c and ti-ads7950.c
7
+
*/
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+
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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+
#include <linux/bitops.h>
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+
#include <linux/bits.h>
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#include <linux/dev_printk.h>
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+
#include <linux/err.h>
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+
#include <linux/errno.h>
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+
#include <linux/gpio/driver.h>
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+
#include <linux/mod_devicetable.h>
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+
#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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+
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#include <linux/iio/adc-helpers.h>
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#include <linux/iio/iio.h>
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+
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#define BD79112_MAX_NUM_CHANNELS 32
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+
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struct bd79112_data {
31
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struct spi_device *spi;
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struct regmap *map;
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+
struct device *dev;
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struct gpio_chip gc;
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unsigned long gpio_valid_mask;
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unsigned int vref_mv;
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struct spi_transfer read_xfer[2];
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struct spi_transfer write_xfer;
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struct spi_message read_msg;
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struct spi_message write_msg;
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/* 16-bit TX, valid data in high byte */
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u8 read_tx[2] __aligned(IIO_DMA_MINALIGN);
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/* 8-bit address followed by 8-bit data */
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u8 reg_write_tx[2];
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/* 12-bit of ADC data or 8 bit of reg data */
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__be16 read_rx;
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+
};
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+
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/*
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* The ADC data is read issuing SPI-command matching the channel number.
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* We treat this as a register address.
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+
*/
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#define BD79112_REG_AGIO0A 0x00
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#define BD79112_REG_AGIO15B 0x1f
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+
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/*
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* ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is being
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* read for a channel, which input pin is muxed to be a GPIO.
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+
*/
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#define BD79112_ADC_STATUS_FLAG BIT(14)
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+
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/*
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* The BD79112 requires "R/W bit" to be set for SPI register (not ADC data)
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* reads and an "IOSET bit" to be set for read/write operations (which aren't
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* reading the ADC data).
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*/
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#define BD79112_BIT_RW BIT(4)
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#define BD79112_BIT_IO BIT(5)
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+
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#define BD79112_REG_GPI_VALUE_B8_15 (BD79112_BIT_IO | 0x0)
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#define BD79112_REG_GPI_VALUE_B0_B7 (BD79112_BIT_IO | 0x1)
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#define BD79112_REG_GPI_VALUE_A8_15 (BD79112_BIT_IO | 0x2)
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#define BD79112_REG_GPI_VALUE_A0_A7 (BD79112_BIT_IO | 0x3)
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+
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#define BD79112_REG_GPI_EN_B7_B15 (BD79112_BIT_IO | 0x4)
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#define BD79112_REG_GPI_EN_B0_B7 (BD79112_BIT_IO | 0x5)
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#define BD79112_REG_GPI_EN_A8_A15 (BD79112_BIT_IO | 0x6)
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#define BD79112_REG_GPI_EN_A0_A7 (BD79112_BIT_IO | 0x7)
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+
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#define BD79112_REG_GPO_EN_B7_B15 (BD79112_BIT_IO | 0x8)
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#define BD79112_REG_GPO_EN_B0_B7 (BD79112_BIT_IO | 0x9)
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#define BD79112_REG_GPO_EN_A8_A15 (BD79112_BIT_IO | 0xa)
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#define BD79112_REG_GPO_EN_A0_A7 (BD79112_BIT_IO | 0xb)
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+
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#define BD79112_NUM_GPIO_EN_REGS 8
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#define BD79112_FIRST_GPIO_EN_REG BD79112_REG_GPI_EN_B7_B15
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+
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#define BD79112_REG_GPO_VALUE_B8_15 (BD79112_BIT_IO | 0xc)
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#define BD79112_REG_GPO_VALUE_B0_B7 (BD79112_BIT_IO | 0xd)
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#define BD79112_REG_GPO_VALUE_A8_15 (BD79112_BIT_IO | 0xe)
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#define BD79112_REG_GPO_VALUE_A0_A7 (BD79112_BIT_IO | 0xf)
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+
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#define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7
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+
95
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/*
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* Read transaction consists of two 16-bit sequences separated by CSB.
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* For register read, 'IOSET' bit must be set. For ADC read, IOSET is cleared
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* and ADDR equals the channel number (0 ... 31).
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*
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* First 16-bit sequence, MOSI as below, MISO data ignored:
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* - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 |
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* - MOSI:| 0 | 0 | IOSET | RW (1) | ADDR | 8'b0 |
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*
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* CSB released and re-acquired between these sequences
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*
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* Second 16-bit sequence, MISO as below, MOSI data ignored:
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* For Register read data is 8 bits:
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* - SCK: | 1 .. 8 | 9 .. 16 |
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* - MISO:| 8'b0 | 8-bit data |
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*
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* For ADC read data is 12 bits:
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* - SCK: | 1 | 2 | 3 4 | 4 .. 16 |
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* - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data |
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* The 'STATUS_FLAG' is set if the read input pin was configured as a GPIO.
115
+
*/
116
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static int bd79112_reg_read(void *context, unsigned int reg, unsigned int *val)
117
+
{
118
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struct bd79112_data *data = context;
119
+
int ret;
120
+
121
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if (reg & BD79112_BIT_IO)
122
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reg |= BD79112_BIT_RW;
123
+
124
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data->read_tx[0] = reg;
125
+
126
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ret = spi_sync(data->spi, &data->read_msg);
127
+
if (!ret)
128
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*val = be16_to_cpu(data->read_rx);
129
+
130
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return ret;
131
+
}
132
+
133
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/*
134
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* Write, single 16-bit sequence (broken down below):
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*
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* First 8-bit, MOSI as below, MISO data ignored:
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* - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 |
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* - MOSI:| 0 | 0 |IOSET| RW(0) | ADDR |
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*
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* Last 8 SCK cycles (b8 ... b15), MISO contains register data, MOSI ignored.
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* - SCK: | 9 .. 16 |
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* - MISO:| data |
143
+
*/
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static int bd79112_reg_write(void *context, unsigned int reg, unsigned int val)
145
+
{
146
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struct bd79112_data *data = context;
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+
148
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data->reg_write_tx[0] = reg;
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data->reg_write_tx[1] = val;
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+
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return spi_sync(data->spi, &data->write_msg);
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}
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+
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static int _get_gpio_reg(unsigned int offset, unsigned int base)
155
+
{
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int regoffset = offset / 8;
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+
158
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if (offset > 31)
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return -EINVAL;
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+
161
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return base - regoffset;
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}
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+
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#define GET_GPIO_BIT(offset) BIT((offset) % 8)
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#define GET_GPO_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_EN_A0_A7)
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#define GET_GPI_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_EN_A0_A7)
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#define GET_GPO_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_VALUE_A0_A7)
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#define GET_GPI_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_VALUE_A0_A7)
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+
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static const struct regmap_range bd71815_volatile_ro_ranges[] = {
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{
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/* Read ADC data */
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.range_min = BD79112_REG_AGIO0A,
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.range_max = BD79112_REG_AGIO15B,
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}, {
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/* GPI state */
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.range_min = BD79112_REG_GPI_VALUE_B8_15,
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.range_max = BD79112_REG_GPI_VALUE_A0_A7,
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},
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};
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+
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static const struct regmap_access_table bd79112_volatile_regs = {
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.yes_ranges = &bd71815_volatile_ro_ranges[0],
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.n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges),
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};
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static const struct regmap_access_table bd79112_ro_regs = {
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.no_ranges = &bd71815_volatile_ro_ranges[0],
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.n_no_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges),
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};
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static const struct regmap_config bd79112_regmap = {
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.reg_read = bd79112_reg_read,
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.reg_write = bd79112_reg_write,
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.volatile_table = &bd79112_volatile_regs,
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.wr_table = &bd79112_ro_regs,
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.cache_type = REGCACHE_MAPLE,
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.max_register = BD79112_REG_MAX,
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};
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+
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static int bd79112_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val,
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int *val2, long m)
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{
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struct bd79112_data *data = iio_priv(indio_dev);
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int ret;
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+
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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ret = regmap_read(data->map, chan->channel, val);
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if (ret < 0)
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return ret;
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+
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return IIO_VAL_INT;
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+
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case IIO_CHAN_INFO_SCALE:
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*val = data->vref_mv;
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*val2 = 12;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
225
+
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static const struct iio_info bd79112_info = {
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.read_raw = bd79112_read_raw,
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};
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+
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static const struct iio_chan_spec bd79112_chan_template = {
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.type = IIO_VOLTAGE,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
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.indexed = 1,
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};
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+
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static int bd79112_gpio_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask,
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unsigned int ngpios)
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{
241
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struct bd79112_data *data = gpiochip_get_data(gc);
242
+
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*valid_mask = data->gpio_valid_mask;
244
+
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return 0;
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}
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+
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static int bd79112_gpio_dir_get(struct gpio_chip *gc, unsigned int offset)
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{
250
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struct bd79112_data *data = gpiochip_get_data(gc);
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unsigned int reg, bit, val;
252
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int ret;
253
+
254
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bit = GET_GPIO_BIT(offset);
255
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reg = GET_GPO_EN_REG(offset);
256
+
257
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ret = regmap_read(data->map, reg, &val);
258
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if (ret)
259
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return ret;
260
+
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if (bit & val)
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return GPIO_LINE_DIRECTION_OUT;
263
+
264
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reg = GET_GPI_EN_REG(offset);
265
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ret = regmap_read(data->map, reg, &val);
266
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if (ret)
267
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return ret;
268
+
269
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if (bit & val)
270
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return GPIO_LINE_DIRECTION_IN;
271
+
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/*
273
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* Ouch. Seems the pin is ADC input - shouldn't happen as changing mux
274
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* at runtime is not supported and non GPIO pins should be invalidated
275
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* by the valid_mask at probe. Maybe someone wrote a register bypassing
276
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* the driver?
277
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*/
278
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dev_err(data->dev, "Pin not a GPIO\n");
279
+
280
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return -EINVAL;
281
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}
282
+
283
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static int bd79112_gpio_get(struct gpio_chip *gc, unsigned int offset)
284
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{
285
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struct bd79112_data *data = gpiochip_get_data(gc);
286
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unsigned int reg, bit, val;
287
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int ret;
288
+
289
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bit = GET_GPIO_BIT(offset);
290
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reg = GET_GPI_VAL_REG(offset);
291
+
292
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ret = regmap_read(data->map, reg, &val);
293
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if (ret)
294
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return ret;
295
+
296
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return !!(val & bit);
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}
298
+
299
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static int bd79112_gpio_set(struct gpio_chip *gc, unsigned int offset,
300
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int value)
301
+
{
302
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struct bd79112_data *data = gpiochip_get_data(gc);
303
+
unsigned int reg, bit;
304
+
305
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bit = GET_GPIO_BIT(offset);
306
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reg = GET_GPO_VAL_REG(offset);
307
+
308
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return regmap_assign_bits(data->map, reg, bit, value);
309
+
}
310
+
311
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static int bd79112_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
312
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unsigned long *bits)
313
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{
314
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struct bd79112_data *data = gpiochip_get_data(gc);
315
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unsigned long i, bank_mask;
316
+
317
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for_each_set_clump8(i, bank_mask, mask, gc->ngpio) {
318
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unsigned long bank_bits;
319
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unsigned int reg;
320
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int ret;
321
+
322
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bank_bits = bitmap_get_value8(bits, i);
323
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reg = BD79112_REG_GPO_VALUE_A0_A7 - i / 8;
324
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ret = regmap_update_bits(data->map, reg, bank_mask, bank_bits);
325
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if (ret)
326
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return ret;
327
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}
328
+
329
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return 0;
330
+
}
331
+
332
+
static int bd79112_gpio_dir_set(struct bd79112_data *data, unsigned int offset,
333
+
int dir)
334
+
{
335
+
unsigned int gpi_reg, gpo_reg, bit;
336
+
int ret;
337
+
338
+
bit = GET_GPIO_BIT(offset);
339
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gpi_reg = GET_GPI_EN_REG(offset);
340
+
gpo_reg = GET_GPO_EN_REG(offset);
341
+
342
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if (dir == GPIO_LINE_DIRECTION_OUT) {
343
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ret = regmap_clear_bits(data->map, gpi_reg, bit);
344
+
if (ret)
345
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return ret;
346
+
347
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return regmap_set_bits(data->map, gpo_reg, bit);
348
+
}
349
+
350
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ret = regmap_set_bits(data->map, gpi_reg, bit);
351
+
if (ret)
352
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return ret;
353
+
354
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return regmap_clear_bits(data->map, gpo_reg, bit);
355
+
}
356
+
357
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static int bd79112_gpio_input(struct gpio_chip *gc, unsigned int offset)
358
+
{
359
+
struct bd79112_data *data = gpiochip_get_data(gc);
360
+
361
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return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_IN);
362
+
}
363
+
364
+
static int bd79112_gpio_output(struct gpio_chip *gc, unsigned int offset,
365
+
int value)
366
+
{
367
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struct bd79112_data *data = gpiochip_get_data(gc);
368
+
int ret;
369
+
370
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ret = bd79112_gpio_set(gc, offset, value);
371
+
if (ret)
372
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return ret;
373
+
374
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return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_OUT);
375
+
}
376
+
377
+
static const struct gpio_chip bd79112_gpio_chip = {
378
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.label = "bd79112-gpio",
379
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.get_direction = bd79112_gpio_dir_get,
380
+
.direction_input = bd79112_gpio_input,
381
+
.direction_output = bd79112_gpio_output,
382
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.get = bd79112_gpio_get,
383
+
.set = bd79112_gpio_set,
384
+
.set_multiple = bd79112_gpio_set_multiple,
385
+
.init_valid_mask = bd79112_gpio_init_valid_mask,
386
+
.can_sleep = true,
387
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.ngpio = 32,
388
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.base = -1,
389
+
};
390
+
391
+
static unsigned int bd79112_get_gpio_pins(const struct iio_chan_spec *cs, int num_channels)
392
+
{
393
+
unsigned int i, gpio_channels;
394
+
395
+
/*
396
+
* Let's initialize the mux config to say that all 32 channels are
397
+
* GPIOs. Then we can just loop through the iio_chan_spec and clear the
398
+
* bits for found ADC channels.
399
+
*/
400
+
gpio_channels = GENMASK(31, 0);
401
+
for (i = 0; i < num_channels; i++)
402
+
gpio_channels &= ~BIT(cs[i].channel);
403
+
404
+
return gpio_channels;
405
+
}
406
+
407
+
/* ADC channels as named in the data-sheet */
408
+
static const char * const bd79112_chan_names[] = {
409
+
"AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", /* 0 - 3 */
410
+
"AGIO4A", "AGIO5A", "AGIO6A", "AGIO7A", /* 4 - 7 */
411
+
"AGIO8A", "AGIO9A", "AGIO10A", "AGIO11A", /* 8 - 11 */
412
+
"AGIO12A", "AGIO13A", "AGIO14A", "AGIO15A", /* 12 - 15 */
413
+
"AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B", /* 16 - 19 */
414
+
"AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", /* 20 - 23 */
415
+
"AGIO8B", "AGIO9B", "AGIO10B", "AGIO11B", /* 24 - 27 */
416
+
"AGIO12B", "AGIO13B", "AGIO14B", "AGIO15B", /* 28 - 31 */
417
+
};
418
+
419
+
static int bd79112_probe(struct spi_device *spi)
420
+
{
421
+
struct bd79112_data *data;
422
+
struct iio_dev *iio_dev;
423
+
struct iio_chan_spec *cs;
424
+
struct device *dev = &spi->dev;
425
+
unsigned long gpio_pins, pin;
426
+
unsigned int i;
427
+
int ret;
428
+
429
+
iio_dev = devm_iio_device_alloc(dev, sizeof(*data));
430
+
if (!iio_dev)
431
+
return -ENOMEM;
432
+
433
+
data = iio_priv(iio_dev);
434
+
data->spi = spi;
435
+
data->dev = dev;
436
+
data->map = devm_regmap_init(dev, NULL, data, &bd79112_regmap);
437
+
if (IS_ERR(data->map))
438
+
return dev_err_probe(dev, PTR_ERR(data->map),
439
+
"Failed to initialize Regmap\n");
440
+
441
+
ret = devm_regulator_get_enable_read_voltage(dev, "vdd");
442
+
if (ret < 0)
443
+
return dev_err_probe(dev, ret, "Failed to get the Vdd\n");
444
+
445
+
data->vref_mv = ret / 1000;
446
+
447
+
ret = devm_regulator_get_enable(dev, "iovdd");
448
+
if (ret < 0)
449
+
return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n");
450
+
451
+
data->read_xfer[0].tx_buf = &data->read_tx[0];
452
+
data->read_xfer[0].len = sizeof(data->read_tx);
453
+
data->read_xfer[0].cs_change = 1;
454
+
data->read_xfer[1].rx_buf = &data->read_rx;
455
+
data->read_xfer[1].len = sizeof(data->read_rx);
456
+
spi_message_init_with_transfers(&data->read_msg, data->read_xfer, 2);
457
+
ret = devm_spi_optimize_message(dev, spi, &data->read_msg);
458
+
if (ret < 0)
459
+
return dev_err_probe(dev, ret,
460
+
"Failed to optimize SPI read message\n");
461
+
462
+
data->write_xfer.tx_buf = &data->reg_write_tx[0];
463
+
data->write_xfer.len = sizeof(data->reg_write_tx);
464
+
spi_message_init_with_transfers(&data->write_msg, &data->write_xfer, 1);
465
+
ret = devm_spi_optimize_message(dev, spi, &data->write_msg);
466
+
if (ret < 0)
467
+
return dev_err_probe(dev, ret,
468
+
"Failed to optimize SPI write message\n");
469
+
470
+
ret = devm_iio_adc_device_alloc_chaninfo_se(dev, &bd79112_chan_template,
471
+
BD79112_MAX_NUM_CHANNELS - 1,
472
+
&cs);
473
+
474
+
/* Register all pins as GPIOs if there are no ADC channels */
475
+
if (ret == -ENOENT)
476
+
goto register_gpios;
477
+
478
+
if (ret < 0)
479
+
return ret;
480
+
481
+
iio_dev->num_channels = ret;
482
+
iio_dev->channels = cs;
483
+
484
+
for (i = 0; i < iio_dev->num_channels; i++)
485
+
cs[i].datasheet_name = bd79112_chan_names[cs[i].channel];
486
+
487
+
iio_dev->info = &bd79112_info;
488
+
iio_dev->name = "bd79112";
489
+
iio_dev->modes = INDIO_DIRECT_MODE;
490
+
491
+
/*
492
+
* Ensure all channels are ADCs. This allows us to register the IIO
493
+
* device early (before checking which pins are to be used for GPIO)
494
+
* without having to worry about some pins being initially used for
495
+
* GPIO.
496
+
*/
497
+
for (i = 0; i < BD79112_NUM_GPIO_EN_REGS; i++) {
498
+
ret = regmap_write(data->map, BD79112_FIRST_GPIO_EN_REG + i, 0);
499
+
if (ret)
500
+
return dev_err_probe(dev, ret,
501
+
"Failed to initialize channels\n");
502
+
}
503
+
504
+
ret = devm_iio_device_register(data->dev, iio_dev);
505
+
if (ret)
506
+
return dev_err_probe(data->dev, ret, "Failed to register ADC\n");
507
+
508
+
register_gpios:
509
+
gpio_pins = bd79112_get_gpio_pins(iio_dev->channels,
510
+
iio_dev->num_channels);
511
+
512
+
/* If all channels are reserved for ADC, then we're done. */
513
+
if (!gpio_pins)
514
+
return 0;
515
+
516
+
/* Default all the GPIO pins to GPI */
517
+
for_each_set_bit(pin, &gpio_pins, BD79112_MAX_NUM_CHANNELS) {
518
+
ret = bd79112_gpio_dir_set(data, pin, GPIO_LINE_DIRECTION_IN);
519
+
if (ret)
520
+
return dev_err_probe(dev, ret,
521
+
"Failed to mark pin as GPI\n");
522
+
}
523
+
524
+
data->gpio_valid_mask = gpio_pins;
525
+
data->gc = bd79112_gpio_chip;
526
+
data->gc.parent = dev;
527
+
528
+
return devm_gpiochip_add_data(dev, &data->gc, data);
529
+
}
530
+
531
+
static const struct of_device_id bd79112_of_match[] = {
532
+
{ .compatible = "rohm,bd79112" },
533
+
{ }
534
+
};
535
+
MODULE_DEVICE_TABLE(of, bd79112_of_match);
536
+
537
+
static const struct spi_device_id bd79112_id[] = {
538
+
{ "bd79112" },
539
+
{ }
540
+
};
541
+
MODULE_DEVICE_TABLE(spi, bd79112_id);
542
+
543
+
static struct spi_driver bd79112_driver = {
544
+
.driver = {
545
+
.name = "bd79112",
546
+
.of_match_table = bd79112_of_match,
547
+
},
548
+
.probe = bd79112_probe,
549
+
.id_table = bd79112_id,
550
+
};
551
+
module_spi_driver(bd79112_driver);
552
+
553
+
MODULE_AUTHOR("Matti Vaittinen <mazziesaccount@gmail.com>");
554
+
MODULE_DESCRIPTION("Driver for ROHM BD79112 ADC/GPIO");
555
+
MODULE_LICENSE("GPL");
556
+
MODULE_IMPORT_NS("IIO_DRIVER");