Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Peter Anvin:
"Trying again to get the fixes queue, including the fixed IDT alignment
patch.
The UEFI patch is by far the biggest issue at hand: it is currently
causing quite a few machines to boot. Which is sad, because the only
reason they would is because their BIOSes touch memory that has
already been freed. The other major issue is that we finally have
tracked down the root cause of a significant number of machines
failing to suspend/resume"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86: Make sure IDT is page aligned
x86, suspend: Handle CPUs which fail to #GP on RDMSR
x86/platform/ce4100: Add header file for reboot type
Revert "UEFI: Don't pass boot services regions to SetVirtualAddressMap()"
efivars: check for EFI_RUNTIME_SERVICES
+28
-34
+16
-2
arch/x86/kernel/acpi/sleep.c
+16
-2
arch/x86/kernel/acpi/sleep.c
···
48
48
#ifndef CONFIG_64BIT
49
49
native_store_gdt((struct desc_ptr *)&header->pmode_gdt);
50
50
51
+
/*
52
+
* We have to check that we can write back the value, and not
53
+
* just read it. At least on 90 nm Pentium M (Family 6, Model
54
+
* 13), reading an invalid MSR is not guaranteed to trap, see
55
+
* Erratum X4 in "Intel Pentium M Processor on 90 nm Process
56
+
* with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90
57
+
* nm process with 512-KB L2 Cache Specification Update".
58
+
*/
51
59
if (!rdmsr_safe(MSR_EFER,
52
60
&header->pmode_efer_low,
53
-
&header->pmode_efer_high))
61
+
&header->pmode_efer_high) &&
62
+
!wrmsr_safe(MSR_EFER,
63
+
header->pmode_efer_low,
64
+
header->pmode_efer_high))
54
65
header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
55
66
#endif /* !CONFIG_64BIT */
56
67
···
72
61
}
73
62
if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
74
63
&header->pmode_misc_en_low,
75
-
&header->pmode_misc_en_high))
64
+
&header->pmode_misc_en_high) &&
65
+
!wrmsr_safe(MSR_IA32_MISC_ENABLE,
66
+
header->pmode_misc_en_low,
67
+
header->pmode_misc_en_high))
76
68
header->pmode_behavior |=
77
69
(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
78
70
header->realmode_flags = acpi_realmode_flags;
-15
arch/x86/kernel/head_64.S
-15
arch/x86/kernel/head_64.S
···
512
512
513
513
#include "../../x86/xen/xen-head.S"
514
514
515
-
.section .bss, "aw", @nobits
516
-
.align L1_CACHE_BYTES
517
-
ENTRY(idt_table)
518
-
.skip IDT_ENTRIES * 16
519
-
520
-
.align L1_CACHE_BYTES
521
-
ENTRY(debug_idt_table)
522
-
.skip IDT_ENTRIES * 16
523
-
524
-
#ifdef CONFIG_TRACING
525
-
.align L1_CACHE_BYTES
526
-
ENTRY(trace_idt_table)
527
-
.skip IDT_ENTRIES * 16
528
-
#endif
529
-
530
515
__PAGE_ALIGNED_BSS
531
516
NEXT_PAGE(empty_zero_page)
532
517
.skip PAGE_SIZE
+2
-4
arch/x86/kernel/tracepoint.c
+2
-4
arch/x86/kernel/tracepoint.c
···
12
12
struct desc_ptr trace_idt_descr = { NR_VECTORS * 16 - 1,
13
13
(unsigned long) trace_idt_table };
14
14
15
-
#ifndef CONFIG_X86_64
16
-
gate_desc trace_idt_table[NR_VECTORS] __page_aligned_data
17
-
= { { { { 0, 0 } } }, };
18
-
#endif
15
+
/* No need to be aligned, but done to keep all IDTs defined the same way. */
16
+
gate_desc trace_idt_table[NR_VECTORS] __page_aligned_bss;
19
17
20
18
static int trace_irq_vector_refcount;
21
19
static DEFINE_MUTEX(irq_vector_mutex);
+6
-6
arch/x86/kernel/traps.c
+6
-6
arch/x86/kernel/traps.c
···
63
63
#include <asm/x86_init.h>
64
64
#include <asm/pgalloc.h>
65
65
#include <asm/proto.h>
66
+
67
+
/* No need to be aligned, but done to keep all IDTs defined the same way. */
68
+
gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss;
66
69
#else
67
70
#include <asm/processor-flags.h>
68
71
#include <asm/setup.h>
69
72
70
73
asmlinkage int system_call(void);
71
-
72
-
/*
73
-
* The IDT has to be page-aligned to simplify the Pentium
74
-
* F0 0F bug workaround.
75
-
*/
76
-
gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
77
74
#endif
75
+
76
+
/* Must be page-aligned because the real IDT is used in a fixmap. */
77
+
gate_desc idt_table[NR_VECTORS] __page_aligned_bss;
78
78
79
79
DECLARE_BITMAP(used_vectors, NR_VECTORS);
80
80
EXPORT_SYMBOL_GPL(used_vectors);
+1
arch/x86/platform/ce4100/ce4100.c
+1
arch/x86/platform/ce4100/ce4100.c
-7
arch/x86/platform/efi/efi.c
-7
arch/x86/platform/efi/efi.c
···
931
931
va = efi_ioremap(md->phys_addr, size,
932
932
md->type, md->attribute);
933
933
934
-
if (!(md->attribute & EFI_MEMORY_RUNTIME)) {
935
-
if (!va)
936
-
pr_err("ioremap of 0x%llX failed!\n",
937
-
(unsigned long long)md->phys_addr);
938
-
continue;
939
-
}
940
-
941
934
md->virt_addr = (u64) (unsigned long) va;
942
935
943
936
if (!va) {