Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-msm-next-2025-11-18' of https://gitlab.freedesktop.org/drm/msm into drm-next
Changes for v6.19:
GPU:
- Gen8 support: A840 (Kaanapali) and X2-85 (Glymur)
- A612 support
- A few NULL check fixes
MDSS:
- Added support for Glymur and QCS8300 platforms
DPU:
- Enabled Quad-Pipe support, unlocking higher resolutions support
- Added support for Glymur platform
- Documented DPU on QCS8300 platform as supported
- Misc small fixes
DisplayPort:
- Added support for Glymur platform
- Added support lame remapping inside DP block
- Documented DisplayPort controller on QCS8300 and SM6150/QCS615 as
supported
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV00sFi65XrZipHCU3C0bYji7vgu7OgWvLeOQ1Cg475_pUA@mail.gmail.com
+7344
-2252
+16
-1
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+16
-1
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
···
18
18
compatible:
19
19
oneOf:
20
20
- enum:
21
+
- qcom,glymur-dp
21
22
- qcom,sa8775p-dp
22
23
- qcom,sc7180-dp
23
24
- qcom,sc7280-dp
···
31
30
- qcom,sm8350-dp
32
31
- qcom,sm8650-dp
33
32
- qcom,x1e80100-dp
33
+
34
+
- items:
35
+
- enum:
36
+
- qcom,qcs8300-dp
37
+
- const: qcom,sa8775p-dp
34
38
35
39
- items:
36
40
- enum:
···
57
51
- qcom,sm8250-dp
58
52
- qcom,sm8450-dp
59
53
- qcom,sm8550-dp
54
+
- const: qcom,sm8350-dp
55
+
56
+
- items:
57
+
- enum:
58
+
- qcom,sm6150-dp
59
+
- const: qcom,sm8150-dp
60
60
- const: qcom,sm8350-dp
61
61
62
62
- items:
···
207
195
compatible:
208
196
contains:
209
197
enum:
198
+
- qcom,glymur-dp
210
199
- qcom,sa8775p-dp
211
200
- qcom,x1e80100-dp
212
201
then:
202
+
$ref: /schemas/sound/dai-common.yaml#
213
203
oneOf:
214
204
- required:
215
205
- aux-bus
···
253
239
enum:
254
240
# these platforms support 2 streams MST on some interfaces,
255
241
# others are SST only
242
+
- qcom,glymur-dp
256
243
- qcom,sc8280xp-dp
257
244
- qcom,x1e80100-dp
258
245
then:
···
310
295
minItems: 6
311
296
maxItems: 8
312
297
313
-
additionalProperties: false
298
+
unevaluatedProperties: false
314
299
315
300
examples:
316
301
- |
+59
-1
Documentation/devicetree/bindings/display/msm/gmu.yaml
+59
-1
Documentation/devicetree/bindings/display/msm/gmu.yaml
···
21
21
compatible:
22
22
oneOf:
23
23
- items:
24
-
- pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
24
+
- pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
25
25
- const: qcom,adreno-gmu
26
26
- items:
27
27
- pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
···
298
298
299
299
required:
300
300
- qcom,qmp
301
+
302
+
- if:
303
+
properties:
304
+
compatible:
305
+
contains:
306
+
const: qcom,adreno-gmu-840.1
307
+
then:
308
+
properties:
309
+
reg:
310
+
items:
311
+
- description: Core GMU registers
312
+
reg-names:
313
+
items:
314
+
- const: gmu
315
+
clocks:
316
+
items:
317
+
- description: GPU AHB clock
318
+
- description: GMU clock
319
+
- description: GPU CX clock
320
+
- description: GPU MEMNOC clock
321
+
- description: GMU HUB clock
322
+
clock-names:
323
+
items:
324
+
- const: ahb
325
+
- const: gmu
326
+
- const: cxo
327
+
- const: memnoc
328
+
- const: hub
329
+
330
+
- if:
331
+
properties:
332
+
compatible:
333
+
contains:
334
+
const: qcom,adreno-gmu-x285.1
335
+
then:
336
+
properties:
337
+
reg:
338
+
items:
339
+
- description: Core GMU registers
340
+
reg-names:
341
+
items:
342
+
- const: gmu
343
+
clocks:
344
+
items:
345
+
- description: GPU AHB clock
346
+
- description: GMU clock
347
+
- description: GPU CX clock
348
+
- description: GPU MEMNOC clock
349
+
- description: GMU HUB clock
350
+
- description: GMU RSCC HUB clock
351
+
clock-names:
352
+
items:
353
+
- const: ahb
354
+
- const: gmu
355
+
- const: cxo
356
+
- const: memnoc
357
+
- const: hub
358
+
- const: rscc
301
359
302
360
- if:
303
361
properties:
+264
Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml
+264
Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Glymur Display MDSS
8
+
9
+
maintainers:
10
+
- Abel Vesa <abel.vesa@linaro.org>
11
+
12
+
description:
13
+
Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14
+
DPU display controller, DP interfaces, etc.
15
+
16
+
$ref: /schemas/display/msm/mdss-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,glymur-mdss
21
+
22
+
clocks:
23
+
items:
24
+
- description: Display AHB
25
+
- description: Display hf AXI
26
+
- description: Display core
27
+
28
+
iommus:
29
+
maxItems: 1
30
+
31
+
interconnects:
32
+
items:
33
+
- description: Interconnect path from mdp0 port to the data bus
34
+
- description: Interconnect path from CPU to the reg bus
35
+
36
+
interconnect-names:
37
+
items:
38
+
- const: mdp0-mem
39
+
- const: cpu-cfg
40
+
41
+
patternProperties:
42
+
"^display-controller@[0-9a-f]+$":
43
+
type: object
44
+
additionalProperties: true
45
+
properties:
46
+
compatible:
47
+
const: qcom,glymur-dpu
48
+
49
+
"^displayport-controller@[0-9a-f]+$":
50
+
type: object
51
+
additionalProperties: true
52
+
properties:
53
+
compatible:
54
+
const: qcom,glymur-dp
55
+
56
+
"^phy@[0-9a-f]+$":
57
+
type: object
58
+
additionalProperties: true
59
+
properties:
60
+
compatible:
61
+
const: qcom,glymur-dp-phy
62
+
63
+
required:
64
+
- compatible
65
+
66
+
unevaluatedProperties: false
67
+
68
+
examples:
69
+
- |
70
+
#include <dt-bindings/clock/qcom,rpmh.h>
71
+
#include <dt-bindings/interconnect/qcom,icc.h>
72
+
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
73
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
74
+
#include <dt-bindings/phy/phy-qcom-qmp.h>
75
+
#include <dt-bindings/power/qcom,rpmhpd.h>
76
+
77
+
display-subsystem@ae00000 {
78
+
compatible = "qcom,glymur-mdss";
79
+
reg = <0x0ae00000 0x1000>;
80
+
reg-names = "mdss";
81
+
82
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
83
+
84
+
clocks = <&dispcc_ahb_clk>,
85
+
<&gcc_disp_hf_axi_clk>,
86
+
<&dispcc_mdp_clk>;
87
+
clock-names = "bus", "nrt_bus", "core";
88
+
89
+
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
90
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
91
+
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
92
+
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
93
+
interconnect-names = "mdp0-mem",
94
+
"cpu-cfg";
95
+
96
+
resets = <&disp_cc_mdss_core_bcr>;
97
+
98
+
power-domains = <&mdss_gdsc>;
99
+
100
+
iommus = <&apps_smmu 0x1c00 0x2>;
101
+
102
+
interrupt-controller;
103
+
#interrupt-cells = <1>;
104
+
105
+
#address-cells = <1>;
106
+
#size-cells = <1>;
107
+
ranges;
108
+
109
+
display-controller@ae01000 {
110
+
compatible = "qcom,glymur-dpu";
111
+
reg = <0x0ae01000 0x8f000>,
112
+
<0x0aeb0000 0x2008>;
113
+
reg-names = "mdp", "vbif";
114
+
115
+
clocks = <&gcc_axi_clk>,
116
+
<&dispcc_ahb_clk>,
117
+
<&dispcc_mdp_lut_clk>,
118
+
<&dispcc_mdp_clk>,
119
+
<&dispcc_mdp_vsync_clk>;
120
+
clock-names = "nrt_bus",
121
+
"iface",
122
+
"lut",
123
+
"core",
124
+
"vsync";
125
+
126
+
assigned-clocks = <&dispcc_mdp_vsync_clk>;
127
+
assigned-clock-rates = <19200000>;
128
+
129
+
operating-points-v2 = <&mdp_opp_table>;
130
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
131
+
132
+
interrupt-parent = <&mdss>;
133
+
interrupts = <0>;
134
+
135
+
ports {
136
+
#address-cells = <1>;
137
+
#size-cells = <0>;
138
+
139
+
port@0 {
140
+
reg = <0>;
141
+
dpu_intf1_out: endpoint {
142
+
remote-endpoint = <&dsi0_in>;
143
+
};
144
+
};
145
+
146
+
port@1 {
147
+
reg = <1>;
148
+
dpu_intf2_out: endpoint {
149
+
remote-endpoint = <&dsi1_in>;
150
+
};
151
+
};
152
+
};
153
+
154
+
mdp_opp_table: opp-table {
155
+
compatible = "operating-points-v2";
156
+
157
+
opp-200000000 {
158
+
opp-hz = /bits/ 64 <200000000>;
159
+
required-opps = <&rpmhpd_opp_low_svs>;
160
+
};
161
+
162
+
opp-325000000 {
163
+
opp-hz = /bits/ 64 <325000000>;
164
+
required-opps = <&rpmhpd_opp_svs>;
165
+
};
166
+
167
+
opp-375000000 {
168
+
opp-hz = /bits/ 64 <375000000>;
169
+
required-opps = <&rpmhpd_opp_svs_l1>;
170
+
};
171
+
172
+
opp-514000000 {
173
+
opp-hz = /bits/ 64 <514000000>;
174
+
required-opps = <&rpmhpd_opp_nom>;
175
+
};
176
+
};
177
+
};
178
+
179
+
displayport-controller@ae90000 {
180
+
compatible = "qcom,glymur-dp";
181
+
reg = <0xae90000 0x200>,
182
+
<0xae90200 0x200>,
183
+
<0xae90400 0x600>,
184
+
<0xae91000 0x400>,
185
+
<0xae91400 0x400>;
186
+
187
+
interrupt-parent = <&mdss>;
188
+
interrupts = <12>;
189
+
190
+
clocks = <&dispcc_mdss_ahb_clk>,
191
+
<&dispcc_dptx0_aux_clk>,
192
+
<&dispcc_dptx0_link_clk>,
193
+
<&dispcc_dptx0_link_intf_clk>,
194
+
<&dispcc_dptx0_pixel0_clk>,
195
+
<&dispcc_dptx0_pixel1_clk>;
196
+
clock-names = "core_iface",
197
+
"core_aux",
198
+
"ctrl_link",
199
+
"ctrl_link_iface",
200
+
"stream_pixel",
201
+
"stream_1_pixel";
202
+
203
+
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
204
+
<&dispcc_mdss_dptx0_pixel0_clk_src>,
205
+
<&dispcc_mdss_dptx0_pixel1_clk_src>;
206
+
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
207
+
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
208
+
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
209
+
210
+
operating-points-v2 = <&mdss_dp0_opp_table>;
211
+
212
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
213
+
214
+
phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
215
+
phy-names = "dp";
216
+
217
+
#sound-dai-cells = <0>;
218
+
219
+
ports {
220
+
#address-cells = <1>;
221
+
#size-cells = <0>;
222
+
223
+
port@0 {
224
+
reg = <0>;
225
+
226
+
mdss_dp0_in: endpoint {
227
+
remote-endpoint = <&mdss_intf0_out>;
228
+
};
229
+
};
230
+
231
+
port@1 {
232
+
reg = <1>;
233
+
234
+
mdss_dp0_out: endpoint {
235
+
};
236
+
};
237
+
};
238
+
239
+
mdss_dp0_opp_table: opp-table {
240
+
compatible = "operating-points-v2";
241
+
242
+
opp-160000000 {
243
+
opp-hz = /bits/ 64 <160000000>;
244
+
required-opps = <&rpmhpd_opp_low_svs>;
245
+
};
246
+
247
+
opp-270000000 {
248
+
opp-hz = /bits/ 64 <270000000>;
249
+
required-opps = <&rpmhpd_opp_svs>;
250
+
};
251
+
252
+
opp-540000000 {
253
+
opp-hz = /bits/ 64 <540000000>;
254
+
required-opps = <&rpmhpd_opp_svs_l1>;
255
+
};
256
+
257
+
opp-810000000 {
258
+
opp-hz = /bits/ 64 <810000000>;
259
+
required-opps = <&rpmhpd_opp_nom>;
260
+
};
261
+
};
262
+
};
263
+
};
264
+
...
+286
Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
+286
Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. QCS8300 Display MDSS
8
+
9
+
maintainers:
10
+
- Yongxing Mou <yongxing.mou@oss.qualcomm.com>
11
+
12
+
description:
13
+
QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14
+
DPU display controller, DP interfaces and EDP etc.
15
+
16
+
$ref: /schemas/display/msm/mdss-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,qcs8300-mdss
21
+
22
+
clocks:
23
+
items:
24
+
- description: Display AHB
25
+
- description: Display hf AXI
26
+
- description: Display core
27
+
28
+
iommus:
29
+
maxItems: 1
30
+
31
+
interconnects:
32
+
maxItems: 3
33
+
34
+
interconnect-names:
35
+
maxItems: 3
36
+
37
+
patternProperties:
38
+
"^display-controller@[0-9a-f]+$":
39
+
type: object
40
+
additionalProperties: true
41
+
42
+
properties:
43
+
compatible:
44
+
contains:
45
+
const: qcom,qcs8300-dpu
46
+
47
+
"^displayport-controller@[0-9a-f]+$":
48
+
type: object
49
+
additionalProperties: true
50
+
51
+
properties:
52
+
compatible:
53
+
contains:
54
+
const: qcom,qcs8300-dp
55
+
56
+
"^phy@[0-9a-f]+$":
57
+
type: object
58
+
additionalProperties: true
59
+
properties:
60
+
compatible:
61
+
contains:
62
+
const: qcom,qcs8300-edp-phy
63
+
64
+
required:
65
+
- compatible
66
+
67
+
unevaluatedProperties: false
68
+
69
+
examples:
70
+
- |
71
+
#include <dt-bindings/interconnect/qcom,icc.h>
72
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
73
+
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
74
+
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
75
+
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
76
+
#include <dt-bindings/power/qcom,rpmhpd.h>
77
+
#include <dt-bindings/power/qcom-rpmpd.h>
78
+
79
+
mdss: display-subsystem@ae00000 {
80
+
compatible = "qcom,qcs8300-mdss";
81
+
reg = <0x0ae00000 0x1000>;
82
+
reg-names = "mdss";
83
+
84
+
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
85
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
86
+
<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
87
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
88
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
89
+
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
90
+
interconnect-names = "mdp0-mem",
91
+
"mdp1-mem",
92
+
"cpu-cfg";
93
+
94
+
resets = <&dispcc_core_bcr>;
95
+
power-domains = <&dispcc_gdsc>;
96
+
97
+
clocks = <&dispcc_ahb_clk>,
98
+
<&gcc GCC_DISP_HF_AXI_CLK>,
99
+
<&dispcc_mdp_clk>;
100
+
101
+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
102
+
interrupt-controller;
103
+
#interrupt-cells = <1>;
104
+
105
+
iommus = <&apps_smmu 0x1000 0x402>;
106
+
107
+
#address-cells = <1>;
108
+
#size-cells = <1>;
109
+
ranges;
110
+
111
+
display-controller@ae01000 {
112
+
compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";
113
+
reg = <0x0ae01000 0x8f000>,
114
+
<0x0aeb0000 0x2008>;
115
+
reg-names = "mdp", "vbif";
116
+
117
+
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
118
+
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
119
+
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
120
+
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
121
+
<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
122
+
clock-names = "nrt_bus",
123
+
"iface",
124
+
"lut",
125
+
"core",
126
+
"vsync";
127
+
128
+
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
129
+
assigned-clock-rates = <19200000>;
130
+
operating-points-v2 = <&mdp_opp_table>;
131
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
132
+
133
+
interrupt-parent = <&mdss>;
134
+
interrupts = <0>;
135
+
ports {
136
+
#address-cells = <1>;
137
+
#size-cells = <0>;
138
+
port@0 {
139
+
reg = <0>;
140
+
141
+
dpu_intf0_out: endpoint {
142
+
remote-endpoint = <&mdss_dp0_in>;
143
+
};
144
+
};
145
+
};
146
+
147
+
mdp_opp_table: opp-table {
148
+
compatible = "operating-points-v2";
149
+
150
+
opp-375000000 {
151
+
opp-hz = /bits/ 64 <375000000>;
152
+
required-opps = <&rpmhpd_opp_svs_l1>;
153
+
};
154
+
155
+
opp-500000000 {
156
+
opp-hz = /bits/ 64 <500000000>;
157
+
required-opps = <&rpmhpd_opp_nom>;
158
+
};
159
+
160
+
opp-575000000 {
161
+
opp-hz = /bits/ 64 <575000000>;
162
+
required-opps = <&rpmhpd_opp_turbo>;
163
+
};
164
+
165
+
opp-650000000 {
166
+
opp-hz = /bits/ 64 <650000000>;
167
+
required-opps = <&rpmhpd_opp_turbo_l1>;
168
+
};
169
+
};
170
+
};
171
+
172
+
mdss_dp0_phy: phy@aec2a00 {
173
+
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
174
+
175
+
reg = <0x0aec2a00 0x200>,
176
+
<0x0aec2200 0xd0>,
177
+
<0x0aec2600 0xd0>,
178
+
<0x0aec2000 0x1c8>;
179
+
180
+
clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
181
+
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
182
+
clock-names = "aux",
183
+
"cfg_ahb";
184
+
185
+
#clock-cells = <1>;
186
+
#phy-cells = <0>;
187
+
188
+
vdda-phy-supply = <&vreg_l1c>;
189
+
vdda-pll-supply = <&vreg_l4a>;
190
+
};
191
+
192
+
displayport-controller@af54000 {
193
+
compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp";
194
+
195
+
pinctrl-0 = <&dp_hot_plug_det>;
196
+
pinctrl-names = "default";
197
+
198
+
reg = <0xaf54000 0x104>,
199
+
<0xaf54200 0x0c0>,
200
+
<0xaf55000 0x770>,
201
+
<0xaf56000 0x09c>,
202
+
<0xaf57000 0x09c>,
203
+
<0xaf58000 0x09c>,
204
+
<0xaf59000 0x09c>,
205
+
<0xaf5a000 0x23c>,
206
+
<0xaf5b000 0x23c>;
207
+
208
+
interrupt-parent = <&mdss>;
209
+
interrupts = <12>;
210
+
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
211
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
212
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
213
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
214
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
215
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
216
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
217
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
218
+
clock-names = "core_iface",
219
+
"core_aux",
220
+
"ctrl_link",
221
+
"ctrl_link_iface",
222
+
"stream_pixel",
223
+
"stream_1_pixel",
224
+
"stream_2_pixel",
225
+
"stream_3_pixel";
226
+
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
227
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
228
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
229
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
230
+
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
231
+
assigned-clock-parents = <&mdss_dp0_phy 0>,
232
+
<&mdss_dp0_phy 1>,
233
+
<&mdss_dp0_phy 1>,
234
+
<&mdss_dp0_phy 1>;
235
+
phys = <&mdss_dp0_phy>;
236
+
phy-names = "dp";
237
+
operating-points-v2 = <&dp_opp_table>;
238
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
239
+
240
+
#sound-dai-cells = <0>;
241
+
242
+
ports {
243
+
#address-cells = <1>;
244
+
#size-cells = <0>;
245
+
246
+
port@0 {
247
+
reg = <0>;
248
+
249
+
mdss_dp0_in: endpoint {
250
+
remote-endpoint = <&dpu_intf0_out>;
251
+
};
252
+
};
253
+
254
+
port@1 {
255
+
reg = <1>;
256
+
257
+
mdss_dp_out: endpoint { };
258
+
};
259
+
};
260
+
261
+
dp_opp_table: opp-table {
262
+
compatible = "operating-points-v2";
263
+
264
+
opp-160000000 {
265
+
opp-hz = /bits/ 64 <160000000>;
266
+
required-opps = <&rpmhpd_opp_low_svs>;
267
+
};
268
+
269
+
opp-270000000 {
270
+
opp-hz = /bits/ 64 <270000000>;
271
+
required-opps = <&rpmhpd_opp_svs>;
272
+
};
273
+
274
+
opp-540000000 {
275
+
opp-hz = /bits/ 64 <540000000>;
276
+
required-opps = <&rpmhpd_opp_svs_l1>;
277
+
};
278
+
279
+
opp-810000000 {
280
+
opp-hz = /bits/ 64 <810000000>;
281
+
required-opps = <&rpmhpd_opp_nom>;
282
+
};
283
+
};
284
+
};
285
+
};
286
+
...
+25
-15
Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
+25
-15
Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
···
51
51
compatible:
52
52
const: qcom,sm6150-dpu
53
53
54
+
"^displayport-controller@[0-9a-f]+$":
55
+
type: object
56
+
additionalProperties: true
57
+
properties:
58
+
compatible:
59
+
contains:
60
+
const: qcom,sm6150-dp
61
+
54
62
"^dsi@[0-9a-f]+$":
55
63
type: object
56
64
additionalProperties: true
···
138
130
#size-cells = <0>;
139
131
140
132
port@0 {
141
-
reg = <0>;
142
-
dpu_intf0_out: endpoint {
143
-
};
133
+
reg = <0>;
134
+
135
+
dpu_intf0_out: endpoint {
136
+
};
144
137
};
145
138
146
139
port@1 {
147
-
reg = <1>;
148
-
dpu_intf1_out: endpoint {
149
-
remote-endpoint = <&mdss_dsi0_in>;
150
-
};
140
+
reg = <1>;
141
+
142
+
dpu_intf1_out: endpoint {
143
+
remote-endpoint = <&mdss_dsi0_in>;
144
+
};
151
145
};
152
146
};
153
147
154
148
mdp_opp_table: opp-table {
155
149
compatible = "operating-points-v2";
156
150
157
-
opp-19200000 {
158
-
opp-hz = /bits/ 64 <19200000>;
159
-
required-opps = <&rpmhpd_opp_low_svs>;
151
+
opp-192000000 {
152
+
opp-hz = /bits/ 64 <192000000>;
153
+
required-opps = <&rpmhpd_opp_low_svs>;
160
154
};
161
155
162
-
opp-25600000 {
163
-
opp-hz = /bits/ 64 <25600000>;
164
-
required-opps = <&rpmhpd_opp_svs>;
156
+
opp-256000000 {
157
+
opp-hz = /bits/ 64 <256000000>;
158
+
required-opps = <&rpmhpd_opp_svs>;
165
159
};
166
160
167
161
opp-307200000 {
168
-
opp-hz = /bits/ 64 <307200000>;
169
-
required-opps = <&rpmhpd_opp_nom>;
162
+
opp-hz = /bits/ 64 <307200000>;
163
+
required-opps = <&rpmhpd_opp_nom>;
170
164
};
171
165
};
172
166
};
+11
-5
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+11
-5
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
···
13
13
14
14
properties:
15
15
compatible:
16
-
enum:
17
-
- qcom,sa8775p-dpu
18
-
- qcom,sm8650-dpu
19
-
- qcom,sm8750-dpu
20
-
- qcom,x1e80100-dpu
16
+
oneOf:
17
+
- enum:
18
+
- qcom,glymur-dpu
19
+
- qcom,sa8775p-dpu
20
+
- qcom,sm8650-dpu
21
+
- qcom,sm8750-dpu
22
+
- qcom,x1e80100-dpu
23
+
- items:
24
+
- enum:
25
+
- qcom,qcs8300-dpu
26
+
- const: qcom,sa8775p-dpu
21
27
22
28
reg:
23
29
items:
+2
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+2
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+1
MAINTAINERS
+1
MAINTAINERS
···
7887
7887
M: Rob Clark <robin.clark@oss.qualcomm.com>
7888
7888
R: Sean Paul <sean@poorly.run>
7889
7889
R: Konrad Dybcio <konradybcio@kernel.org>
7890
+
R: Akhil P Oommen <akhilpo@oss.qualcomm.com>
7890
7891
L: linux-arm-msm@vger.kernel.org
7891
7892
L: dri-devel@lists.freedesktop.org
7892
7893
L: freedreno@lists.freedesktop.org
+2
drivers/gpu/drm/msm/Makefile
+2
drivers/gpu/drm/msm/Makefile
···
24
24
adreno/a6xx_gmu.o \
25
25
adreno/a6xx_hfi.o \
26
26
adreno/a6xx_preempt.o \
27
+
adreno/a8xx_gpu.o \
27
28
28
29
adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
29
30
···
202
201
generated/a6xx_perfcntrs.xml.h \
203
202
generated/a7xx_enums.xml.h \
204
203
generated/a7xx_perfcntrs.xml.h \
204
+
generated/a8xx_enums.xml.h \
205
205
generated/a6xx_gmu.xml.h \
206
206
generated/adreno_common.xml.h \
207
207
generated/adreno_pm4.xml.h \
+4
-3
drivers/gpu/drm/msm/adreno/a2xx_catalog.c
+4
-3
drivers/gpu/drm/msm/adreno/a2xx_catalog.c
···
7
7
*/
8
8
9
9
#include "adreno_gpu.h"
10
+
#include "a2xx_gpu.h"
10
11
11
12
static const struct adreno_info a2xx_gpus[] = {
12
13
{
···
20
19
},
21
20
.gmem = SZ_256K,
22
21
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
23
-
.init = a2xx_gpu_init,
22
+
.funcs = &a2xx_gpu_funcs,
24
23
}, { /* a200 on i.mx51 has only 128kib gmem */
25
24
.chip_ids = ADRENO_CHIP_IDS(0x02000001),
26
25
.family = ADRENO_2XX_GEN1,
···
31
30
},
32
31
.gmem = SZ_128K,
33
32
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
34
-
.init = a2xx_gpu_init,
33
+
.funcs = &a2xx_gpu_funcs,
35
34
}, {
36
35
.chip_ids = ADRENO_CHIP_IDS(0x02020000),
37
36
.family = ADRENO_2XX_GEN2,
···
42
41
},
43
42
.gmem = SZ_512K,
44
43
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
45
-
.init = a2xx_gpu_init,
44
+
.funcs = &a2xx_gpu_funcs,
46
45
}
47
46
};
48
47
DECLARE_ADRENO_GPULIST(a2xx);
+27
-25
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+27
-25
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
···
234
234
* word (0x20xxxx for A200, 0x220xxx for A220, 0x225xxx for A225).
235
235
* Older firmware files, which lack protection support, have 0 instead.
236
236
*/
237
-
if (ptr[1] == 0) {
237
+
if (ptr[1] == 0 && !a2xx_gpu->protection_disabled) {
238
238
dev_warn(gpu->dev->dev,
239
239
"Legacy firmware detected, disabling protection support\n");
240
240
a2xx_gpu->protection_disabled = true;
···
486
486
return ring->memptrs->rptr;
487
487
}
488
488
489
-
static const struct adreno_gpu_funcs funcs = {
490
-
.base = {
491
-
.get_param = adreno_get_param,
492
-
.set_param = adreno_set_param,
493
-
.hw_init = a2xx_hw_init,
494
-
.pm_suspend = msm_gpu_pm_suspend,
495
-
.pm_resume = msm_gpu_pm_resume,
496
-
.recover = a2xx_recover,
497
-
.submit = a2xx_submit,
498
-
.active_ring = adreno_active_ring,
499
-
.irq = a2xx_irq,
500
-
.destroy = a2xx_destroy,
501
-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
502
-
.show = adreno_show,
503
-
#endif
504
-
.gpu_state_get = a2xx_gpu_state_get,
505
-
.gpu_state_put = adreno_gpu_state_put,
506
-
.create_vm = a2xx_create_vm,
507
-
.get_rptr = a2xx_get_rptr,
508
-
},
509
-
};
510
-
511
489
static const struct msm_gpu_perfcntr perfcntrs[] = {
512
490
/* TODO */
513
491
};
514
492
515
-
struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
493
+
static struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
516
494
{
517
495
struct a2xx_gpu *a2xx_gpu = NULL;
518
496
struct adreno_gpu *adreno_gpu;
519
497
struct msm_gpu *gpu;
520
498
struct msm_drm_private *priv = dev->dev_private;
521
499
struct platform_device *pdev = priv->gpu_pdev;
500
+
struct adreno_platform_config *config = pdev->dev.platform_data;
522
501
int ret;
523
502
524
503
if (!pdev) {
···
518
539
gpu->perfcntrs = perfcntrs;
519
540
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
520
541
521
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
542
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1);
522
543
if (ret)
523
544
goto fail;
524
545
···
537
558
538
559
return ERR_PTR(ret);
539
560
}
561
+
562
+
const struct adreno_gpu_funcs a2xx_gpu_funcs = {
563
+
.base = {
564
+
.get_param = adreno_get_param,
565
+
.set_param = adreno_set_param,
566
+
.hw_init = a2xx_hw_init,
567
+
.pm_suspend = msm_gpu_pm_suspend,
568
+
.pm_resume = msm_gpu_pm_resume,
569
+
.recover = a2xx_recover,
570
+
.submit = a2xx_submit,
571
+
.active_ring = adreno_active_ring,
572
+
.irq = a2xx_irq,
573
+
.destroy = a2xx_destroy,
574
+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
575
+
.show = adreno_show,
576
+
#endif
577
+
.gpu_state_get = a2xx_gpu_state_get,
578
+
.gpu_state_put = adreno_gpu_state_put,
579
+
.create_vm = a2xx_create_vm,
580
+
.get_rptr = a2xx_get_rptr,
581
+
},
582
+
.init = a2xx_gpu_init,
583
+
};
+2
drivers/gpu/drm/msm/adreno/a2xx_gpu.h
+2
drivers/gpu/drm/msm/adreno/a2xx_gpu.h
···
19
19
};
20
20
#define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base)
21
21
22
+
extern const struct adreno_gpu_funcs a2xx_gpu_funcs;
23
+
22
24
struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu);
23
25
void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
24
26
dma_addr_t *tran_error);
+7
-6
drivers/gpu/drm/msm/adreno/a3xx_catalog.c
+7
-6
drivers/gpu/drm/msm/adreno/a3xx_catalog.c
···
7
7
*/
8
8
9
9
#include "adreno_gpu.h"
10
+
#include "a3xx_gpu.h"
10
11
11
12
static const struct adreno_info a3xx_gpus[] = {
12
13
{
···
19
18
},
20
19
.gmem = SZ_128K,
21
20
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
22
-
.init = a3xx_gpu_init,
21
+
.funcs = &a3xx_gpu_funcs,
23
22
}, {
24
23
.chip_ids = ADRENO_CHIP_IDS(0x03000520),
25
24
.family = ADRENO_3XX,
···
30
29
},
31
30
.gmem = SZ_256K,
32
31
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
33
-
.init = a3xx_gpu_init,
32
+
.funcs = &a3xx_gpu_funcs,
34
33
}, {
35
34
.chip_ids = ADRENO_CHIP_IDS(0x03000600),
36
35
.family = ADRENO_3XX,
···
41
40
},
42
41
.gmem = SZ_128K,
43
42
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
44
-
.init = a3xx_gpu_init,
43
+
.funcs = &a3xx_gpu_funcs,
45
44
}, {
46
45
.chip_ids = ADRENO_CHIP_IDS(0x03000620),
47
46
.family = ADRENO_3XX,
···
52
51
},
53
52
.gmem = SZ_128K,
54
53
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
55
-
.init = a3xx_gpu_init,
54
+
.funcs = &a3xx_gpu_funcs,
56
55
}, {
57
56
.chip_ids = ADRENO_CHIP_IDS(
58
57
0x03020000,
···
67
66
},
68
67
.gmem = SZ_512K,
69
68
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
70
-
.init = a3xx_gpu_init,
69
+
.funcs = &a3xx_gpu_funcs,
71
70
}, {
72
71
.chip_ids = ADRENO_CHIP_IDS(
73
72
0x03030000,
···
82
81
},
83
82
.gmem = SZ_1M,
84
83
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
85
-
.init = a3xx_gpu_init,
84
+
.funcs = &a3xx_gpu_funcs,
86
85
}
87
86
};
88
87
DECLARE_ADRENO_GPULIST(a3xx);
+27
-25
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+27
-25
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
···
508
508
return ring->memptrs->rptr;
509
509
}
510
510
511
-
static const struct adreno_gpu_funcs funcs = {
512
-
.base = {
513
-
.get_param = adreno_get_param,
514
-
.set_param = adreno_set_param,
515
-
.hw_init = a3xx_hw_init,
516
-
.pm_suspend = msm_gpu_pm_suspend,
517
-
.pm_resume = msm_gpu_pm_resume,
518
-
.recover = a3xx_recover,
519
-
.submit = a3xx_submit,
520
-
.active_ring = adreno_active_ring,
521
-
.irq = a3xx_irq,
522
-
.destroy = a3xx_destroy,
523
-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
524
-
.show = adreno_show,
525
-
#endif
526
-
.gpu_busy = a3xx_gpu_busy,
527
-
.gpu_state_get = a3xx_gpu_state_get,
528
-
.gpu_state_put = adreno_gpu_state_put,
529
-
.create_vm = adreno_create_vm,
530
-
.get_rptr = a3xx_get_rptr,
531
-
},
532
-
};
533
-
534
511
static const struct msm_gpu_perfcntr perfcntrs[] = {
535
512
{ REG_A3XX_SP_PERFCOUNTER6_SELECT, REG_A3XX_RBBM_PERFCTR_SP_6_LO,
536
513
SP_ALU_ACTIVE_CYCLES, "ALUACTIVE" },
···
515
538
SP_FS_FULL_ALU_INSTRUCTIONS, "ALUFULL" },
516
539
};
517
540
518
-
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
541
+
static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
519
542
{
520
543
struct a3xx_gpu *a3xx_gpu = NULL;
521
544
struct adreno_gpu *adreno_gpu;
522
545
struct msm_gpu *gpu;
523
546
struct msm_drm_private *priv = dev->dev_private;
524
547
struct platform_device *pdev = priv->gpu_pdev;
548
+
struct adreno_platform_config *config = pdev->dev.platform_data;
525
549
struct icc_path *ocmem_icc_path;
526
550
struct icc_path *icc_path;
527
551
int ret;
···
547
569
548
570
adreno_gpu->registers = a3xx_registers;
549
571
550
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
572
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1);
551
573
if (ret)
552
574
goto fail;
553
575
···
591
613
592
614
return ERR_PTR(ret);
593
615
}
616
+
617
+
const struct adreno_gpu_funcs a3xx_gpu_funcs = {
618
+
.base = {
619
+
.get_param = adreno_get_param,
620
+
.set_param = adreno_set_param,
621
+
.hw_init = a3xx_hw_init,
622
+
.pm_suspend = msm_gpu_pm_suspend,
623
+
.pm_resume = msm_gpu_pm_resume,
624
+
.recover = a3xx_recover,
625
+
.submit = a3xx_submit,
626
+
.active_ring = adreno_active_ring,
627
+
.irq = a3xx_irq,
628
+
.destroy = a3xx_destroy,
629
+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
630
+
.show = adreno_show,
631
+
#endif
632
+
.gpu_busy = a3xx_gpu_busy,
633
+
.gpu_state_get = a3xx_gpu_state_get,
634
+
.gpu_state_put = adreno_gpu_state_put,
635
+
.create_vm = adreno_create_vm,
636
+
.get_rptr = a3xx_get_rptr,
637
+
},
638
+
.init = a3xx_gpu_init,
639
+
};
+2
drivers/gpu/drm/msm/adreno/a3xx_gpu.h
+2
drivers/gpu/drm/msm/adreno/a3xx_gpu.h
+4
-3
drivers/gpu/drm/msm/adreno/a4xx_catalog.c
+4
-3
drivers/gpu/drm/msm/adreno/a4xx_catalog.c
···
7
7
*/
8
8
9
9
#include "adreno_gpu.h"
10
+
#include "a4xx_gpu.h"
10
11
11
12
static const struct adreno_info a4xx_gpus[] = {
12
13
{
···
20
19
},
21
20
.gmem = SZ_256K,
22
21
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
23
-
.init = a4xx_gpu_init,
22
+
.funcs = &a4xx_gpu_funcs,
24
23
}, {
25
24
.chip_ids = ADRENO_CHIP_IDS(0x04020000),
26
25
.family = ADRENO_4XX,
···
31
30
},
32
31
.gmem = (SZ_1M + SZ_512K),
33
32
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
34
-
.init = a4xx_gpu_init,
33
+
.funcs = &a4xx_gpu_funcs,
35
34
}, {
36
35
.chip_ids = ADRENO_CHIP_IDS(0x04030002),
37
36
.family = ADRENO_4XX,
···
42
41
},
43
42
.gmem = (SZ_1M + SZ_512K),
44
43
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
45
-
.init = a4xx_gpu_init,
44
+
.funcs = &a4xx_gpu_funcs,
46
45
}
47
46
};
48
47
DECLARE_ADRENO_GPULIST(a4xx);
+28
-26
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+28
-26
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
···
627
627
return ring->memptrs->rptr;
628
628
}
629
629
630
-
static const struct adreno_gpu_funcs funcs = {
631
-
.base = {
632
-
.get_param = adreno_get_param,
633
-
.set_param = adreno_set_param,
634
-
.hw_init = a4xx_hw_init,
635
-
.pm_suspend = a4xx_pm_suspend,
636
-
.pm_resume = a4xx_pm_resume,
637
-
.recover = a4xx_recover,
638
-
.submit = a4xx_submit,
639
-
.active_ring = adreno_active_ring,
640
-
.irq = a4xx_irq,
641
-
.destroy = a4xx_destroy,
642
-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
643
-
.show = adreno_show,
644
-
#endif
645
-
.gpu_busy = a4xx_gpu_busy,
646
-
.gpu_state_get = a4xx_gpu_state_get,
647
-
.gpu_state_put = adreno_gpu_state_put,
648
-
.create_vm = adreno_create_vm,
649
-
.get_rptr = a4xx_get_rptr,
650
-
},
651
-
.get_timestamp = a4xx_get_timestamp,
652
-
};
653
-
654
-
struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
630
+
static struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
655
631
{
656
632
struct a4xx_gpu *a4xx_gpu = NULL;
657
633
struct adreno_gpu *adreno_gpu;
658
634
struct msm_gpu *gpu;
659
635
struct msm_drm_private *priv = dev->dev_private;
660
636
struct platform_device *pdev = priv->gpu_pdev;
637
+
struct adreno_platform_config *config = pdev->dev.platform_data;
661
638
struct icc_path *ocmem_icc_path;
662
639
struct icc_path *icc_path;
663
640
int ret;
···
657
680
gpu->perfcntrs = NULL;
658
681
gpu->num_perfcntrs = 0;
659
682
660
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
683
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1);
661
684
if (ret)
662
685
goto fail;
663
686
···
703
726
704
727
return ERR_PTR(ret);
705
728
}
729
+
730
+
const struct adreno_gpu_funcs a4xx_gpu_funcs = {
731
+
.base = {
732
+
.get_param = adreno_get_param,
733
+
.set_param = adreno_set_param,
734
+
.hw_init = a4xx_hw_init,
735
+
.pm_suspend = a4xx_pm_suspend,
736
+
.pm_resume = a4xx_pm_resume,
737
+
.recover = a4xx_recover,
738
+
.submit = a4xx_submit,
739
+
.active_ring = adreno_active_ring,
740
+
.irq = a4xx_irq,
741
+
.destroy = a4xx_destroy,
742
+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
743
+
.show = adreno_show,
744
+
#endif
745
+
.gpu_busy = a4xx_gpu_busy,
746
+
.gpu_state_get = a4xx_gpu_state_get,
747
+
.gpu_state_put = adreno_gpu_state_put,
748
+
.create_vm = adreno_create_vm,
749
+
.get_rptr = a4xx_get_rptr,
750
+
},
751
+
.init = a4xx_gpu_init,
752
+
.get_timestamp = a4xx_get_timestamp,
753
+
};
+2
drivers/gpu/drm/msm/adreno/a4xx_gpu.h
+2
drivers/gpu/drm/msm/adreno/a4xx_gpu.h
+9
-8
drivers/gpu/drm/msm/adreno/a5xx_catalog.c
+9
-8
drivers/gpu/drm/msm/adreno/a5xx_catalog.c
···
7
7
*/
8
8
9
9
#include "adreno_gpu.h"
10
+
#include "a5xx_gpu.h"
10
11
11
12
static const struct adreno_info a5xx_gpus[] = {
12
13
{
···
22
21
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
23
22
.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
24
23
ADRENO_QUIRK_LMLOADKILL_DISABLE,
25
-
.init = a5xx_gpu_init,
24
+
.funcs = &a5xx_gpu_funcs,
26
25
}, {
27
26
.chip_ids = ADRENO_CHIP_IDS(0x05000600),
28
27
.family = ADRENO_5XX,
···
39
38
.inactive_period = 250,
40
39
.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
41
40
ADRENO_QUIRK_LMLOADKILL_DISABLE,
42
-
.init = a5xx_gpu_init,
41
+
.funcs = &a5xx_gpu_funcs,
43
42
.zapfw = "a506_zap.mdt",
44
43
}, {
45
44
.chip_ids = ADRENO_CHIP_IDS(0x05000800),
···
56
55
*/
57
56
.inactive_period = 250,
58
57
.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
59
-
.init = a5xx_gpu_init,
58
+
.funcs = &a5xx_gpu_funcs,
60
59
.zapfw = "a508_zap.mdt",
61
60
}, {
62
61
.chip_ids = ADRENO_CHIP_IDS(0x05000900),
···
73
72
*/
74
73
.inactive_period = 250,
75
74
.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
76
-
.init = a5xx_gpu_init,
75
+
.funcs = &a5xx_gpu_funcs,
77
76
/* Adreno 509 uses the same ZAP as 512 */
78
77
.zapfw = "a512_zap.mdt",
79
78
}, {
···
90
89
* the GDSC which appears to make it grumpy
91
90
*/
92
91
.inactive_period = 250,
93
-
.init = a5xx_gpu_init,
92
+
.funcs = &a5xx_gpu_funcs,
94
93
}, {
95
94
.chip_ids = ADRENO_CHIP_IDS(0x05010200),
96
95
.family = ADRENO_5XX,
···
106
105
*/
107
106
.inactive_period = 250,
108
107
.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
109
-
.init = a5xx_gpu_init,
108
+
.funcs = &a5xx_gpu_funcs,
110
109
.zapfw = "a512_zap.mdt",
111
110
}, {
112
111
.chip_ids = ADRENO_CHIP_IDS(
···
128
127
.inactive_period = 250,
129
128
.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
130
129
ADRENO_QUIRK_FAULT_DETECT_MASK,
131
-
.init = a5xx_gpu_init,
130
+
.funcs = &a5xx_gpu_funcs,
132
131
.zapfw = "a530_zap.mdt",
133
132
}, {
134
133
.chip_ids = ADRENO_CHIP_IDS(0x05040001),
···
146
145
*/
147
146
.inactive_period = 250,
148
147
.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
149
-
.init = a5xx_gpu_init,
148
+
.funcs = &a5xx_gpu_funcs,
150
149
.zapfw = "a540_zap.mdt",
151
150
}
152
151
};
+31
-30
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+31
-30
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
···
1691
1691
return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR);
1692
1692
}
1693
1693
1694
-
static const struct adreno_gpu_funcs funcs = {
1695
-
.base = {
1696
-
.get_param = adreno_get_param,
1697
-
.set_param = adreno_set_param,
1698
-
.hw_init = a5xx_hw_init,
1699
-
.ucode_load = a5xx_ucode_load,
1700
-
.pm_suspend = a5xx_pm_suspend,
1701
-
.pm_resume = a5xx_pm_resume,
1702
-
.recover = a5xx_recover,
1703
-
.submit = a5xx_submit,
1704
-
.active_ring = a5xx_active_ring,
1705
-
.irq = a5xx_irq,
1706
-
.destroy = a5xx_destroy,
1707
-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
1708
-
.show = a5xx_show,
1709
-
#endif
1710
-
#if defined(CONFIG_DEBUG_FS)
1711
-
.debugfs_init = a5xx_debugfs_init,
1712
-
#endif
1713
-
.gpu_busy = a5xx_gpu_busy,
1714
-
.gpu_state_get = a5xx_gpu_state_get,
1715
-
.gpu_state_put = a5xx_gpu_state_put,
1716
-
.create_vm = adreno_create_vm,
1717
-
.get_rptr = a5xx_get_rptr,
1718
-
},
1719
-
.get_timestamp = a5xx_get_timestamp,
1720
-
};
1721
-
1722
1694
static void check_speed_bin(struct device *dev)
1723
1695
{
1724
1696
struct nvmem_cell *cell;
···
1723
1751
devm_pm_opp_set_supported_hw(dev, &val, 1);
1724
1752
}
1725
1753
1726
-
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
1754
+
static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
1727
1755
{
1728
1756
struct msm_drm_private *priv = dev->dev_private;
1729
1757
struct platform_device *pdev = priv->gpu_pdev;
···
1753
1781
if (config->info->revn == 510)
1754
1782
nr_rings = 1;
1755
1783
1756
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
1784
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_rings);
1757
1785
if (ret) {
1758
1786
a5xx_destroy(&(a5xx_gpu->base.base));
1759
1787
return ERR_PTR(ret);
···
1778
1806
1779
1807
return gpu;
1780
1808
}
1809
+
1810
+
const struct adreno_gpu_funcs a5xx_gpu_funcs = {
1811
+
.base = {
1812
+
.get_param = adreno_get_param,
1813
+
.set_param = adreno_set_param,
1814
+
.hw_init = a5xx_hw_init,
1815
+
.ucode_load = a5xx_ucode_load,
1816
+
.pm_suspend = a5xx_pm_suspend,
1817
+
.pm_resume = a5xx_pm_resume,
1818
+
.recover = a5xx_recover,
1819
+
.submit = a5xx_submit,
1820
+
.active_ring = a5xx_active_ring,
1821
+
.irq = a5xx_irq,
1822
+
.destroy = a5xx_destroy,
1823
+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
1824
+
.show = a5xx_show,
1825
+
#endif
1826
+
#if defined(CONFIG_DEBUG_FS)
1827
+
.debugfs_init = a5xx_debugfs_init,
1828
+
#endif
1829
+
.gpu_busy = a5xx_gpu_busy,
1830
+
.gpu_state_get = a5xx_gpu_state_get,
1831
+
.gpu_state_put = a5xx_gpu_state_put,
1832
+
.create_vm = adreno_create_vm,
1833
+
.get_rptr = a5xx_get_rptr,
1834
+
},
1835
+
.init = a5xx_gpu_init,
1836
+
.get_timestamp = a5xx_get_timestamp,
1837
+
};
+1
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+1
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+362
-23
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+362
-23
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
···
672
672
};
673
673
DECLARE_ADRENO_PROTECT(a690_protect, 48);
674
674
675
+
static const struct adreno_reglist a640_gbif[] = {
676
+
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 },
677
+
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 },
678
+
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 },
679
+
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 },
680
+
{ },
681
+
};
682
+
675
683
static const struct adreno_info a6xx_gpus[] = {
676
684
{
677
685
.chip_ids = ADRENO_CHIP_IDS(0x06010000),
···
691
683
.gmem = (SZ_128K + SZ_4K),
692
684
.quirks = ADRENO_QUIRK_4GB_VA,
693
685
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
694
-
.init = a6xx_gpu_init,
686
+
.funcs = &a6xx_gmuwrapper_funcs,
695
687
.zapfw = "a610_zap.mdt",
696
688
.a6xx = &(const struct a6xx_info) {
697
689
.hwcg = a612_hwcg,
698
690
.protect = &a630_protect,
691
+
.gbif_cx = a640_gbif,
699
692
.gmu_cgc_mode = 0x00020202,
700
693
.prim_fifo_threshold = 0x00080000,
701
694
},
···
715
706
{ 127, 4 },
716
707
),
717
708
}, {
709
+
.chip_ids = ADRENO_CHIP_IDS(0x06010200),
710
+
.family = ADRENO_6XX_GEN1,
711
+
.fw = {
712
+
[ADRENO_FW_SQE] = "a630_sqe.fw",
713
+
[ADRENO_FW_GMU] = "a612_rgmu.bin",
714
+
},
715
+
.gmem = (SZ_128K + SZ_4K),
716
+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
717
+
.funcs = &a6xx_gmuwrapper_funcs,
718
+
.a6xx = &(const struct a6xx_info) {
719
+
.hwcg = a612_hwcg,
720
+
.protect = &a630_protect,
721
+
.gmu_cgc_mode = 0x00000022,
722
+
.prim_fifo_threshold = 0x00080000,
723
+
},
724
+
}, {
718
725
.chip_ids = ADRENO_CHIP_IDS(0x06010500),
719
726
.family = ADRENO_6XX_GEN1,
720
727
.revn = 615,
···
741
716
.gmem = SZ_512K,
742
717
.quirks = ADRENO_QUIRK_4GB_VA,
743
718
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
744
-
.init = a6xx_gpu_init,
719
+
.funcs = &a6xx_gpu_funcs,
745
720
.zapfw = "a615_zap.mdt",
746
721
.a6xx = &(const struct a6xx_info) {
747
722
.hwcg = a615_hwcg,
···
772
747
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
773
748
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
774
749
ADRENO_QUIRK_4GB_VA,
775
-
.init = a6xx_gpu_init,
750
+
.funcs = &a6xx_gpu_funcs,
776
751
.zapfw = "a615_zap.mbn",
777
752
.a6xx = &(const struct a6xx_info) {
778
753
.hwcg = a615_hwcg,
···
799
774
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
800
775
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
801
776
ADRENO_QUIRK_4GB_VA,
802
-
.init = a6xx_gpu_init,
777
+
.funcs = &a6xx_gpu_funcs,
803
778
.a6xx = &(const struct a6xx_info) {
804
779
.protect = &a630_protect,
805
780
.gmu_cgc_mode = 0x00000222,
···
822
797
.gmem = SZ_512K,
823
798
.quirks = ADRENO_QUIRK_4GB_VA,
824
799
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
825
-
.init = a6xx_gpu_init,
800
+
.funcs = &a6xx_gpu_funcs,
826
801
.zapfw = "a615_zap.mdt",
827
802
.a6xx = &(const struct a6xx_info) {
828
803
.hwcg = a615_hwcg,
···
847
822
.gmem = SZ_512K,
848
823
.quirks = ADRENO_QUIRK_4GB_VA,
849
824
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
850
-
.init = a6xx_gpu_init,
825
+
.funcs = &a6xx_gpu_funcs,
851
826
.zapfw = "a615_zap.mdt",
852
827
.a6xx = &(const struct a6xx_info) {
853
828
.hwcg = a615_hwcg,
···
872
847
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
873
848
ADRENO_QUIRK_4GB_VA,
874
849
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
875
-
.init = a6xx_gpu_init,
850
+
.funcs = &a6xx_gpu_funcs,
876
851
.zapfw = "a615_zap.mdt",
877
852
.a6xx = &(const struct a6xx_info) {
878
853
.hwcg = a615_hwcg,
···
898
873
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
899
874
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
900
875
ADRENO_QUIRK_HAS_HW_APRIV,
901
-
.init = a6xx_gpu_init,
876
+
.funcs = &a6xx_gpu_funcs,
902
877
.zapfw = "a620_zap.mbn",
903
878
.a6xx = &(const struct a6xx_info) {
904
879
.hwcg = a620_hwcg,
905
880
.protect = &a650_protect,
881
+
.gbif_cx = a640_gbif,
906
882
.gmu_cgc_mode = 0x00020200,
907
883
.prim_fifo_threshold = 0x00010000,
908
884
},
···
922
896
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
923
897
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
924
898
ADRENO_QUIRK_HAS_HW_APRIV,
925
-
.init = a6xx_gpu_init,
899
+
.funcs = &a6xx_gpu_funcs,
926
900
.a6xx = &(const struct a6xx_info) {
927
901
.hwcg = a690_hwcg,
928
902
.protect = &a650_protect,
903
+
.gbif_cx = a640_gbif,
929
904
.gmu_cgc_mode = 0x00020200,
930
905
.prim_fifo_threshold = 0x00010000,
931
906
.bcms = (const struct a6xx_bcm[]) {
···
960
933
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
961
934
ADRENO_QUIRK_4GB_VA,
962
935
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
963
-
.init = a6xx_gpu_init,
936
+
.funcs = &a6xx_gpu_funcs,
964
937
.zapfw = "a630_zap.mdt",
965
938
.a6xx = &(const struct a6xx_info) {
966
939
.hwcg = a630_hwcg,
···
980
953
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
981
954
ADRENO_QUIRK_4GB_VA,
982
955
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
983
-
.init = a6xx_gpu_init,
956
+
.funcs = &a6xx_gpu_funcs,
984
957
.zapfw = "a640_zap.mdt",
985
958
.a6xx = &(const struct a6xx_info) {
986
959
.hwcg = a640_hwcg,
···
1004
977
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1005
978
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1006
979
ADRENO_QUIRK_HAS_HW_APRIV,
1007
-
.init = a6xx_gpu_init,
980
+
.funcs = &a6xx_gpu_funcs,
1008
981
.zapfw = "a650_zap.mdt",
1009
982
.a6xx = &(const struct a6xx_info) {
1010
983
.hwcg = a650_hwcg,
1011
984
.protect = &a650_protect,
985
+
.gbif_cx = a640_gbif,
1012
986
.gmu_cgc_mode = 0x00020202,
1013
987
.prim_fifo_threshold = 0x00300200,
1014
988
},
···
1031
1003
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1032
1004
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1033
1005
ADRENO_QUIRK_HAS_HW_APRIV,
1034
-
.init = a6xx_gpu_init,
1006
+
.funcs = &a6xx_gpu_funcs,
1035
1007
.zapfw = "a660_zap.mdt",
1036
1008
.a6xx = &(const struct a6xx_info) {
1037
1009
.hwcg = a660_hwcg,
1038
1010
.protect = &a660_protect,
1011
+
.gbif_cx = a640_gbif,
1039
1012
.gmu_cgc_mode = 0x00020000,
1040
1013
.prim_fifo_threshold = 0x00300200,
1041
1014
},
···
1051
1022
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1052
1023
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1053
1024
ADRENO_QUIRK_HAS_HW_APRIV,
1054
-
.init = a6xx_gpu_init,
1025
+
.funcs = &a6xx_gpu_funcs,
1055
1026
.a6xx = &(const struct a6xx_info) {
1056
1027
.hwcg = a690_hwcg,
1057
1028
.protect = &a660_protect,
1029
+
.gbif_cx = a640_gbif,
1058
1030
.gmu_cgc_mode = 0x00020200,
1059
1031
.prim_fifo_threshold = 0x00300200,
1060
1032
},
···
1075
1045
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1076
1046
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1077
1047
ADRENO_QUIRK_HAS_HW_APRIV,
1078
-
.init = a6xx_gpu_init,
1048
+
.funcs = &a6xx_gpu_funcs,
1079
1049
.zapfw = "a660_zap.mbn",
1080
1050
.a6xx = &(const struct a6xx_info) {
1081
1051
.hwcg = a660_hwcg,
1082
1052
.protect = &a660_protect,
1053
+
.gbif_cx = a640_gbif,
1083
1054
.gmu_cgc_mode = 0x00020202,
1084
1055
.prim_fifo_threshold = 0x00200200,
1085
1056
},
···
1103
1072
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1104
1073
ADRENO_QUIRK_4GB_VA,
1105
1074
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1106
-
.init = a6xx_gpu_init,
1075
+
.funcs = &a6xx_gpu_funcs,
1107
1076
.zapfw = "a640_zap.mdt",
1108
1077
.a6xx = &(const struct a6xx_info) {
1109
1078
.hwcg = a640_hwcg,
···
1122
1091
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1123
1092
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1124
1093
ADRENO_QUIRK_HAS_HW_APRIV,
1125
-
.init = a6xx_gpu_init,
1094
+
.funcs = &a6xx_gpu_funcs,
1126
1095
.zapfw = "a690_zap.mdt",
1127
1096
.a6xx = &(const struct a6xx_info) {
1128
1097
.hwcg = a690_hwcg,
1129
1098
.protect = &a690_protect,
1099
+
.gbif_cx = a640_gbif,
1130
1100
.gmu_cgc_mode = 0x00020200,
1131
1101
.prim_fifo_threshold = 0x00800200,
1132
1102
},
···
1458
1426
.gmem = SZ_128K,
1459
1427
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1460
1428
.quirks = ADRENO_QUIRK_HAS_HW_APRIV,
1461
-
.init = a6xx_gpu_init,
1429
+
.funcs = &a6xx_gmuwrapper_funcs,
1462
1430
.zapfw = "a702_zap.mbn",
1463
1431
.a6xx = &(const struct a6xx_info) {
1464
1432
.hwcg = a702_hwcg,
1465
1433
.protect = &a650_protect,
1434
+
.gbif_cx = a640_gbif,
1466
1435
.gmu_cgc_mode = 0x00020202,
1467
1436
.prim_fifo_threshold = 0x0000c000,
1468
1437
},
···
1485
1452
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1486
1453
ADRENO_QUIRK_HAS_HW_APRIV |
1487
1454
ADRENO_QUIRK_PREEMPTION,
1488
-
.init = a6xx_gpu_init,
1455
+
.funcs = &a7xx_gpu_funcs,
1489
1456
.zapfw = "a730_zap.mdt",
1490
1457
.a6xx = &(const struct a6xx_info) {
1491
1458
.hwcg = a730_hwcg,
1492
1459
.protect = &a730_protect,
1493
1460
.pwrup_reglist = &a7xx_pwrup_reglist,
1461
+
.gbif_cx = a640_gbif,
1494
1462
.gmu_cgc_mode = 0x00020000,
1495
1463
},
1496
1464
.preempt_record_size = 2860 * SZ_1K,
···
1507
1473
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1508
1474
ADRENO_QUIRK_HAS_HW_APRIV |
1509
1475
ADRENO_QUIRK_PREEMPTION,
1510
-
.init = a6xx_gpu_init,
1476
+
.funcs = &a7xx_gpu_funcs,
1511
1477
.zapfw = "a740_zap.mdt",
1512
1478
.a6xx = &(const struct a6xx_info) {
1513
1479
.hwcg = a740_hwcg,
1514
1480
.protect = &a730_protect,
1515
1481
.pwrup_reglist = &a7xx_pwrup_reglist,
1482
+
.gbif_cx = a640_gbif,
1516
1483
.gmu_chipid = 0x7020100,
1517
1484
.gmu_cgc_mode = 0x00020202,
1518
1485
.bcms = (const struct a6xx_bcm[]) {
···
1542
1507
ADRENO_QUIRK_HAS_HW_APRIV |
1543
1508
ADRENO_QUIRK_PREEMPTION |
1544
1509
ADRENO_QUIRK_IFPC,
1545
-
.init = a6xx_gpu_init,
1510
+
.funcs = &a7xx_gpu_funcs,
1546
1511
.a6xx = &(const struct a6xx_info) {
1547
1512
.hwcg = a740_hwcg,
1548
1513
.protect = &a730_protect,
1549
1514
.pwrup_reglist = &a7xx_pwrup_reglist,
1550
1515
.ifpc_reglist = &a750_ifpc_reglist,
1516
+
.gbif_cx = a640_gbif,
1551
1517
.gmu_chipid = 0x7050001,
1552
1518
.gmu_cgc_mode = 0x00020202,
1553
1519
.bcms = (const struct a6xx_bcm[]) {
···
1584
1548
ADRENO_QUIRK_HAS_HW_APRIV |
1585
1549
ADRENO_QUIRK_PREEMPTION |
1586
1550
ADRENO_QUIRK_IFPC,
1587
-
.init = a6xx_gpu_init,
1551
+
.funcs = &a7xx_gpu_funcs,
1588
1552
.zapfw = "gen70900_zap.mbn",
1589
1553
.a6xx = &(const struct a6xx_info) {
1590
1554
.protect = &a730_protect,
1591
1555
.pwrup_reglist = &a7xx_pwrup_reglist,
1592
1556
.ifpc_reglist = &a750_ifpc_reglist,
1557
+
.gbif_cx = a640_gbif,
1593
1558
.gmu_chipid = 0x7090100,
1594
1559
.gmu_cgc_mode = 0x00020202,
1595
1560
.bcms = (const struct a6xx_bcm[]) {
···
1618
1581
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1619
1582
ADRENO_QUIRK_HAS_HW_APRIV |
1620
1583
ADRENO_QUIRK_PREEMPTION,
1621
-
.init = a6xx_gpu_init,
1584
+
.funcs = &a7xx_gpu_funcs,
1622
1585
.a6xx = &(const struct a6xx_info) {
1623
1586
.hwcg = a740_hwcg,
1624
1587
.protect = &a730_protect,
1625
1588
.pwrup_reglist = &a7xx_pwrup_reglist,
1589
+
.gbif_cx = a640_gbif,
1626
1590
.gmu_chipid = 0x70f0000,
1627
1591
.gmu_cgc_mode = 0x00020222,
1628
1592
.bcms = (const struct a6xx_bcm[]) {
···
1650
1612
};
1651
1613
DECLARE_ADRENO_GPULIST(a7xx);
1652
1614
1615
+
static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
1616
+
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1617
+
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1618
+
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1619
+
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1620
+
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1621
+
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1622
+
{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1623
+
{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1624
+
{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1625
+
{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1626
+
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
1627
+
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1628
+
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1629
+
{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1630
+
{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1631
+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1632
+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1633
+
{ REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1634
+
{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1635
+
{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1636
+
{ REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
1637
+
{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1638
+
{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1639
+
/* Disable CS dead batch merge */
1640
+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) },
1641
+
{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1642
+
{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1643
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
1644
+
/* BIT(26): Disable final clamp for bicubic filtering */
1645
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
1646
+
{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1647
+
{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1648
+
{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1649
+
{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1650
+
{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1651
+
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1652
+
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1653
+
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1654
+
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1655
+
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1656
+
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1657
+
{ },
1658
+
};
1659
+
1660
+
static const u32 x285_protect_regs[] = {
1661
+
A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1662
+
A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1663
+
A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1664
+
A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1665
+
A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1666
+
A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1667
+
A6XX_PROTECT_RDONLY(0x00759, 0x0026),
1668
+
A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1669
+
A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1670
+
A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1671
+
A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
1672
+
A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1673
+
A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1674
+
A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1675
+
A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1676
+
A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1677
+
A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1678
+
A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1679
+
A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1680
+
A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1681
+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1682
+
A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1683
+
A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1684
+
A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1685
+
A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1686
+
A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1687
+
A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1688
+
A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1689
+
A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1690
+
A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1691
+
A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1692
+
A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1693
+
A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
1694
+
A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1695
+
A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1696
+
A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1697
+
A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1698
+
A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1699
+
A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1700
+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1701
+
A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1702
+
A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1703
+
A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1704
+
A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1705
+
A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1706
+
A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1707
+
A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1708
+
A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1709
+
A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1710
+
A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1711
+
A6XX_PROTECT_NORDWR(0x27882, 0x000a),
1712
+
A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1713
+
};
1714
+
1715
+
DECLARE_ADRENO_PROTECT(x285_protect, 64);
1716
+
1717
+
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
1718
+
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1719
+
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1720
+
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1721
+
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1722
+
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1723
+
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1724
+
{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1725
+
{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1726
+
{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1727
+
{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1728
+
/* Disable Dead Draw Merge scheme on RB-HLSQ */
1729
+
{ REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) },
1730
+
{ REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
1731
+
/* Partially enable perf clear, Disable DINT to c/z be data forwarding */
1732
+
{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
1733
+
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
1734
+
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1735
+
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1736
+
{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1737
+
{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1738
+
{ REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) },
1739
+
{ REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) },
1740
+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1741
+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1742
+
{ REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1743
+
{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1744
+
{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1745
+
/* Disable mode_switch optimization in UMAS */
1746
+
{ REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) },
1747
+
/* Disable LPAC large-LM mode */
1748
+
{ REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) },
1749
+
/* Disable PS out of order retire */
1750
+
{ REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) },
1751
+
{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1752
+
/* Disable SP2TP info attribute */
1753
+
{ REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) },
1754
+
{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1755
+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) },
1756
+
/* Ignore HLSQ shared constant feedback from SP */
1757
+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) },
1758
+
/* Disable CS dead batch merge */
1759
+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) },
1760
+
{ REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) },
1761
+
{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1762
+
{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1763
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
1764
+
/* BIT(26): Disable final clamp for bicubic filtering */
1765
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
1766
+
{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1767
+
{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1768
+
{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1769
+
{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1770
+
{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1771
+
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1772
+
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1773
+
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1774
+
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1775
+
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1776
+
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1777
+
{ },
1778
+
};
1779
+
1780
+
static const u32 a840_protect_regs[] = {
1781
+
A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1782
+
A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1783
+
A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1784
+
A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1785
+
A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1786
+
A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1787
+
A6XX_PROTECT_RDONLY(0x00759, 0x001b),
1788
+
A6XX_PROTECT_NORDWR(0x00775, 0x000a),
1789
+
A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1790
+
A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1791
+
A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1792
+
A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1793
+
A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1794
+
A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1795
+
A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1796
+
A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
1797
+
A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1798
+
A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1799
+
A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1800
+
A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1801
+
A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1802
+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1803
+
A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1804
+
A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1805
+
A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1806
+
A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1807
+
A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1808
+
A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1809
+
A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1810
+
A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1811
+
A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1812
+
A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1813
+
A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1814
+
A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
1815
+
A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
1816
+
A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1817
+
A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1818
+
A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1819
+
A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1820
+
A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1821
+
A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1822
+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1823
+
A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1824
+
A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1825
+
A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1826
+
A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1827
+
A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1828
+
A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1829
+
A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1830
+
A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1831
+
A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1832
+
A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1833
+
A6XX_PROTECT_NORDWR(0x27882, 0x0009),
1834
+
A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1835
+
};
1836
+
DECLARE_ADRENO_PROTECT(a840_protect, 15);
1837
+
1838
+
static const struct adreno_reglist a840_gbif[] = {
1839
+
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },
1840
+
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
1841
+
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },
1842
+
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },
1843
+
{ REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },
1844
+
{ },
1845
+
};
1846
+
1847
+
static const struct adreno_info a8xx_gpus[] = {
1848
+
{
1849
+
.chip_ids = ADRENO_CHIP_IDS(0x44070001),
1850
+
.family = ADRENO_8XX_GEN2,
1851
+
.fw = {
1852
+
[ADRENO_FW_SQE] = "gen80100_sqe.fw",
1853
+
[ADRENO_FW_GMU] = "gen80100_gmu.bin",
1854
+
},
1855
+
.gmem = 21 * SZ_1M,
1856
+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1857
+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1858
+
ADRENO_QUIRK_HAS_HW_APRIV,
1859
+
.funcs = &a8xx_gpu_funcs,
1860
+
.a6xx = &(const struct a6xx_info) {
1861
+
.protect = &x285_protect,
1862
+
.nonctxt_reglist = x285_nonctxt_regs,
1863
+
.gbif_cx = a840_gbif,
1864
+
.max_slices = 4,
1865
+
.gmu_chipid = 0x8010100,
1866
+
.bcms = (const struct a6xx_bcm[]) {
1867
+
{ .name = "SH0", .buswidth = 16 },
1868
+
{ .name = "MC0", .buswidth = 4 },
1869
+
{
1870
+
.name = "ACV",
1871
+
.fixed = true,
1872
+
.perfmode = BIT(2),
1873
+
.perfmode_bw = 16500000,
1874
+
},
1875
+
{ /* sentinel */ },
1876
+
},
1877
+
},
1878
+
}, {
1879
+
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
1880
+
.family = ADRENO_8XX_GEN2,
1881
+
.fw = {
1882
+
[ADRENO_FW_SQE] = "gen80200_sqe.fw",
1883
+
[ADRENO_FW_GMU] = "gen80200_gmu.bin",
1884
+
[ADRENO_FW_AQE] = "gen80200_aqe.fw",
1885
+
},
1886
+
.gmem = 18 * SZ_1M,
1887
+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1888
+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1889
+
ADRENO_QUIRK_HAS_HW_APRIV,
1890
+
.funcs = &a8xx_gpu_funcs,
1891
+
.a6xx = &(const struct a6xx_info) {
1892
+
.protect = &a840_protect,
1893
+
.nonctxt_reglist = a840_nonctxt_regs,
1894
+
.gbif_cx = a840_gbif,
1895
+
.max_slices = 3,
1896
+
.gmu_chipid = 0x8020100,
1897
+
.bcms = (const struct a6xx_bcm[]) {
1898
+
{ .name = "SH0", .buswidth = 16 },
1899
+
{ .name = "MC0", .buswidth = 4 },
1900
+
{
1901
+
.name = "ACV",
1902
+
.fixed = true,
1903
+
.perfmode = BIT(2),
1904
+
.perfmode_bw = 10687500,
1905
+
},
1906
+
{ /* sentinel */ },
1907
+
},
1908
+
},
1909
+
.preempt_record_size = 19708 * SZ_1K,
1910
+
}
1911
+
};
1912
+
1913
+
DECLARE_ADRENO_GPULIST(a8xx);
1914
+
1653
1915
static inline __always_unused void __build_asserts(void)
1654
1916
{
1655
1917
BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
···
1957
1619
BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
1958
1620
BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
1959
1621
BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
1622
+
BUILD_BUG_ON(a840_protect.count > a840_protect.count_max);
1960
1623
}
+249
-83
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+249
-83
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
224
224
225
225
static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
226
226
{
227
-
u32 val;
227
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
228
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
228
229
int local = gmu->idle_level;
230
+
u32 val;
229
231
230
232
/* SPTP and IFPC both report as IFPC */
231
233
if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
232
234
local = GMU_IDLE_STATE_IFPC;
233
235
234
-
val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
236
+
if (adreno_is_a8xx(adreno_gpu))
237
+
val = gmu_read(gmu, REG_A8XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
238
+
else
239
+
val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
235
240
236
241
if (val == local) {
237
242
if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
···
274
269
/* Set the log wptr index
275
270
* note: downstream saves the value in poweroff and restores it here
276
271
*/
277
-
if (adreno_is_a7xx(adreno_gpu))
272
+
if (adreno_is_a8xx(adreno_gpu))
273
+
gmu_write(gmu, REG_A8XX_GMU_GENERAL_9, 0);
274
+
else if (adreno_is_a7xx(adreno_gpu))
278
275
gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0);
279
276
else
280
277
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
···
357
350
/* Trigger a OOB (out of band) request to the GMU */
358
351
int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
359
352
{
353
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
354
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
360
355
int ret;
361
356
u32 val;
362
357
int request, ack;
363
358
364
359
WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
360
+
361
+
/* Skip OOB calls since RGMU is not enabled */
362
+
if (adreno_has_rgmu(adreno_gpu))
363
+
return 0;
365
364
366
365
if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
367
366
return -EINVAL;
···
389
376
/* Trigger the equested OOB operation */
390
377
gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
391
378
392
-
/* Wait for the acknowledge interrupt */
393
-
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
394
-
val & (1 << ack), 100, 10000);
379
+
do {
380
+
/* Wait for the acknowledge interrupt */
381
+
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
382
+
val & (1 << ack), 100, 10000);
383
+
384
+
if (!ret)
385
+
break;
386
+
387
+
if (completion_done(&a6xx_gpu->base.fault_coredump_done))
388
+
break;
389
+
390
+
/* We may timeout because the GMU is temporarily wedged from
391
+
* pending faults from the GPU and we are taking a devcoredump.
392
+
* Wait until the MMU is resumed and try again.
393
+
*/
394
+
wait_for_completion(&a6xx_gpu->base.fault_coredump_done);
395
+
} while (true);
395
396
396
397
if (ret)
397
398
DRM_DEV_ERROR(gmu->dev,
···
422
395
/* Clear a pending OOB state in the GMU */
423
396
void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
424
397
{
398
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
399
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
425
400
int bit;
426
401
427
402
WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
403
+
404
+
/* Skip OOB calls since RGMU is not enabled */
405
+
if (adreno_has_rgmu(adreno_gpu))
406
+
return;
428
407
429
408
if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
430
409
return;
···
518
485
* in the power down sequence not being fully executed. That in turn can
519
486
* prevent CX_GDSC from collapsing. Assert Qactive to avoid this.
520
487
*/
521
-
if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu))
522
-
gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0));
488
+
if (adreno_is_a8xx(adreno_gpu))
489
+
gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0));
490
+
else if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) ||
491
+
adreno_is_7c3(adreno_gpu)))
492
+
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0));
523
493
}
524
494
525
495
/* Let the GMU know that we are about to go into slumber */
526
496
static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
527
497
{
498
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
499
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
528
500
int ret;
529
501
530
502
/* Disable the power counter so the GMU isn't busy */
531
-
gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
503
+
if (adreno_is_a8xx(adreno_gpu))
504
+
gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
505
+
else
506
+
gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
532
507
533
508
/* Disable SPTP_PC if the CPU is responsible for it */
534
509
if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
···
563
522
}
564
523
565
524
out:
566
-
a6xx_gemnoc_workaround(gmu);
567
-
568
525
/* Put fence into allow mode */
569
526
gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
527
+
a6xx_gemnoc_workaround(gmu);
570
528
return ret;
571
529
}
572
530
···
601
561
602
562
static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
603
563
{
564
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
565
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
566
+
u32 bitmask = BIT(16);
604
567
int ret;
605
568
u32 val;
606
569
607
570
if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status))
608
571
return;
609
572
573
+
if (adreno_is_a840(adreno_gpu))
574
+
bitmask = BIT(30);
575
+
610
576
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
611
577
612
578
ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
613
-
val, val & (1 << 16), 100, 10000);
579
+
val, val & bitmask, 100, 10000);
614
580
if (ret)
615
581
DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
616
582
···
630
584
writel(value, ptr + (offset << 2));
631
585
}
632
586
633
-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
634
-
const char *name);
635
-
636
587
static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
637
588
{
638
589
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
639
590
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
640
591
struct platform_device *pdev = to_platform_device(gmu->dev);
641
-
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
642
592
u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;
643
593
void __iomem *seqptr = NULL;
644
594
uint32_t pdc_address_offset;
595
+
void __iomem *pdcptr;
645
596
bool pdc_in_aop = false;
646
597
598
+
/* On A8x and above, RPMH/PDC configurations are entirely configured in AOP */
599
+
if (adreno_is_a8xx(adreno_gpu))
600
+
return;
601
+
602
+
pdcptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc");
647
603
if (IS_ERR(pdcptr))
648
-
goto err;
604
+
return;
649
605
650
606
if (adreno_is_a650_family(adreno_gpu) ||
651
607
adreno_is_a7xx(adreno_gpu))
···
660
612
pdc_address_offset = 0x30080;
661
613
662
614
if (!pdc_in_aop) {
663
-
seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
615
+
seqptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc_seq");
664
616
if (IS_ERR(seqptr))
665
-
goto err;
617
+
return;
666
618
}
667
619
668
620
/* Disable SDE clock gating */
···
752
704
753
705
/* ensure no writes happen before the uCode is fully written */
754
706
wmb();
755
-
756
-
err:
757
-
if (!IS_ERR_OR_NULL(pdcptr))
758
-
iounmap(pdcptr);
759
-
if (!IS_ERR_OR_NULL(seqptr))
760
-
iounmap(seqptr);
761
707
}
762
708
763
709
/*
···
774
732
gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
775
733
776
734
/* A7xx knows better by default! */
777
-
if (adreno_is_a7xx(adreno_gpu))
735
+
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))
778
736
return;
779
737
780
738
gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
···
837
795
u32 itcm_base = 0x00000000;
838
796
u32 dtcm_base = 0x00040000;
839
797
840
-
if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
798
+
if (adreno_is_a650_family(adreno_gpu) ||
799
+
adreno_is_a7xx(adreno_gpu) ||
800
+
adreno_is_a8xx(adreno_gpu))
841
801
dtcm_base = 0x10004000;
842
802
843
803
if (gmu->legacy) {
···
894
850
{
895
851
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
896
852
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
853
+
struct msm_gpu *gpu = &adreno_gpu->base;
897
854
const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx;
855
+
const struct adreno_reglist *gbif_cx = a6xx_info->gbif_cx;
898
856
u32 fence_range_lower, fence_range_upper;
899
857
u32 chipid = 0;
900
858
int ret;
···
905
859
if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) {
906
860
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
907
861
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
862
+
} else if (adreno_is_a8xx(adreno_gpu)) {
863
+
gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
864
+
gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
908
865
}
909
866
910
867
/* Turn on TCM (Tightly Coupled Memory) retention */
911
868
if (adreno_is_a7xx(adreno_gpu))
912
869
a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
913
-
else
870
+
else if (!adreno_is_a8xx(adreno_gpu))
914
871
gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
915
872
916
873
ret = a6xx_rpmh_start(gmu);
···
938
889
gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
939
890
gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
940
891
941
-
if (adreno_is_a7xx(adreno_gpu)) {
892
+
if (adreno_is_a8xx(adreno_gpu)) {
893
+
fence_range_upper = 0x32;
894
+
fence_range_lower = 0x8c0;
895
+
} else if (adreno_is_a7xx(adreno_gpu)) {
942
896
fence_range_upper = 0x32;
943
897
fence_range_lower = 0x8a0;
944
898
} else {
···
975
923
chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
976
924
}
977
925
978
-
if (adreno_is_a7xx(adreno_gpu)) {
926
+
if (adreno_is_a8xx(adreno_gpu)) {
927
+
gmu_write(gmu, REG_A8XX_GMU_GENERAL_10, chipid);
928
+
gmu_write(gmu, REG_A8XX_GMU_GENERAL_8,
929
+
(gmu->log.iova & GENMASK(31, 12)) |
930
+
((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));
931
+
} else if (adreno_is_a7xx(adreno_gpu)) {
979
932
gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid);
980
933
gmu_write(gmu, REG_A7XX_GMU_GENERAL_8,
981
934
(gmu->log.iova & GENMASK(31, 12)) |
···
990
933
991
934
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
992
935
gmu->log.iova | (gmu->log.size / SZ_4K - 1));
936
+
}
937
+
938
+
/* For A7x and newer, do the CX GBIF configurations before GMU wake up */
939
+
for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++)
940
+
gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value);
941
+
942
+
if (adreno_is_a8xx(adreno_gpu)) {
943
+
gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
944
+
gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
993
945
}
994
946
995
947
/* Set up the lowest idle level on the GMU */
···
1052
986
u32 val, seqmem_off = 0;
1053
987
1054
988
/* The second spin of A7xx GPUs messed with some register offsets.. */
1055
-
if (adreno_is_a740_family(adreno_gpu))
989
+
if (adreno_is_a740_family(adreno_gpu) || adreno_is_a8xx(adreno_gpu))
1056
990
seqmem_off = 4;
1057
991
1058
992
/* Make sure there are no outstanding RPMh votes */
···
1065
999
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off,
1066
1000
val, (val & 1), 100, 1000);
1067
1001
1068
-
if (!adreno_is_a740_family(adreno_gpu))
1002
+
if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu))
1069
1003
return;
1070
1004
1071
1005
gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off,
···
1093
1027
* Turn off keep alive that might have been enabled by the hang
1094
1028
* interrupt
1095
1029
*/
1096
-
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1030
+
if (adreno_is_a8xx(adreno_gpu))
1031
+
gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1032
+
else
1033
+
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1097
1034
1098
1035
/* Flush all the queues */
1099
1036
a6xx_hfi_stop(gmu);
···
1122
1053
/* Halt the gmu cm3 core */
1123
1054
gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
1124
1055
1125
-
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
1056
+
adreno_gpu->funcs->bus_halt(adreno_gpu, true);
1126
1057
1127
1058
/* Reset GPU core blocks */
1128
1059
a6xx_gpu_sw_reset(gpu, true);
···
1191
1122
return ret;
1192
1123
}
1193
1124
1125
+
/* Read the slice info on A8x GPUs */
1126
+
a8xx_gpu_get_slice_info(gpu);
1127
+
1194
1128
/* Set the bus quota to a reasonable value for boot */
1195
1129
a6xx_gmu_set_initial_bw(gpu, gmu);
1196
1130
···
1203
1131
enable_irq(gmu->gmu_irq);
1204
1132
1205
1133
/* Check to see if we are doing a cold or warm boot */
1206
-
if (adreno_is_a7xx(adreno_gpu)) {
1134
+
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
1207
1135
status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
1208
1136
GMU_WARM_BOOT : GMU_COLD_BOOT;
1209
1137
} else if (gmu->legacy) {
···
1297
1225
if (ret)
1298
1226
goto force_off;
1299
1227
1300
-
a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
1228
+
adreno_gpu->funcs->bus_halt(adreno_gpu, a6xx_gpu->hung);
1301
1229
1302
1230
/* tell the GMU we want to slumber */
1303
1231
ret = a6xx_gmu_notify_slumber(gmu);
···
1532
1460
vote = clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK);
1533
1461
1534
1462
/* GMUs on A7xx votes on both x & y */
1535
-
if (adreno_is_a7xx(adreno_gpu))
1463
+
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))
1536
1464
data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote);
1537
1465
else
1538
1466
data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote);
···
1564
1492
}
1565
1493
1566
1494
static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1567
-
unsigned long *freqs, int freqs_count, const char *id)
1495
+
unsigned long *freqs, int freqs_count,
1496
+
const char *pri_id, const char *sec_id)
1568
1497
{
1569
1498
int i, j;
1570
1499
const u16 *pri, *sec;
1571
1500
size_t pri_count, sec_count;
1572
1501
1573
-
pri = cmd_db_read_aux_data(id, &pri_count);
1502
+
pri = cmd_db_read_aux_data(pri_id, &pri_count);
1574
1503
if (IS_ERR(pri))
1575
1504
return PTR_ERR(pri);
1576
1505
/*
···
1582
1509
if (!pri_count)
1583
1510
return -EINVAL;
1584
1511
1585
-
/*
1586
-
* Some targets have a separate gfx mxc rail. So try to read that first and then fall back
1587
-
* to regular mx rail if it is missing
1588
-
*/
1589
-
sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count);
1590
-
if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER))
1591
-
sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1512
+
sec = cmd_db_read_aux_data(sec_id, &sec_count);
1592
1513
if (IS_ERR(sec))
1593
1514
return PTR_ERR(sec);
1594
1515
···
1636
1569
return 0;
1637
1570
}
1638
1571
1572
+
static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes,
1573
+
unsigned long *freqs, int freqs_count)
1574
+
{
1575
+
const u16 *mx;
1576
+
size_t count;
1577
+
1578
+
mx = cmd_db_read_aux_data("mx.lvl", &count);
1579
+
if (IS_ERR(mx))
1580
+
return PTR_ERR(mx);
1581
+
/*
1582
+
* The data comes back as an array of unsigned shorts so adjust the
1583
+
* count accordingly
1584
+
*/
1585
+
count >>= 1;
1586
+
if (!count)
1587
+
return -EINVAL;
1588
+
1589
+
/* Fix the vote for zero frequency */
1590
+
votes[0] = 0xffffffff;
1591
+
1592
+
/* Construct a vote for rest of the corners */
1593
+
for (int i = 1; i < freqs_count; i++) {
1594
+
unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1595
+
u8 j, index = 0;
1596
+
1597
+
/* Get the primary index that matches the arc level */
1598
+
for (j = 0; j < count; j++) {
1599
+
if (mx[j] >= level) {
1600
+
index = j;
1601
+
break;
1602
+
}
1603
+
}
1604
+
1605
+
if (j == count) {
1606
+
DRM_DEV_ERROR(dev,
1607
+
"Mx Level %u not found in the RPMh list\n",
1608
+
level);
1609
+
DRM_DEV_ERROR(dev, "Available levels:\n");
1610
+
for (j = 0; j < count; j++)
1611
+
DRM_DEV_ERROR(dev, " %u\n", mx[j]);
1612
+
1613
+
return -EINVAL;
1614
+
}
1615
+
1616
+
/* Construct the vote */
1617
+
votes[i] = (0x3fff << 14) | (index << 8) | (0xff);
1618
+
}
1619
+
1620
+
return 0;
1621
+
}
1622
+
1639
1623
/*
1640
1624
* The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1641
1625
* to construct the list of votes on the CPU and send it over. Query the RPMh
···
1701
1583
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1702
1584
const struct a6xx_info *info = adreno_gpu->info->a6xx;
1703
1585
struct msm_gpu *gpu = &adreno_gpu->base;
1586
+
const char *sec_id;
1587
+
const u16 *gmxc;
1704
1588
int ret;
1589
+
1590
+
gmxc = cmd_db_read_aux_data("gmxc.lvl", NULL);
1591
+
if (gmxc == ERR_PTR(-EPROBE_DEFER))
1592
+
return -EPROBE_DEFER;
1593
+
1594
+
/* If GMxC is present, prefer that as secondary rail for GX votes */
1595
+
sec_id = IS_ERR_OR_NULL(gmxc) ? "mx.lvl" : "gmxc.lvl";
1705
1596
1706
1597
/* Build the GX votes */
1707
1598
ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1708
-
gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1599
+
gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl", sec_id);
1709
1600
1710
1601
/* Build the CX votes */
1711
1602
ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1712
-
gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1603
+
gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl");
1604
+
1605
+
ret |= a6xx_gmu_rpmh_dep_votes_init(gmu->dev, gmu->dep_arc_votes,
1606
+
gmu->gpu_freqs, gmu->nr_gpu_freqs);
1713
1607
1714
1608
/* Build the interconnect votes */
1715
1609
if (info->bcms && gmu->nr_gpu_bws > 1)
···
1925
1795
return 0;
1926
1796
}
1927
1797
1928
-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1929
-
const char *name)
1930
-
{
1931
-
void __iomem *ret;
1932
-
struct resource *res = platform_get_resource_byname(pdev,
1933
-
IORESOURCE_MEM, name);
1934
-
1935
-
if (!res) {
1936
-
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1937
-
return ERR_PTR(-EINVAL);
1938
-
}
1939
-
1940
-
ret = ioremap(res->start, resource_size(res));
1941
-
if (!ret) {
1942
-
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1943
-
return ERR_PTR(-EINVAL);
1944
-
}
1945
-
1946
-
return ret;
1947
-
}
1948
-
1949
1798
static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1950
1799
const char *name, irq_handler_t handler)
1951
1800
{
···
1975
1866
{
1976
1867
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1977
1868
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1978
-
struct platform_device *pdev = to_platform_device(gmu->dev);
1979
1869
1980
1870
mutex_lock(&gmu->lock);
1981
1871
if (!gmu->initialized) {
···
2003
1895
qmp_put(gmu->qmp);
2004
1896
2005
1897
iounmap(gmu->mmio);
2006
-
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
2007
-
iounmap(gmu->rscc);
2008
1898
gmu->mmio = NULL;
2009
1899
gmu->rscc = NULL;
2010
1900
2011
-
if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1901
+
if (!adreno_has_gmu_wrapper(adreno_gpu) &&
1902
+
!adreno_has_rgmu(adreno_gpu)) {
2012
1903
a6xx_gmu_memory_free(gmu);
2013
1904
2014
1905
free_irq(gmu->gmu_irq, gmu);
···
2029
1922
return 0;
2030
1923
}
2031
1924
1925
+
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1926
+
const char *name, resource_size_t *start)
1927
+
{
1928
+
void __iomem *ret;
1929
+
struct resource *res = platform_get_resource_byname(pdev,
1930
+
IORESOURCE_MEM, name);
1931
+
1932
+
if (!res) {
1933
+
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1934
+
return ERR_PTR(-EINVAL);
1935
+
}
1936
+
1937
+
ret = ioremap(res->start, resource_size(res));
1938
+
if (!ret) {
1939
+
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1940
+
return ERR_PTR(-EINVAL);
1941
+
}
1942
+
1943
+
if (start)
1944
+
*start = res->start;
1945
+
1946
+
return ret;
1947
+
}
1948
+
2032
1949
int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
2033
1950
{
2034
1951
struct platform_device *pdev = of_find_device_by_node(node);
1952
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1953
+
struct msm_gpu *gpu = &adreno_gpu->base;
2035
1954
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1955
+
resource_size_t start;
1956
+
struct resource *res;
2036
1957
int ret;
2037
1958
2038
1959
if (!pdev)
···
2077
1942
/* Mark legacy for manual SPTPRAC control */
2078
1943
gmu->legacy = true;
2079
1944
1945
+
/* RGMU requires clocks */
1946
+
ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1947
+
if (ret < 0)
1948
+
goto err_clk;
1949
+
1950
+
gmu->nr_clocks = ret;
1951
+
2080
1952
/* Map the GMU registers */
2081
-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1953
+
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
2082
1954
if (IS_ERR(gmu->mmio)) {
2083
1955
ret = PTR_ERR(gmu->mmio);
2084
1956
goto err_mmio;
2085
1957
}
1958
+
1959
+
res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");
1960
+
if (!res) {
1961
+
ret = -EINVAL;
1962
+
goto err_mmio;
1963
+
}
1964
+
1965
+
/* Identify gmu base offset from gpu base address */
1966
+
gmu->mmio_offset = (u32)(start - res->start);
2086
1967
2087
1968
gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
2088
1969
if (IS_ERR(gmu->cxpd)) {
···
2132
1981
err_mmio:
2133
1982
iounmap(gmu->mmio);
2134
1983
1984
+
err_clk:
2135
1985
/* Drop reference taken in of_find_device_by_node */
2136
1986
put_device(gmu->dev);
2137
1987
···
2141
1989
2142
1990
int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
2143
1991
{
2144
-
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
2145
-
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2146
1992
struct platform_device *pdev = of_find_device_by_node(node);
1993
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1994
+
struct msm_gpu *gpu = &adreno_gpu->base;
1995
+
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2147
1996
struct device_link *link;
1997
+
resource_size_t start;
1998
+
struct resource *res;
2148
1999
int ret;
2149
2000
2150
2001
if (!pdev)
···
2183
2028
*/
2184
2029
gmu->dummy.size = SZ_4K;
2185
2030
if (adreno_is_a660_family(adreno_gpu) ||
2186
-
adreno_is_a7xx(adreno_gpu)) {
2031
+
adreno_is_a7xx(adreno_gpu) ||
2032
+
adreno_is_a8xx(adreno_gpu)) {
2187
2033
ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,
2188
2034
0x60400000, "debug");
2189
2035
if (ret)
2190
2036
goto err_memory;
2191
2037
2192
-
gmu->dummy.size = SZ_8K;
2038
+
gmu->dummy.size = SZ_16K;
2193
2039
}
2194
2040
2195
2041
/* Allocate memory for the GMU dummy page */
···
2201
2045
2202
2046
/* Note that a650 family also includes a660 family: */
2203
2047
if (adreno_is_a650_family(adreno_gpu) ||
2204
-
adreno_is_a7xx(adreno_gpu)) {
2048
+
adreno_is_a7xx(adreno_gpu) ||
2049
+
adreno_is_a8xx(adreno_gpu)) {
2205
2050
ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
2206
2051
SZ_16M - SZ_16K, 0x04000, "icache");
2207
2052
if (ret)
···
2244
2087
goto err_memory;
2245
2088
2246
2089
/* Map the GMU registers */
2247
-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
2090
+
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
2248
2091
if (IS_ERR(gmu->mmio)) {
2249
2092
ret = PTR_ERR(gmu->mmio);
2250
2093
goto err_memory;
2251
2094
}
2252
2095
2096
+
res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");
2097
+
if (!res) {
2098
+
ret = -EINVAL;
2099
+
goto err_mmio;
2100
+
}
2101
+
2102
+
/* Identify gmu base offset from gpu base address */
2103
+
gmu->mmio_offset = (u32)(start - res->start);
2104
+
2253
2105
if (adreno_is_a650_family(adreno_gpu) ||
2254
2106
adreno_is_a7xx(adreno_gpu)) {
2255
-
gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
2107
+
gmu->rscc = devm_platform_ioremap_resource_byname(pdev, "rscc");
2256
2108
if (IS_ERR(gmu->rscc)) {
2257
2109
ret = -ENODEV;
2258
2110
goto err_mmio;
2259
2111
}
2112
+
} else if (adreno_is_a8xx(adreno_gpu)) {
2113
+
gmu->rscc = gmu->mmio + 0x19000;
2260
2114
} else {
2261
2115
gmu->rscc = gmu->mmio + 0x23000;
2262
2116
}
···
2341
2173
2342
2174
err_mmio:
2343
2175
iounmap(gmu->mmio);
2344
-
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
2345
-
iounmap(gmu->rscc);
2346
2176
free_irq(gmu->gmu_irq, gmu);
2347
2177
free_irq(gmu->hfi_irq, gmu);
2348
2178
+15
-10
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+15
-10
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
···
19
19
u64 iova;
20
20
};
21
21
22
-
#define GMU_MAX_GX_FREQS 16
23
-
#define GMU_MAX_CX_FREQS 4
22
+
#define GMU_MAX_GX_FREQS 32
23
+
#define GMU_MAX_CX_FREQS 6
24
24
#define GMU_MAX_BCMS 3
25
25
26
26
struct a6xx_bcm {
···
68
68
struct drm_gpuvm *vm;
69
69
70
70
void __iomem *mmio;
71
+
u32 mmio_offset;
71
72
void __iomem *rscc;
72
73
73
74
int hfi_irq;
···
97
96
int nr_gpu_freqs;
98
97
unsigned long gpu_freqs[GMU_MAX_GX_FREQS];
99
98
u32 gx_arc_votes[GMU_MAX_GX_FREQS];
99
+
u32 dep_arc_votes[GMU_MAX_GX_FREQS];
100
100
struct a6xx_hfi_acd_table acd_table;
101
101
102
102
int nr_gpu_bws;
···
132
130
unsigned long status;
133
131
};
134
132
133
+
#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset)
134
+
135
135
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
136
136
{
137
-
return readl(gmu->mmio + (offset << 2));
137
+
/* The 'offset' is based on GPU's start address. Adjust it */
138
+
return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
138
139
}
139
140
140
141
static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
141
142
{
142
-
writel(value, gmu->mmio + (offset << 2));
143
+
writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
143
144
}
144
145
145
146
static inline void
146
147
gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
147
148
{
148
-
memcpy_toio(gmu->mmio + (offset << 2), data, size);
149
+
memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size);
149
150
wmb();
150
151
}
151
152
···
165
160
{
166
161
u64 val;
167
162
168
-
val = (u64) readl(gmu->mmio + (lo << 2));
169
-
val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
163
+
val = gmu_read(gmu, lo);
164
+
val |= ((u64) gmu_read(gmu, hi) << 32);
170
165
171
166
return val;
172
167
}
173
168
174
169
#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
175
-
readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
176
-
interval, timeout)
170
+
readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \
171
+
cond, interval, timeout)
177
172
#define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \
178
-
readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \
173
+
readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, cond, \
179
174
interval, timeout)
180
175
181
176
static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
+273
-165
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+273
-165
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
157
157
}
158
158
}
159
159
160
-
static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
160
+
void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
161
161
{
162
162
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
163
163
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
···
224
224
OUT_RING(ring, submit->seqno - 1);
225
225
226
226
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
227
-
OUT_RING(ring, CP_SET_THREAD_BOTH);
227
+
OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);
228
228
229
229
/* Reset state used to synchronize BR and BV */
230
230
OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1);
···
235
235
CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS);
236
236
237
237
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
238
-
OUT_RING(ring, CP_SET_THREAD_BR);
238
+
OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);
239
+
240
+
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
241
+
OUT_RING(ring, LRZ_FLUSH_INVALIDATE);
242
+
243
+
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
244
+
OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
239
245
}
240
246
241
247
if (!sysprof) {
242
-
if (!adreno_is_a7xx(adreno_gpu)) {
248
+
if (!(adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))) {
243
249
/* Turn off protected mode to write to special registers */
244
250
OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
245
251
OUT_RING(ring, 0);
246
252
}
247
253
248
-
OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
249
-
OUT_RING(ring, 1);
254
+
if (adreno_is_a8xx(adreno_gpu)) {
255
+
OUT_PKT4(ring, REG_A8XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
256
+
OUT_RING(ring, 1);
257
+
OUT_PKT4(ring, REG_A8XX_RBBM_SLICE_PERFCTR_SRAM_INIT_CMD, 1);
258
+
OUT_RING(ring, 1);
259
+
} else {
260
+
OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
261
+
OUT_RING(ring, 1);
262
+
}
250
263
}
251
264
252
265
/* Execute the table update */
···
288
275
* to make sure BV doesn't race ahead while BR is still switching
289
276
* pagetables.
290
277
*/
291
-
if (adreno_is_a7xx(&a6xx_gpu->base)) {
278
+
if (adreno_is_a7xx(&a6xx_gpu->base) || adreno_is_a8xx(&a6xx_gpu->base)) {
292
279
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
293
280
OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
294
281
}
···
302
289
OUT_RING(ring, CACHE_INVALIDATE);
303
290
304
291
if (!sysprof) {
292
+
u32 reg_status = adreno_is_a8xx(adreno_gpu) ?
293
+
REG_A8XX_RBBM_PERFCTR_SRAM_INIT_STATUS :
294
+
REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS;
305
295
/*
306
296
* Wait for SRAM clear after the pgtable update, so the
307
297
* two can happen in parallel:
308
298
*/
309
299
OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
310
300
OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));
311
-
OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO(
312
-
REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS));
301
+
OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO(reg_status));
313
302
OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0));
314
303
OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));
315
304
OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));
316
305
OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));
317
306
318
-
if (!adreno_is_a7xx(adreno_gpu)) {
307
+
if (!(adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))) {
319
308
/* Re-enable protected mode: */
320
309
OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
321
310
OUT_RING(ring, 1);
···
390
375
rbmemptr_stats(ring, index, alwayson_end));
391
376
392
377
/* Write the fence to the scratch register */
393
-
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
378
+
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);
394
379
OUT_RING(ring, submit->seqno);
395
380
396
381
/*
···
455
440
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
456
441
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
457
442
struct msm_ringbuffer *ring = submit->ring;
443
+
u32 rbbm_perfctr_cp0, cp_always_on_counter;
458
444
unsigned int i, ibs = 0;
459
445
460
446
adreno_check_and_reenable_stall(adreno_gpu);
···
476
460
if (gpu->nr_rings > 1)
477
461
a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue);
478
462
479
-
get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
480
-
rbmemptr_stats(ring, index, cpcycles_start));
481
-
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
482
-
rbmemptr_stats(ring, index, alwayson_start));
463
+
if (adreno_is_a8xx(adreno_gpu)) {
464
+
rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0);
465
+
cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_COUNTER;
466
+
} else {
467
+
rbbm_perfctr_cp0 = REG_A7XX_RBBM_PERFCTR_CP(0);
468
+
cp_always_on_counter = REG_A6XX_CP_ALWAYS_ON_COUNTER;
469
+
}
470
+
471
+
get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_start));
472
+
get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index, alwayson_start));
483
473
484
474
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
485
475
OUT_RING(ring, CP_SET_THREAD_BOTH);
···
532
510
OUT_RING(ring, 0x00e); /* IB1LIST end */
533
511
}
534
512
535
-
get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
536
-
rbmemptr_stats(ring, index, cpcycles_end));
537
-
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
538
-
rbmemptr_stats(ring, index, alwayson_end));
513
+
get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_end));
514
+
get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index, alwayson_end));
539
515
540
516
/* Write the fence to the scratch register */
541
-
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
542
-
OUT_RING(ring, submit->seqno);
517
+
if (adreno_is_a8xx(adreno_gpu)) {
518
+
OUT_PKT4(ring, REG_A8XX_CP_SCRATCH_GLOBAL(2), 1);
519
+
OUT_RING(ring, submit->seqno);
520
+
} else {
521
+
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);
522
+
OUT_RING(ring, submit->seqno);
523
+
}
543
524
544
525
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
545
526
OUT_RING(ring, CP_SET_THREAD_BR);
···
637
612
638
613
if (adreno_is_a630(adreno_gpu))
639
614
clock_cntl_on = 0x8aa8aa02;
640
-
else if (adreno_is_a610(adreno_gpu))
615
+
else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu))
641
616
clock_cntl_on = 0xaaa8aa82;
642
617
else if (adreno_is_a702(adreno_gpu))
643
618
clock_cntl_on = 0xaaaaaa82;
644
619
else
645
620
clock_cntl_on = 0x8aa8aa82;
646
621
647
-
cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
648
-
cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
622
+
if (adreno_is_a612(adreno_gpu))
623
+
cgc_delay = 0x11;
624
+
else if (adreno_is_a615_family(adreno_gpu))
625
+
cgc_delay = 0x111;
626
+
else
627
+
cgc_delay = 0x10111;
628
+
629
+
if (adreno_is_a612(adreno_gpu))
630
+
cgc_hyst = 0x55;
631
+
else if (adreno_is_a615_family(adreno_gpu))
632
+
cgc_hyst = 0x555;
633
+
else
634
+
cgc_hyst = 0x5555;
649
635
650
636
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
651
637
state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
···
742
706
/* Copy the data into the internal struct to drop the const qualifier (temporarily) */
743
707
*cfg = *common_cfg;
744
708
745
-
cfg->ubwc_swizzle = 0x6;
746
-
cfg->highest_bank_bit = 15;
709
+
/* Use common config as is for A8x */
710
+
if (!adreno_is_a8xx(gpu)) {
711
+
cfg->ubwc_swizzle = 0x6;
712
+
cfg->highest_bank_bit = 15;
713
+
}
747
714
748
715
if (adreno_is_a610(gpu)) {
749
716
cfg->highest_bank_bit = 13;
750
717
cfg->ubwc_swizzle = 0x7;
751
718
}
719
+
720
+
if (adreno_is_a612(gpu))
721
+
cfg->highest_bank_bit = 14;
752
722
753
723
if (adreno_is_a618(gpu))
754
724
cfg->highest_bank_bit = 14;
···
1035
993
return false;
1036
994
1037
995
/* A7xx is safe! */
1038
-
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu))
996
+
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) || adreno_is_a8xx(adreno_gpu))
1039
997
return true;
1040
998
1041
999
/*
···
1118
1076
}
1119
1077
}
1120
1078
1079
+
if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) {
1080
+
a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu,
1081
+
adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova);
1082
+
1083
+
if (IS_ERR(a6xx_gpu->aqe_bo)) {
1084
+
int ret = PTR_ERR(a6xx_gpu->aqe_bo);
1085
+
1086
+
a6xx_gpu->aqe_bo = NULL;
1087
+
DRM_DEV_ERROR(&gpu->pdev->dev,
1088
+
"Could not allocate AQE ucode: %d\n", ret);
1089
+
1090
+
return ret;
1091
+
}
1092
+
1093
+
msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw");
1094
+
}
1095
+
1121
1096
/*
1122
1097
* Expanded APRIV and targets that support WHERE_AM_I both need a
1123
1098
* privileged buffer to store the RPTR shadow
···
1166
1107
return 0;
1167
1108
}
1168
1109
1169
-
static int a6xx_zap_shader_init(struct msm_gpu *gpu)
1110
+
int a6xx_zap_shader_init(struct msm_gpu *gpu)
1170
1111
{
1171
1112
static bool loaded;
1172
1113
int ret;
···
1279
1220
/* enable hardware clockgating */
1280
1221
a6xx_set_hwcg(gpu, true);
1281
1222
1282
-
/* VBIF/GBIF start*/
1283
-
if (adreno_is_a610_family(adreno_gpu) ||
1284
-
adreno_is_a640_family(adreno_gpu) ||
1285
-
adreno_is_a650_family(adreno_gpu) ||
1286
-
adreno_is_a7xx(adreno_gpu)) {
1223
+
/* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */
1224
+
if (adreno_is_a610_family(adreno_gpu)) {
1287
1225
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
1288
1226
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
1289
1227
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
1290
1228
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1291
-
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
1292
-
adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3);
1229
+
}
1230
+
1231
+
if (adreno_is_a610_family(adreno_gpu) ||
1232
+
adreno_is_a640_family(adreno_gpu) ||
1233
+
adreno_is_a650_family(adreno_gpu)) {
1234
+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
1235
+
} else if (adreno_is_a7xx(adreno_gpu)) {
1236
+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212);
1293
1237
} else {
1294
1238
gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
1295
1239
}
···
1347
1285
}
1348
1286
1349
1287
if (adreno_is_a660_family(adreno_gpu))
1350
-
gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
1288
+
gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
1351
1289
1352
1290
/* Setting the mem pool size */
1353
-
if (adreno_is_a610(adreno_gpu)) {
1291
+
if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
1354
1292
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
1355
1293
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
1356
1294
} else if (adreno_is_a702(adreno_gpu)) {
···
1383
1321
a6xx_set_ubwc_config(gpu);
1384
1322
1385
1323
/* Enable fault detection */
1386
-
if (adreno_is_a730(adreno_gpu) ||
1324
+
if (adreno_is_a612(adreno_gpu) ||
1325
+
adreno_is_a730(adreno_gpu) ||
1387
1326
adreno_is_a740_family(adreno_gpu))
1388
1327
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
1389
1328
else if (adreno_is_a690(adreno_gpu))
···
1603
1540
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1604
1541
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1605
1542
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1606
-
int i, active_submits;
1543
+
int active_submits;
1607
1544
1608
1545
adreno_dump_info(gpu);
1609
1546
1610
1547
if (a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) {
1611
1548
/* Sometimes crashstate capture is skipped, so SQE should be halted here again */
1612
1549
gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
1613
-
1614
-
for (i = 0; i < 8; i++)
1615
-
DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
1616
-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
1617
1550
1618
1551
if (hang_debug)
1619
1552
a6xx_dump(gpu);
···
1635
1576
*/
1636
1577
gpu->active_submits = 0;
1637
1578
1638
-
if (adreno_has_gmu_wrapper(adreno_gpu)) {
1579
+
if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) {
1639
1580
/* Drain the outstanding traffic on memory buses */
1640
-
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
1581
+
adreno_gpu->funcs->bus_halt(adreno_gpu, true);
1641
1582
1642
1583
/* Reset the GPU to a clean state */
1643
1584
a6xx_gpu_sw_reset(gpu, true);
···
1796
1737
const char *block = "unknown";
1797
1738
1798
1739
u32 scratch[] = {
1799
-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1800
-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1801
-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1802
-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),
1740
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)),
1741
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)),
1742
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)),
1743
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)),
1803
1744
};
1804
1745
1805
1746
if (info)
···
2131
2072
u32 fuse_val;
2132
2073
int ret;
2133
2074
2134
-
if (adreno_is_a750(adreno_gpu)) {
2075
+
if (adreno_is_a750(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
2135
2076
/*
2136
2077
* Assume that if qcom scm isn't available, that whatever
2137
2078
* replacement allows writing the fuse register ourselves.
···
2157
2098
return ret;
2158
2099
2159
2100
/*
2160
-
* On a750 raytracing may be disabled by the firmware, find out
2161
-
* whether that's the case. The scm call above sets the fuse
2162
-
* register.
2101
+
* On A7XX_GEN3 and newer, raytracing may be disabled by the
2102
+
* firmware, find out whether that's the case. The scm call
2103
+
* above sets the fuse register.
2163
2104
*/
2164
2105
fuse_val = a6xx_llc_read(a6xx_gpu,
2165
2106
REG_A7XX_CX_MISC_SW_FUSE_VALUE);
···
2220
2161
void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
2221
2162
{
2222
2163
/* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */
2223
-
if (adreno_is_a610(to_adreno_gpu(gpu)))
2164
+
if (adreno_is_a610(to_adreno_gpu(gpu)) || adreno_is_a8xx(to_adreno_gpu(gpu)))
2224
2165
return;
2225
2166
2226
2167
gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
···
2251
2192
2252
2193
msm_devfreq_resume(gpu);
2253
2194
2254
-
adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu);
2195
+
if (adreno_is_a8xx(adreno_gpu))
2196
+
a8xx_llc_activate(a6xx_gpu);
2197
+
else if (adreno_is_a7xx(adreno_gpu))
2198
+
a7xx_llc_activate(a6xx_gpu);
2199
+
else
2200
+
a6xx_llc_activate(a6xx_gpu);
2255
2201
2256
2202
return ret;
2257
2203
}
···
2293
2229
if (ret)
2294
2230
goto err_bulk_clk;
2295
2231
2232
+
ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
2233
+
if (ret) {
2234
+
clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
2235
+
goto err_bulk_clk;
2236
+
}
2237
+
2296
2238
if (adreno_is_a619_holi(adreno_gpu))
2297
2239
a6xx_sptprac_enable(gmu);
2298
2240
···
2312
2242
err_set_opp:
2313
2243
mutex_unlock(&a6xx_gpu->gmu.lock);
2314
2244
2315
-
if (!ret)
2245
+
if (!ret) {
2316
2246
msm_devfreq_resume(gpu);
2247
+
a6xx_llc_activate(a6xx_gpu);
2248
+
}
2317
2249
2318
2250
return ret;
2319
2251
}
···
2356
2284
2357
2285
trace_msm_gpu_suspend(0);
2358
2286
2287
+
a6xx_llc_deactivate(a6xx_gpu);
2288
+
2359
2289
msm_devfreq_suspend(gpu);
2360
2290
2361
2291
mutex_lock(&a6xx_gpu->gmu.lock);
2362
2292
2363
2293
/* Drain the outstanding traffic on memory buses */
2364
-
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
2294
+
adreno_gpu->funcs->bus_halt(adreno_gpu, true);
2365
2295
2366
2296
if (adreno_is_a619_holi(adreno_gpu))
2367
2297
a6xx_sptprac_disable(gmu);
2368
2298
2369
2299
clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
2300
+
clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
2370
2301
2371
2302
pm_runtime_put_sync(gmu->gxpd);
2372
2303
dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
···
2418
2343
if (a6xx_gpu->sqe_bo) {
2419
2344
msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm);
2420
2345
drm_gem_object_put(a6xx_gpu->sqe_bo);
2346
+
}
2347
+
2348
+
if (a6xx_gpu->aqe_bo) {
2349
+
msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm);
2350
+
drm_gem_object_put(a6xx_gpu->aqe_bo);
2421
2351
}
2422
2352
2423
2353
if (a6xx_gpu->shadow_bo) {
···
2607
2527
return 0;
2608
2528
}
2609
2529
2610
-
static const struct adreno_gpu_funcs funcs = {
2530
+
static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
2531
+
{
2532
+
struct msm_drm_private *priv = dev->dev_private;
2533
+
struct platform_device *pdev = priv->gpu_pdev;
2534
+
struct adreno_platform_config *config = pdev->dev.platform_data;
2535
+
struct device_node *node;
2536
+
struct a6xx_gpu *a6xx_gpu;
2537
+
struct adreno_gpu *adreno_gpu;
2538
+
struct msm_gpu *gpu;
2539
+
extern int enable_preemption;
2540
+
bool is_a7xx;
2541
+
int ret, nr_rings = 1;
2542
+
2543
+
a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
2544
+
if (!a6xx_gpu)
2545
+
return ERR_PTR(-ENOMEM);
2546
+
2547
+
adreno_gpu = &a6xx_gpu->base;
2548
+
gpu = &adreno_gpu->base;
2549
+
2550
+
mutex_init(&a6xx_gpu->gmu.lock);
2551
+
2552
+
adreno_gpu->registers = NULL;
2553
+
2554
+
/* Check if there is a GMU phandle and set it up */
2555
+
node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
2556
+
/* FIXME: How do we gracefully handle this? */
2557
+
BUG_ON(!node);
2558
+
2559
+
adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
2560
+
2561
+
adreno_gpu->base.hw_apriv =
2562
+
!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
2563
+
2564
+
/* gpu->info only gets assigned in adreno_gpu_init(). A8x is included intentionally */
2565
+
is_a7xx = config->info->family >= ADRENO_7XX_GEN1;
2566
+
2567
+
a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
2568
+
2569
+
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
2570
+
if (ret) {
2571
+
a6xx_llc_slices_destroy(a6xx_gpu);
2572
+
kfree(a6xx_gpu);
2573
+
return ERR_PTR(ret);
2574
+
}
2575
+
2576
+
if ((enable_preemption == 1) || (enable_preemption == -1 &&
2577
+
(config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
2578
+
nr_rings = 4;
2579
+
2580
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_rings);
2581
+
if (ret) {
2582
+
a6xx_destroy(&(a6xx_gpu->base.base));
2583
+
return ERR_PTR(ret);
2584
+
}
2585
+
2586
+
/*
2587
+
* For now only clamp to idle freq for devices where this is known not
2588
+
* to cause power supply issues:
2589
+
*/
2590
+
if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu))
2591
+
priv->gpu_clamp_to_idle = true;
2592
+
2593
+
if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu))
2594
+
ret = a6xx_gmu_wrapper_init(a6xx_gpu, node);
2595
+
else
2596
+
ret = a6xx_gmu_init(a6xx_gpu, node);
2597
+
of_node_put(node);
2598
+
if (ret) {
2599
+
a6xx_destroy(&(a6xx_gpu->base.base));
2600
+
return ERR_PTR(ret);
2601
+
}
2602
+
2603
+
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
2604
+
ret = a7xx_cx_mem_init(a6xx_gpu);
2605
+
if (ret) {
2606
+
a6xx_destroy(&(a6xx_gpu->base.base));
2607
+
return ERR_PTR(ret);
2608
+
}
2609
+
}
2610
+
2611
+
adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
2612
+
2613
+
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
2614
+
adreno_gpu->funcs->mmu_fault_handler);
2615
+
2616
+
ret = a6xx_calc_ubwc_config(adreno_gpu);
2617
+
if (ret) {
2618
+
a6xx_destroy(&(a6xx_gpu->base.base));
2619
+
return ERR_PTR(ret);
2620
+
}
2621
+
2622
+
/* Set up the preemption specific bits and pieces for each ringbuffer */
2623
+
a6xx_preempt_init(gpu);
2624
+
2625
+
return gpu;
2626
+
}
2627
+
2628
+
const struct adreno_gpu_funcs a6xx_gpu_funcs = {
2611
2629
.base = {
2612
2630
.get_param = adreno_get_param,
2613
2631
.set_param = adreno_set_param,
···
2732
2554
.create_private_vm = a6xx_create_private_vm,
2733
2555
.get_rptr = a6xx_get_rptr,
2734
2556
.progress = a6xx_progress,
2735
-
.sysprof_setup = a6xx_gmu_sysprof_setup,
2736
2557
},
2558
+
.init = a6xx_gpu_init,
2737
2559
.get_timestamp = a6xx_gmu_get_timestamp,
2560
+
.bus_halt = a6xx_bus_clear_pending_transactions,
2561
+
.mmu_fault_handler = a6xx_fault_handler,
2738
2562
};
2739
2563
2740
-
static const struct adreno_gpu_funcs funcs_gmuwrapper = {
2564
+
const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
2741
2565
.base = {
2742
2566
.get_param = adreno_get_param,
2743
2567
.set_param = adreno_set_param,
···
2765
2585
.get_rptr = a6xx_get_rptr,
2766
2586
.progress = a6xx_progress,
2767
2587
},
2588
+
.init = a6xx_gpu_init,
2768
2589
.get_timestamp = a6xx_get_timestamp,
2590
+
.bus_halt = a6xx_bus_clear_pending_transactions,
2591
+
.mmu_fault_handler = a6xx_fault_handler,
2769
2592
};
2770
2593
2771
-
static const struct adreno_gpu_funcs funcs_a7xx = {
2594
+
const struct adreno_gpu_funcs a7xx_gpu_funcs = {
2772
2595
.base = {
2773
2596
.get_param = adreno_get_param,
2774
2597
.set_param = adreno_set_param,
···
2798
2615
.create_private_vm = a6xx_create_private_vm,
2799
2616
.get_rptr = a6xx_get_rptr,
2800
2617
.progress = a6xx_progress,
2801
-
.sysprof_setup = a6xx_gmu_sysprof_setup,
2802
2618
},
2619
+
.init = a6xx_gpu_init,
2803
2620
.get_timestamp = a6xx_gmu_get_timestamp,
2621
+
.bus_halt = a6xx_bus_clear_pending_transactions,
2622
+
.mmu_fault_handler = a6xx_fault_handler,
2804
2623
};
2805
2624
2806
-
struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
2807
-
{
2808
-
struct msm_drm_private *priv = dev->dev_private;
2809
-
struct platform_device *pdev = priv->gpu_pdev;
2810
-
struct adreno_platform_config *config = pdev->dev.platform_data;
2811
-
struct device_node *node;
2812
-
struct a6xx_gpu *a6xx_gpu;
2813
-
struct adreno_gpu *adreno_gpu;
2814
-
struct msm_gpu *gpu;
2815
-
extern int enable_preemption;
2816
-
bool is_a7xx;
2817
-
int ret;
2818
-
2819
-
a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
2820
-
if (!a6xx_gpu)
2821
-
return ERR_PTR(-ENOMEM);
2822
-
2823
-
adreno_gpu = &a6xx_gpu->base;
2824
-
gpu = &adreno_gpu->base;
2825
-
2826
-
mutex_init(&a6xx_gpu->gmu.lock);
2827
-
2828
-
adreno_gpu->registers = NULL;
2829
-
2830
-
/* Check if there is a GMU phandle and set it up */
2831
-
node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
2832
-
/* FIXME: How do we gracefully handle this? */
2833
-
BUG_ON(!node);
2834
-
2835
-
adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
2836
-
2837
-
adreno_gpu->base.hw_apriv =
2838
-
!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
2839
-
2840
-
/* gpu->info only gets assigned in adreno_gpu_init() */
2841
-
is_a7xx = config->info->family == ADRENO_7XX_GEN1 ||
2842
-
config->info->family == ADRENO_7XX_GEN2 ||
2843
-
config->info->family == ADRENO_7XX_GEN3;
2844
-
2845
-
a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
2846
-
2847
-
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
2848
-
if (ret) {
2849
-
a6xx_llc_slices_destroy(a6xx_gpu);
2850
-
kfree(a6xx_gpu);
2851
-
return ERR_PTR(ret);
2852
-
}
2853
-
2854
-
if ((enable_preemption == 1) || (enable_preemption == -1 &&
2855
-
(config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
2856
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4);
2857
-
else if (is_a7xx)
2858
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1);
2859
-
else if (adreno_has_gmu_wrapper(adreno_gpu))
2860
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1);
2861
-
else
2862
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
2863
-
if (ret) {
2864
-
a6xx_destroy(&(a6xx_gpu->base.base));
2865
-
return ERR_PTR(ret);
2866
-
}
2867
-
2868
-
/*
2869
-
* For now only clamp to idle freq for devices where this is known not
2870
-
* to cause power supply issues:
2871
-
*/
2872
-
if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu))
2873
-
priv->gpu_clamp_to_idle = true;
2874
-
2875
-
if (adreno_has_gmu_wrapper(adreno_gpu))
2876
-
ret = a6xx_gmu_wrapper_init(a6xx_gpu, node);
2877
-
else
2878
-
ret = a6xx_gmu_init(a6xx_gpu, node);
2879
-
of_node_put(node);
2880
-
if (ret) {
2881
-
a6xx_destroy(&(a6xx_gpu->base.base));
2882
-
return ERR_PTR(ret);
2883
-
}
2884
-
2885
-
if (adreno_is_a7xx(adreno_gpu)) {
2886
-
ret = a7xx_cx_mem_init(a6xx_gpu);
2887
-
if (ret) {
2888
-
a6xx_destroy(&(a6xx_gpu->base.base));
2889
-
return ERR_PTR(ret);
2890
-
}
2891
-
}
2892
-
2893
-
adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
2894
-
2895
-
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
2896
-
a6xx_fault_handler);
2897
-
2898
-
ret = a6xx_calc_ubwc_config(adreno_gpu);
2899
-
if (ret) {
2900
-
a6xx_destroy(&(a6xx_gpu->base.base));
2901
-
return ERR_PTR(ret);
2902
-
}
2903
-
2904
-
/* Set up the preemption specific bits and pieces for each ringbuffer */
2905
-
a6xx_preempt_init(gpu);
2906
-
2907
-
return gpu;
2908
-
}
2625
+
const struct adreno_gpu_funcs a8xx_gpu_funcs = {
2626
+
.base = {
2627
+
.get_param = adreno_get_param,
2628
+
.set_param = adreno_set_param,
2629
+
.hw_init = a8xx_hw_init,
2630
+
.ucode_load = a6xx_ucode_load,
2631
+
.pm_suspend = a6xx_gmu_pm_suspend,
2632
+
.pm_resume = a6xx_gmu_pm_resume,
2633
+
.recover = a8xx_recover,
2634
+
.submit = a7xx_submit,
2635
+
.active_ring = a6xx_active_ring,
2636
+
.irq = a8xx_irq,
2637
+
.destroy = a6xx_destroy,
2638
+
.gpu_busy = a8xx_gpu_busy,
2639
+
.gpu_get_freq = a6xx_gmu_get_freq,
2640
+
.gpu_set_freq = a6xx_gpu_set_freq,
2641
+
.create_vm = a6xx_create_vm,
2642
+
.create_private_vm = a6xx_create_private_vm,
2643
+
.get_rptr = a6xx_get_rptr,
2644
+
.progress = a8xx_progress,
2645
+
},
2646
+
.init = a6xx_gpu_init,
2647
+
.get_timestamp = a8xx_gmu_get_timestamp,
2648
+
.bus_halt = a8xx_bus_clear_pending_transactions,
2649
+
.mmu_fault_handler = a8xx_fault_handler,
2650
+
};
+29
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+29
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
···
46
46
const struct adreno_protect *protect;
47
47
const struct adreno_reglist_list *pwrup_reglist;
48
48
const struct adreno_reglist_list *ifpc_reglist;
49
+
const struct adreno_reglist *gbif_cx;
50
+
const struct adreno_reglist_pipe *nonctxt_reglist;
51
+
u32 max_slices;
49
52
u32 gmu_chipid;
50
53
u32 gmu_cgc_mode;
51
54
u32 prim_fifo_threshold;
···
60
57
61
58
struct drm_gem_object *sqe_bo;
62
59
uint64_t sqe_iova;
60
+
struct drm_gem_object *aqe_bo;
61
+
uint64_t aqe_iova;
63
62
64
63
struct msm_ringbuffer *cur_ring;
65
64
struct msm_ringbuffer *next_ring;
···
106
101
void *htw_llc_slice;
107
102
bool have_mmu500;
108
103
bool hung;
104
+
105
+
u32 cached_aperture;
106
+
spinlock_t aperture_lock;
107
+
108
+
u32 slice_mask;
109
109
};
110
110
111
111
#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
···
226
216
#define A6XX_PROTECT_RDONLY(_reg, _len) \
227
217
((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
228
218
219
+
extern const struct adreno_gpu_funcs a6xx_gpu_funcs;
220
+
extern const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs;
221
+
extern const struct adreno_gpu_funcs a7xx_gpu_funcs;
222
+
extern const struct adreno_gpu_funcs a8xx_gpu_funcs;
223
+
229
224
static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
230
225
{
231
226
if(adreno_is_a630(gpu))
···
313
298
void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);
314
299
void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
315
300
int a6xx_fenced_write(struct a6xx_gpu *gpu, u32 offset, u64 value, u32 mask, bool is_64b);
301
+
void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
302
+
int a6xx_zap_shader_init(struct msm_gpu *gpu);
316
303
304
+
void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);
305
+
int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *data);
306
+
void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
307
+
int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value);
308
+
u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate);
309
+
int a8xx_gpu_feature_probe(struct msm_gpu *gpu);
310
+
void a8xx_gpu_get_slice_info(struct msm_gpu *gpu);
311
+
int a8xx_hw_init(struct msm_gpu *gpu);
312
+
irqreturn_t a8xx_irq(struct msm_gpu *gpu);
313
+
void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu);
314
+
bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
315
+
void a8xx_recover(struct msm_gpu *gpu);
317
316
#endif /* __A6XX_GPU_H__ */
+3
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+3
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
1255
1255
return;
1256
1256
1257
1257
/* Set the fence to ALLOW mode so we can access the registers */
1258
-
gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
1258
+
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
1259
1259
1260
1260
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],
1261
1261
&a6xx_state->gmu_registers[3], false);
···
1596
1596
/* Get the generic state from the adreno core */
1597
1597
adreno_gpu_state_get(gpu, &a6xx_state->base);
1598
1598
1599
-
if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1599
+
if (!adreno_has_gmu_wrapper(adreno_gpu) &&
1600
+
!adreno_has_rgmu(adreno_gpu)) {
1600
1601
a6xx_get_gmu_registers(gpu, a6xx_state);
1601
1602
1602
1603
a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log);
+37
-37
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+37
-37
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
···
71
71
u32 sel_val;
72
72
} a6xx_clusters[] = {
73
73
CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
74
-
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
75
-
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
74
+
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
75
+
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
76
76
CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
77
77
CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
78
78
CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
···
303
303
static const struct a6xx_registers a6xx_reglist[] = {
304
304
REGS(a6xx_registers, 0, 0),
305
305
REGS(a660_registers, 0, 0),
306
-
REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307
-
REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
306
+
REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307
+
REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
308
308
};
309
309
310
310
static const u32 a6xx_ahb_registers[] = {
···
343
343
344
344
static const u32 a6xx_gmu_gx_registers[] = {
345
345
/* GMU GX */
346
-
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
347
-
0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
348
-
0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
349
-
0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
350
-
0x0100, 0x012b, 0x0140, 0x0140,
346
+
0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b,
347
+
0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b,
348
+
0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b,
349
+
0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884,
350
+
0x1a900, 0x1a92b, 0x1a940, 0x1a940,
351
351
};
352
352
353
353
static const u32 a6xx_gmu_cx_registers[] = {
354
354
/* GMU CX */
355
-
0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
356
-
0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
357
-
0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
358
-
0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
359
-
0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
360
-
0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
361
-
0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
362
-
0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
363
-
0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
355
+
0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a,
356
+
0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c,
357
+
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889,
358
+
0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0,
359
+
0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940,
360
+
0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954,
361
+
0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965,
362
+
0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc,
363
+
0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01,
364
364
/* GMU AO */
365
-
0x9300, 0x9316, 0x9400, 0x9400,
365
+
0x23b00, 0x23b16, 0x23c00, 0x23c00,
366
366
};
367
367
368
368
static const u32 a6xx_gmu_gpucc_registers[] = {
369
369
/* GPU CC */
370
-
0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
371
-
0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
372
-
0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
373
-
0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
374
-
0xb800, 0xb802,
370
+
0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b,
371
+
0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440,
372
+
0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802,
373
+
0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02,
374
+
0x26000, 0x26002,
375
375
/* GPU CC ACD */
376
-
0xbc00, 0xbc16, 0xbc20, 0xbc27,
376
+
0x26400, 0x26416, 0x26420, 0x26427,
377
377
};
378
378
379
379
static const u32 a621_gmu_gpucc_registers[] = {
380
380
/* GPU CC */
381
-
0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,
382
-
0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,
383
-
0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,
384
-
0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,
385
-
0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,
386
-
0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,
387
-
0xbe20, 0xbe2d,
381
+
0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04,
382
+
0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430,
383
+
0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a,
384
+
0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5,
385
+
0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc,
386
+
0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616,
387
+
0x26620, 0x2662d,
388
388
};
389
389
390
390
static const u32 a6xx_gmu_cx_rscc_registers[] = {
···
575
575
/* statetype: SP block state type for the cluster */
576
576
enum a7xx_statetype_id statetype;
577
577
/* pipe_id: Pipe identifier */
578
-
enum a7xx_pipe pipe_id;
578
+
enum adreno_pipe pipe_id;
579
579
/* context_id: Context identifier */
580
580
int context_id;
581
581
/* location_id: Location identifier */
···
801
801
};
802
802
803
803
static const char *a7xx_pipe_names[] = {
804
-
A7XX_NAME(A7XX_PIPE_NONE),
805
-
A7XX_NAME(A7XX_PIPE_BR),
806
-
A7XX_NAME(A7XX_PIPE_BV),
807
-
A7XX_NAME(A7XX_PIPE_LPAC),
804
+
A7XX_NAME(PIPE_NONE),
805
+
A7XX_NAME(PIPE_BR),
806
+
A7XX_NAME(PIPE_BV),
807
+
A7XX_NAME(PIPE_LPAC),
808
808
};
809
809
810
810
static const char *a7xx_cluster_names[] = {
+71
-3
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+71
-3
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
···
23
23
HFI_MSG_ID(HFI_H2F_MSG_START),
24
24
HFI_MSG_ID(HFI_H2F_FEATURE_CTRL),
25
25
HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START),
26
+
HFI_MSG_ID(HFI_H2F_MSG_TABLE),
26
27
HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE),
27
28
HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER),
28
29
};
···
106
105
{
107
106
int ret;
108
107
u32 val;
108
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
109
109
110
-
/* Wait for a response */
111
-
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
112
-
val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 1000000);
110
+
do {
111
+
/* Wait for a response */
112
+
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
113
+
val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 1000000);
114
+
115
+
if (!ret)
116
+
break;
117
+
118
+
if (completion_done(&a6xx_gpu->base.fault_coredump_done))
119
+
break;
120
+
121
+
/* We may timeout because the GMU is temporarily wedged from
122
+
* pending faults from the GPU and we are taking a devcoredump.
123
+
* Wait until the MMU is resumed and try again.
124
+
*/
125
+
wait_for_completion(&a6xx_gpu->base.fault_coredump_done);
126
+
} while (true);
113
127
114
128
if (ret) {
115
129
DRM_DEV_ERROR(gmu->dev,
···
271
255
NULL, 0);
272
256
}
273
257
258
+
static int a8xx_hfi_send_perf_table(struct a6xx_gmu *gmu)
259
+
{
260
+
unsigned int num_gx_votes = 3, num_cx_votes = 2;
261
+
struct a6xx_hfi_table_entry *entry;
262
+
struct a6xx_hfi_table *tbl;
263
+
int ret, i;
264
+
u32 size;
265
+
266
+
size = sizeof(*tbl) + (2 * sizeof(tbl->entry[0])) +
267
+
(gmu->nr_gpu_freqs * num_gx_votes * sizeof(gmu->gx_arc_votes[0])) +
268
+
(gmu->nr_gmu_freqs * num_cx_votes * sizeof(gmu->cx_arc_votes[0]));
269
+
tbl = kzalloc(size, GFP_KERNEL);
270
+
tbl->type = HFI_TABLE_GPU_PERF;
271
+
272
+
/* First fill GX votes */
273
+
entry = &tbl->entry[0];
274
+
entry->count = gmu->nr_gpu_freqs;
275
+
entry->stride = num_gx_votes;
276
+
277
+
for (i = 0; i < gmu->nr_gpu_freqs; i++) {
278
+
unsigned int base = i * entry->stride;
279
+
280
+
entry->data[base+0] = gmu->gx_arc_votes[i];
281
+
entry->data[base+1] = gmu->dep_arc_votes[i];
282
+
entry->data[base+2] = gmu->gpu_freqs[i] / 1000;
283
+
}
284
+
285
+
/* Then fill CX votes */
286
+
entry = (struct a6xx_hfi_table_entry *)
287
+
&tbl->entry[0].data[gmu->nr_gpu_freqs * num_gx_votes];
288
+
289
+
entry->count = gmu->nr_gmu_freqs;
290
+
entry->stride = num_cx_votes;
291
+
292
+
for (i = 0; i < gmu->nr_gmu_freqs; i++) {
293
+
unsigned int base = i * entry->stride;
294
+
295
+
entry->data[base] = gmu->cx_arc_votes[i];
296
+
entry->data[base+1] = gmu->gmu_freqs[i] / 1000;
297
+
}
298
+
299
+
ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0);
300
+
301
+
kfree(tbl);
302
+
return ret;
303
+
}
304
+
274
305
static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu)
275
306
{
307
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
308
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
276
309
struct a6xx_hfi_msg_perf_table msg = { 0 };
277
310
int i;
311
+
312
+
if (adreno_is_a8xx(adreno_gpu))
313
+
return a8xx_hfi_send_perf_table(gmu);
278
314
279
315
msg.num_gpu_levels = gmu->nr_gpu_freqs;
280
316
msg.num_gmu_levels = gmu->nr_gmu_freqs;
+17
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+17
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
···
185
185
u32 handle;
186
186
};
187
187
188
+
#define HFI_H2F_MSG_TABLE 15
189
+
190
+
struct a6xx_hfi_table_entry {
191
+
u32 count;
192
+
u32 stride;
193
+
u32 data[];
194
+
};
195
+
196
+
struct a6xx_hfi_table {
197
+
u32 header;
198
+
u32 version;
199
+
u32 type;
200
+
#define HFI_TABLE_BW_VOTE 0
201
+
#define HFI_TABLE_GPU_PERF 1
202
+
struct a6xx_hfi_table_entry entry[];
203
+
};
204
+
188
205
#define HFI_H2F_MSG_GX_BW_PERF_VOTE 30
189
206
190
207
struct a6xx_hfi_gx_bw_perf_vote_cmd {
+1201
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+1201
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */
3
+
4
+
5
+
#include "msm_gem.h"
6
+
#include "msm_mmu.h"
7
+
#include "msm_gpu_trace.h"
8
+
#include "a6xx_gpu.h"
9
+
#include "a6xx_gmu.xml.h"
10
+
11
+
#include <linux/bitfield.h>
12
+
#include <linux/devfreq.h>
13
+
#include <linux/firmware/qcom/qcom_scm.h>
14
+
#include <linux/pm_domain.h>
15
+
#include <linux/soc/qcom/llcc-qcom.h>
16
+
17
+
#define GPU_PAS_ID 13
18
+
19
+
static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice)
20
+
{
21
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
22
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
23
+
u32 val;
24
+
25
+
val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice);
26
+
27
+
if (a6xx_gpu->cached_aperture == val)
28
+
return;
29
+
30
+
gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val);
31
+
32
+
a6xx_gpu->cached_aperture = val;
33
+
}
34
+
35
+
static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags)
36
+
{
37
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
38
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
39
+
40
+
spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags);
41
+
42
+
a8xx_aperture_slice_set(gpu, pipe, 0);
43
+
}
44
+
45
+
static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags)
46
+
{
47
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
48
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
49
+
50
+
spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags);
51
+
}
52
+
53
+
static void a8xx_aperture_clear(struct msm_gpu *gpu)
54
+
{
55
+
unsigned long flags;
56
+
57
+
a8xx_aperture_acquire(gpu, PIPE_NONE, &flags);
58
+
a8xx_aperture_release(gpu, flags);
59
+
}
60
+
61
+
static void a8xx_write_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 offset, u32 data)
62
+
{
63
+
unsigned long flags;
64
+
65
+
a8xx_aperture_acquire(gpu, pipe, &flags);
66
+
gpu_write(gpu, offset, data);
67
+
a8xx_aperture_release(gpu, flags);
68
+
}
69
+
70
+
static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice, u32 offset)
71
+
{
72
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
73
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
74
+
unsigned long flags;
75
+
u32 val;
76
+
77
+
spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags);
78
+
a8xx_aperture_slice_set(gpu, pipe, slice);
79
+
val = gpu_read(gpu, offset);
80
+
spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags);
81
+
82
+
return val;
83
+
}
84
+
85
+
void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
86
+
{
87
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
88
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
89
+
const struct a6xx_info *info = adreno_gpu->info->a6xx;
90
+
u32 slice_mask;
91
+
92
+
if (adreno_gpu->info->family < ADRENO_8XX_GEN1)
93
+
return;
94
+
95
+
if (a6xx_gpu->slice_mask)
96
+
return;
97
+
98
+
slice_mask = GENMASK(info->max_slices - 1, 0);
99
+
100
+
/* GEN1 doesn't support partial slice configurations */
101
+
if (adreno_gpu->info->family == ADRENO_8XX_GEN1) {
102
+
a6xx_gpu->slice_mask = slice_mask;
103
+
return;
104
+
}
105
+
106
+
slice_mask &= a6xx_llc_read(a6xx_gpu,
107
+
REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL);
108
+
109
+
a6xx_gpu->slice_mask = slice_mask;
110
+
111
+
/* Chip ID depends on the number of slices available. So update it */
112
+
adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask));
113
+
}
114
+
115
+
static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu)
116
+
{
117
+
return ffs(a6xx_gpu->slice_mask) - 1;
118
+
}
119
+
120
+
static inline bool _a8xx_check_idle(struct msm_gpu *gpu)
121
+
{
122
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
123
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
124
+
125
+
/* Check that the GMU is idle */
126
+
if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
127
+
return false;
128
+
129
+
/* Check that the CX master is idle */
130
+
if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) &
131
+
~A8XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
132
+
return false;
133
+
134
+
return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) &
135
+
A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
136
+
}
137
+
138
+
static bool a8xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
139
+
{
140
+
/* wait for CP to drain ringbuffer: */
141
+
if (!adreno_idle(gpu, ring))
142
+
return false;
143
+
144
+
if (spin_until(_a8xx_check_idle(gpu))) {
145
+
DRM_ERROR(
146
+
"%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
147
+
gpu->name, __builtin_return_address(0),
148
+
gpu_read(gpu, REG_A8XX_RBBM_STATUS),
149
+
gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS),
150
+
gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
151
+
gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
152
+
return false;
153
+
}
154
+
155
+
return true;
156
+
}
157
+
158
+
void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
159
+
{
160
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
161
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
162
+
uint32_t wptr;
163
+
unsigned long flags;
164
+
165
+
spin_lock_irqsave(&ring->preempt_lock, flags);
166
+
167
+
/* Copy the shadow to the actual register */
168
+
ring->cur = ring->next;
169
+
170
+
/* Make sure to wrap wptr if we need to */
171
+
wptr = get_wptr(ring);
172
+
173
+
/* Update HW if this is the current ring and we are not in preempt*/
174
+
if (!a6xx_in_preempt(a6xx_gpu)) {
175
+
if (a6xx_gpu->cur_ring == ring)
176
+
gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
177
+
else
178
+
ring->restore_wptr = true;
179
+
} else {
180
+
ring->restore_wptr = true;
181
+
}
182
+
183
+
spin_unlock_irqrestore(&ring->preempt_lock, flags);
184
+
}
185
+
186
+
static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state)
187
+
{
188
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
189
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
190
+
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
191
+
u32 val;
192
+
193
+
if (adreno_is_x285(adreno_gpu) && state)
194
+
gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702);
195
+
196
+
gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
197
+
state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
198
+
gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
199
+
state ? 0x110111 : 0);
200
+
gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
201
+
state ? 0x55555 : 0);
202
+
203
+
gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
204
+
gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, !!state);
205
+
206
+
if (state) {
207
+
gpu_write(gpu, REG_A8XX_RBBM_CGC_P2S_TRIG_CMD, 1);
208
+
209
+
if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_CGC_P2S_STATUS, val,
210
+
val & A8XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) {
211
+
dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n");
212
+
return;
213
+
}
214
+
215
+
gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 0);
216
+
} else {
217
+
/*
218
+
* GMU enables clk gating in GBIF during boot up. So,
219
+
* override that here when hwcg feature is disabled
220
+
*/
221
+
gpu_rmw(gpu, REG_A8XX_GBIF_CX_CONFIG, BIT(0), 0);
222
+
}
223
+
}
224
+
225
+
static void a8xx_set_cp_protect(struct msm_gpu *gpu)
226
+
{
227
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
228
+
const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect;
229
+
u32 cntl, final_cfg;
230
+
unsigned int i;
231
+
232
+
cntl = A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_PROT_EN |
233
+
A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_FAULT_ON_VIOL_EN |
234
+
A8XX_CP_PROTECT_CNTL_PIPE_LAST_SPAN_INF_RANGE |
235
+
A8XX_CP_PROTECT_CNTL_PIPE_HALT_SQE_RANGE__MASK;
236
+
/*
237
+
* Enable access protection to privileged registers, fault on an access
238
+
* protect violation and select the last span to protect from the start
239
+
* address all the way to the end of the register address space
240
+
*/
241
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl);
242
+
a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl);
243
+
244
+
a8xx_aperture_clear(gpu);
245
+
246
+
for (i = 0; i < protect->count; i++) {
247
+
/* Intentionally skip writing to some registers */
248
+
if (protect->regs[i]) {
249
+
gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]);
250
+
final_cfg = protect->regs[i];
251
+
}
252
+
}
253
+
254
+
/*
255
+
* Last span feature is only supported on PIPE specific register.
256
+
* So update those here
257
+
*/
258
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
259
+
a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
260
+
261
+
a8xx_aperture_clear(gpu);
262
+
}
263
+
264
+
static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
265
+
{
266
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
267
+
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config;
268
+
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2);
269
+
u32 level3_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL3);
270
+
bool rgba8888_lossless = false, fp16compoptdis = false;
271
+
bool yuvnotcomptofc = false, min_acc_len_64b = false;
272
+
bool rgb565_predicator = false, amsbc = false;
273
+
bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
274
+
u32 ubwc_version = cfg->ubwc_enc_version;
275
+
u32 hbb, hbb_hi, hbb_lo, mode = 1;
276
+
u8 uavflagprd_inv = 2;
277
+
278
+
switch (ubwc_version) {
279
+
case UBWC_5_0:
280
+
amsbc = true;
281
+
rgb565_predicator = true;
282
+
mode = 4;
283
+
break;
284
+
case UBWC_4_0:
285
+
amsbc = true;
286
+
rgb565_predicator = true;
287
+
fp16compoptdis = true;
288
+
rgba8888_lossless = true;
289
+
mode = 2;
290
+
break;
291
+
case UBWC_3_0:
292
+
amsbc = true;
293
+
mode = 1;
294
+
break;
295
+
default:
296
+
dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", ubwc_version);
297
+
break;
298
+
}
299
+
300
+
/*
301
+
* We subtract 13 from the highest bank bit (13 is the minimum value
302
+
* allowed by hw) and write the lowest two bits of the remaining value
303
+
* as hbb_lo and the one above it as hbb_hi to the hardware.
304
+
*/
305
+
WARN_ON(cfg->highest_bank_bit < 13);
306
+
hbb = cfg->highest_bank_bit - 13;
307
+
hbb_hi = hbb >> 2;
308
+
hbb_lo = hbb & 3;
309
+
a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5);
310
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5);
311
+
312
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CCU_NC_MODE_CNTL,
313
+
yuvnotcomptofc << 6 |
314
+
hbb_hi << 3 |
315
+
hbb_lo << 1);
316
+
317
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CMP_NC_MODE_CNTL,
318
+
mode << 15 |
319
+
yuvnotcomptofc << 6 |
320
+
rgba8888_lossless << 4 |
321
+
fp16compoptdis << 3 |
322
+
rgb565_predicator << 2 |
323
+
amsbc << 1 |
324
+
min_acc_len_64b);
325
+
326
+
a8xx_aperture_clear(gpu);
327
+
328
+
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
329
+
level3_swizzling_dis << 13 |
330
+
level2_swizzling_dis << 12 |
331
+
hbb_hi << 10 |
332
+
uavflagprd_inv << 4 |
333
+
min_acc_len_64b << 3 |
334
+
hbb_lo << 1 | ubwc_mode);
335
+
336
+
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
337
+
level3_swizzling_dis << 7 |
338
+
level2_swizzling_dis << 6 |
339
+
hbb_hi << 4 |
340
+
min_acc_len_64b << 3 |
341
+
hbb_lo << 1 | ubwc_mode);
342
+
}
343
+
344
+
static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect)
345
+
{
346
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
347
+
const struct a6xx_info *info = adreno_gpu->info->a6xx;
348
+
const struct adreno_reglist_pipe *regs = info->nonctxt_reglist;
349
+
unsigned int pipe_id, i;
350
+
unsigned long flags;
351
+
352
+
for (pipe_id = PIPE_NONE; pipe_id <= PIPE_DDE_BV; pipe_id++) {
353
+
/* We don't have support for LPAC yet */
354
+
if (pipe_id == PIPE_LPAC)
355
+
continue;
356
+
357
+
a8xx_aperture_acquire(gpu, pipe_id, &flags);
358
+
359
+
for (i = 0; regs[i].offset; i++) {
360
+
if (!(BIT(pipe_id) & regs[i].pipe))
361
+
continue;
362
+
363
+
if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT)
364
+
*gmem_protect = regs[i].value;
365
+
366
+
gpu_write(gpu, regs[i].offset, regs[i].value);
367
+
}
368
+
369
+
a8xx_aperture_release(gpu, flags);
370
+
}
371
+
372
+
a8xx_aperture_clear(gpu);
373
+
}
374
+
375
+
static int a8xx_cp_init(struct msm_gpu *gpu)
376
+
{
377
+
struct msm_ringbuffer *ring = gpu->rb[0];
378
+
u32 mask;
379
+
380
+
/* Disable concurrent binning before sending CP init */
381
+
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
382
+
OUT_RING(ring, BIT(27));
383
+
384
+
OUT_PKT7(ring, CP_ME_INIT, 4);
385
+
386
+
/* Use multiple HW contexts */
387
+
mask = BIT(0);
388
+
389
+
/* Enable error detection */
390
+
mask |= BIT(1);
391
+
392
+
/* Set default reset state */
393
+
mask |= BIT(3);
394
+
395
+
/* Disable save/restore of performance counters across preemption */
396
+
mask |= BIT(6);
397
+
398
+
OUT_RING(ring, mask);
399
+
400
+
/* Enable multiple hardware contexts */
401
+
OUT_RING(ring, 0x00000003);
402
+
403
+
/* Enable error detection */
404
+
OUT_RING(ring, 0x20000000);
405
+
406
+
/* Operation mode mask */
407
+
OUT_RING(ring, 0x00000002);
408
+
409
+
a6xx_flush(gpu, ring);
410
+
return a8xx_idle(gpu, ring) ? 0 : -EINVAL;
411
+
}
412
+
413
+
#define A8XX_INT_MASK \
414
+
(A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
415
+
A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
416
+
A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \
417
+
A6XX_RBBM_INT_0_MASK_CP_SW | \
418
+
A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
419
+
A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \
420
+
A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \
421
+
A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
422
+
A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
423
+
A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
424
+
A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
425
+
A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
426
+
A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
427
+
A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
428
+
429
+
#define A8XX_APRIV_MASK \
430
+
(A8XX_CP_APRIV_CNTL_PIPE_ICACHE | \
431
+
A8XX_CP_APRIV_CNTL_PIPE_RBFETCH | \
432
+
A8XX_CP_APRIV_CNTL_PIPE_RBPRIVLEVEL | \
433
+
A8XX_CP_APRIV_CNTL_PIPE_RBRPWB)
434
+
435
+
#define A8XX_BR_APRIV_MASK \
436
+
(A8XX_APRIV_MASK | \
437
+
A8XX_CP_APRIV_CNTL_PIPE_CDREAD | \
438
+
A8XX_CP_APRIV_CNTL_PIPE_CDWRITE)
439
+
440
+
#define A8XX_CP_GLOBAL_INT_MASK \
441
+
(A8XX_CP_GLOBAL_INT_MASK_HWFAULTBR | \
442
+
A8XX_CP_GLOBAL_INT_MASK_HWFAULTBV | \
443
+
A8XX_CP_GLOBAL_INT_MASK_HWFAULTLPAC | \
444
+
A8XX_CP_GLOBAL_INT_MASK_HWFAULTAQE0 | \
445
+
A8XX_CP_GLOBAL_INT_MASK_HWFAULTAQE1 | \
446
+
A8XX_CP_GLOBAL_INT_MASK_HWFAULTDDEBR | \
447
+
A8XX_CP_GLOBAL_INT_MASK_HWFAULTDDEBV | \
448
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTBR | \
449
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTBV | \
450
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTLPAC | \
451
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTAQE0 | \
452
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTAQE1 | \
453
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTDDEBR | \
454
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTDDEBV)
455
+
456
+
#define A8XX_CP_INTERRUPT_STATUS_MASK_PIPE \
457
+
(A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFRBWRAP | \
458
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB1WRAP | \
459
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB2WRAP | \
460
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB3WRAP | \
461
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFSDSWRAP | \
462
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFMRBWRAP | \
463
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFVSDWRAP | \
464
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_OPCODEERROR | \
465
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VSDPARITYERROR | \
466
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_REGISTERPROTECTIONERROR | \
467
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_ILLEGALINSTRUCTION | \
468
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_SMMUFAULT | \
469
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPCLIENT| \
470
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPTYPE | \
471
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPREAD | \
472
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESP | \
473
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_RTWROVF | \
474
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTWROVF | \
475
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTREFCNTOVF | \
476
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTCLRRESMISS)
477
+
478
+
#define A8XX_CP_HW_FAULT_STATUS_MASK_PIPE \
479
+
(A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFRBFAULT | \
480
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB1FAULT | \
481
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB2FAULT | \
482
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB3FAULT | \
483
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFSDSFAULT | \
484
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFMRBFAULT | \
485
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFVSDFAULT | \
486
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_SQEREADBURSTOVF | \
487
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_EVENTENGINEOVF | \
488
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_UCODEERROR)
489
+
490
+
static int hw_init(struct msm_gpu *gpu)
491
+
{
492
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
493
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
494
+
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
495
+
unsigned int pipe_id, i;
496
+
u32 gmem_protect = 0;
497
+
u64 gmem_range_min;
498
+
int ret;
499
+
500
+
ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
501
+
if (ret)
502
+
return ret;
503
+
504
+
/* Clear the cached value to force aperture configuration next time */
505
+
a6xx_gpu->cached_aperture = UINT_MAX;
506
+
a8xx_aperture_clear(gpu);
507
+
508
+
/* Clear GBIF halt in case GX domain was not collapsed */
509
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
510
+
gpu_read(gpu, REG_A6XX_GBIF_HALT);
511
+
512
+
gpu_write(gpu, REG_A8XX_RBBM_GBIF_HALT, 0);
513
+
gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT);
514
+
515
+
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
516
+
517
+
/*
518
+
* Disable the trusted memory range - we don't actually supported secure
519
+
* memory rendering at this point in time and we don't want to block off
520
+
* part of the virtual memory space.
521
+
*/
522
+
gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000);
523
+
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
524
+
525
+
/* Make all blocks contribute to the GPU BUSY perf counter */
526
+
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
527
+
528
+
/* Setup GMEM Range in UCHE */
529
+
gmem_range_min = SZ_64M;
530
+
/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
531
+
gpu_write64(gpu, REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, gmem_range_min);
532
+
gpu_write64(gpu, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, gmem_range_min);
533
+
534
+
/* Setup UCHE Trap region */
535
+
gpu_write64(gpu, REG_A8XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base);
536
+
gpu_write64(gpu, REG_A8XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);
537
+
gpu_write64(gpu, REG_A8XX_UCHE_CCHE_TRAP_BASE, adreno_gpu->uche_trap_base);
538
+
gpu_write64(gpu, REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);
539
+
540
+
/* Turn on performance counters */
541
+
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_CNTL, 0x1);
542
+
gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, 0x1);
543
+
544
+
/* Turn on the IFPC counter (countable 4 on XOCLK1) */
545
+
gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1,
546
+
FIELD_PREP(GENMASK(7, 0), 0x4));
547
+
548
+
/* Select CP0 to always count cycles */
549
+
gpu_write(gpu, REG_A8XX_CP_PERFCTR_CP_SEL(0), 1);
550
+
551
+
a8xx_set_ubwc_config(gpu);
552
+
553
+
/* Set weights for bicubic filtering */
554
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0);
555
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 0x3fe05ff4);
556
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 0x3fa0ebee);
557
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 0x3f5193ed);
558
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 0x3f0243f0);
559
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), 0x00000000);
560
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), 0x3fd093e8);
561
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), 0x3f4133dc);
562
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), 0x3ea1dfdb);
563
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), 0x3e0283e0);
564
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), 0x0000ac2b);
565
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), 0x0000f01d);
566
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), 0x00114412);
567
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), 0x0021980a);
568
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), 0x0051ec05);
569
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), 0x0000380e);
570
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), 0x3ff09001);
571
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), 0x3fc10bfa);
572
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), 0x3f9193f7);
573
+
gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), 0x3f7227f7);
574
+
575
+
gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
576
+
577
+
a8xx_nonctxt_config(gpu, &gmem_protect);
578
+
579
+
/* Enable fault detection */
580
+
gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff);
581
+
gpu_write(gpu, REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, BIT(30));
582
+
583
+
/* Set up the CX GMU counter 0 to count busy ticks */
584
+
gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
585
+
586
+
/* Enable the power counter */
587
+
gmu_rmw(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0, 0xff, BIT(5));
588
+
gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
589
+
590
+
/* Protect registers from the CP */
591
+
a8xx_set_cp_protect(gpu);
592
+
593
+
/* Enable the GMEM save/restore feature for preemption */
594
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 1);
595
+
596
+
for (pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) {
597
+
u32 apriv_mask = A8XX_APRIV_MASK;
598
+
unsigned long flags;
599
+
600
+
if (pipe_id == PIPE_LPAC)
601
+
continue;
602
+
603
+
if (pipe_id == PIPE_BR)
604
+
apriv_mask = A8XX_BR_APRIV_MASK;
605
+
606
+
a8xx_aperture_acquire(gpu, pipe_id, &flags);
607
+
gpu_write(gpu, REG_A8XX_CP_APRIV_CNTL_PIPE, apriv_mask);
608
+
gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE,
609
+
A8XX_CP_INTERRUPT_STATUS_MASK_PIPE);
610
+
gpu_write(gpu, REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE,
611
+
A8XX_CP_HW_FAULT_STATUS_MASK_PIPE);
612
+
a8xx_aperture_release(gpu, flags);
613
+
}
614
+
615
+
a8xx_aperture_clear(gpu);
616
+
617
+
/* Enable interrupts */
618
+
gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, A8XX_CP_GLOBAL_INT_MASK);
619
+
gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, A8XX_INT_MASK);
620
+
621
+
ret = adreno_hw_init(gpu);
622
+
if (ret)
623
+
goto out;
624
+
625
+
gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);
626
+
if (a6xx_gpu->aqe_iova)
627
+
gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova);
628
+
629
+
/* Set the ringbuffer address */
630
+
gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova);
631
+
gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
632
+
633
+
/* Configure the RPTR shadow if needed: */
634
+
gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0]));
635
+
gpu_write64(gpu, REG_A8XX_CP_RB_RPTR_ADDR_BV, rbmemptr(gpu->rb[0], bv_rptr));
636
+
637
+
for (i = 0; i < gpu->nr_rings; i++)
638
+
a6xx_gpu->shadow[i] = 0;
639
+
640
+
/* Always come up on rb 0 */
641
+
a6xx_gpu->cur_ring = gpu->rb[0];
642
+
643
+
for (i = 0; i < gpu->nr_rings; i++)
644
+
gpu->rb[i]->cur_ctx_seqno = 0;
645
+
646
+
/* Enable the SQE_to start the CP engine */
647
+
gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 1);
648
+
649
+
ret = a8xx_cp_init(gpu);
650
+
if (ret)
651
+
goto out;
652
+
653
+
/*
654
+
* Try to load a zap shader into the secure world. If successful
655
+
* we can use the CP to switch out of secure mode. If not then we
656
+
* have no resource but to try to switch ourselves out manually. If we
657
+
* guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
658
+
* be blocked and a permissions violation will soon follow.
659
+
*/
660
+
ret = a6xx_zap_shader_init(gpu);
661
+
if (!ret) {
662
+
OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
663
+
OUT_RING(gpu->rb[0], 0x00000000);
664
+
665
+
a6xx_flush(gpu, gpu->rb[0]);
666
+
if (!a8xx_idle(gpu, gpu->rb[0]))
667
+
return -EINVAL;
668
+
} else if (ret == -ENODEV) {
669
+
/*
670
+
* This device does not use zap shader (but print a warning
671
+
* just in case someone got their dt wrong.. hopefully they
672
+
* have a debug UART to realize the error of their ways...
673
+
* if you mess this up you are about to crash horribly)
674
+
*/
675
+
dev_warn_once(gpu->dev->dev,
676
+
"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
677
+
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
678
+
ret = 0;
679
+
} else {
680
+
return ret;
681
+
}
682
+
683
+
/*
684
+
* GMEM_PROTECT register should be programmed after GPU is transitioned to
685
+
* non-secure mode
686
+
*/
687
+
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect);
688
+
WARN_ON(!gmem_protect);
689
+
a8xx_aperture_clear(gpu);
690
+
691
+
/* Enable hardware clockgating */
692
+
a8xx_set_hwcg(gpu, true);
693
+
out:
694
+
/*
695
+
* Tell the GMU that we are done touching the GPU and it can start power
696
+
* management
697
+
*/
698
+
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
699
+
700
+
return ret;
701
+
}
702
+
703
+
int a8xx_hw_init(struct msm_gpu *gpu)
704
+
{
705
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
706
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
707
+
int ret;
708
+
709
+
mutex_lock(&a6xx_gpu->gmu.lock);
710
+
ret = hw_init(gpu);
711
+
mutex_unlock(&a6xx_gpu->gmu.lock);
712
+
713
+
return ret;
714
+
}
715
+
716
+
static void a8xx_dump(struct msm_gpu *gpu)
717
+
{
718
+
DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", gpu_read(gpu, REG_A8XX_RBBM_STATUS));
719
+
adreno_dump(gpu);
720
+
}
721
+
722
+
void a8xx_recover(struct msm_gpu *gpu)
723
+
{
724
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
725
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
726
+
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
727
+
int active_submits;
728
+
729
+
adreno_dump_info(gpu);
730
+
731
+
if (hang_debug)
732
+
a8xx_dump(gpu);
733
+
734
+
/*
735
+
* To handle recovery specific sequences during the rpm suspend we are
736
+
* about to trigger
737
+
*/
738
+
a6xx_gpu->hung = true;
739
+
740
+
/* Halt SQE first */
741
+
gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 3);
742
+
743
+
pm_runtime_dont_use_autosuspend(&gpu->pdev->dev);
744
+
745
+
/* active_submit won't change until we make a submission */
746
+
mutex_lock(&gpu->active_lock);
747
+
active_submits = gpu->active_submits;
748
+
749
+
/*
750
+
* Temporarily clear active_submits count to silence a WARN() in the
751
+
* runtime suspend cb
752
+
*/
753
+
gpu->active_submits = 0;
754
+
755
+
reinit_completion(&gmu->pd_gate);
756
+
dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb);
757
+
dev_pm_genpd_synced_poweroff(gmu->cxpd);
758
+
759
+
/* Drop the rpm refcount from active submits */
760
+
if (active_submits)
761
+
pm_runtime_put(&gpu->pdev->dev);
762
+
763
+
/* And the final one from recover worker */
764
+
pm_runtime_put_sync(&gpu->pdev->dev);
765
+
766
+
if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000)))
767
+
DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n");
768
+
769
+
dev_pm_genpd_remove_notifier(gmu->cxpd);
770
+
771
+
pm_runtime_use_autosuspend(&gpu->pdev->dev);
772
+
773
+
if (active_submits)
774
+
pm_runtime_get(&gpu->pdev->dev);
775
+
776
+
pm_runtime_get_sync(&gpu->pdev->dev);
777
+
778
+
gpu->active_submits = active_submits;
779
+
mutex_unlock(&gpu->active_lock);
780
+
781
+
msm_gpu_hw_init(gpu);
782
+
a6xx_gpu->hung = false;
783
+
}
784
+
785
+
static const char *a8xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
786
+
{
787
+
static const char * const uche_clients[] = {
788
+
"BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP",
789
+
"BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP",
790
+
"STCHE",
791
+
};
792
+
static const char * const uche_clients_lpac[] = {
793
+
"-", "SP_LPAC", "-", "-", "HLSQ_LPAC", "-", "-", "TP_LPAC",
794
+
};
795
+
u32 val;
796
+
797
+
/*
798
+
* The source of the data depends on the mid ID read from FSYNR1.
799
+
* and the client ID read from the UCHE block
800
+
*/
801
+
val = gpu_read(gpu, REG_A8XX_UCHE_CLIENT_PF);
802
+
803
+
val &= GENMASK(6, 0);
804
+
805
+
/* mid=3 refers to BR or BV */
806
+
if (mid == 3) {
807
+
if (val < ARRAY_SIZE(uche_clients))
808
+
return uche_clients[val];
809
+
else
810
+
return "UCHE";
811
+
}
812
+
813
+
/* mid=8 refers to LPAC */
814
+
if (mid == 8) {
815
+
if (val < ARRAY_SIZE(uche_clients_lpac))
816
+
return uche_clients_lpac[val];
817
+
else
818
+
return "UCHE_LPAC";
819
+
}
820
+
821
+
return "Unknown";
822
+
}
823
+
824
+
static const char *a8xx_fault_block(struct msm_gpu *gpu, u32 id)
825
+
{
826
+
switch (id) {
827
+
case 0x0:
828
+
return "CP";
829
+
case 0x1:
830
+
return "UCHE: Unknown";
831
+
case 0x2:
832
+
return "UCHE_LPAC: Unknown";
833
+
case 0x3:
834
+
case 0x8:
835
+
return a8xx_uche_fault_block(gpu, id);
836
+
case 0x4:
837
+
return "CCU";
838
+
case 0x5:
839
+
return "Flag cache";
840
+
case 0x6:
841
+
return "PREFETCH";
842
+
case 0x7:
843
+
return "GMU";
844
+
case 0x9:
845
+
return "UCHE_HPAC";
846
+
}
847
+
848
+
return "Unknown";
849
+
}
850
+
851
+
int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
852
+
{
853
+
struct msm_gpu *gpu = arg;
854
+
struct adreno_smmu_fault_info *info = data;
855
+
const char *block = "unknown";
856
+
857
+
u32 scratch[] = {
858
+
gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(0)),
859
+
gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(1)),
860
+
gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(2)),
861
+
gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(3)),
862
+
};
863
+
864
+
if (info)
865
+
block = a8xx_fault_block(gpu, info->fsynr1 & 0xff);
866
+
867
+
return adreno_fault_handler(gpu, iova, flags, info, block, scratch);
868
+
}
869
+
870
+
static void a8xx_cp_hw_err_irq(struct msm_gpu *gpu)
871
+
{
872
+
u32 status = gpu_read(gpu, REG_A8XX_CP_INTERRUPT_STATUS_GLOBAL);
873
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
874
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
875
+
u32 slice = a8xx_get_first_slice(a6xx_gpu);
876
+
u32 hw_fault_mask = GENMASK(6, 0);
877
+
u32 sw_fault_mask = GENMASK(22, 16);
878
+
u32 pipe = 0;
879
+
880
+
dev_err_ratelimited(&gpu->pdev->dev, "CP Fault Global INT status: 0x%x\n", status);
881
+
882
+
if (status & (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBR |
883
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTBR))
884
+
pipe |= BIT(PIPE_BR);
885
+
886
+
if (status & (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBV |
887
+
A8XX_CP_GLOBAL_INT_MASK_SWFAULTBV))
888
+
pipe |= BIT(PIPE_BV);
889
+
890
+
if (!pipe) {
891
+
dev_err_ratelimited(&gpu->pdev->dev, "CP Fault Unknown pipe\n");
892
+
goto out;
893
+
}
894
+
895
+
for (unsigned int pipe_id = PIPE_NONE; pipe_id <= PIPE_DDE_BV; pipe_id++) {
896
+
if (!(BIT(pipe_id) & pipe))
897
+
continue;
898
+
899
+
if (hw_fault_mask & status) {
900
+
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
901
+
REG_A8XX_CP_HW_FAULT_STATUS_PIPE);
902
+
dev_err_ratelimited(&gpu->pdev->dev,
903
+
"CP HW FAULT pipe: %u status: 0x%x\n", pipe_id, status);
904
+
}
905
+
906
+
if (sw_fault_mask & status) {
907
+
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
908
+
REG_A8XX_CP_INTERRUPT_STATUS_PIPE);
909
+
dev_err_ratelimited(&gpu->pdev->dev,
910
+
"CP SW FAULT pipe: %u status: 0x%x\n", pipe_id, status);
911
+
912
+
if (status & BIT(8)) {
913
+
a8xx_write_pipe(gpu, pipe_id, REG_A8XX_CP_SQE_STAT_ADDR_PIPE, 1);
914
+
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
915
+
REG_A8XX_CP_SQE_STAT_DATA_PIPE);
916
+
dev_err_ratelimited(&gpu->pdev->dev,
917
+
"CP Opcode error, opcode=0x%x\n", status);
918
+
}
919
+
920
+
if (status & BIT(10)) {
921
+
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
922
+
REG_A8XX_CP_PROTECT_STATUS_PIPE);
923
+
dev_err_ratelimited(&gpu->pdev->dev,
924
+
"CP REG PROTECT error, status=0x%x\n", status);
925
+
}
926
+
}
927
+
}
928
+
929
+
out:
930
+
/* Turn off interrupts to avoid triggering recovery again */
931
+
a8xx_aperture_clear(gpu);
932
+
gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, 0);
933
+
gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, 0);
934
+
935
+
kthread_queue_work(gpu->worker, &gpu->recover_work);
936
+
}
937
+
938
+
static u32 gpu_periph_read(struct msm_gpu *gpu, u32 dbg_offset)
939
+
{
940
+
gpu_write(gpu, REG_A8XX_CP_SQE_UCODE_DBG_ADDR_PIPE, dbg_offset);
941
+
942
+
return gpu_read(gpu, REG_A8XX_CP_SQE_UCODE_DBG_DATA_PIPE);
943
+
}
944
+
945
+
static u64 gpu_periph_read64(struct msm_gpu *gpu, u32 dbg_offset)
946
+
{
947
+
u64 lo, hi;
948
+
949
+
lo = gpu_periph_read(gpu, dbg_offset);
950
+
hi = gpu_periph_read(gpu, dbg_offset + 1);
951
+
952
+
return (hi << 32) | lo;
953
+
}
954
+
955
+
#define CP_PERIPH_IB1_BASE_LO 0x7005
956
+
#define CP_PERIPH_IB1_BASE_HI 0x7006
957
+
#define CP_PERIPH_IB1_SIZE 0x7007
958
+
#define CP_PERIPH_IB1_OFFSET 0x7008
959
+
#define CP_PERIPH_IB2_BASE_LO 0x7009
960
+
#define CP_PERIPH_IB2_BASE_HI 0x700a
961
+
#define CP_PERIPH_IB2_SIZE 0x700b
962
+
#define CP_PERIPH_IB2_OFFSET 0x700c
963
+
#define CP_PERIPH_IB3_BASE_LO 0x700d
964
+
#define CP_PERIPH_IB3_BASE_HI 0x700e
965
+
#define CP_PERIPH_IB3_SIZE 0x700f
966
+
#define CP_PERIPH_IB3_OFFSET 0x7010
967
+
968
+
static void a8xx_fault_detect_irq(struct msm_gpu *gpu)
969
+
{
970
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
971
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
972
+
struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
973
+
unsigned long flags;
974
+
975
+
/*
976
+
* If stalled on SMMU fault, we could trip the GPU's hang detection,
977
+
* but the fault handler will trigger the devcore dump, and we want
978
+
* to otherwise resume normally rather than killing the submit, so
979
+
* just bail.
980
+
*/
981
+
if (gpu_read(gpu, REG_A8XX_RBBM_MISC_STATUS) & A8XX_RBBM_MISC_STATUS_SMMU_STALLED_ON_FAULT)
982
+
return;
983
+
984
+
/*
985
+
* Force the GPU to stay on until after we finish
986
+
* collecting information
987
+
*/
988
+
if (!adreno_has_gmu_wrapper(adreno_gpu))
989
+
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
990
+
991
+
DRM_DEV_ERROR(&gpu->pdev->dev,
992
+
"gpu fault ring %d fence %x status %8.8X gfx_status %8.8X\n",
993
+
ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0,
994
+
gpu_read(gpu, REG_A8XX_RBBM_STATUS), gpu_read(gpu, REG_A8XX_RBBM_GFX_STATUS));
995
+
996
+
a8xx_aperture_acquire(gpu, PIPE_BR, &flags);
997
+
998
+
DRM_DEV_ERROR(&gpu->pdev->dev,
999
+
"BR: status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x ib3 %16.16llX/%4.4x\n",
1000
+
gpu_read(gpu, REG_A8XX_RBBM_GFX_BR_STATUS),
1001
+
gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1002
+
gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1003
+
gpu_periph_read64(gpu, CP_PERIPH_IB1_BASE_LO),
1004
+
gpu_periph_read(gpu, CP_PERIPH_IB1_OFFSET),
1005
+
gpu_periph_read64(gpu, CP_PERIPH_IB2_BASE_LO),
1006
+
gpu_periph_read(gpu, CP_PERIPH_IB2_OFFSET),
1007
+
gpu_periph_read64(gpu, CP_PERIPH_IB3_BASE_LO),
1008
+
gpu_periph_read(gpu, CP_PERIPH_IB3_OFFSET));
1009
+
1010
+
a8xx_aperture_release(gpu, flags);
1011
+
a8xx_aperture_acquire(gpu, PIPE_BV, &flags);
1012
+
1013
+
DRM_DEV_ERROR(&gpu->pdev->dev,
1014
+
"BV: status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x ib3 %16.16llX/%4.4x\n",
1015
+
gpu_read(gpu, REG_A8XX_RBBM_GFX_BV_STATUS),
1016
+
gpu_read(gpu, REG_A8XX_CP_RB_RPTR_BV),
1017
+
gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1018
+
gpu_periph_read64(gpu, CP_PERIPH_IB1_BASE_LO),
1019
+
gpu_periph_read(gpu, CP_PERIPH_IB1_OFFSET),
1020
+
gpu_periph_read64(gpu, CP_PERIPH_IB2_BASE_LO),
1021
+
gpu_periph_read(gpu, CP_PERIPH_IB2_OFFSET),
1022
+
gpu_periph_read64(gpu, CP_PERIPH_IB3_BASE_LO),
1023
+
gpu_periph_read(gpu, CP_PERIPH_IB3_OFFSET));
1024
+
1025
+
a8xx_aperture_release(gpu, flags);
1026
+
a8xx_aperture_clear(gpu);
1027
+
1028
+
/* Turn off the hangcheck timer to keep it from bothering us */
1029
+
timer_delete(&gpu->hangcheck_timer);
1030
+
1031
+
kthread_queue_work(gpu->worker, &gpu->recover_work);
1032
+
}
1033
+
1034
+
static void a8xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
1035
+
{
1036
+
u32 status;
1037
+
1038
+
status = gpu_read(gpu, REG_A8XX_RBBM_SW_FUSE_INT_STATUS);
1039
+
gpu_write(gpu, REG_A8XX_RBBM_SW_FUSE_INT_MASK, 0);
1040
+
1041
+
dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
1042
+
1043
+
/*
1044
+
* Ignore FASTBLEND violations, because the HW will silently fall back
1045
+
* to legacy blending.
1046
+
*/
1047
+
if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
1048
+
A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
1049
+
timer_delete(&gpu->hangcheck_timer);
1050
+
1051
+
kthread_queue_work(gpu->worker, &gpu->recover_work);
1052
+
}
1053
+
}
1054
+
1055
+
irqreturn_t a8xx_irq(struct msm_gpu *gpu)
1056
+
{
1057
+
struct msm_drm_private *priv = gpu->dev->dev_private;
1058
+
u32 status = gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS);
1059
+
1060
+
gpu_write(gpu, REG_A8XX_RBBM_INT_CLEAR_CMD, status);
1061
+
1062
+
if (priv->disable_err_irq)
1063
+
status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
1064
+
1065
+
if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1066
+
a8xx_fault_detect_irq(gpu);
1067
+
1068
+
if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
1069
+
u32 rl0, rl1;
1070
+
1071
+
rl0 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0);
1072
+
rl1 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1);
1073
+
dev_err_ratelimited(&gpu->pdev->dev,
1074
+
"CP | AHB bus error RL_ERROR_0: %x, RL_ERROR_1: %x\n", rl0, rl1);
1075
+
}
1076
+
1077
+
if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1078
+
a8xx_cp_hw_err_irq(gpu);
1079
+
1080
+
if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1081
+
dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1082
+
1083
+
if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1084
+
dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1085
+
1086
+
if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1087
+
dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1088
+
1089
+
if (status & A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
1090
+
dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Trap interrupt\n");
1091
+
1092
+
if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
1093
+
a8xx_sw_fuse_violation_irq(gpu);
1094
+
1095
+
if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) {
1096
+
msm_gpu_retire(gpu);
1097
+
a6xx_preempt_trigger(gpu);
1098
+
}
1099
+
1100
+
if (status & A6XX_RBBM_INT_0_MASK_CP_SW)
1101
+
a6xx_preempt_irq(gpu);
1102
+
1103
+
return IRQ_HANDLED;
1104
+
}
1105
+
1106
+
void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1107
+
{
1108
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1109
+
struct msm_gpu *gpu = &adreno_gpu->base;
1110
+
1111
+
if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1112
+
u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1113
+
1114
+
gpu_scid &= GENMASK(5, 0);
1115
+
1116
+
gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1,
1117
+
FIELD_PREP(GENMASK(29, 24), gpu_scid) |
1118
+
FIELD_PREP(GENMASK(23, 18), gpu_scid) |
1119
+
FIELD_PREP(GENMASK(17, 12), gpu_scid) |
1120
+
FIELD_PREP(GENMASK(11, 6), gpu_scid) |
1121
+
FIELD_PREP(GENMASK(5, 0), gpu_scid));
1122
+
1123
+
gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0,
1124
+
FIELD_PREP(GENMASK(27, 22), gpu_scid) |
1125
+
FIELD_PREP(GENMASK(21, 16), gpu_scid) |
1126
+
FIELD_PREP(GENMASK(15, 10), gpu_scid) |
1127
+
BIT(8));
1128
+
}
1129
+
1130
+
llcc_slice_activate(a6xx_gpu->htw_llc_slice);
1131
+
}
1132
+
1133
+
#define GBIF_CLIENT_HALT_MASK BIT(0)
1134
+
#define GBIF_ARB_HALT_MASK BIT(1)
1135
+
#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0)
1136
+
#define VBIF_RESET_ACK_MASK 0xF0
1137
+
#define GPR0_GBIF_HALT_REQUEST 0x1E0
1138
+
1139
+
void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off)
1140
+
{
1141
+
struct msm_gpu *gpu = &adreno_gpu->base;
1142
+
1143
+
if (gx_off) {
1144
+
/* Halt the gx side of GBIF */
1145
+
gpu_write(gpu, REG_A8XX_RBBM_GBIF_HALT, 1);
1146
+
spin_until(gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT_ACK) & 1);
1147
+
}
1148
+
1149
+
/* Halt new client requests on GBIF */
1150
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1151
+
spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1152
+
(GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1153
+
1154
+
/* Halt all AXI requests on GBIF */
1155
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1156
+
spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1157
+
(GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1158
+
1159
+
/* The GBIF halt needs to be explicitly cleared */
1160
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1161
+
}
1162
+
1163
+
int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1164
+
{
1165
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1166
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1167
+
1168
+
mutex_lock(&a6xx_gpu->gmu.lock);
1169
+
1170
+
/* Force the GPU power on so we can read this register */
1171
+
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1172
+
1173
+
*value = gpu_read64(gpu, REG_A8XX_CP_ALWAYS_ON_COUNTER);
1174
+
1175
+
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1176
+
1177
+
mutex_unlock(&a6xx_gpu->gmu.lock);
1178
+
1179
+
return 0;
1180
+
}
1181
+
1182
+
u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
1183
+
{
1184
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1185
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1186
+
u64 busy_cycles;
1187
+
1188
+
/* 19.2MHz */
1189
+
*out_sample_rate = 19200000;
1190
+
1191
+
busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1192
+
REG_A8XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1193
+
REG_A8XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1194
+
1195
+
return busy_cycles;
1196
+
}
1197
+
1198
+
bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1199
+
{
1200
+
return true;
1201
+
}
+3
-1
drivers/gpu/drm/msm/adreno/adreno_device.c
+3
-1
drivers/gpu/drm/msm/adreno/adreno_device.c
···
34
34
extern const struct adreno_gpulist a5xx_gpulist;
35
35
extern const struct adreno_gpulist a6xx_gpulist;
36
36
extern const struct adreno_gpulist a7xx_gpulist;
37
+
extern const struct adreno_gpulist a8xx_gpulist;
37
38
38
39
static const struct adreno_gpulist *gpulists[] = {
39
40
&a2xx_gpulist,
···
43
42
&a5xx_gpulist,
44
43
&a6xx_gpulist,
45
44
&a7xx_gpulist,
45
+
&a8xx_gpulist,
46
46
};
47
47
48
48
static const struct adreno_info *adreno_info(uint32_t chip_id)
···
237
235
priv->has_cached_coherent =
238
236
!!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
239
237
240
-
gpu = info->init(drm);
238
+
gpu = info->funcs->init(drm);
241
239
if (IS_ERR(gpu)) {
242
240
dev_warn(drm->dev, "failed to load adreno gpu\n");
243
241
return PTR_ERR(gpu);
+210
-210
drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h
+210
-210
drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h
···
82
82
};
83
83
84
84
static const struct gen7_shader_block gen7_0_0_shader_blocks[] = {
85
-
{A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
86
-
{A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
87
-
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
88
-
{A7XX_SP_INST_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
89
-
{A7XX_SP_INST_DATA_1, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
90
-
{A7XX_SP_LB_0_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
91
-
{A7XX_SP_LB_1_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
92
-
{A7XX_SP_LB_2_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
93
-
{A7XX_SP_LB_3_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
94
-
{A7XX_SP_LB_4_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
95
-
{A7XX_SP_LB_5_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
96
-
{A7XX_SP_LB_6_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
97
-
{A7XX_SP_LB_7_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
98
-
{A7XX_SP_CB_RAM, 0x390, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
99
-
{A7XX_SP_INST_TAG, 0x90, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
100
-
{A7XX_SP_INST_DATA_2, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
101
-
{A7XX_SP_TMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
102
-
{A7XX_SP_SMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
103
-
{A7XX_SP_STATE_DATA, 0x40, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
104
-
{A7XX_SP_HWAVE_RAM, 0x100, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
105
-
{A7XX_SP_L0_INST_BUF, 0x50, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
106
-
{A7XX_SP_LB_8_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
107
-
{A7XX_SP_LB_9_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
108
-
{A7XX_SP_LB_10_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
109
-
{A7XX_SP_LB_11_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
110
-
{A7XX_SP_LB_12_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
111
-
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
112
-
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
113
-
{A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
114
-
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
115
-
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
116
-
{A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
117
-
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
118
-
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
119
-
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
120
-
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
121
-
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
122
-
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
123
-
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
124
-
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
125
-
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
126
-
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
127
-
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
128
-
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
129
-
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
130
-
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
131
-
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
132
-
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
133
-
{A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
134
-
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
135
-
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
136
-
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
137
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
138
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
139
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
140
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
141
-
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
142
-
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
143
-
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
144
-
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
145
-
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
146
-
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
147
-
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
148
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
149
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
150
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
151
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
152
-
{A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
153
-
{A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
154
-
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
155
-
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
156
-
{A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
157
-
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
158
-
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
159
-
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
160
-
{A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
161
-
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
162
-
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
163
-
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
85
+
{A7XX_TP0_TMO_DATA, 0x200, 4, 2, PIPE_BR, A7XX_USPTP},
86
+
{A7XX_TP0_SMO_DATA, 0x80, 4, 2, PIPE_BR, A7XX_USPTP},
87
+
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, PIPE_BR, A7XX_USPTP},
88
+
{A7XX_SP_INST_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
89
+
{A7XX_SP_INST_DATA_1, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
90
+
{A7XX_SP_LB_0_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
91
+
{A7XX_SP_LB_1_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
92
+
{A7XX_SP_LB_2_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
93
+
{A7XX_SP_LB_3_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
94
+
{A7XX_SP_LB_4_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
95
+
{A7XX_SP_LB_5_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
96
+
{A7XX_SP_LB_6_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
97
+
{A7XX_SP_LB_7_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
98
+
{A7XX_SP_CB_RAM, 0x390, 4, 2, PIPE_BR, A7XX_USPTP},
99
+
{A7XX_SP_INST_TAG, 0x90, 4, 2, PIPE_BR, A7XX_USPTP},
100
+
{A7XX_SP_INST_DATA_2, 0x200, 4, 2, PIPE_BR, A7XX_USPTP},
101
+
{A7XX_SP_TMO_TAG, 0x80, 4, 2, PIPE_BR, A7XX_USPTP},
102
+
{A7XX_SP_SMO_TAG, 0x80, 4, 2, PIPE_BR, A7XX_USPTP},
103
+
{A7XX_SP_STATE_DATA, 0x40, 4, 2, PIPE_BR, A7XX_USPTP},
104
+
{A7XX_SP_HWAVE_RAM, 0x100, 4, 2, PIPE_BR, A7XX_USPTP},
105
+
{A7XX_SP_L0_INST_BUF, 0x50, 4, 2, PIPE_BR, A7XX_USPTP},
106
+
{A7XX_SP_LB_8_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
107
+
{A7XX_SP_LB_9_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
108
+
{A7XX_SP_LB_10_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
109
+
{A7XX_SP_LB_11_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
110
+
{A7XX_SP_LB_12_DATA, 0x200, 4, 2, PIPE_BR, A7XX_USPTP},
111
+
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
112
+
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
113
+
{A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
114
+
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
115
+
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
116
+
{A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
117
+
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
118
+
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
119
+
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
120
+
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
121
+
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
122
+
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
123
+
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
124
+
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
125
+
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
126
+
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
127
+
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
128
+
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
129
+
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
130
+
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
131
+
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
132
+
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
133
+
{A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
134
+
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
135
+
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
136
+
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
137
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
138
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
139
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
140
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
141
+
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
142
+
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
143
+
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
144
+
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
145
+
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
146
+
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
147
+
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
148
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
149
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
150
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
151
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
152
+
{A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
153
+
{A7XX_HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
154
+
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
155
+
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
156
+
{A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
157
+
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
158
+
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
159
+
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
160
+
{A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
161
+
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
162
+
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
163
+
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
164
164
};
165
165
166
166
static const u32 gen7_0_0_pre_crashdumper_gpu_registers[] = {
···
303
303
};
304
304
static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rbp_pipe_br_registers), 8));
305
305
306
-
/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */
306
+
/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: PIPE_BR */
307
307
static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] = {
308
308
0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
309
309
0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
···
313
313
};
314
314
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_br_registers), 8));
315
315
316
-
/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */
316
+
/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: PIPE_BV */
317
317
static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] = {
318
318
0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
319
319
0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
···
323
323
};
324
324
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_bv_registers), 8));
325
325
326
-
/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
326
+
/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */
327
327
static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] = {
328
328
0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
329
329
0x09b00, 0x09b08,
···
331
331
};
332
332
static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_br_registers), 8));
333
333
334
-
/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
334
+
/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */
335
335
static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] = {
336
336
0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
337
337
0x09b00, 0x09b08,
···
339
339
};
340
340
static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_bv_registers), 8));
341
341
342
-
/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
342
+
/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: PIPE_BR */
343
343
static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] = {
344
344
0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811,
345
345
0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829,
···
355
355
};
356
356
static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rac_cluster_ps_pipe_br_registers), 8));
357
357
358
-
/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
358
+
/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: PIPE_BR */
359
359
static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] = {
360
360
0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812,
361
361
0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a,
···
370
370
};
371
371
static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers), 8));
372
372
373
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
373
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_STATE */
374
374
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = {
375
375
0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7,
376
376
0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba,
···
381
381
};
382
382
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers), 8));
383
383
384
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
384
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLSQ_STATE */
385
385
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = {
386
386
0x0a9b0, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
387
387
0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc,
···
390
390
};
391
391
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8));
392
392
393
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_DP */
393
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_DP */
394
394
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers[] = {
395
395
0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df,
396
396
UINT_MAX, UINT_MAX,
397
397
};
398
398
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers), 8));
399
399
400
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_DP */
400
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLSQ_DP */
401
401
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers[] = {
402
402
0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df,
403
403
UINT_MAX, UINT_MAX,
404
404
};
405
405
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers), 8));
406
406
407
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: SP_TOP */
407
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: SP_TOP */
408
408
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = {
409
409
0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8,
410
410
0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5,
···
414
414
};
415
415
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers), 8));
416
416
417
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */
417
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: SP_TOP */
418
418
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = {
419
419
0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9e2, 0x0a9e3,
420
420
0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00,
···
422
422
};
423
423
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers), 8));
424
424
425
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: uSPTP */
425
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: uSPTP */
426
426
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = {
427
427
0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae,
428
428
0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3,
···
432
432
};
433
433
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers), 8));
434
434
435
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: uSPTP */
435
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: uSPTP */
436
436
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = {
437
437
0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3,
438
438
0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01,
···
440
440
};
441
441
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8));
442
442
443
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
443
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR Location: HLSQ_STATE */
444
444
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = {
445
445
0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
446
446
0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a,
···
453
453
};
454
454
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers), 8));
455
455
456
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */
456
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV Location: HLSQ_STATE */
457
457
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = {
458
458
0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
459
459
0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a,
···
466
466
};
467
467
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers), 8));
468
468
469
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: SP_TOP */
469
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR Location: SP_TOP */
470
470
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = {
471
471
0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831,
472
472
0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d,
···
477
477
};
478
478
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers), 8));
479
479
480
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: SP_TOP */
480
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV Location: SP_TOP */
481
481
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = {
482
482
0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831,
483
483
0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d,
···
488
488
};
489
489
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers), 8));
490
490
491
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: uSPTP */
491
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR Location: uSPTP */
492
492
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = {
493
493
0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833,
494
494
0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867,
···
498
498
};
499
499
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers), 8));
500
500
501
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: uSPTP */
501
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV Location: uSPTP */
502
502
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = {
503
503
0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833,
504
504
0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867,
···
508
508
};
509
509
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers), 8));
510
510
511
-
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR */
511
+
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR */
512
512
static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] = {
513
513
0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307,
514
514
0x0b309, 0x0b309, 0x0b310, 0x0b310,
···
516
516
};
517
517
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers), 8));
518
518
519
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */
519
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV Location: HLSQ_STATE */
520
520
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers[] = {
521
521
0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
522
522
UINT_MAX, UINT_MAX,
523
523
};
524
524
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers), 8));
525
525
526
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: SP_TOP */
526
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV Location: SP_TOP */
527
527
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers[] = {
528
528
0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
529
529
UINT_MAX, UINT_MAX,
530
530
};
531
531
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers), 8));
532
532
533
-
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: uSPTP */
533
+
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV Location: uSPTP */
534
534
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers[] = {
535
535
0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
536
536
UINT_MAX, UINT_MAX,
537
537
};
538
538
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers), 8));
539
539
540
-
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV */
540
+
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV */
541
541
static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers[] = {
542
542
0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
543
543
UINT_MAX, UINT_MAX,
544
544
};
545
545
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers), 8));
546
546
547
-
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC */
547
+
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC */
548
548
static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] = {
549
549
0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309,
550
550
0x0b310, 0x0b310,
···
552
552
};
553
553
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers), 8));
554
554
555
-
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR */
555
+
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR */
556
556
static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers[] = {
557
557
0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
558
558
UINT_MAX, UINT_MAX,
559
559
};
560
560
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers), 8));
561
561
562
-
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV */
562
+
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV */
563
563
static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers[] = {
564
564
0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
565
565
UINT_MAX, UINT_MAX,
566
566
};
567
567
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers), 8));
568
568
569
-
/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
569
+
/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */
570
570
static const u32 gen7_0_0_vfd_cluster_fe_pipe_br_registers[] = {
571
571
0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
572
572
UINT_MAX, UINT_MAX,
573
573
};
574
574
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_br_registers), 8));
575
575
576
-
/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
576
+
/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */
577
577
static const u32 gen7_0_0_vfd_cluster_fe_pipe_bv_registers[] = {
578
578
0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
579
579
UINT_MAX, UINT_MAX,
580
580
};
581
581
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_bv_registers), 8));
582
582
583
-
/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
583
+
/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */
584
584
static const u32 gen7_0_0_vpc_cluster_fe_pipe_br_registers[] = {
585
585
0x09300, 0x09307,
586
586
UINT_MAX, UINT_MAX,
587
587
};
588
588
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_br_registers), 8));
589
589
590
-
/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
590
+
/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */
591
591
static const u32 gen7_0_0_vpc_cluster_fe_pipe_bv_registers[] = {
592
592
0x09300, 0x09307,
593
593
UINT_MAX, UINT_MAX,
594
594
};
595
595
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_bv_registers), 8));
596
596
597
-
/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BR */
597
+
/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: PIPE_BR */
598
598
static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers[] = {
599
599
0x09101, 0x0910c, 0x09300, 0x09307,
600
600
UINT_MAX, UINT_MAX,
601
601
};
602
602
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers), 8));
603
603
604
-
/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BV */
604
+
/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: PIPE_BV */
605
605
static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers[] = {
606
606
0x09101, 0x0910c, 0x09300, 0x09307,
607
607
UINT_MAX, UINT_MAX,
608
608
};
609
609
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers), 8));
610
610
611
-
/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BR */
611
+
/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: PIPE_BR */
612
612
static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers[] = {
613
613
0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307,
614
614
UINT_MAX, UINT_MAX,
615
615
};
616
616
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers), 8));
617
617
618
-
/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BV */
618
+
/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: PIPE_BV */
619
619
static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers[] = {
620
620
0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307,
621
621
UINT_MAX, UINT_MAX,
622
622
};
623
623
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers), 8));
624
624
625
-
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
625
+
/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: HLSQ_STATE */
626
626
static const u32 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers[] = {
627
627
0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae73,
628
628
UINT_MAX, UINT_MAX,
629
629
};
630
630
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers), 8));
631
631
632
-
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: SP_TOP */
632
+
/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: SP_TOP */
633
633
static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] = {
634
634
0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c,
635
635
0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f,
···
638
638
};
639
639
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_sp_top_registers), 8));
640
640
641
-
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: uSPTP */
641
+
/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: uSPTP */
642
642
static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] = {
643
643
0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c,
644
644
0x0ae0f, 0x0ae0f, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3b,
···
647
647
};
648
648
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_usptp_registers), 8));
649
649
650
-
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
650
+
/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: HLSQ_STATE */
651
651
static const u32 gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
652
652
0x0af88, 0x0af8a,
653
653
UINT_MAX, UINT_MAX,
654
654
};
655
655
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
656
656
657
-
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */
657
+
/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: SP_TOP */
658
658
static const u32 gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers[] = {
659
659
0x0af80, 0x0af84,
660
660
UINT_MAX, UINT_MAX,
661
661
};
662
662
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers), 8));
663
663
664
-
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: uSPTP */
664
+
/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: uSPTP */
665
665
static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = {
666
666
0x0af80, 0x0af84, 0x0af90, 0x0af92,
667
667
UINT_MAX, UINT_MAX,
668
668
};
669
669
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8));
670
670
671
-
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */
671
+
/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_NONE */
672
672
static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] = {
673
673
0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c,
674
674
0x0b60f, 0x0b621, 0x0b630, 0x0b633,
···
676
676
};
677
677
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registers), 8));
678
678
679
-
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */
679
+
/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_BR */
680
680
static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {
681
681
0x0b600, 0x0b600,
682
682
UINT_MAX, UINT_MAX,
683
683
};
684
684
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8));
685
685
686
-
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */
686
+
/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_LPAC */
687
687
static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = {
688
688
0x0b780, 0x0b780,
689
689
UINT_MAX, UINT_MAX,
···
691
691
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8));
692
692
693
693
static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = {
694
-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
695
-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
694
+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
695
+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
696
696
.val = 0x0,
697
697
};
698
698
699
699
static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {
700
-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
701
-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
700
+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
701
+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
702
702
.val = 0x9,
703
703
};
704
704
705
705
static const struct gen7_cluster_registers gen7_0_0_clusters[] = {
706
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
706
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
707
707
gen7_0_0_noncontext_pipe_br_registers, },
708
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
708
+
{ A7XX_CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT,
709
709
gen7_0_0_noncontext_pipe_bv_registers, },
710
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
710
+
{ A7XX_CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT,
711
711
gen7_0_0_noncontext_pipe_lpac_registers, },
712
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
712
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
713
713
gen7_0_0_noncontext_rb_rac_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
714
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
714
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
715
715
gen7_0_0_noncontext_rb_rbp_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
716
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
716
+
{ A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0,
717
717
gen7_0_0_gras_cluster_gras_pipe_br_registers, },
718
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
718
+
{ A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0,
719
719
gen7_0_0_gras_cluster_gras_pipe_bv_registers, },
720
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
720
+
{ A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1,
721
721
gen7_0_0_gras_cluster_gras_pipe_br_registers, },
722
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
722
+
{ A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1,
723
723
gen7_0_0_gras_cluster_gras_pipe_bv_registers, },
724
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
724
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
725
725
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
726
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
726
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
727
727
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
728
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
728
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
729
729
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
730
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
730
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
731
731
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
732
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
732
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
733
733
gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
734
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
734
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
735
735
gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
736
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
736
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
737
737
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
738
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
738
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
739
739
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
740
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
740
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
741
741
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
742
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
742
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
743
743
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
744
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
744
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
745
745
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
746
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
746
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
747
747
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
748
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
748
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
749
749
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
750
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
750
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
751
751
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
752
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
752
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
753
753
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
754
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
754
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
755
755
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
756
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
756
+
{ A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0,
757
757
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
758
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
758
+
{ A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0,
759
759
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
760
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
760
+
{ A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1,
761
761
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
762
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
762
+
{ A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1,
763
763
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
764
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
764
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0,
765
765
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
766
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
766
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0,
767
767
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
768
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
768
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1,
769
769
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
770
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
770
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1,
771
771
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
772
772
};
773
773
774
774
static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {
775
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
775
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
776
776
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
777
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
777
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP,
778
778
gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 },
779
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
779
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP,
780
780
gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 },
781
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
781
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE,
782
782
gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 },
783
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
783
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_SP_TOP,
784
784
gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 },
785
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
785
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP,
786
786
gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
787
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
787
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP,
788
788
gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
789
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
789
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP,
790
790
gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
791
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
791
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
792
792
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
793
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
793
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP,
794
794
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
795
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
795
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP,
796
796
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
797
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
797
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP,
798
798
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
799
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
799
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE,
800
800
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
801
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
801
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP,
802
802
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
803
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
803
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP,
804
804
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
805
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
805
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP,
806
806
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
807
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_STATE,
807
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_STATE,
808
808
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
809
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
809
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP,
810
810
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
811
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
811
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP,
812
812
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
813
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
813
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP,
814
814
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
815
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_STATE,
815
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_STATE,
816
816
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
817
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
817
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP,
818
818
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
819
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
819
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP,
820
820
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
821
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
821
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP,
822
822
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
823
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
823
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE,
824
824
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 },
825
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
825
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_DP,
826
826
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 },
827
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
827
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_SP_TOP,
828
828
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 },
829
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
829
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP,
830
830
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 },
831
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
831
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
832
832
gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
833
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
833
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_HLSQ_STATE,
834
834
gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
835
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
835
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP,
836
836
gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
837
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
837
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_SP_TOP,
838
838
gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
839
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
839
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP,
840
840
gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
841
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
841
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP,
842
842
gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
843
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
843
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE,
844
844
gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
845
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
845
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_HLSQ_STATE,
846
846
gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
847
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
847
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP,
848
848
gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
849
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
849
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_SP_TOP,
850
850
gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
851
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
851
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP,
852
852
gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
853
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
853
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP,
854
854
gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
855
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
855
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP,
856
856
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
857
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
857
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP,
858
858
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
859
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
859
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP,
860
860
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
861
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
861
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP,
862
862
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
863
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
863
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP,
864
864
gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 },
865
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
865
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP,
866
866
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
867
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
867
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP,
868
868
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
869
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
869
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP,
870
870
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
871
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
871
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP,
872
872
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
873
873
};
874
874
+166
-166
drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h
+166
-166
drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h
···
96
96
};
97
97
98
98
static const struct gen7_shader_block gen7_2_0_shader_blocks[] = {
99
-
{A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
100
-
{A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
101
-
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
102
-
{A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
103
-
{A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
104
-
{A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
105
-
{A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
106
-
{A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
107
-
{A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
108
-
{A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
109
-
{A7XX_SP_LB_5_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
110
-
{A7XX_SP_LB_6_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
111
-
{A7XX_SP_LB_7_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
112
-
{A7XX_SP_CB_RAM, 0x390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
113
-
{A7XX_SP_LB_13_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
114
-
{A7XX_SP_LB_14_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
115
-
{A7XX_SP_INST_TAG, 0xc0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
116
-
{A7XX_SP_INST_DATA_2, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
117
-
{A7XX_SP_TMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
118
-
{A7XX_SP_SMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
119
-
{A7XX_SP_STATE_DATA, 0x40, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
120
-
{A7XX_SP_HWAVE_RAM, 0x100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
121
-
{A7XX_SP_L0_INST_BUF, 0x50, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
122
-
{A7XX_SP_LB_8_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
123
-
{A7XX_SP_LB_9_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
124
-
{A7XX_SP_LB_10_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
125
-
{A7XX_SP_LB_11_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
126
-
{A7XX_SP_LB_12_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
127
-
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
128
-
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
129
-
{A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
130
-
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
131
-
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
132
-
{A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
133
-
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
134
-
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
135
-
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
136
-
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
137
-
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
138
-
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
139
-
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
140
-
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
141
-
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
142
-
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
143
-
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
144
-
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
145
-
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
146
-
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
147
-
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
148
-
{A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
149
-
{A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
150
-
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
151
-
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
152
-
{A7XX_HLSQ_INST_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
153
-
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
154
-
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
155
-
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
156
-
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
157
-
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
158
-
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
159
-
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
160
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
161
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
162
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
163
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
164
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
165
-
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
166
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
167
-
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
168
-
{A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
169
-
{A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
170
-
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
171
-
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
172
-
{A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
173
-
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
174
-
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
175
-
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
176
-
{A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
177
-
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
178
-
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
179
-
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
99
+
{A7XX_TP0_TMO_DATA, 0x200, 6, 2, PIPE_BR, A7XX_USPTP},
100
+
{A7XX_TP0_SMO_DATA, 0x80, 6, 2, PIPE_BR, A7XX_USPTP},
101
+
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, PIPE_BR, A7XX_USPTP},
102
+
{A7XX_SP_INST_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
103
+
{A7XX_SP_INST_DATA_1, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
104
+
{A7XX_SP_LB_0_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
105
+
{A7XX_SP_LB_1_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
106
+
{A7XX_SP_LB_2_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
107
+
{A7XX_SP_LB_3_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
108
+
{A7XX_SP_LB_4_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
109
+
{A7XX_SP_LB_5_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
110
+
{A7XX_SP_LB_6_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
111
+
{A7XX_SP_LB_7_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
112
+
{A7XX_SP_CB_RAM, 0x390, 6, 2, PIPE_BR, A7XX_USPTP},
113
+
{A7XX_SP_LB_13_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
114
+
{A7XX_SP_LB_14_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
115
+
{A7XX_SP_INST_TAG, 0xc0, 6, 2, PIPE_BR, A7XX_USPTP},
116
+
{A7XX_SP_INST_DATA_2, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
117
+
{A7XX_SP_TMO_TAG, 0x80, 6, 2, PIPE_BR, A7XX_USPTP},
118
+
{A7XX_SP_SMO_TAG, 0x80, 6, 2, PIPE_BR, A7XX_USPTP},
119
+
{A7XX_SP_STATE_DATA, 0x40, 6, 2, PIPE_BR, A7XX_USPTP},
120
+
{A7XX_SP_HWAVE_RAM, 0x100, 6, 2, PIPE_BR, A7XX_USPTP},
121
+
{A7XX_SP_L0_INST_BUF, 0x50, 6, 2, PIPE_BR, A7XX_USPTP},
122
+
{A7XX_SP_LB_8_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
123
+
{A7XX_SP_LB_9_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
124
+
{A7XX_SP_LB_10_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
125
+
{A7XX_SP_LB_11_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
126
+
{A7XX_SP_LB_12_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
127
+
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
128
+
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
129
+
{A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
130
+
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
131
+
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
132
+
{A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
133
+
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
134
+
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
135
+
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
136
+
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
137
+
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
138
+
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
139
+
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
140
+
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
141
+
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
142
+
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
143
+
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
144
+
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
145
+
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
146
+
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
147
+
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
148
+
{A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
149
+
{A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
150
+
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
151
+
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
152
+
{A7XX_HLSQ_INST_RAM, 0x200, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
153
+
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
154
+
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
155
+
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
156
+
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
157
+
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
158
+
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
159
+
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
160
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
161
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
162
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
163
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
164
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
165
+
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
166
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
167
+
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
168
+
{A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
169
+
{A7XX_HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
170
+
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
171
+
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
172
+
{A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
173
+
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
174
+
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
175
+
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
176
+
{A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
177
+
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE},
178
+
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE},
179
+
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE},
180
180
};
181
181
182
182
static const u32 gen7_2_0_gpu_registers[] = {
···
478
478
static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
479
479
480
480
static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = {
481
-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
482
-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
481
+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
482
+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
483
483
.val = 0x0,
484
484
};
485
485
486
486
static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {
487
-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
488
-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
487
+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
488
+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
489
489
.val = 0x9,
490
490
};
491
491
492
492
static const struct gen7_cluster_registers gen7_2_0_clusters[] = {
493
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
493
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
494
494
gen7_2_0_noncontext_pipe_br_registers, },
495
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
495
+
{ A7XX_CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT,
496
496
gen7_2_0_noncontext_pipe_bv_registers, },
497
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
497
+
{ A7XX_CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT,
498
498
gen7_0_0_noncontext_pipe_lpac_registers, },
499
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
499
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
500
500
gen7_2_0_noncontext_rb_rac_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
501
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
501
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
502
502
gen7_2_0_noncontext_rb_rbp_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
503
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
503
+
{ A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0,
504
504
gen7_2_0_gras_cluster_gras_pipe_br_registers, },
505
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
505
+
{ A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0,
506
506
gen7_2_0_gras_cluster_gras_pipe_bv_registers, },
507
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
507
+
{ A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1,
508
508
gen7_2_0_gras_cluster_gras_pipe_br_registers, },
509
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
509
+
{ A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1,
510
510
gen7_2_0_gras_cluster_gras_pipe_bv_registers, },
511
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
511
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
512
512
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
513
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
513
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
514
514
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
515
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
515
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
516
516
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
517
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
517
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
518
518
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
519
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
519
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
520
520
gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
521
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
521
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
522
522
gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
523
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
523
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
524
524
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
525
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
525
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
526
526
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
527
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
527
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
528
528
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
529
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
529
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
530
530
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
531
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
531
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
532
532
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
533
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
533
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
534
534
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
535
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
535
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
536
536
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
537
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
537
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
538
538
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
539
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
539
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
540
540
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
541
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
541
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
542
542
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
543
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
543
+
{ A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0,
544
544
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
545
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
545
+
{ A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0,
546
546
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
547
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
547
+
{ A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1,
548
548
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
549
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
549
+
{ A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1,
550
550
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
551
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
551
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0,
552
552
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
553
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
553
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0,
554
554
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
555
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
555
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1,
556
556
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
557
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
557
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1,
558
558
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
559
559
};
560
560
561
561
static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {
562
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
562
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
563
563
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
564
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
564
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP,
565
565
gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 },
566
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
566
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP,
567
567
gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 },
568
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
568
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE,
569
569
gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 },
570
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
570
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_SP_TOP,
571
571
gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 },
572
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
572
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP,
573
573
gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
574
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
574
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP,
575
575
gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
576
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP,
576
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_NONE, 0, A7XX_USPTP,
577
577
gen7_0_0_tpl1_noncontext_pipe_none_registers, 0xb600 },
578
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
578
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP,
579
579
gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
580
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
580
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
581
581
gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
582
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
582
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP,
583
583
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
584
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
584
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP,
585
585
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
586
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
586
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP,
587
587
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
588
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
588
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE,
589
589
gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
590
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
590
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP,
591
591
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
592
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
592
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP,
593
593
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
594
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
594
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP,
595
595
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
596
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
596
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP,
597
597
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
598
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
598
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP,
599
599
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
600
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
600
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP,
601
601
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
602
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
602
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP,
603
603
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
604
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
604
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP,
605
605
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
606
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
606
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP,
607
607
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
608
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
608
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE,
609
609
gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 },
610
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
610
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_DP,
611
611
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 },
612
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
612
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_SP_TOP,
613
613
gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 },
614
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
614
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP,
615
615
gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 },
616
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
616
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
617
617
gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
618
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
618
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_HLSQ_STATE,
619
619
gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
620
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
620
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP,
621
621
gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
622
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
622
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_SP_TOP,
623
623
gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
624
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
624
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP,
625
625
gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
626
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
626
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP,
627
627
gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
628
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
628
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE,
629
629
gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
630
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
630
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_HLSQ_STATE,
631
631
gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
632
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
632
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP,
633
633
gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
634
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
634
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_SP_TOP,
635
635
gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
636
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
636
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP,
637
637
gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
638
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
638
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP,
639
639
gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
640
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
640
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP,
641
641
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
642
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
642
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP,
643
643
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
644
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
644
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP,
645
645
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
646
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
646
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP,
647
647
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
648
-
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
648
+
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP,
649
649
gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 },
650
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
650
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP,
651
651
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
652
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
652
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP,
653
653
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
654
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
654
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP,
655
655
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
656
-
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
656
+
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP,
657
657
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
658
658
};
659
659
+235
-235
drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
+235
-235
drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
···
118
118
};
119
119
120
120
static const struct gen7_shader_block gen7_9_0_shader_blocks[] = {
121
-
{ A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
122
-
{ A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
123
-
{ A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
124
-
{ A7XX_SP_INST_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
125
-
{ A7XX_SP_INST_DATA_1, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
126
-
{ A7XX_SP_LB_0_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
127
-
{ A7XX_SP_LB_1_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
128
-
{ A7XX_SP_LB_2_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
129
-
{ A7XX_SP_LB_3_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
130
-
{ A7XX_SP_LB_4_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
131
-
{ A7XX_SP_LB_5_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
132
-
{ A7XX_SP_LB_6_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
133
-
{ A7XX_SP_LB_7_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
134
-
{ A7XX_SP_CB_RAM, 0x0390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
135
-
{ A7XX_SP_LB_13_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
136
-
{ A7XX_SP_LB_14_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
137
-
{ A7XX_SP_INST_TAG, 0x00C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
138
-
{ A7XX_SP_INST_DATA_2, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
139
-
{ A7XX_SP_TMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
140
-
{ A7XX_SP_SMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
141
-
{ A7XX_SP_STATE_DATA, 0x0040, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
142
-
{ A7XX_SP_HWAVE_RAM, 0x0100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
143
-
{ A7XX_SP_L0_INST_BUF, 0x0050, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
144
-
{ A7XX_SP_LB_8_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
145
-
{ A7XX_SP_LB_9_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
146
-
{ A7XX_SP_LB_10_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
147
-
{ A7XX_SP_LB_11_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
148
-
{ A7XX_SP_LB_12_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
149
-
{ A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
150
-
{ A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
151
-
{ A7XX_HLSQ_L2STC_TAG_RAM, 0x0200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
152
-
{ A7XX_HLSQ_L2STC_INFO_CMD, 0x0474, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
153
-
{ A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
154
-
{ A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
155
-
{ A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
156
-
{ A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
157
-
{ A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
158
-
{ A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
159
-
{ A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
160
-
{ A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
161
-
{ A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
162
-
{ A7XX_HLSQ_CHUNK_CPS_RAM, 0x0180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
163
-
{ A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
164
-
{ A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
165
-
{ A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
166
-
{ A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
167
-
{ A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
168
-
{ A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
169
-
{ A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
170
-
{ A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
171
-
{ A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
172
-
{ A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
173
-
{ A7XX_HLSQ_CPS_MISC_RAM, 0x0640, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
174
-
{ A7XX_HLSQ_CPS_MISC_RAM, 0x00B0, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
175
-
{ A7XX_HLSQ_CPS_MISC_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
176
-
{ A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
177
-
{ A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
178
-
{ A7XX_HLSQ_INST_RAM, 0x0200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
179
-
{ A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
180
-
{ A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
181
-
{ A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
182
-
{ A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
183
-
{ A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
184
-
{ A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
185
-
{ A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
186
-
{ A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
187
-
{ A7XX_HLSQ_INST_RAM_TAG, 0x0014, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
188
-
{ A7XX_HLSQ_INST_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
189
-
{ A7XX_HLSQ_INST_RAM_TAG, 0x0004, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
190
-
{ A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
191
-
{ A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
192
-
{ A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
193
-
{ A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0020, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
194
-
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x03C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
195
-
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
196
-
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0050, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
197
-
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
198
-
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
199
-
{ A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
200
-
{ A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
201
-
{ A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
202
-
{ A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
203
-
{ A7XX_HLSQ_INST_RAM_2, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
204
-
{ A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
205
-
{ A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
206
-
{ A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
207
-
{ A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
208
-
{ A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
209
-
{ A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
210
-
{ A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
211
-
{ A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
121
+
{ A7XX_TP0_TMO_DATA, 0x0200, 6, 2, PIPE_BR, A7XX_USPTP },
122
+
{ A7XX_TP0_SMO_DATA, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP },
123
+
{ A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, PIPE_BR, A7XX_USPTP },
124
+
{ A7XX_SP_INST_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
125
+
{ A7XX_SP_INST_DATA_1, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
126
+
{ A7XX_SP_LB_0_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
127
+
{ A7XX_SP_LB_1_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
128
+
{ A7XX_SP_LB_2_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
129
+
{ A7XX_SP_LB_3_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
130
+
{ A7XX_SP_LB_4_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
131
+
{ A7XX_SP_LB_5_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
132
+
{ A7XX_SP_LB_6_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
133
+
{ A7XX_SP_LB_7_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
134
+
{ A7XX_SP_CB_RAM, 0x0390, 6, 2, PIPE_BR, A7XX_USPTP },
135
+
{ A7XX_SP_LB_13_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
136
+
{ A7XX_SP_LB_14_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
137
+
{ A7XX_SP_INST_TAG, 0x00C0, 6, 2, PIPE_BR, A7XX_USPTP },
138
+
{ A7XX_SP_INST_DATA_2, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
139
+
{ A7XX_SP_TMO_TAG, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP },
140
+
{ A7XX_SP_SMO_TAG, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP },
141
+
{ A7XX_SP_STATE_DATA, 0x0040, 6, 2, PIPE_BR, A7XX_USPTP },
142
+
{ A7XX_SP_HWAVE_RAM, 0x0100, 6, 2, PIPE_BR, A7XX_USPTP },
143
+
{ A7XX_SP_L0_INST_BUF, 0x0050, 6, 2, PIPE_BR, A7XX_USPTP },
144
+
{ A7XX_SP_LB_8_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
145
+
{ A7XX_SP_LB_9_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
146
+
{ A7XX_SP_LB_10_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
147
+
{ A7XX_SP_LB_11_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
148
+
{ A7XX_SP_LB_12_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
149
+
{ A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
150
+
{ A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
151
+
{ A7XX_HLSQ_L2STC_TAG_RAM, 0x0200, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
152
+
{ A7XX_HLSQ_L2STC_INFO_CMD, 0x0474, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
153
+
{ A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
154
+
{ A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
155
+
{ A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
156
+
{ A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
157
+
{ A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
158
+
{ A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
159
+
{ A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
160
+
{ A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
161
+
{ A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
162
+
{ A7XX_HLSQ_CHUNK_CPS_RAM, 0x0180, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
163
+
{ A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
164
+
{ A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
165
+
{ A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
166
+
{ A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
167
+
{ A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
168
+
{ A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
169
+
{ A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
170
+
{ A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
171
+
{ A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
172
+
{ A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
173
+
{ A7XX_HLSQ_CPS_MISC_RAM, 0x0640, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
174
+
{ A7XX_HLSQ_CPS_MISC_RAM, 0x00B0, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
175
+
{ A7XX_HLSQ_CPS_MISC_RAM_1, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
176
+
{ A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
177
+
{ A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
178
+
{ A7XX_HLSQ_INST_RAM, 0x0200, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
179
+
{ A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
180
+
{ A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
181
+
{ A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
182
+
{ A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
183
+
{ A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
184
+
{ A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
185
+
{ A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0050, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
186
+
{ A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0008, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
187
+
{ A7XX_HLSQ_INST_RAM_TAG, 0x0014, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
188
+
{ A7XX_HLSQ_INST_RAM_TAG, 0x0010, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
189
+
{ A7XX_HLSQ_INST_RAM_TAG, 0x0004, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
190
+
{ A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
191
+
{ A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
192
+
{ A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
193
+
{ A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0020, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
194
+
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x03C0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
195
+
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0280, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
196
+
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0050, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
197
+
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
198
+
{ A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0008, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
199
+
{ A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
200
+
{ A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
201
+
{ A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
202
+
{ A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
203
+
{ A7XX_HLSQ_INST_RAM_2, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
204
+
{ A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
205
+
{ A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
206
+
{ A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
207
+
{ A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
208
+
{ A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
209
+
{ A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE },
210
+
{ A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_BV, A7XX_HLSQ_STATE },
211
+
{ A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE },
212
212
};
213
213
214
214
/*
···
226
226
* Block : ['BROADCAST', 'CP', 'GRAS', 'GXCLKCTL']
227
227
* Block : ['PC', 'RBBM', 'RDVM', 'UCHE']
228
228
* Block : ['VFD', 'VPC', 'VSC']
229
-
* Pipeline: A7XX_PIPE_NONE
229
+
* Pipeline: PIPE_NONE
230
230
* pairs : 196 (Regs:1778)
231
231
*/
232
232
static const u32 gen7_9_0_gpu_registers[] = {
···
290
290
291
291
/*
292
292
* Block : ['GMUAO', 'GMUCX', 'GMUCX_RAM']
293
-
* Pipeline: A7XX_PIPE_NONE
293
+
* Pipeline: PIPE_NONE
294
294
* pairs : 134 (Regs:429)
295
295
*/
296
296
static const u32 gen7_9_0_gmu_registers[] = {
···
334
334
335
335
/*
336
336
* Block : ['GMUGX']
337
-
* Pipeline: A7XX_PIPE_NONE
337
+
* Pipeline: PIPE_NONE
338
338
* pairs : 44 (Regs:454)
339
339
*/
340
340
static const u32 gen7_9_0_gmugx_registers[] = {
···
355
355
356
356
/*
357
357
* Block : ['CX_MISC']
358
-
* Pipeline: A7XX_PIPE_NONE
358
+
* Pipeline: PIPE_NONE
359
359
* pairs : 7 (Regs:56)
360
360
*/
361
361
static const u32 gen7_9_0_cx_misc_registers[] = {
···
367
367
368
368
/*
369
369
* Block : ['DBGC']
370
-
* Pipeline: A7XX_PIPE_NONE
370
+
* Pipeline: PIPE_NONE
371
371
* pairs : 19 (Regs:155)
372
372
*/
373
373
static const u32 gen7_9_0_dbgc_registers[] = {
···
382
382
383
383
/*
384
384
* Block : ['CX_DBGC']
385
-
* Pipeline: A7XX_PIPE_NONE
385
+
* Pipeline: PIPE_NONE
386
386
* pairs : 7 (Regs:75)
387
387
*/
388
388
static const u32 gen7_9_0_cx_dbgc_registers[] = {
···
396
396
* Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
397
397
* Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
398
398
* Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
399
-
* Pipeline: A7XX_PIPE_BR
399
+
* Pipeline: PIPE_BR
400
400
* Cluster : A7XX_CLUSTER_NONE
401
401
* pairs : 29 (Regs:573)
402
402
*/
···
417
417
* Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
418
418
* Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
419
419
* Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
420
-
* Pipeline: A7XX_PIPE_BV
420
+
* Pipeline: PIPE_BV
421
421
* Cluster : A7XX_CLUSTER_NONE
422
422
* pairs : 29 (Regs:573)
423
423
*/
···
438
438
* Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
439
439
* Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
440
440
* Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
441
-
* Pipeline: A7XX_PIPE_LPAC
441
+
* Pipeline: PIPE_LPAC
442
442
* Cluster : A7XX_CLUSTER_NONE
443
443
* pairs : 2 (Regs:7)
444
444
*/
···
450
450
451
451
/*
452
452
* Block : ['RB']
453
-
* Pipeline: A7XX_PIPE_BR
453
+
* Pipeline: PIPE_BR
454
454
* Cluster : A7XX_CLUSTER_NONE
455
455
* pairs : 5 (Regs:37)
456
456
*/
···
463
463
464
464
/*
465
465
* Block : ['RB']
466
-
* Pipeline: A7XX_PIPE_BR
466
+
* Pipeline: PIPE_BR
467
467
* Cluster : A7XX_CLUSTER_NONE
468
468
* pairs : 15 (Regs:66)
469
469
*/
···
478
478
479
479
/*
480
480
* Block : ['SP']
481
-
* Pipeline: A7XX_PIPE_BR
481
+
* Pipeline: PIPE_BR
482
482
* Cluster : A7XX_CLUSTER_NONE
483
483
* Location: A7XX_HLSQ_STATE
484
484
* pairs : 4 (Regs:28)
···
491
491
492
492
/*
493
493
* Block : ['SP']
494
-
* Pipeline: A7XX_PIPE_BR
494
+
* Pipeline: PIPE_BR
495
495
* Cluster : A7XX_CLUSTER_NONE
496
496
* Location: A7XX_SP_TOP
497
497
* pairs : 10 (Regs:61)
···
506
506
507
507
/*
508
508
* Block : ['SP']
509
-
* Pipeline: A7XX_PIPE_BR
509
+
* Pipeline: PIPE_BR
510
510
* Cluster : A7XX_CLUSTER_NONE
511
511
* Location: A7XX_USPTP
512
512
* pairs : 12 (Regs:62)
···
521
521
522
522
/*
523
523
* Block : ['SP']
524
-
* Pipeline: A7XX_PIPE_BR
524
+
* Pipeline: PIPE_BR
525
525
* Cluster : A7XX_CLUSTER_NONE
526
526
* Location: A7XX_HLSQ_DP_STR
527
527
* pairs : 2 (Regs:5)
···
534
534
535
535
/*
536
536
* Block : ['SP']
537
-
* Pipeline: A7XX_PIPE_LPAC
537
+
* Pipeline: PIPE_LPAC
538
538
* Cluster : A7XX_CLUSTER_NONE
539
539
* Location: A7XX_HLSQ_STATE
540
540
* pairs : 1 (Regs:5)
···
547
547
548
548
/*
549
549
* Block : ['SP']
550
-
* Pipeline: A7XX_PIPE_LPAC
550
+
* Pipeline: PIPE_LPAC
551
551
* Cluster : A7XX_CLUSTER_NONE
552
552
* Location: A7XX_SP_TOP
553
553
* pairs : 1 (Regs:6)
···
560
560
561
561
/*
562
562
* Block : ['SP']
563
-
* Pipeline: A7XX_PIPE_LPAC
563
+
* Pipeline: PIPE_LPAC
564
564
* Cluster : A7XX_CLUSTER_NONE
565
565
* Location: A7XX_USPTP
566
566
* pairs : 2 (Regs:9)
···
573
573
574
574
/*
575
575
* Block : ['TPL1']
576
-
* Pipeline: A7XX_PIPE_NONE
576
+
* Pipeline: PIPE_NONE
577
577
* Cluster : A7XX_CLUSTER_NONE
578
578
* Location: A7XX_USPTP
579
579
* pairs : 5 (Regs:29)
···
587
587
588
588
/*
589
589
* Block : ['TPL1']
590
-
* Pipeline: A7XX_PIPE_BR
590
+
* Pipeline: PIPE_BR
591
591
* Cluster : A7XX_CLUSTER_NONE
592
592
* Location: A7XX_USPTP
593
593
* pairs : 1 (Regs:1)
···
600
600
601
601
/*
602
602
* Block : ['TPL1']
603
-
* Pipeline: A7XX_PIPE_LPAC
603
+
* Pipeline: PIPE_LPAC
604
604
* Cluster : A7XX_CLUSTER_NONE
605
605
* Location: A7XX_USPTP
606
606
* pairs : 1 (Regs:1)
···
613
613
614
614
/*
615
615
* Block : ['GRAS']
616
-
* Pipeline: A7XX_PIPE_BR
616
+
* Pipeline: PIPE_BR
617
617
* Cluster : A7XX_CLUSTER_GRAS
618
618
* pairs : 14 (Regs:293)
619
619
*/
···
628
628
629
629
/*
630
630
* Block : ['GRAS']
631
-
* Pipeline: A7XX_PIPE_BV
631
+
* Pipeline: PIPE_BV
632
632
* Cluster : A7XX_CLUSTER_GRAS
633
633
* pairs : 14 (Regs:293)
634
634
*/
···
643
643
644
644
/*
645
645
* Block : ['PC']
646
-
* Pipeline: A7XX_PIPE_BR
646
+
* Pipeline: PIPE_BR
647
647
* Cluster : A7XX_CLUSTER_FE
648
648
* pairs : 6 (Regs:31)
649
649
*/
···
656
656
657
657
/*
658
658
* Block : ['PC']
659
-
* Pipeline: A7XX_PIPE_BV
659
+
* Pipeline: PIPE_BV
660
660
* Cluster : A7XX_CLUSTER_FE
661
661
* pairs : 6 (Regs:31)
662
662
*/
···
669
669
670
670
/*
671
671
* Block : ['VFD']
672
-
* Pipeline: A7XX_PIPE_BR
672
+
* Pipeline: PIPE_BR
673
673
* Cluster : A7XX_CLUSTER_FE
674
674
* pairs : 2 (Regs:236)
675
675
*/
···
681
681
682
682
/*
683
683
* Block : ['VFD']
684
-
* Pipeline: A7XX_PIPE_BV
684
+
* Pipeline: PIPE_BV
685
685
* Cluster : A7XX_CLUSTER_FE
686
686
* pairs : 2 (Regs:236)
687
687
*/
···
693
693
694
694
/*
695
695
* Block : ['VPC']
696
-
* Pipeline: A7XX_PIPE_BR
696
+
* Pipeline: PIPE_BR
697
697
* Cluster : A7XX_CLUSTER_FE
698
698
* pairs : 2 (Regs:18)
699
699
*/
···
705
705
706
706
/*
707
707
* Block : ['VPC']
708
-
* Pipeline: A7XX_PIPE_BR
708
+
* Pipeline: PIPE_BR
709
709
* Cluster : A7XX_CLUSTER_PC_VS
710
710
* pairs : 3 (Regs:30)
711
711
*/
···
717
717
718
718
/*
719
719
* Block : ['VPC']
720
-
* Pipeline: A7XX_PIPE_BR
720
+
* Pipeline: PIPE_BR
721
721
* Cluster : A7XX_CLUSTER_VPC_PS
722
722
* pairs : 5 (Regs:76)
723
723
*/
···
730
730
731
731
/*
732
732
* Block : ['VPC']
733
-
* Pipeline: A7XX_PIPE_BV
733
+
* Pipeline: PIPE_BV
734
734
* Cluster : A7XX_CLUSTER_FE
735
735
* pairs : 2 (Regs:18)
736
736
*/
···
742
742
743
743
/*
744
744
* Block : ['VPC']
745
-
* Pipeline: A7XX_PIPE_BV
745
+
* Pipeline: PIPE_BV
746
746
* Cluster : A7XX_CLUSTER_PC_VS
747
747
* pairs : 3 (Regs:30)
748
748
*/
···
754
754
755
755
/*
756
756
* Block : ['VPC']
757
-
* Pipeline: A7XX_PIPE_BV
757
+
* Pipeline: PIPE_BV
758
758
* Cluster : A7XX_CLUSTER_VPC_PS
759
759
* pairs : 5 (Regs:76)
760
760
*/
···
767
767
768
768
/*
769
769
* Block : ['RB']
770
-
* Pipeline: A7XX_PIPE_BR
770
+
* Pipeline: PIPE_BR
771
771
* Cluster : A7XX_CLUSTER_PS
772
772
* pairs : 39 (Regs:133)
773
773
*/
···
788
788
789
789
/*
790
790
* Block : ['RB']
791
-
* Pipeline: A7XX_PIPE_BR
791
+
* Pipeline: PIPE_BR
792
792
* Cluster : A7XX_CLUSTER_PS
793
793
* pairs : 34 (Regs:100)
794
794
*/
···
808
808
809
809
/*
810
810
* Block : ['SP']
811
-
* Pipeline: A7XX_PIPE_BR
811
+
* Pipeline: PIPE_BR
812
812
* Cluster : A7XX_CLUSTER_SP_VS
813
813
* Location: A7XX_HLSQ_STATE
814
814
* pairs : 29 (Regs:215)
···
828
828
829
829
/*
830
830
* Block : ['SP']
831
-
* Pipeline: A7XX_PIPE_BR
831
+
* Pipeline: PIPE_BR
832
832
* Cluster : A7XX_CLUSTER_SP_VS
833
833
* Location: A7XX_SP_TOP
834
834
* pairs : 22 (Regs:73)
···
846
846
847
847
/*
848
848
* Block : ['SP']
849
-
* Pipeline: A7XX_PIPE_BR
849
+
* Pipeline: PIPE_BR
850
850
* Cluster : A7XX_CLUSTER_SP_VS
851
851
* Location: A7XX_USPTP
852
852
* pairs : 16 (Regs:269)
···
862
862
863
863
/*
864
864
* Block : ['SP']
865
-
* Pipeline: A7XX_PIPE_BR
865
+
* Pipeline: PIPE_BR
866
866
* Cluster : A7XX_CLUSTER_SP_PS
867
867
* Location: A7XX_HLSQ_STATE
868
868
* pairs : 21 (Regs:334)
···
880
880
881
881
/*
882
882
* Block : ['SP']
883
-
* Pipeline: A7XX_PIPE_BR
883
+
* Pipeline: PIPE_BR
884
884
* Cluster : A7XX_CLUSTER_SP_PS
885
885
* Location: A7XX_HLSQ_DP
886
886
* pairs : 3 (Regs:19)
···
893
893
894
894
/*
895
895
* Block : ['SP']
896
-
* Pipeline: A7XX_PIPE_BR
896
+
* Pipeline: PIPE_BR
897
897
* Cluster : A7XX_CLUSTER_SP_PS
898
898
* Location: A7XX_SP_TOP
899
899
* pairs : 18 (Regs:77)
···
910
910
911
911
/*
912
912
* Block : ['SP']
913
-
* Pipeline: A7XX_PIPE_BR
913
+
* Pipeline: PIPE_BR
914
914
* Cluster : A7XX_CLUSTER_SP_PS
915
915
* Location: A7XX_USPTP
916
916
* pairs : 17 (Regs:333)
···
927
927
928
928
/*
929
929
* Block : ['SP']
930
-
* Pipeline: A7XX_PIPE_BR
930
+
* Pipeline: PIPE_BR
931
931
* Cluster : A7XX_CLUSTER_SP_PS
932
932
* Location: A7XX_HLSQ_DP_STR
933
933
* pairs : 1 (Regs:6)
···
940
940
941
941
/*
942
942
* Block : ['SP']
943
-
* Pipeline: A7XX_PIPE_BV
943
+
* Pipeline: PIPE_BV
944
944
* Cluster : A7XX_CLUSTER_SP_VS
945
945
* Location: A7XX_HLSQ_STATE
946
946
* pairs : 28 (Regs:213)
···
959
959
960
960
/*
961
961
* Block : ['SP']
962
-
* Pipeline: A7XX_PIPE_BV
962
+
* Pipeline: PIPE_BV
963
963
* Cluster : A7XX_CLUSTER_SP_VS
964
964
* Location: A7XX_SP_TOP
965
965
* pairs : 21 (Regs:71)
···
977
977
978
978
/*
979
979
* Block : ['SP']
980
-
* Pipeline: A7XX_PIPE_BV
980
+
* Pipeline: PIPE_BV
981
981
* Cluster : A7XX_CLUSTER_SP_VS
982
982
* Location: A7XX_USPTP
983
983
* pairs : 16 (Regs:266)
···
993
993
994
994
/*
995
995
* Block : ['SP']
996
-
* Pipeline: A7XX_PIPE_LPAC
996
+
* Pipeline: PIPE_LPAC
997
997
* Cluster : A7XX_CLUSTER_SP_PS
998
998
* Location: A7XX_HLSQ_STATE
999
999
* pairs : 14 (Regs:299)
···
1009
1009
1010
1010
/*
1011
1011
* Block : ['SP']
1012
-
* Pipeline: A7XX_PIPE_LPAC
1012
+
* Pipeline: PIPE_LPAC
1013
1013
* Cluster : A7XX_CLUSTER_SP_PS
1014
1014
* Location: A7XX_HLSQ_DP
1015
1015
* pairs : 2 (Regs:13)
···
1022
1022
1023
1023
/*
1024
1024
* Block : ['SP']
1025
-
* Pipeline: A7XX_PIPE_LPAC
1025
+
* Pipeline: PIPE_LPAC
1026
1026
* Cluster : A7XX_CLUSTER_SP_PS
1027
1027
* Location: A7XX_SP_TOP
1028
1028
* pairs : 9 (Regs:34)
···
1037
1037
1038
1038
/*
1039
1039
* Block : ['SP']
1040
-
* Pipeline: A7XX_PIPE_LPAC
1040
+
* Pipeline: PIPE_LPAC
1041
1041
* Cluster : A7XX_CLUSTER_SP_PS
1042
1042
* Location: A7XX_USPTP
1043
1043
* pairs : 11 (Regs:279)
···
1052
1052
1053
1053
/*
1054
1054
* Block : ['TPL1']
1055
-
* Pipeline: A7XX_PIPE_BR
1055
+
* Pipeline: PIPE_BR
1056
1056
* Cluster : A7XX_CLUSTER_SP_VS
1057
1057
* Location: A7XX_USPTP
1058
1058
* pairs : 3 (Regs:10)
···
1065
1065
1066
1066
/*
1067
1067
* Block : ['TPL1']
1068
-
* Pipeline: A7XX_PIPE_BR
1068
+
* Pipeline: PIPE_BR
1069
1069
* Cluster : A7XX_CLUSTER_SP_PS
1070
1070
* Location: A7XX_USPTP
1071
1071
* pairs : 6 (Regs:42)
···
1079
1079
1080
1080
/*
1081
1081
* Block : ['TPL1']
1082
-
* Pipeline: A7XX_PIPE_BV
1082
+
* Pipeline: PIPE_BV
1083
1083
* Cluster : A7XX_CLUSTER_SP_VS
1084
1084
* Location: A7XX_USPTP
1085
1085
* pairs : 3 (Regs:10)
···
1092
1092
1093
1093
/*
1094
1094
* Block : ['TPL1']
1095
-
* Pipeline: A7XX_PIPE_LPAC
1095
+
* Pipeline: PIPE_LPAC
1096
1096
* Cluster : A7XX_CLUSTER_SP_PS
1097
1097
* Location: A7XX_USPTP
1098
1098
* pairs : 5 (Regs:7)
···
1105
1105
static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8));
1106
1106
1107
1107
static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = {
1108
-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
1109
-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
1108
+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
1109
+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
1110
1110
.val = 0,
1111
1111
};
1112
1112
1113
1113
static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = {
1114
-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
1115
-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
1114
+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
1115
+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
1116
1116
.val = 0x9,
1117
1117
};
1118
1118
1119
1119
static const struct gen7_cluster_registers gen7_9_0_clusters[] = {
1120
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
1120
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
1121
1121
gen7_9_0_non_context_pipe_br_registers, },
1122
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
1122
+
{ A7XX_CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT,
1123
1123
gen7_9_0_non_context_pipe_bv_registers, },
1124
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
1124
+
{ A7XX_CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT,
1125
1125
gen7_9_0_non_context_pipe_lpac_registers, },
1126
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
1126
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
1127
1127
gen7_9_0_non_context_rb_pipe_br_rac_registers, &gen7_9_0_rb_rac_sel, },
1128
-
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
1128
+
{ A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
1129
1129
gen7_9_0_non_context_rb_pipe_br_rbp_registers, &gen7_9_0_rb_rbp_sel, },
1130
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1130
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
1131
1131
gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, },
1132
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1132
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
1133
1133
gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, },
1134
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1134
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
1135
1135
gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, },
1136
-
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1136
+
{ A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
1137
1137
gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, },
1138
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1138
+
{ A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0,
1139
1139
gen7_9_0_gras_pipe_br_cluster_gras_registers, },
1140
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1140
+
{ A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1,
1141
1141
gen7_9_0_gras_pipe_br_cluster_gras_registers, },
1142
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
1142
+
{ A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0,
1143
1143
gen7_9_0_gras_pipe_bv_cluster_gras_registers, },
1144
-
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
1144
+
{ A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1,
1145
1145
gen7_9_0_gras_pipe_bv_cluster_gras_registers, },
1146
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1146
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
1147
1147
gen7_9_0_pc_pipe_br_cluster_fe_registers, },
1148
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1148
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
1149
1149
gen7_9_0_pc_pipe_br_cluster_fe_registers, },
1150
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
1150
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
1151
1151
gen7_9_0_pc_pipe_bv_cluster_fe_registers, },
1152
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
1152
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
1153
1153
gen7_9_0_pc_pipe_bv_cluster_fe_registers, },
1154
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1154
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
1155
1155
gen7_9_0_vfd_pipe_br_cluster_fe_registers, },
1156
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1156
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
1157
1157
gen7_9_0_vfd_pipe_br_cluster_fe_registers, },
1158
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
1158
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
1159
1159
gen7_9_0_vfd_pipe_bv_cluster_fe_registers, },
1160
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
1160
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
1161
1161
gen7_9_0_vfd_pipe_bv_cluster_fe_registers, },
1162
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1162
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
1163
1163
gen7_9_0_vpc_pipe_br_cluster_fe_registers, },
1164
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1164
+
{ A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
1165
1165
gen7_9_0_vpc_pipe_br_cluster_fe_registers, },
1166
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1166
+
{ A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0,
1167
1167
gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, },
1168
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1168
+
{ A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1,
1169
1169
gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, },
1170
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
1170
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0,
1171
1171
gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, },
1172
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
1172
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1,
1173
1173
gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, },
1174
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
1174
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
1175
1175
gen7_9_0_vpc_pipe_bv_cluster_fe_registers, },
1176
-
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
1176
+
{ A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
1177
1177
gen7_9_0_vpc_pipe_bv_cluster_fe_registers, },
1178
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
1178
+
{ A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0,
1179
1179
gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, },
1180
-
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
1180
+
{ A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1,
1181
1181
gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, },
1182
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
1182
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0,
1183
1183
gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, },
1184
-
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
1184
+
{ A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1,
1185
1185
gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, },
1186
1186
};
1187
1187
1188
1188
static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {
1189
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
1189
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
1190
1190
gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00},
1191
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
1191
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP,
1192
1192
gen7_9_0_non_context_sp_pipe_br_sp_top_registers, 0xae00},
1193
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
1193
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP,
1194
1194
gen7_9_0_non_context_sp_pipe_br_usptp_registers, 0xae00},
1195
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR,
1195
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_DP_STR,
1196
1196
gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers, 0xae00},
1197
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
1197
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE,
1198
1198
gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers, 0xaf80},
1199
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
1199
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_SP_TOP,
1200
1200
gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers, 0xaf80},
1201
-
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
1201
+
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP,
1202
1202
gen7_9_0_non_context_sp_pipe_lpac_usptp_registers, 0xaf80},
1203
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP,
1203
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_NONE, 0, A7XX_USPTP,
1204
1204
gen7_9_0_non_context_tpl1_pipe_none_usptp_registers, 0xb600},
1205
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
1205
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP,
1206
1206
gen7_9_0_non_context_tpl1_pipe_br_usptp_registers, 0xb600},
1207
-
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
1207
+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP,
1208
1208
gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers, 0xb780},
1209
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
1209
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
1210
1210
gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800},
1211
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
1211
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP,
1212
1212
gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800},
1213
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
1213
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP,
1214
1214
gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800},
1215
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
1215
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_HLSQ_STATE,
1216
1216
gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800},
1217
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
1217
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_SP_TOP,
1218
1218
gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800},
1219
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
1219
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP,
1220
1220
gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800},
1221
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
1221
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE,
1222
1222
gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800},
1223
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
1223
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP,
1224
1224
gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800},
1225
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
1225
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP,
1226
1226
gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800},
1227
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
1227
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_HLSQ_STATE,
1228
1228
gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800},
1229
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
1229
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_SP_TOP,
1230
1230
gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800},
1231
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
1231
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP,
1232
1232
gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800},
1233
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
1233
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE,
1234
1234
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800},
1235
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
1235
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP,
1236
1236
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
1237
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
1237
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP,
1238
1238
gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
1239
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
1239
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP,
1240
1240
gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
1241
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR,
1241
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP_STR,
1242
1242
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
1243
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
1243
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE,
1244
1244
gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers, 0xa800},
1245
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
1245
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_DP,
1246
1246
gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers, 0xa800},
1247
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
1247
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_SP_TOP,
1248
1248
gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers, 0xa800},
1249
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
1249
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP,
1250
1250
gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers, 0xa800},
1251
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
1251
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE,
1252
1252
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800},
1253
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
1253
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP,
1254
1254
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
1255
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
1255
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP,
1256
1256
gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
1257
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
1257
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP,
1258
1258
gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
1259
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP_STR,
1259
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP_STR,
1260
1260
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
1261
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
1261
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP,
1262
1262
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
1263
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
1263
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP,
1264
1264
gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
1265
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
1265
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP,
1266
1266
gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
1267
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP_STR,
1267
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP_STR,
1268
1268
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
1269
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
1269
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP,
1270
1270
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
1271
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
1271
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP,
1272
1272
gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
1273
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
1273
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP,
1274
1274
gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
1275
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP_STR,
1275
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP_STR,
1276
1276
gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
1277
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
1277
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP,
1278
1278
gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000},
1279
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
1279
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP,
1280
1280
gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000},
1281
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
1281
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP,
1282
1282
gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000},
1283
-
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
1283
+
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP,
1284
1284
gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000},
1285
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
1285
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP,
1286
1286
gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
1287
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
1287
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP,
1288
1288
gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers, 0xb000},
1289
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
1289
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP,
1290
1290
gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
1291
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
1291
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP,
1292
1292
gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
1293
-
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
1293
+
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP,
1294
1294
gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
1295
1295
};
1296
1296
+12
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+12
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
284
284
struct adreno_smmu_fault_info *info, const char *block,
285
285
u32 scratch[4])
286
286
{
287
+
struct adreno_gpu *adreno_gpu = container_of(gpu, struct adreno_gpu, base);
287
288
struct msm_drm_private *priv = gpu->dev->dev_private;
288
289
struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
289
290
const char *type = "UNKNOWN";
···
337
336
/* Turn off the hangcheck timer to keep it from bothering us */
338
337
timer_delete(&gpu->hangcheck_timer);
339
338
339
+
/* Let any concurrent GMU transactions know that the MMU may be
340
+
* blocked for a while and they should wait on us.
341
+
*/
342
+
reinit_completion(&adreno_gpu->fault_coredump_done);
343
+
340
344
fault_info.ttbr0 = info->ttbr0;
341
345
fault_info.iova = iova;
342
346
fault_info.flags = flags;
···
349
343
fault_info.block = block;
350
344
351
345
msm_gpu_fault_crashstate_capture(gpu, &fault_info);
346
+
347
+
complete_all(&adreno_gpu->fault_coredump_done);
352
348
}
353
349
354
350
return 0;
···
1197
1189
1198
1190
/* Only handle the core clock when GMU is not in use (or is absent). */
1199
1191
if (adreno_has_gmu_wrapper(adreno_gpu) ||
1192
+
adreno_has_rgmu(adreno_gpu) ||
1200
1193
adreno_gpu->info->family < ADRENO_6XX_GEN1) {
1201
1194
/*
1202
1195
* This can only be done before devm_pm_opp_of_add_table(), or
···
1230
1221
ret = adreno_get_pwrlevels(dev, gpu);
1231
1222
if (ret)
1232
1223
return ret;
1224
+
1225
+
init_completion(&adreno_gpu->fault_coredump_done);
1226
+
complete_all(&adreno_gpu->fault_coredump_done);
1233
1227
1234
1228
pm_runtime_set_autosuspend_delay(dev,
1235
1229
adreno_gpu->info->inactive_period);
+46
-10
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+46
-10
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
27
27
ADRENO_FW_PFP = 1,
28
28
ADRENO_FW_GMU = 1, /* a6xx */
29
29
ADRENO_FW_GPMU = 2,
30
+
ADRENO_FW_AQE = 3,
30
31
ADRENO_FW_MAX,
31
32
};
32
33
···
51
50
ADRENO_7XX_GEN1, /* a730 family */
52
51
ADRENO_7XX_GEN2, /* a740 family */
53
52
ADRENO_7XX_GEN3, /* a750 family */
53
+
ADRENO_8XX_GEN1, /* a830 family */
54
+
ADRENO_8XX_GEN2, /* a840 family */
54
55
};
55
56
56
57
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
···
74
71
(((_c) >> 8) & 0xff), \
75
72
((_c) & 0xff)
76
73
74
+
struct adreno_gpu;
75
+
77
76
struct adreno_gpu_funcs {
78
77
struct msm_gpu_funcs base;
78
+
struct msm_gpu *(*init)(struct drm_device *dev);
79
79
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
80
+
void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
81
+
int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
80
82
};
81
83
82
84
struct adreno_reglist {
83
85
u32 offset;
84
86
u32 value;
87
+
};
88
+
89
+
/* Reglist with pipe information */
90
+
struct adreno_reglist_pipe {
91
+
u32 offset;
92
+
u32 value;
93
+
u32 pipe;
85
94
};
86
95
87
96
struct adreno_speedbin {
···
116
101
const char *fw[ADRENO_FW_MAX];
117
102
uint32_t gmem;
118
103
u64 quirks;
119
-
struct msm_gpu *(*init)(struct drm_device *dev);
104
+
const struct adreno_gpu_funcs *funcs;
120
105
const char *zapfw;
121
106
u32 inactive_period;
122
107
union {
···
194
179
uint32_t chip_id;
195
180
uint16_t speedbin;
196
181
const struct adreno_gpu_funcs *funcs;
182
+
183
+
struct completion fault_coredump_done;
197
184
198
185
/* interesting register offsets to dump: */
199
186
const unsigned int *registers;
···
409
392
return adreno_is_revn(gpu, 610);
410
393
}
411
394
395
+
static inline int adreno_is_a612(const struct adreno_gpu *gpu)
396
+
{
397
+
return gpu->info->chip_ids[0] == 0x06010200;
398
+
}
399
+
400
+
static inline bool adreno_has_rgmu(const struct adreno_gpu *gpu)
401
+
{
402
+
return adreno_is_a612(gpu);
403
+
}
404
+
412
405
static inline int adreno_is_a618(const struct adreno_gpu *gpu)
413
406
{
414
407
return adreno_is_revn(gpu, 618);
···
493
466
{
494
467
if (WARN_ON_ONCE(!gpu->info))
495
468
return false;
496
-
497
-
/* TODO: A612 */
498
-
return adreno_is_a610(gpu) || adreno_is_a702(gpu);
469
+
return adreno_is_a610(gpu) ||
470
+
adreno_is_a612(gpu) ||
471
+
adreno_is_a702(gpu);
499
472
}
500
473
501
474
/* TODO: 615/616 */
···
573
546
/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */
574
547
return gpu->info->family == ADRENO_7XX_GEN1 ||
575
548
adreno_is_a740_family(gpu);
549
+
}
550
+
551
+
static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
552
+
{
553
+
return gpu->info->family >= ADRENO_8XX_GEN1;
554
+
}
555
+
556
+
static inline int adreno_is_x285(struct adreno_gpu *gpu)
557
+
{
558
+
return gpu->info->chip_ids[0] == 0x44070001;
559
+
}
560
+
561
+
static inline int adreno_is_a840(struct adreno_gpu *gpu)
562
+
{
563
+
return gpu->info->chip_ids[0] == 0x44050a01;
576
564
}
577
565
578
566
/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
···
714
672
adreno_wait_ring(ring, cnt + 1);
715
673
OUT_RING(ring, PKT7(opcode, cnt));
716
674
}
717
-
718
-
struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
719
-
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
720
-
struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
721
-
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
722
-
struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
723
675
724
676
static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
725
677
{
+541
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
+541
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2025 Linaro Limited
4
+
*/
5
+
6
+
#ifndef _DPU_12_2_GLYMUR_H
7
+
#define _DPU_12_2_GLYMUR_H
8
+
9
+
static const struct dpu_caps glymur_dpu_caps = {
10
+
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
11
+
.max_mixer_blendstages = 0xb,
12
+
.has_src_split = true,
13
+
.has_dim_layer = true,
14
+
.has_idle_pc = true,
15
+
.has_3d_merge = true,
16
+
.max_linewidth = 8192,
17
+
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18
+
};
19
+
20
+
static const struct dpu_mdp_cfg glymur_mdp = {
21
+
.name = "top_0",
22
+
.base = 0, .len = 0x494,
23
+
.clk_ctrls = {
24
+
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
25
+
},
26
+
};
27
+
28
+
static const struct dpu_ctl_cfg glymur_ctl[] = {
29
+
{
30
+
.name = "ctl_0", .id = CTL_0,
31
+
.base = 0x15000, .len = 0x1000,
32
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
33
+
}, {
34
+
.name = "ctl_1", .id = CTL_1,
35
+
.base = 0x16000, .len = 0x1000,
36
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
37
+
}, {
38
+
.name = "ctl_2", .id = CTL_2,
39
+
.base = 0x17000, .len = 0x1000,
40
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
41
+
}, {
42
+
.name = "ctl_3", .id = CTL_3,
43
+
.base = 0x18000, .len = 0x1000,
44
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
45
+
}, {
46
+
.name = "ctl_4", .id = CTL_4,
47
+
.base = 0x19000, .len = 0x1000,
48
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
49
+
}, {
50
+
.name = "ctl_5", .id = CTL_5,
51
+
.base = 0x1a000, .len = 0x1000,
52
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
53
+
}, {
54
+
.name = "ctl_6", .id = CTL_6,
55
+
.base = 0x1b000, .len = 0x1000,
56
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 14),
57
+
}, {
58
+
.name = "ctl_7", .id = CTL_7,
59
+
.base = 0x1c000, .len = 0x1000,
60
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 15),
61
+
},
62
+
};
63
+
64
+
static const struct dpu_sspp_cfg glymur_sspp[] = {
65
+
{
66
+
.name = "sspp_0", .id = SSPP_VIG0,
67
+
.base = 0x4000, .len = 0x344,
68
+
.features = VIG_SDM845_MASK_SDMA,
69
+
.sblk = &dpu_vig_sblk_qseed3_3_4,
70
+
.xin_id = 0,
71
+
.type = SSPP_TYPE_VIG,
72
+
}, {
73
+
.name = "sspp_1", .id = SSPP_VIG1,
74
+
.base = 0x6000, .len = 0x344,
75
+
.features = VIG_SDM845_MASK_SDMA,
76
+
.sblk = &dpu_vig_sblk_qseed3_3_4,
77
+
.xin_id = 4,
78
+
.type = SSPP_TYPE_VIG,
79
+
}, {
80
+
.name = "sspp_2", .id = SSPP_VIG2,
81
+
.base = 0x8000, .len = 0x344,
82
+
.features = VIG_SDM845_MASK_SDMA,
83
+
.sblk = &dpu_vig_sblk_qseed3_3_4,
84
+
.xin_id = 8,
85
+
.type = SSPP_TYPE_VIG,
86
+
}, {
87
+
.name = "sspp_3", .id = SSPP_VIG3,
88
+
.base = 0xa000, .len = 0x344,
89
+
.features = VIG_SDM845_MASK_SDMA,
90
+
.sblk = &dpu_vig_sblk_qseed3_3_4,
91
+
.xin_id = 12,
92
+
.type = SSPP_TYPE_VIG,
93
+
}, {
94
+
.name = "sspp_8", .id = SSPP_DMA0,
95
+
.base = 0x24000, .len = 0x344,
96
+
.features = DMA_SDM845_MASK_SDMA,
97
+
.sblk = &dpu_dma_sblk,
98
+
.xin_id = 1,
99
+
.type = SSPP_TYPE_DMA,
100
+
}, {
101
+
.name = "sspp_9", .id = SSPP_DMA1,
102
+
.base = 0x26000, .len = 0x344,
103
+
.features = DMA_SDM845_MASK_SDMA,
104
+
.sblk = &dpu_dma_sblk,
105
+
.xin_id = 5,
106
+
.type = SSPP_TYPE_DMA,
107
+
}, {
108
+
.name = "sspp_10", .id = SSPP_DMA2,
109
+
.base = 0x28000, .len = 0x344,
110
+
.features = DMA_SDM845_MASK_SDMA,
111
+
.sblk = &dpu_dma_sblk,
112
+
.xin_id = 9,
113
+
.type = SSPP_TYPE_DMA,
114
+
}, {
115
+
.name = "sspp_11", .id = SSPP_DMA3,
116
+
.base = 0x2a000, .len = 0x344,
117
+
.features = DMA_SDM845_MASK_SDMA,
118
+
.sblk = &dpu_dma_sblk,
119
+
.xin_id = 13,
120
+
.type = SSPP_TYPE_DMA,
121
+
}, {
122
+
.name = "sspp_12", .id = SSPP_DMA4,
123
+
.base = 0x2c000, .len = 0x344,
124
+
.features = DMA_CURSOR_SDM845_MASK_SDMA,
125
+
.sblk = &dpu_dma_sblk,
126
+
.xin_id = 14,
127
+
.type = SSPP_TYPE_DMA,
128
+
}, {
129
+
.name = "sspp_13", .id = SSPP_DMA5,
130
+
.base = 0x2e000, .len = 0x344,
131
+
.features = DMA_CURSOR_SDM845_MASK_SDMA,
132
+
.sblk = &dpu_dma_sblk,
133
+
.xin_id = 15,
134
+
.type = SSPP_TYPE_DMA,
135
+
},
136
+
};
137
+
138
+
static const struct dpu_lm_cfg glymur_lm[] = {
139
+
{
140
+
.name = "lm_0", .id = LM_0,
141
+
.base = 0x44000, .len = 0x400,
142
+
.features = MIXER_MSM8998_MASK,
143
+
.sblk = &sm8750_lm_sblk,
144
+
.lm_pair = LM_1,
145
+
.pingpong = PINGPONG_0,
146
+
.dspp = DSPP_0,
147
+
}, {
148
+
.name = "lm_1", .id = LM_1,
149
+
.base = 0x45000, .len = 0x400,
150
+
.features = MIXER_MSM8998_MASK,
151
+
.sblk = &sm8750_lm_sblk,
152
+
.lm_pair = LM_0,
153
+
.pingpong = PINGPONG_1,
154
+
.dspp = DSPP_1,
155
+
}, {
156
+
.name = "lm_2", .id = LM_2,
157
+
.base = 0x46000, .len = 0x400,
158
+
.features = MIXER_MSM8998_MASK,
159
+
.sblk = &sm8750_lm_sblk,
160
+
.lm_pair = LM_3,
161
+
.pingpong = PINGPONG_2,
162
+
.dspp = DSPP_2,
163
+
}, {
164
+
.name = "lm_3", .id = LM_3,
165
+
.base = 0x47000, .len = 0x400,
166
+
.features = MIXER_MSM8998_MASK,
167
+
.sblk = &sm8750_lm_sblk,
168
+
.lm_pair = LM_2,
169
+
.pingpong = PINGPONG_3,
170
+
.dspp = DSPP_3,
171
+
}, {
172
+
.name = "lm_4", .id = LM_4,
173
+
.base = 0x48000, .len = 0x400,
174
+
.features = MIXER_MSM8998_MASK,
175
+
.sblk = &sm8750_lm_sblk,
176
+
.lm_pair = LM_5,
177
+
.pingpong = PINGPONG_4,
178
+
}, {
179
+
.name = "lm_5", .id = LM_5,
180
+
.base = 0x49000, .len = 0x400,
181
+
.features = MIXER_MSM8998_MASK,
182
+
.sblk = &sm8750_lm_sblk,
183
+
.lm_pair = LM_4,
184
+
.pingpong = PINGPONG_5,
185
+
}, {
186
+
.name = "lm_6", .id = LM_6,
187
+
.base = 0x4a000, .len = 0x400,
188
+
.features = MIXER_MSM8998_MASK,
189
+
.sblk = &sm8750_lm_sblk,
190
+
.lm_pair = LM_7,
191
+
.pingpong = PINGPONG_6,
192
+
}, {
193
+
.name = "lm_7", .id = LM_7,
194
+
.base = 0x4b000, .len = 0x400,
195
+
.features = MIXER_MSM8998_MASK,
196
+
.sblk = &sm8750_lm_sblk,
197
+
.lm_pair = LM_6,
198
+
.pingpong = PINGPONG_7,
199
+
},
200
+
};
201
+
202
+
static const struct dpu_dspp_cfg glymur_dspp[] = {
203
+
{
204
+
.name = "dspp_0", .id = DSPP_0,
205
+
.base = 0x54000, .len = 0x1800,
206
+
.sblk = &sm8750_dspp_sblk,
207
+
}, {
208
+
.name = "dspp_1", .id = DSPP_1,
209
+
.base = 0x56000, .len = 0x1800,
210
+
.sblk = &sm8750_dspp_sblk,
211
+
}, {
212
+
.name = "dspp_2", .id = DSPP_2,
213
+
.base = 0x58000, .len = 0x1800,
214
+
.sblk = &sm8750_dspp_sblk,
215
+
}, {
216
+
.name = "dspp_3", .id = DSPP_3,
217
+
.base = 0x5a000, .len = 0x1800,
218
+
.sblk = &sm8750_dspp_sblk,
219
+
}, {
220
+
.name = "dspp_4", .id = DSPP_4,
221
+
.base = 0x5c000, .len = 0x1800,
222
+
.sblk = &sm8750_dspp_sblk,
223
+
}, {
224
+
.name = "dspp_5", .id = DSPP_5,
225
+
.base = 0x5e000, .len = 0x1800,
226
+
.sblk = &sm8750_dspp_sblk,
227
+
}, {
228
+
.name = "dspp_6", .id = DSPP_6,
229
+
.base = 0x60000, .len = 0x1800,
230
+
.sblk = &sm8750_dspp_sblk,
231
+
}, {
232
+
.name = "dspp_7", .id = DSPP_7,
233
+
.base = 0x62000, .len = 0x1800,
234
+
.sblk = &sm8750_dspp_sblk,
235
+
},
236
+
};
237
+
238
+
static const struct dpu_pingpong_cfg glymur_pp[] = {
239
+
{
240
+
.name = "pingpong_0", .id = PINGPONG_0,
241
+
.base = 0x69000, .len = 0,
242
+
.sblk = &sc7280_pp_sblk,
243
+
.merge_3d = MERGE_3D_0,
244
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
245
+
}, {
246
+
.name = "pingpong_1", .id = PINGPONG_1,
247
+
.base = 0x6a000, .len = 0,
248
+
.sblk = &sc7280_pp_sblk,
249
+
.merge_3d = MERGE_3D_0,
250
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
251
+
}, {
252
+
.name = "pingpong_2", .id = PINGPONG_2,
253
+
.base = 0x6b000, .len = 0,
254
+
.sblk = &sc7280_pp_sblk,
255
+
.merge_3d = MERGE_3D_1,
256
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
257
+
}, {
258
+
.name = "pingpong_3", .id = PINGPONG_3,
259
+
.base = 0x6c000, .len = 0,
260
+
.sblk = &sc7280_pp_sblk,
261
+
.merge_3d = MERGE_3D_1,
262
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
263
+
}, {
264
+
.name = "pingpong_4", .id = PINGPONG_4,
265
+
.base = 0x6d000, .len = 0,
266
+
.sblk = &sc7280_pp_sblk,
267
+
.merge_3d = MERGE_3D_2,
268
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
269
+
}, {
270
+
.name = "pingpong_5", .id = PINGPONG_5,
271
+
.base = 0x6e000, .len = 0,
272
+
.sblk = &sc7280_pp_sblk,
273
+
.merge_3d = MERGE_3D_2,
274
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
275
+
}, {
276
+
.name = "pingpong_6", .id = PINGPONG_6,
277
+
.base = 0x6f000, .len = 0,
278
+
.sblk = &sc7280_pp_sblk,
279
+
.merge_3d = MERGE_3D_3,
280
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
281
+
}, {
282
+
.name = "pingpong_7", .id = PINGPONG_7,
283
+
.base = 0x70000, .len = 0,
284
+
.sblk = &sc7280_pp_sblk,
285
+
.merge_3d = MERGE_3D_3,
286
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
287
+
}, {
288
+
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
289
+
.base = 0x66000, .len = 0,
290
+
.sblk = &sc7280_pp_sblk,
291
+
.merge_3d = MERGE_3D_4,
292
+
}, {
293
+
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
294
+
.base = 0x66400, .len = 0,
295
+
.sblk = &sc7280_pp_sblk,
296
+
.merge_3d = MERGE_3D_4,
297
+
},
298
+
};
299
+
300
+
static const struct dpu_merge_3d_cfg glymur_merge_3d[] = {
301
+
{
302
+
.name = "merge_3d_0", .id = MERGE_3D_0,
303
+
.base = 0x4e000, .len = 0x1c,
304
+
}, {
305
+
.name = "merge_3d_1", .id = MERGE_3D_1,
306
+
.base = 0x4f000, .len = 0x1c,
307
+
}, {
308
+
.name = "merge_3d_2", .id = MERGE_3D_2,
309
+
.base = 0x50000, .len = 0x1c,
310
+
}, {
311
+
.name = "merge_3d_3", .id = MERGE_3D_3,
312
+
.base = 0x51000, .len = 0x1c,
313
+
},
314
+
};
315
+
316
+
/*
317
+
* NOTE: Each display compression engine (DCE) contains dual hard
318
+
* slice DSC encoders so both share same base address but with
319
+
* its own different sub block address.
320
+
*/
321
+
static const struct dpu_dsc_cfg glymur_dsc[] = {
322
+
{
323
+
.name = "dce_0_0", .id = DSC_0,
324
+
.base = 0x80000, .len = 0x8,
325
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
326
+
.sblk = &sm8750_dsc_sblk_0,
327
+
}, {
328
+
.name = "dce_0_1", .id = DSC_1,
329
+
.base = 0x80000, .len = 0x8,
330
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
331
+
.sblk = &sm8750_dsc_sblk_1,
332
+
}, {
333
+
.name = "dce_1_0", .id = DSC_2,
334
+
.base = 0x81000, .len = 0x8,
335
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
336
+
.sblk = &sm8750_dsc_sblk_0,
337
+
}, {
338
+
.name = "dce_1_1", .id = DSC_3,
339
+
.base = 0x81000, .len = 0x8,
340
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
341
+
.sblk = &sm8750_dsc_sblk_1,
342
+
}, {
343
+
.name = "dce_2_0", .id = DSC_4,
344
+
.base = 0x82000, .len = 0x8,
345
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
346
+
.sblk = &sm8750_dsc_sblk_0,
347
+
}, {
348
+
.name = "dce_2_1", .id = DSC_5,
349
+
.base = 0x82000, .len = 0x8,
350
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
351
+
.sblk = &sm8750_dsc_sblk_1,
352
+
}, {
353
+
.name = "dce_3_0", .id = DSC_6,
354
+
.base = 0x83000, .len = 0x8,
355
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
356
+
.sblk = &sm8750_dsc_sblk_0,
357
+
}, {
358
+
.name = "dce_3_1", .id = DSC_7,
359
+
.base = 0x83000, .len = 0x8,
360
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
361
+
.sblk = &sm8750_dsc_sblk_1,
362
+
},
363
+
364
+
};
365
+
366
+
static const struct dpu_wb_cfg glymur_wb[] = {
367
+
{
368
+
.name = "wb_2", .id = WB_2,
369
+
.base = 0x65000, .len = 0x2c8,
370
+
.features = WB_SDM845_MASK,
371
+
.format_list = wb2_formats_rgb_yuv,
372
+
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
373
+
.xin_id = 6,
374
+
.vbif_idx = VBIF_RT,
375
+
.maxlinewidth = 4096,
376
+
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
377
+
},
378
+
};
379
+
380
+
static const struct dpu_cwb_cfg glymur_cwb[] = {
381
+
{
382
+
.name = "cwb_0", .id = CWB_0,
383
+
.base = 0x66200, .len = 0x20,
384
+
},
385
+
{
386
+
.name = "cwb_1", .id = CWB_1,
387
+
.base = 0x66600, .len = 0x20,
388
+
},
389
+
{
390
+
.name = "cwb_2", .id = CWB_2,
391
+
.base = 0x7e200, .len = 0x20,
392
+
},
393
+
{
394
+
.name = "cwb_3", .id = CWB_3,
395
+
.base = 0x7e600, .len = 0x20,
396
+
},
397
+
};
398
+
399
+
static const struct dpu_intf_cfg glymur_intf[] = {
400
+
{
401
+
.name = "intf_0", .id = INTF_0,
402
+
.base = 0x34000, .len = 0x400,
403
+
.type = INTF_DP,
404
+
.controller_id = MSM_DP_CONTROLLER_0,
405
+
.prog_fetch_lines_worst_case = 24,
406
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
407
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
408
+
}, {
409
+
.name = "intf_1", .id = INTF_1,
410
+
.base = 0x35000, .len = 0x400,
411
+
.type = INTF_DSI,
412
+
.controller_id = MSM_DSI_CONTROLLER_0,
413
+
.prog_fetch_lines_worst_case = 24,
414
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
415
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
416
+
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
417
+
}, {
418
+
.name = "intf_2", .id = INTF_2,
419
+
.base = 0x36000, .len = 0x400,
420
+
.type = INTF_DSI,
421
+
.controller_id = MSM_DSI_CONTROLLER_1,
422
+
.prog_fetch_lines_worst_case = 24,
423
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
424
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
425
+
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
426
+
}, {
427
+
.name = "intf_3", .id = INTF_3,
428
+
.base = 0x37000, .len = 0x400,
429
+
.type = INTF_NONE,
430
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
431
+
.prog_fetch_lines_worst_case = 24,
432
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
433
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
434
+
}, {
435
+
.name = "intf_4", .id = INTF_4,
436
+
.base = 0x38000, .len = 0x400,
437
+
.type = INTF_DP,
438
+
.controller_id = MSM_DP_CONTROLLER_1,
439
+
.prog_fetch_lines_worst_case = 24,
440
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
441
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
442
+
}, {
443
+
.name = "intf_5", .id = INTF_5,
444
+
.base = 0x39000, .len = 0x400,
445
+
.type = INTF_DP,
446
+
.controller_id = MSM_DP_CONTROLLER_3,
447
+
.prog_fetch_lines_worst_case = 24,
448
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
449
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
450
+
}, {
451
+
.name = "intf_6", .id = INTF_6,
452
+
.base = 0x3A000, .len = 0x400,
453
+
.type = INTF_DP,
454
+
.controller_id = MSM_DP_CONTROLLER_2,
455
+
.prog_fetch_lines_worst_case = 24,
456
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
457
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
458
+
}, {
459
+
.name = "intf_7", .id = INTF_7,
460
+
.base = 0x3b000, .len = 0x400,
461
+
.type = INTF_NONE,
462
+
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
463
+
.prog_fetch_lines_worst_case = 24,
464
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
465
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
466
+
}, {
467
+
.name = "intf_8", .id = INTF_8,
468
+
.base = 0x3c000, .len = 0x400,
469
+
.type = INTF_NONE,
470
+
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
471
+
.prog_fetch_lines_worst_case = 24,
472
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
473
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
474
+
},
475
+
};
476
+
477
+
static const struct dpu_perf_cfg glymur_perf_data = {
478
+
.max_bw_low = 18900000,
479
+
.max_bw_high = 28500000,
480
+
.min_core_ib = 2500000,
481
+
.min_llcc_ib = 0,
482
+
.min_dram_ib = 800000,
483
+
.min_prefill_lines = 35,
484
+
.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
485
+
.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
486
+
.qos_lut_tbl = {
487
+
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
488
+
.entries = sc7180_qos_linear
489
+
},
490
+
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
491
+
.entries = sc7180_qos_macrotile
492
+
},
493
+
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
494
+
.entries = sc7180_qos_nrt
495
+
},
496
+
/* TODO: macrotile-qseed is different from macrotile */
497
+
},
498
+
.cdp_cfg = {
499
+
{.rd_enable = 1, .wr_enable = 1},
500
+
{.rd_enable = 1, .wr_enable = 0}
501
+
},
502
+
.clk_inefficiency_factor = 105,
503
+
.bw_inefficiency_factor = 120,
504
+
};
505
+
506
+
static const struct dpu_mdss_version glymur_mdss_ver = {
507
+
.core_major_ver = 12,
508
+
.core_minor_ver = 2,
509
+
};
510
+
511
+
const struct dpu_mdss_cfg dpu_glymur_cfg = {
512
+
.mdss_ver = &glymur_mdss_ver,
513
+
.caps = &glymur_dpu_caps,
514
+
.mdp = &glymur_mdp,
515
+
.cdm = &dpu_cdm_5_x,
516
+
.ctl_count = ARRAY_SIZE(glymur_ctl),
517
+
.ctl = glymur_ctl,
518
+
.sspp_count = ARRAY_SIZE(glymur_sspp),
519
+
.sspp = glymur_sspp,
520
+
.mixer_count = ARRAY_SIZE(glymur_lm),
521
+
.mixer = glymur_lm,
522
+
.dspp_count = ARRAY_SIZE(glymur_dspp),
523
+
.dspp = glymur_dspp,
524
+
.pingpong_count = ARRAY_SIZE(glymur_pp),
525
+
.pingpong = glymur_pp,
526
+
.dsc_count = ARRAY_SIZE(glymur_dsc),
527
+
.dsc = glymur_dsc,
528
+
.merge_3d_count = ARRAY_SIZE(glymur_merge_3d),
529
+
.merge_3d = glymur_merge_3d,
530
+
.wb_count = ARRAY_SIZE(glymur_wb),
531
+
.wb = glymur_wb,
532
+
.cwb_count = ARRAY_SIZE(glymur_cwb),
533
+
.cwb = sm8650_cwb,
534
+
.intf_count = ARRAY_SIZE(glymur_intf),
535
+
.intf = glymur_intf,
536
+
.vbif_count = ARRAY_SIZE(sm8650_vbif),
537
+
.vbif = sm8650_vbif,
538
+
.perf = &glymur_perf_data,
539
+
};
540
+
541
+
#endif
+73
-42
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+73
-42
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
200
200
struct dpu_crtc_state *crtc_state)
201
201
{
202
202
struct dpu_crtc_mixer *m;
203
-
u32 crcs[CRTC_DUAL_MIXERS];
203
+
u32 crcs[CRTC_QUAD_MIXERS];
204
204
205
205
int rc = 0;
206
206
int i;
···
400
400
static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
401
401
struct drm_plane *plane,
402
402
struct dpu_crtc_mixer *mixer,
403
-
u32 num_mixers,
403
+
u32 lms_in_pair,
404
404
enum dpu_stage stage,
405
405
const struct msm_format *format,
406
406
uint64_t modifier,
···
419
419
420
420
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
421
421
state, to_dpu_plane_state(state), stage_idx,
422
-
format->pixel_format,
422
+
format->pixel_format, pipe,
423
423
modifier);
424
424
425
425
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
···
434
434
stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;
435
435
436
436
/* blend config update */
437
-
for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
437
+
for (lm_idx = 0; lm_idx < lms_in_pair; lm_idx++)
438
438
mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
439
439
}
440
440
···
449
449
struct dpu_plane_state *pstate = NULL;
450
450
const struct msm_format *format;
451
451
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
452
-
u32 lm_idx;
452
+
u32 lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_pair;
453
453
bool bg_alpha_enable = false;
454
454
DECLARE_BITMAP(active_fetch, SSPP_MAX);
455
455
DECLARE_BITMAP(active_pipes, SSPP_MAX);
···
472
472
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
473
473
bg_alpha_enable = true;
474
474
475
-
set_bit(pstate->pipe.sspp->idx, active_fetch);
476
-
set_bit(pstate->pipe.sspp->idx, active_pipes);
477
-
_dpu_crtc_blend_setup_pipe(crtc, plane,
478
-
mixer, cstate->num_mixers,
479
-
pstate->stage,
480
-
format, fb ? fb->modifier : 0,
481
-
&pstate->pipe, 0, stage_cfg);
482
-
483
-
if (pstate->r_pipe.sspp) {
484
-
set_bit(pstate->r_pipe.sspp->idx, active_fetch);
485
-
set_bit(pstate->r_pipe.sspp->idx, active_pipes);
486
-
_dpu_crtc_blend_setup_pipe(crtc, plane,
487
-
mixer, cstate->num_mixers,
488
-
pstate->stage,
489
-
format, fb ? fb->modifier : 0,
490
-
&pstate->r_pipe, 1, stage_cfg);
475
+
/* loop pipe per mixer pair with config in stage structure */
476
+
for (stage = 0; stage < STAGES_PER_PLANE; stage++) {
477
+
head_pipe_in_stage = stage * PIPES_PER_STAGE;
478
+
for (i = 0; i < PIPES_PER_STAGE; i++) {
479
+
pipe_idx = i + head_pipe_in_stage;
480
+
if (!pstate->pipe[pipe_idx].sspp)
481
+
continue;
482
+
lms_in_pair = min(cstate->num_mixers - (stage * PIPES_PER_STAGE),
483
+
PIPES_PER_STAGE);
484
+
set_bit(pstate->pipe[pipe_idx].sspp->idx, active_fetch);
485
+
set_bit(pstate->pipe[pipe_idx].sspp->idx, active_pipes);
486
+
_dpu_crtc_blend_setup_pipe(crtc, plane,
487
+
&mixer[head_pipe_in_stage],
488
+
lms_in_pair,
489
+
pstate->stage,
490
+
format, fb ? fb->modifier : 0,
491
+
&pstate->pipe[pipe_idx], i,
492
+
&stage_cfg[stage]);
493
+
}
491
494
}
492
495
493
496
/* blend config update */
···
526
523
struct dpu_crtc_mixer *mixer = cstate->mixers;
527
524
struct dpu_hw_ctl *ctl;
528
525
struct dpu_hw_mixer *lm;
529
-
struct dpu_hw_stage_cfg stage_cfg;
526
+
struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE];
530
527
DECLARE_BITMAP(active_lms, LM_MAX);
531
528
int i;
532
529
···
547
544
}
548
545
549
546
/* initialize stage cfg */
550
-
memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
547
+
memset(&stage_cfg, 0, sizeof(stage_cfg));
551
548
memset(active_lms, 0, sizeof(active_lms));
552
549
553
-
_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
550
+
_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg);
554
551
555
552
for (i = 0; i < cstate->num_mixers; i++) {
556
553
ctl = mixer[i].lm_ctl;
···
571
568
mixer[i].mixer_op_mode,
572
569
ctl->idx - CTL_0);
573
570
571
+
/*
572
+
* call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg.
573
+
* stage data is shared between PIPES_PER_STAGE pipes.
574
+
*/
574
575
if (ctl->ops.setup_blendstage)
575
576
ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
576
-
&stage_cfg);
577
+
&stage_cfg[i / PIPES_PER_STAGE]);
577
578
578
579
if (lm->ops.setup_blendstage)
579
580
lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx,
580
-
&stage_cfg);
581
+
&stage_cfg[i / PIPES_PER_STAGE]);
581
582
}
582
583
}
583
584
···
1317
1310
return ret;
1318
1311
}
1319
1312
1320
-
#define MAX_CHANNELS_PER_CRTC 2
1313
+
#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
1321
1314
#define MAX_HDISPLAY_SPLIT 1080
1322
1315
1323
1316
static struct msm_display_topology dpu_crtc_get_topology(
···
1328
1321
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1329
1322
struct msm_display_topology topology = {0};
1330
1323
struct drm_encoder *drm_enc;
1324
+
u32 num_rt_intf;
1331
1325
1332
1326
drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
1333
1327
dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
···
1342
1334
* Dual display
1343
1335
* 2 LM, 2 INTF ( Split display using 2 interfaces)
1344
1336
*
1337
+
* If DSC is enabled, try to use 4:4:2 topology if there is enough
1338
+
* resource. Otherwise, use 2:2:2 topology.
1339
+
*
1345
1340
* Single display
1346
1341
* 1 LM, 1 INTF
1347
1342
* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
1348
1343
*
1349
-
* If DSC is enabled, use 2 LMs for 2:2:1 topology
1344
+
* If DSC is enabled, use 2:2:1 topology
1350
1345
*
1351
1346
* Add dspps to the reservation requirements if ctm is requested
1352
1347
*
···
1361
1350
* (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
1362
1351
*/
1363
1352
1364
-
if (topology.num_intf == 2 && !topology.cwb_enabled)
1353
+
num_rt_intf = topology.num_intf;
1354
+
if (topology.cwb_enabled)
1355
+
num_rt_intf--;
1356
+
1357
+
if (topology.num_dsc) {
1358
+
if (dpu_kms->catalog->dsc_count >= num_rt_intf * 2)
1359
+
topology.num_dsc = num_rt_intf * 2;
1360
+
else
1361
+
topology.num_dsc = num_rt_intf;
1362
+
topology.num_lm = topology.num_dsc;
1363
+
} else if (num_rt_intf == 2) {
1365
1364
topology.num_lm = 2;
1366
-
else if (topology.num_dsc == 2)
1367
-
topology.num_lm = 2;
1368
-
else if (dpu_kms->catalog->caps->has_3d_merge)
1365
+
} else if (dpu_kms->catalog->caps->has_3d_merge) {
1369
1366
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
1370
-
else
1367
+
} else {
1371
1368
topology.num_lm = 1;
1369
+
}
1372
1370
1373
1371
if (crtc_state->ctm)
1374
1372
topology.num_dspp = topology.num_lm;
···
1620
1600
return 0;
1621
1601
}
1622
1602
1603
+
/**
1604
+
* dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline
1605
+
* @state: Pointer to drm crtc state object
1606
+
*/
1607
+
unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state)
1608
+
{
1609
+
struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
1610
+
1611
+
return cstate->num_mixers;
1612
+
}
1613
+
1623
1614
#ifdef CONFIG_DEBUG_FS
1624
1615
static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
1625
1616
{
···
1713
1682
seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
1714
1683
state->crtc_x, state->crtc_y, state->crtc_w,
1715
1684
state->crtc_h);
1716
-
seq_printf(s, "\tsspp[0]:%s\n",
1717
-
pstate->pipe.sspp->cap->name);
1718
-
seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
1719
-
pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
1720
-
if (pstate->r_pipe.sspp) {
1721
-
seq_printf(s, "\tsspp[1]:%s\n",
1722
-
pstate->r_pipe.sspp->cap->name);
1723
-
seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
1724
-
pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
1685
+
1686
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
1687
+
if (!pstate->pipe[i].sspp)
1688
+
continue;
1689
+
seq_printf(s, "\tsspp[%d]:%s\n",
1690
+
i, pstate->pipe[i].sspp->cap->name);
1691
+
seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n",
1692
+
i, pstate->pipe[i].multirect_mode,
1693
+
pstate->pipe[i].multirect_index);
1725
1694
}
1726
1695
1727
1696
seq_puts(s, "\n");
+5
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+5
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
···
210
210
211
211
bool bw_control;
212
212
bool bw_split_vote;
213
-
struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
213
+
struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];
214
214
215
215
uint64_t input_fence_timeout_ns;
216
216
···
218
218
219
219
/* HW Resources reserved for the crtc */
220
220
u32 num_mixers;
221
-
struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
221
+
struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];
222
222
223
223
u32 num_ctls;
224
-
struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
224
+
struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];
225
225
226
226
enum dpu_crtc_crc_source crc_source;
227
227
int crc_frame_skip_count;
···
266
266
}
267
267
268
268
void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event);
269
+
270
+
unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state);
269
271
270
272
#endif /* _DPU_CRTC_H_ */
+20
-27
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+20
-27
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
55
55
#define MAX_PHYS_ENCODERS_PER_VIRTUAL \
56
56
(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
57
57
58
-
#define MAX_CHANNELS_PER_ENC 2
58
+
#define MAX_CHANNELS_PER_ENC 4
59
+
#define MAX_CWB_PER_ENC 2
59
60
60
61
#define IDLE_SHORT_TIMEOUT 1
61
62
···
183
182
struct dpu_encoder_phys *cur_master;
184
183
struct dpu_encoder_phys *cur_slave;
185
184
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
186
-
struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
185
+
struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC];
187
186
struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
188
187
189
188
unsigned int dsc_mask;
···
661
660
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
662
661
struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
663
662
struct msm_display_info *disp_info = &dpu_enc->disp_info;
664
-
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
665
663
struct drm_connector *connector;
666
664
struct drm_connector_state *conn_state;
667
665
struct drm_framebuffer *fb;
···
674
674
675
675
dsc = dpu_encoder_get_dsc_config(drm_enc);
676
676
677
-
/* We only support 2 DSC mode (with 2 LM and 1 INTF) */
678
-
if (dsc) {
679
-
/*
680
-
* Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
681
-
* when Display Stream Compression (DSC) is enabled,
682
-
* and when enough DSC blocks are available.
683
-
* This is power-optimal and can drive up to (including) 4k
684
-
* screens.
685
-
*/
686
-
WARN(topology->num_intf > 2,
687
-
"DSC topology cannot support more than 2 interfaces\n");
688
-
if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
689
-
topology->num_dsc = 2;
690
-
else
691
-
topology->num_dsc = 1;
692
-
}
677
+
/*
678
+
* Set DSC number as 1 to mark the enabled status, will be adjusted
679
+
* in dpu_crtc_get_topology()
680
+
*/
681
+
if (dsc)
682
+
topology->num_dsc = 1;
693
683
694
684
connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
695
685
if (!connector)
···
1150
1160
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1151
1161
struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1152
1162
struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC];
1153
-
int num_ctl, num_pp, num_dsc;
1163
+
int num_ctl, num_pp, num_dsc, num_pp_per_intf;
1154
1164
int num_cwb = 0;
1155
1165
bool is_cwb_encoder;
1156
1166
unsigned int dsc_mask = 0;
···
1229
1239
dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
1230
1240
}
1231
1241
1242
+
/*
1243
+
* There may be 4 PP and 2 INTF for quad pipe case, so INTF is not
1244
+
* mapped to PP 1:1. Let's calculate the stride with pipe/INTF
1245
+
*/
1246
+
num_pp_per_intf = num_pp / dpu_enc->num_phys_encs;
1247
+
1232
1248
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1233
1249
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1234
1250
1235
-
phys->hw_pp = dpu_enc->hw_pp[i];
1251
+
phys->hw_pp = dpu_enc->hw_pp[num_pp_per_intf * i];
1236
1252
if (!phys->hw_pp) {
1237
1253
DPU_ERROR_ENC(dpu_enc,
1238
1254
"no pp block assigned at idx: %d\n", i);
···
2167
2171
2168
2172
static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
2169
2173
{
2170
-
struct dpu_hw_mixer_cfg mixer;
2171
2174
int i, num_lm;
2172
2175
struct dpu_global_state *global_state;
2173
-
struct dpu_hw_blk *hw_lm[2];
2174
-
struct dpu_hw_mixer *hw_mixer[2];
2176
+
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
2177
+
struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];
2175
2178
struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2176
-
2177
-
memset(&mixer, 0, sizeof(mixer));
2178
2179
2179
2180
/* reset all mixers for this encoder */
2180
2181
if (ctl->ops.clear_all_blendstages)
···
2376
2383
*/
2377
2384
cwb_cfg.input = INPUT_MODE_LM_OUT;
2378
2385
2379
-
for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2386
+
for (int i = 0; i < MAX_CWB_PER_ENC; i++) {
2380
2387
hw_cwb = dpu_enc->hw_cwb[i];
2381
2388
if (!hw_cwb)
2382
2389
continue;
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
···
302
302
303
303
/* Use merge_3d unless DSC MERGE topology is used */
304
304
if (phys_enc->split_role == ENC_ROLE_SOLO &&
305
-
dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
305
+
(dpu_cstate->num_mixers != 1) &&
306
306
!dpu_encoder_use_dsc_merge(phys_enc->parent))
307
307
return BLEND_3D_H_ROW_INT;
308
308
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
24
24
#define DPU_MAX_IMG_WIDTH 0x3fff
25
25
#define DPU_MAX_IMG_HEIGHT 0x3fff
26
26
27
-
#define CRTC_DUAL_MIXERS 2
27
+
#define CRTC_QUAD_MIXERS 4
28
28
29
29
#define MAX_XIN_COUNT 16
30
30
···
749
749
const struct dpu_format_extended *vig_formats;
750
750
};
751
751
752
+
extern const struct dpu_mdss_cfg dpu_glymur_cfg;
752
753
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
753
754
extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
754
755
extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
···
71
71
const struct dpu_dsc_cfg *cfg,
72
72
void __iomem *addr);
73
73
74
-
/**
75
-
* dpu_hw_dsc_destroy - destroys dsc driver context
76
-
* @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
77
-
*/
78
-
void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
79
-
80
74
static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
81
75
{
82
76
return container_of(hw, struct dpu_hw_dsc, base);
+8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
···
34
34
#define DPU_MAX_PLANES 4
35
35
#endif
36
36
37
+
#define STAGES_PER_PLANE 2
37
38
#define PIPES_PER_STAGE 2
39
+
#define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE)
38
40
#ifndef DPU_MAX_DE_CURVES
39
41
#define DPU_MAX_DE_CURVES 3
40
42
#endif
···
151
149
DSPP_1,
152
150
DSPP_2,
153
151
DSPP_3,
152
+
DSPP_4,
153
+
DSPP_5,
154
+
DSPP_6,
155
+
DSPP_7,
154
156
DSPP_MAX
155
157
};
156
158
···
165
159
CTL_3,
166
160
CTL_4,
167
161
CTL_5,
162
+
CTL_6,
163
+
CTL_7,
168
164
CTL_MAX
169
165
};
170
166
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
1505
1505
};
1506
1506
1507
1507
static const struct of_device_id dpu_dt_match[] = {
1508
+
{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
1508
1509
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
1509
1510
{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
1510
1511
{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
+263
-163
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+263
-163
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
···
622
622
struct msm_drm_private *priv = plane->dev->dev_private;
623
623
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
624
624
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
625
+
int i;
625
626
626
627
DPU_DEBUG_PLANE(pdpu, "\n");
627
628
···
636
635
return;
637
636
638
637
/* update sspp */
639
-
_dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect,
640
-
fill_color, fmt);
641
-
642
-
if (pstate->r_pipe.sspp)
643
-
_dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect,
638
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
639
+
if (!pstate->pipe[i].sspp)
640
+
continue;
641
+
_dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i],
642
+
&pstate->pipe_cfg[i].dst_rect,
644
643
fill_color, fmt);
644
+
}
645
645
}
646
646
647
647
static int dpu_plane_prepare_fb(struct drm_plane *plane,
···
824
822
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
825
823
u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate;
826
824
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
827
-
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
828
-
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
825
+
struct dpu_sw_pipe_cfg *pipe_cfg;
826
+
struct dpu_sw_pipe_cfg *r_pipe_cfg;
827
+
struct dpu_sw_pipe_cfg init_pipe_cfg;
829
828
struct drm_rect fb_rect = { 0 };
829
+
const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
830
830
uint32_t max_linewidth;
831
+
u32 num_lm;
832
+
int stage_id, num_stages;
831
833
832
834
min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO);
833
835
max_scale = MAX_DOWNSCALE_RATIO << 16;
···
854
848
return -EINVAL;
855
849
}
856
850
857
-
/* state->src is 16.16, src_rect is not */
858
-
drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
851
+
num_lm = dpu_crtc_get_num_lm(crtc_state);
859
852
860
-
pipe_cfg->dst_rect = new_plane_state->dst;
853
+
/* state->src is 16.16, src_rect is not */
854
+
drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src);
861
855
862
856
fb_rect.x2 = new_plane_state->fb->width;
863
857
fb_rect.y2 = new_plane_state->fb->height;
···
882
876
883
877
max_linewidth = pdpu->catalog->caps->max_linewidth;
884
878
885
-
drm_rect_rotate(&pipe_cfg->src_rect,
879
+
drm_rect_rotate(&init_pipe_cfg.src_rect,
886
880
new_plane_state->fb->width, new_plane_state->fb->height,
887
881
new_plane_state->rotation);
888
882
889
-
if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
890
-
_dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
891
-
if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
892
-
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
893
-
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
894
-
return -E2BIG;
883
+
/*
884
+
* We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair
885
+
* configs for left and right half screen in case of 4:4:2 topology.
886
+
* But we may have 2 rect to split wide plane that exceeds limit with 1
887
+
* config for 2:2:1. So need to handle both wide plane splitting, and
888
+
* two halves of screen splitting for quad-pipe case. Check dest
889
+
* rectangle left/right clipping first, then check wide rectangle
890
+
* splitting in every half next.
891
+
*/
892
+
num_stages = (num_lm + 1) / 2;
893
+
/* iterate mixer configs for this plane, to separate left/right with the id */
894
+
for (stage_id = 0; stage_id < num_stages; stage_id++) {
895
+
struct drm_rect mixer_rect = {
896
+
.x1 = stage_id * mode->hdisplay / num_stages,
897
+
.y1 = 0,
898
+
.x2 = (stage_id + 1) * mode->hdisplay / num_stages,
899
+
.y2 = mode->vdisplay
900
+
};
901
+
int cfg_idx = stage_id * PIPES_PER_STAGE;
902
+
903
+
pipe_cfg = &pstate->pipe_cfg[cfg_idx];
904
+
r_pipe_cfg = &pstate->pipe_cfg[cfg_idx + 1];
905
+
906
+
drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
907
+
pipe_cfg->dst_rect = new_plane_state->dst;
908
+
909
+
DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT
910
+
" vs clip window " DRM_RECT_FMT "\n",
911
+
DRM_RECT_ARG(&pipe_cfg->src_rect),
912
+
DRM_RECT_ARG(&mixer_rect));
913
+
914
+
/*
915
+
* If this plane does not fall into mixer rect, check next
916
+
* mixer rect.
917
+
*/
918
+
if (!drm_rect_clip_scaled(&pipe_cfg->src_rect,
919
+
&pipe_cfg->dst_rect,
920
+
&mixer_rect)) {
921
+
memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg));
922
+
923
+
continue;
895
924
}
896
925
897
-
*r_pipe_cfg = *pipe_cfg;
898
-
pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
899
-
pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
900
-
r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
901
-
r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
902
-
} else {
903
-
memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg));
904
-
}
926
+
pipe_cfg->dst_rect.x1 -= mixer_rect.x1;
927
+
pipe_cfg->dst_rect.x2 -= mixer_rect.x1;
905
928
906
-
drm_rect_rotate_inv(&pipe_cfg->src_rect,
907
-
new_plane_state->fb->width, new_plane_state->fb->height,
908
-
new_plane_state->rotation);
909
-
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
910
-
drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
911
-
new_plane_state->fb->width, new_plane_state->fb->height,
929
+
DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT "\n",
930
+
DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect));
931
+
932
+
/* Split wide rect into 2 rect */
933
+
if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
934
+
_dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) {
935
+
936
+
if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
937
+
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
938
+
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
939
+
return -E2BIG;
940
+
}
941
+
942
+
memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg));
943
+
pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
944
+
pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
945
+
r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
946
+
r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
947
+
DPU_DEBUG_PLANE(pdpu, "Split wide plane into:"
948
+
DRM_RECT_FMT " and " DRM_RECT_FMT "\n",
949
+
DRM_RECT_ARG(&pipe_cfg->src_rect),
950
+
DRM_RECT_ARG(&r_pipe_cfg->src_rect));
951
+
} else {
952
+
memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg));
953
+
}
954
+
955
+
drm_rect_rotate_inv(&pipe_cfg->src_rect,
956
+
new_plane_state->fb->width,
957
+
new_plane_state->fb->height,
912
958
new_plane_state->rotation);
959
+
960
+
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
961
+
drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
962
+
new_plane_state->fb->width,
963
+
new_plane_state->fb->height,
964
+
new_plane_state->rotation);
965
+
}
913
966
914
967
pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
915
968
···
1019
954
dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth);
1020
955
}
1021
956
957
+
static bool dpu_plane_get_single_pipe_in_stage(struct dpu_plane_state *pstate,
958
+
struct dpu_sw_pipe **single_pipe,
959
+
struct dpu_sw_pipe_cfg **single_pipe_cfg,
960
+
int stage_index)
961
+
{
962
+
int pipe_idx;
963
+
964
+
pipe_idx = stage_index * PIPES_PER_STAGE;
965
+
if (drm_rect_width(&pstate->pipe_cfg[pipe_idx].src_rect) != 0 &&
966
+
drm_rect_width(&pstate->pipe_cfg[pipe_idx + 1].src_rect) == 0) {
967
+
*single_pipe = &pstate->pipe[pipe_idx];
968
+
*single_pipe_cfg = &pstate->pipe_cfg[pipe_idx];
969
+
return true;
970
+
}
971
+
972
+
return false;
973
+
}
1022
974
1023
975
static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
1024
976
struct drm_atomic_state *state,
···
1045
963
drm_atomic_get_new_plane_state(state, plane);
1046
964
struct dpu_plane *pdpu = to_dpu_plane(plane);
1047
965
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
1048
-
struct dpu_sw_pipe *pipe = &pstate->pipe;
1049
-
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1050
-
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1051
-
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1052
-
int ret = 0;
966
+
struct dpu_sw_pipe *pipe;
967
+
struct dpu_sw_pipe_cfg *pipe_cfg;
968
+
int ret = 0, i;
1053
969
1054
-
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
1055
-
&crtc_state->adjusted_mode,
1056
-
new_plane_state);
1057
-
if (ret)
1058
-
return ret;
1059
-
1060
-
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
1061
-
ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
970
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
971
+
pipe = &pstate->pipe[i];
972
+
pipe_cfg = &pstate->pipe_cfg[i];
973
+
if (!drm_rect_width(&pipe_cfg->src_rect))
974
+
continue;
975
+
DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i);
976
+
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
1062
977
&crtc_state->adjusted_mode,
1063
978
new_plane_state);
1064
979
if (ret)
···
1098
1019
static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
1099
1020
struct dpu_plane_state *prev_adjacent_pstate,
1100
1021
const struct msm_format *fmt,
1101
-
uint32_t max_linewidth)
1022
+
uint32_t max_linewidth, int stage_index)
1102
1023
{
1103
-
struct dpu_sw_pipe *pipe = &pstate->pipe;
1104
-
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1105
-
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1106
-
struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe;
1107
-
struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg;
1024
+
struct dpu_sw_pipe *pipe, *prev_pipe;
1025
+
struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg;
1108
1026
const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb);
1109
1027
u16 max_tile_height = 1;
1110
1028
1111
-
if (prev_adjacent_pstate->r_pipe.sspp != NULL ||
1029
+
if (!dpu_plane_get_single_pipe_in_stage(pstate, &pipe,
1030
+
&pipe_cfg, stage_index))
1031
+
return false;
1032
+
1033
+
if (!dpu_plane_get_single_pipe_in_stage(prev_adjacent_pstate,
1034
+
&prev_pipe, &prev_pipe_cfg,
1035
+
stage_index) ||
1112
1036
prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE)
1113
1037
return false;
1114
1038
···
1125
1043
1126
1044
if (MSM_FORMAT_IS_UBWC(prev_fmt))
1127
1045
max_tile_height = max(max_tile_height, prev_fmt->tile_height);
1128
-
1129
-
r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1130
-
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1131
-
1132
-
r_pipe->sspp = NULL;
1133
1046
1134
1047
if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) &&
1135
1048
dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth) &&
···
1166
1089
struct dpu_plane *pdpu = to_dpu_plane(plane);
1167
1090
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
1168
1091
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1169
-
struct dpu_sw_pipe *pipe = &pstate->pipe;
1170
-
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1171
-
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1172
-
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1092
+
struct dpu_sw_pipe *pipe = &pstate->pipe[0];
1093
+
struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
1094
+
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
1095
+
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
1173
1096
const struct drm_crtc_state *crtc_state = NULL;
1174
1097
uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;
1175
1098
···
1213
1136
drm_atomic_get_old_plane_state(state, plane);
1214
1137
struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);
1215
1138
struct drm_crtc_state *crtc_state = NULL;
1216
-
int ret;
1139
+
int ret, i;
1217
1140
1218
1141
if (IS_ERR(plane_state))
1219
1142
return PTR_ERR(plane_state);
···
1231
1154
* resources are freed by dpu_crtc_assign_plane_resources(),
1232
1155
* but clean them here.
1233
1156
*/
1234
-
pstate->pipe.sspp = NULL;
1235
-
pstate->r_pipe.sspp = NULL;
1157
+
for (i = 0; i < PIPES_PER_PLANE; i++)
1158
+
pstate->pipe[i].sspp = NULL;
1236
1159
1237
1160
return 0;
1238
1161
}
···
1254
1177
return 0;
1255
1178
}
1256
1179
1180
+
static int dpu_plane_assign_resource_in_stage(struct dpu_sw_pipe *pipe,
1181
+
struct dpu_sw_pipe_cfg *pipe_cfg,
1182
+
struct drm_plane_state *plane_state,
1183
+
struct dpu_global_state *global_state,
1184
+
struct drm_crtc *crtc,
1185
+
struct dpu_rm_sspp_requirements *reqs)
1186
+
{
1187
+
struct drm_plane *plane = plane_state->plane;
1188
+
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1189
+
struct dpu_sw_pipe *r_pipe = pipe + 1;
1190
+
struct dpu_sw_pipe_cfg *r_pipe_cfg = pipe_cfg + 1;
1191
+
1192
+
if (drm_rect_width(&pipe_cfg->src_rect) == 0)
1193
+
return 0;
1194
+
1195
+
pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);
1196
+
if (!pipe->sspp)
1197
+
return -ENODEV;
1198
+
pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1199
+
pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1200
+
1201
+
if (drm_rect_width(&r_pipe_cfg->src_rect) == 0)
1202
+
return 0;
1203
+
1204
+
if (dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
1205
+
pipe->sspp,
1206
+
msm_framebuffer_format(plane_state->fb),
1207
+
dpu_kms->catalog->caps->max_linewidth))
1208
+
return 0;
1209
+
1210
+
r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);
1211
+
if (!r_pipe->sspp)
1212
+
return -ENODEV;
1213
+
r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1214
+
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1215
+
1216
+
return 0;
1217
+
}
1218
+
1257
1219
static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
1258
1220
struct dpu_global_state *global_state,
1259
1221
struct drm_atomic_state *state,
1260
1222
struct drm_plane_state *plane_state,
1261
-
struct drm_plane_state *prev_adjacent_plane_state)
1223
+
struct drm_plane_state **prev_adjacent_plane_state)
1262
1224
{
1263
1225
const struct drm_crtc_state *crtc_state = NULL;
1264
1226
struct drm_plane *plane = plane_state->plane;
1265
1227
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1266
1228
struct dpu_rm_sspp_requirements reqs;
1267
-
struct dpu_plane_state *pstate, *prev_adjacent_pstate;
1229
+
struct dpu_plane_state *pstate, *prev_adjacent_pstate[STAGES_PER_PLANE];
1268
1230
struct dpu_sw_pipe *pipe;
1269
-
struct dpu_sw_pipe *r_pipe;
1270
1231
struct dpu_sw_pipe_cfg *pipe_cfg;
1271
-
struct dpu_sw_pipe_cfg *r_pipe_cfg;
1272
1232
const struct msm_format *fmt;
1233
+
int i, ret;
1273
1234
1274
1235
if (plane_state->crtc)
1275
1236
crtc_state = drm_atomic_get_new_crtc_state(state,
1276
1237
plane_state->crtc);
1277
1238
1278
1239
pstate = to_dpu_plane_state(plane_state);
1279
-
prev_adjacent_pstate = prev_adjacent_plane_state ?
1280
-
to_dpu_plane_state(prev_adjacent_plane_state) : NULL;
1281
-
pipe = &pstate->pipe;
1282
-
r_pipe = &pstate->r_pipe;
1283
-
pipe_cfg = &pstate->pipe_cfg;
1284
-
r_pipe_cfg = &pstate->r_pipe_cfg;
1240
+
for (i = 0; i < STAGES_PER_PLANE; i++)
1241
+
prev_adjacent_pstate[i] = prev_adjacent_plane_state[i] ?
1242
+
to_dpu_plane_state(prev_adjacent_plane_state[i]) : NULL;
1285
1243
1286
-
pipe->sspp = NULL;
1287
-
r_pipe->sspp = NULL;
1244
+
for (i = 0; i < PIPES_PER_PLANE; i++)
1245
+
pstate->pipe[i].sspp = NULL;
1288
1246
1289
1247
if (!plane_state->fb)
1290
1248
return -EINVAL;
···
1331
1219
1332
1220
reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
1333
1221
1334
-
if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) {
1335
-
if (!prev_adjacent_pstate ||
1336
-
!dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt,
1337
-
dpu_kms->catalog->caps->max_linewidth)) {
1338
-
pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
1339
-
if (!pipe->sspp)
1340
-
return -ENODEV;
1222
+
for (i = 0; i < STAGES_PER_PLANE; i++) {
1223
+
if (prev_adjacent_pstate[i] &&
1224
+
dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate[i], fmt,
1225
+
dpu_kms->catalog->caps->max_linewidth,
1226
+
i))
1227
+
continue;
1341
1228
1342
-
r_pipe->sspp = NULL;
1229
+
if (dpu_plane_get_single_pipe_in_stage(pstate, &pipe, &pipe_cfg, i))
1230
+
prev_adjacent_plane_state[i] = plane_state;
1343
1231
1344
-
pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1345
-
pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1346
-
1347
-
r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1348
-
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1349
-
}
1350
-
} else {
1351
-
pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
1352
-
if (!pipe->sspp)
1353
-
return -ENODEV;
1354
-
1355
-
if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
1356
-
pipe->sspp,
1357
-
msm_framebuffer_format(plane_state->fb),
1358
-
dpu_kms->catalog->caps->max_linewidth)) {
1359
-
/* multirect is not possible, use two SSPP blocks */
1360
-
r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
1361
-
if (!r_pipe->sspp)
1362
-
return -ENODEV;
1363
-
1364
-
pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1365
-
pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1366
-
1367
-
r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1368
-
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1369
-
}
1232
+
pipe = &pstate->pipe[i * PIPES_PER_STAGE];
1233
+
pipe_cfg = &pstate->pipe_cfg[i * PIPES_PER_STAGE];
1234
+
ret = dpu_plane_assign_resource_in_stage(pipe, pipe_cfg,
1235
+
plane_state,
1236
+
global_state,
1237
+
crtc, &reqs);
1238
+
if (ret)
1239
+
return ret;
1370
1240
}
1371
1241
1372
1242
return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
···
1361
1267
unsigned int num_planes)
1362
1268
{
1363
1269
unsigned int i;
1364
-
struct drm_plane_state *prev_adjacent_plane_state = NULL;
1270
+
struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] = { NULL };
1365
1271
1366
1272
for (i = 0; i < num_planes; i++) {
1367
1273
struct drm_plane_state *plane_state = states[i];
···
1375
1281
prev_adjacent_plane_state);
1376
1282
if (ret)
1377
1283
return ret;
1378
-
1379
-
prev_adjacent_plane_state = plane_state;
1380
1284
}
1381
1285
1382
1286
return 0;
···
1410
1318
{
1411
1319
struct dpu_plane *pdpu;
1412
1320
struct dpu_plane_state *pstate;
1321
+
int i;
1413
1322
1414
1323
if (!plane || !plane->state) {
1415
1324
DPU_ERROR("invalid plane\n");
···
1431
1338
/* force 100% alpha */
1432
1339
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
1433
1340
else {
1434
-
dpu_plane_flush_csc(pdpu, &pstate->pipe);
1435
-
dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
1341
+
for (i = 0; i < PIPES_PER_PLANE; i++)
1342
+
dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
1436
1343
}
1437
1344
1438
1345
/* flag h/w flush complete */
···
1533
1440
struct dpu_plane *pdpu = to_dpu_plane(plane);
1534
1441
struct drm_plane_state *state = plane->state;
1535
1442
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1536
-
struct dpu_sw_pipe *pipe = &pstate->pipe;
1537
-
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1538
1443
struct drm_crtc *crtc = state->crtc;
1539
1444
struct drm_framebuffer *fb = state->fb;
1540
1445
bool is_rt_pipe;
1541
1446
const struct msm_format *fmt =
1542
1447
msm_framebuffer_format(fb);
1543
-
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1544
-
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1448
+
int i;
1545
1449
1546
1450
pstate->pending = true;
1547
1451
···
1553
1463
crtc->base.id, DRM_RECT_ARG(&state->dst),
1554
1464
&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
1555
1465
1556
-
dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
1557
-
drm_mode_vrefresh(&crtc->mode),
1558
-
&pstate->layout);
1559
-
1560
-
if (r_pipe->sspp) {
1561
-
dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
1466
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
1467
+
if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect))
1468
+
continue;
1469
+
dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
1470
+
&pstate->pipe_cfg[i], fmt,
1562
1471
drm_mode_vrefresh(&crtc->mode),
1563
1472
&pstate->layout);
1564
1473
}
···
1565
1476
if (pstate->needs_qos_remap)
1566
1477
pstate->needs_qos_remap = false;
1567
1478
1568
-
pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
1569
-
&crtc->mode, pipe_cfg);
1479
+
pstate->plane_fetch_bw = 0;
1480
+
pstate->plane_clk = 0;
1481
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
1482
+
if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect))
1483
+
continue;
1484
+
pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
1485
+
&crtc->mode, &pstate->pipe_cfg[i]);
1570
1486
1571
-
pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
1572
-
1573
-
if (r_pipe->sspp) {
1574
-
pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
1575
-
1576
-
pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
1487
+
pstate->plane_clk = max(pstate->plane_clk,
1488
+
_dpu_plane_calc_clk(&crtc->mode,
1489
+
&pstate->pipe_cfg[i]));
1577
1490
}
1578
1491
}
1579
1492
···
1583
1492
{
1584
1493
struct drm_plane_state *state = plane->state;
1585
1494
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1586
-
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1495
+
struct dpu_sw_pipe *pipe;
1496
+
int i;
1587
1497
1588
-
trace_dpu_plane_disable(DRMID(plane), false,
1589
-
pstate->pipe.multirect_mode);
1498
+
for (i = 0; i < PIPES_PER_PLANE; i += 1) {
1499
+
pipe = &pstate->pipe[i];
1500
+
if (!pipe->sspp)
1501
+
continue;
1590
1502
1591
-
if (r_pipe->sspp) {
1592
-
r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1593
-
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1503
+
trace_dpu_plane_disable(DRMID(plane), false,
1504
+
pstate->pipe[i].multirect_mode);
1594
1505
1595
-
if (r_pipe->sspp->ops.setup_multirect)
1596
-
r_pipe->sspp->ops.setup_multirect(r_pipe);
1506
+
if (i % PIPES_PER_STAGE == 0)
1507
+
continue;
1508
+
1509
+
/*
1510
+
* clear multirect for the right pipe so that the SSPP
1511
+
* can be further reused in the solo mode
1512
+
*/
1513
+
pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1514
+
pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1515
+
if (pipe->sspp->ops.setup_multirect)
1516
+
pipe->sspp->ops.setup_multirect(pipe);
1597
1517
}
1598
1518
1599
1519
pstate->pending = true;
···
1699
1597
const struct drm_plane_state *state)
1700
1598
{
1701
1599
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1702
-
const struct dpu_sw_pipe *pipe = &pstate->pipe;
1703
-
const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1704
-
const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1705
-
const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1600
+
const struct dpu_sw_pipe *pipe;
1601
+
const struct dpu_sw_pipe_cfg *pipe_cfg;
1602
+
int i;
1706
1603
1707
1604
drm_printf(p, "\tstage=%d\n", pstate->stage);
1708
1605
1709
-
if (pipe->sspp) {
1710
-
drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name);
1711
-
drm_printf(p, "\tmultirect_mode[0]=%s\n",
1606
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
1607
+
pipe = &pstate->pipe[i];
1608
+
if (!pipe->sspp)
1609
+
continue;
1610
+
pipe_cfg = &pstate->pipe_cfg[i];
1611
+
drm_printf(p, "\tsspp[%d]=%s\n", i, pipe->sspp->cap->name);
1612
+
drm_printf(p, "\tmultirect_mode[%d]=%s\n", i,
1712
1613
dpu_get_multirect_mode(pipe->multirect_mode));
1713
-
drm_printf(p, "\tmultirect_index[0]=%s\n",
1614
+
drm_printf(p, "\tmultirect_index[%d]=%s\n", i,
1714
1615
dpu_get_multirect_index(pipe->multirect_index));
1715
-
drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect));
1716
-
drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect));
1717
-
}
1718
-
1719
-
if (r_pipe->sspp) {
1720
-
drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name);
1721
-
drm_printf(p, "\tmultirect_mode[1]=%s\n",
1722
-
dpu_get_multirect_mode(r_pipe->multirect_mode));
1723
-
drm_printf(p, "\tmultirect_index[1]=%s\n",
1724
-
dpu_get_multirect_index(r_pipe->multirect_index));
1725
-
drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect));
1726
-
drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect));
1616
+
drm_printf(p, "\tsrc[%d]=" DRM_RECT_FMT "\n", i,
1617
+
DRM_RECT_ARG(&pipe_cfg->src_rect));
1618
+
drm_printf(p, "\tdst[%d]=" DRM_RECT_FMT "\n", i,
1619
+
DRM_RECT_ARG(&pipe_cfg->dst_rect));
1727
1620
}
1728
1621
}
1729
1622
···
1756
1659
struct dpu_plane *pdpu = to_dpu_plane(plane);
1757
1660
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
1758
1661
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1662
+
int i;
1759
1663
1760
1664
if (!pdpu->is_rt_pipe)
1761
1665
return;
1762
1666
1763
1667
pm_runtime_get_sync(&dpu_kms->pdev->dev);
1764
-
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable);
1765
-
if (pstate->r_pipe.sspp)
1766
-
_dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable);
1668
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
1669
+
if (!pstate->pipe[i].sspp)
1670
+
continue;
1671
+
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable);
1672
+
}
1767
1673
pm_runtime_put_sync(&dpu_kms->pdev->dev);
1768
1674
}
1769
1675
#endif
+4
-8
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+4
-8
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
···
17
17
/**
18
18
* struct dpu_plane_state: Define dpu extension of drm plane state object
19
19
* @base: base drm plane state object
20
-
* @pipe: software pipe description
21
-
* @r_pipe: software pipe description of the second pipe
22
-
* @pipe_cfg: software pipe configuration
23
-
* @r_pipe_cfg: software pipe configuration for the second pipe
20
+
* @pipe: software pipe description array
21
+
* @pipe_cfg: software pipe configuration array
24
22
* @stage: assigned by crtc blender
25
23
* @needs_qos_remap: qos remap settings need to be updated
26
24
* @multirect_index: index of the rectangle of SSPP
···
31
33
*/
32
34
struct dpu_plane_state {
33
35
struct drm_plane_state base;
34
-
struct dpu_sw_pipe pipe;
35
-
struct dpu_sw_pipe r_pipe;
36
-
struct dpu_sw_pipe_cfg pipe_cfg;
37
-
struct dpu_sw_pipe_cfg r_pipe_cfg;
36
+
struct dpu_sw_pipe pipe[PIPES_PER_PLANE];
37
+
struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];
38
38
enum dpu_stage stage;
39
39
bool needs_qos_remap;
40
40
bool pending;
+5
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+5
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
···
374
374
if (!rm->mixer_blks[i])
375
375
continue;
376
376
377
-
lm_count = 0;
377
+
/*
378
+
* Reset lm_count to an even index. This will drop the previous
379
+
* primary mixer if failed to find its peer.
380
+
*/
381
+
lm_count &= ~1;
378
382
lm_idx[lm_count] = i;
379
383
380
384
if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state,
+5
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+5
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
···
651
651
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
652
652
struct drm_plane_state *state, struct dpu_plane_state *pstate,
653
653
uint32_t stage_idx, uint32_t pixel_format,
654
-
uint64_t modifier),
654
+
struct dpu_sw_pipe *pipe, uint64_t modifier),
655
655
TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
656
-
pixel_format, modifier),
656
+
pixel_format, pipe, modifier),
657
657
TP_STRUCT__entry(
658
658
__field( uint32_t, crtc_id )
659
659
__field( uint32_t, plane_id )
···
676
676
__entry->dst_rect = drm_plane_state_dest(state);
677
677
__entry->stage_idx = stage_idx;
678
678
__entry->stage = pstate->stage;
679
-
__entry->sspp = pstate->pipe.sspp->idx;
680
-
__entry->multirect_idx = pstate->pipe.multirect_index;
681
-
__entry->multirect_mode = pstate->pipe.multirect_mode;
679
+
__entry->sspp = pipe->sspp->idx;
680
+
__entry->multirect_idx = pipe->multirect_index;
681
+
__entry->multirect_mode = pipe->multirect_mode;
682
682
__entry->pixel_format = pixel_format;
683
683
__entry->modifier = modifier;
684
684
),
+7
-6
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h
+7
-6
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h
···
38
38
* struct msm_disp_state - structure to store current dpu state
39
39
* @dev: device pointer
40
40
* @drm_dev: drm device pointer
41
+
* @blocks: list head for hardware state blocks
41
42
* @atomic_state: atomic state duplicated at the time of the error
42
43
* @time: timestamp at which the coredump was captured
43
44
*/
···
56
55
/**
57
56
* struct msm_disp_state_block - structure to store each hardware block state
58
57
* @name: name of the block
59
-
* @drm_dev: handle to the linked list head
58
+
* @node: handle to the linked list head
60
59
* @size: size of the register space of this hardware block
61
60
* @state: array holding the register dump of this hardware block
62
61
* @base_addr: starting address of this hardware block's register space
···
89
88
* msm_disp_snapshot_state_sync - synchronously snapshot display state
90
89
* @kms: the kms object
91
90
*
92
-
* Returns state or error
91
+
* Returns: state or error
93
92
*
93
+
* Context:
94
94
* Must be called with &kms->dump_mutex held
95
95
*/
96
96
struct msm_disp_state *msm_disp_snapshot_state_sync(struct msm_kms *kms);
···
99
97
/**
100
98
* msm_disp_snapshot_state - trigger to dump the display snapshot
101
99
* @drm_dev: handle to drm device
102
-
100
+
*
103
101
* Returns: none
104
102
*/
105
103
void msm_disp_snapshot_state(struct drm_device *drm_dev);
···
116
114
/**
117
115
* msm_disp_snapshot_capture_state - utility to capture atomic state and hw registers
118
116
* @disp_state: handle to msm_disp_state struct
119
-
117
+
*
120
118
* Returns: none
121
119
*/
122
120
void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state);
···
124
122
/**
125
123
* msm_disp_state_free - free the memory after the coredump has been read
126
124
* @data: handle to struct msm_disp_state
127
-
125
+
*
128
126
* Returns: none
129
127
*/
130
128
void msm_disp_state_free(void *data);
···
132
130
/**
133
131
* msm_disp_snapshot_add_block - add a hardware block with its register dump
134
132
* @disp_state: handle to struct msm_disp_state
135
-
* @name: name of the hardware block
136
133
* @len: size of the register space of the hardware block
137
134
* @base_addr: starting address of the register space of the hardware block
138
135
* @fmt: format in which the block names need to be printed
+5
-5
drivers/gpu/drm/msm/dp/dp_ctrl.c
+5
-5
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
423
423
424
424
static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl)
425
425
{
426
-
u32 ln_0 = 0, ln_1 = 1, ln_2 = 2, ln_3 = 3; /* One-to-One mapping */
426
+
u32 *lane_map = ctrl->link->lane_map;
427
427
u32 ln_mapping;
428
428
429
-
ln_mapping = ln_0 << LANE0_MAPPING_SHIFT;
430
-
ln_mapping |= ln_1 << LANE1_MAPPING_SHIFT;
431
-
ln_mapping |= ln_2 << LANE2_MAPPING_SHIFT;
432
-
ln_mapping |= ln_3 << LANE3_MAPPING_SHIFT;
429
+
ln_mapping = lane_map[0] << LANE0_MAPPING_SHIFT;
430
+
ln_mapping |= lane_map[1] << LANE1_MAPPING_SHIFT;
431
+
ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT;
432
+
ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT;
433
433
434
434
msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING,
435
435
ln_mapping);
+9
drivers/gpu/drm/msm/dp/dp_display.c
+9
drivers/gpu/drm/msm/dp/dp_display.c
···
130
130
bool wide_bus_supported;
131
131
};
132
132
133
+
static const struct msm_dp_desc msm_dp_desc_glymur[] = {
134
+
{ .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
135
+
{ .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
136
+
{ .io_start = 0x0af64000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
137
+
{ .io_start = 0x0af6c000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
138
+
{}
139
+
};
140
+
133
141
static const struct msm_dp_desc msm_dp_desc_sa8775p[] = {
134
142
{ .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
135
143
{ .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
···
195
187
};
196
188
197
189
static const struct of_device_id msm_dp_dt_match[] = {
190
+
{ .compatible = "qcom,glymur-dp", .data = &msm_dp_desc_glymur },
198
191
{ .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p },
199
192
{ .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 },
200
193
{ .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 },
+117
drivers/gpu/drm/msm/dp/dp_link.c
+117
drivers/gpu/drm/msm/dp/dp_link.c
···
6
6
#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
7
7
8
8
#include <drm/drm_device.h>
9
+
#include <drm/drm_of.h>
9
10
#include <drm/drm_print.h>
10
11
11
12
#include "dp_reg.h"
12
13
#include "dp_link.h"
13
14
#include "dp_panel.h"
14
15
16
+
#define DP_LINK_RATE_HBR2 540000 /* kbytes */
15
17
#define DP_TEST_REQUEST_MASK 0x7F
16
18
17
19
enum audio_sample_rate {
···
1212
1210
return tbd;
1213
1211
}
1214
1212
1213
+
static u32 msm_dp_link_link_frequencies(struct device_node *of_node)
1214
+
{
1215
+
struct device_node *endpoint;
1216
+
u64 frequency = 0;
1217
+
int cnt;
1218
+
1219
+
endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
1220
+
if (!endpoint)
1221
+
return 0;
1222
+
1223
+
cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
1224
+
1225
+
if (cnt > 0)
1226
+
of_property_read_u64_index(endpoint, "link-frequencies",
1227
+
cnt - 1, &frequency);
1228
+
of_node_put(endpoint);
1229
+
1230
+
do_div(frequency,
1231
+
10 * /* from symbol rate to link rate */
1232
+
1000); /* kbytes */
1233
+
1234
+
return frequency;
1235
+
}
1236
+
1237
+
/*
1238
+
* Always populate msm_dp_link->lane_map with 4 lanes.
1239
+
* - Use DTS "data-lanes" if present; otherwise fall back to default mapping.
1240
+
* - For partial definitions, fill remaining entries with unused lanes in
1241
+
* ascending order.
1242
+
*/
1243
+
static int msm_dp_link_lane_map(struct device *dev, struct msm_dp_link *msm_dp_link)
1244
+
{
1245
+
struct device_node *of_node = dev->of_node;
1246
+
struct device_node *endpoint;
1247
+
int cnt = msm_dp_link->max_dp_lanes;
1248
+
u32 tmp[DP_MAX_NUM_DP_LANES];
1249
+
u32 map[DP_MAX_NUM_DP_LANES] = {0, 1, 2, 3}; /* default 1:1 mapping */
1250
+
bool used[DP_MAX_NUM_DP_LANES] = {false};
1251
+
int i, j = 0, ret = -EINVAL;
1252
+
1253
+
endpoint = of_graph_get_endpoint_by_regs(of_node, 1, -1);
1254
+
if (endpoint) {
1255
+
ret = of_property_read_u32_array(endpoint, "data-lanes", tmp, cnt);
1256
+
if (ret)
1257
+
dev_dbg(dev, "endpoint data-lanes read failed (ret=%d)\n", ret);
1258
+
}
1259
+
1260
+
if (ret) {
1261
+
ret = of_property_read_u32_array(of_node, "data-lanes", tmp, cnt);
1262
+
if (ret) {
1263
+
dev_info(dev, "data-lanes not defined, set to default\n");
1264
+
goto out;
1265
+
}
1266
+
}
1267
+
1268
+
for (i = 0; i < cnt; i++) {
1269
+
if (tmp[i] >= DP_MAX_NUM_DP_LANES) {
1270
+
dev_err(dev, "data-lanes[%d]=%u out of range\n", i, tmp[i]);
1271
+
return -EINVAL;
1272
+
}
1273
+
used[tmp[i]] = true;
1274
+
map[i] = tmp[i];
1275
+
}
1276
+
1277
+
/* Fill the remaining entries with unused physical lanes (ascending) */
1278
+
for (i = cnt; i < DP_MAX_NUM_DP_LANES && j < DP_MAX_NUM_DP_LANES; j++) {
1279
+
if (!used[j])
1280
+
map[i++] = j;
1281
+
}
1282
+
1283
+
out:
1284
+
if (endpoint)
1285
+
of_node_put(endpoint);
1286
+
1287
+
dev_dbg(dev, "data-lanes count %d <%d %d %d %d>\n", cnt, map[0], map[1], map[2], map[3]);
1288
+
memcpy(msm_dp_link->lane_map, map, sizeof(map));
1289
+
return 0;
1290
+
}
1291
+
1292
+
static int msm_dp_link_parse_dt(struct device *dev, struct msm_dp_link *msm_dp_link)
1293
+
{
1294
+
struct device_node *of_node = dev->of_node;
1295
+
int cnt;
1296
+
1297
+
/*
1298
+
* data-lanes is the property of msm_dp_out endpoint
1299
+
*/
1300
+
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
1301
+
if (cnt < 0) {
1302
+
/* legacy code, data-lanes is the property of mdss_dp node */
1303
+
cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
1304
+
}
1305
+
1306
+
if (cnt > 0)
1307
+
msm_dp_link->max_dp_lanes = cnt;
1308
+
else
1309
+
msm_dp_link->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
1310
+
1311
+
if (msm_dp_link_lane_map(dev, msm_dp_link)) {
1312
+
dev_err(dev, "failed to parse data-lanes\n");
1313
+
return -EINVAL;
1314
+
}
1315
+
1316
+
msm_dp_link->max_dp_link_rate = msm_dp_link_link_frequencies(of_node);
1317
+
if (!msm_dp_link->max_dp_link_rate)
1318
+
msm_dp_link->max_dp_link_rate = DP_LINK_RATE_HBR2;
1319
+
1320
+
return 0;
1321
+
}
1322
+
1215
1323
struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux *aux)
1216
1324
{
1217
1325
struct msm_dp_link_private *link;
1218
1326
struct msm_dp_link *msm_dp_link;
1327
+
int ret;
1219
1328
1220
1329
if (!dev || !aux) {
1221
1330
DRM_ERROR("invalid input\n");
···
1341
1228
1342
1229
mutex_init(&link->psm_mutex);
1343
1230
msm_dp_link = &link->msm_dp_link;
1231
+
1232
+
ret = msm_dp_link_parse_dt(dev, msm_dp_link);
1233
+
if (ret)
1234
+
return ERR_PTR(ret);
1344
1235
1345
1236
return msm_dp_link;
1346
1237
}
+5
drivers/gpu/drm/msm/dp/dp_link.h
+5
drivers/gpu/drm/msm/dp/dp_link.h
···
12
12
#define DS_PORT_STATUS_CHANGED 0x200
13
13
#define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF
14
14
#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
15
+
#define DP_MAX_NUM_DP_LANES 4
15
16
16
17
struct msm_dp_link_info {
17
18
unsigned char revision;
···
73
72
struct msm_dp_link_test_audio test_audio;
74
73
struct msm_dp_link_phy_params phy_params;
75
74
struct msm_dp_link_info link_params;
75
+
76
+
u32 lane_map[DP_MAX_NUM_DP_LANES];
77
+
u32 max_dp_lanes;
78
+
u32 max_dp_link_rate;
76
79
};
77
80
78
81
/**
+9
-69
drivers/gpu/drm/msm/dp/dp_panel.c
+9
-69
drivers/gpu/drm/msm/dp/dp_panel.c
···
16
16
17
17
#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4)
18
18
19
-
#define DP_MAX_NUM_DP_LANES 4
20
-
#define DP_LINK_RATE_HBR2 540000 /* kbytes */
21
-
22
19
struct msm_dp_panel_private {
23
20
struct device *dev;
24
21
struct drm_device *drm_dev;
···
88
91
int rc, max_lttpr_lanes, max_lttpr_rate;
89
92
struct msm_dp_panel_private *panel;
90
93
struct msm_dp_link_info *link_info;
94
+
struct msm_dp_link *link;
91
95
u8 *dpcd, major, minor;
92
96
93
97
panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
···
103
105
major = (link_info->revision >> 4) & 0x0f;
104
106
minor = link_info->revision & 0x0f;
105
107
108
+
link = panel->link;
109
+
drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
110
+
link->max_dp_lanes, link->max_dp_link_rate);
111
+
106
112
link_info->rate = drm_dp_max_link_rate(dpcd);
107
113
link_info->num_lanes = drm_dp_max_lane_count(dpcd);
108
114
109
115
/* Limit data lanes from data-lanes of endpoint property of dtsi */
110
-
if (link_info->num_lanes > msm_dp_panel->max_dp_lanes)
111
-
link_info->num_lanes = msm_dp_panel->max_dp_lanes;
116
+
if (link_info->num_lanes > link->max_dp_lanes)
117
+
link_info->num_lanes = link->max_dp_lanes;
112
118
113
119
/* Limit link rate from link-frequencies of endpoint property of dtsi */
114
-
if (link_info->rate > msm_dp_panel->max_dp_link_rate)
115
-
link_info->rate = msm_dp_panel->max_dp_link_rate;
120
+
if (link_info->rate > link->max_dp_link_rate)
121
+
link_info->rate = link->max_dp_link_rate;
116
122
117
123
/* Limit data lanes from LTTPR capabilities, if any */
118
124
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps);
···
174
172
}
175
173
176
174
panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
177
-
178
-
drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
179
-
msm_dp_panel->max_dp_lanes, msm_dp_panel->max_dp_link_rate);
180
175
181
176
rc = msm_dp_panel_read_dpcd(msm_dp_panel);
182
177
if (rc) {
···
647
648
return 0;
648
649
}
649
650
650
-
static u32 msm_dp_panel_link_frequencies(struct device_node *of_node)
651
-
{
652
-
struct device_node *endpoint;
653
-
u64 frequency = 0;
654
-
int cnt;
655
-
656
-
endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
657
-
if (!endpoint)
658
-
return 0;
659
-
660
-
cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
661
-
662
-
if (cnt > 0)
663
-
of_property_read_u64_index(endpoint, "link-frequencies",
664
-
cnt - 1, &frequency);
665
-
of_node_put(endpoint);
666
-
667
-
do_div(frequency,
668
-
10 * /* from symbol rate to link rate */
669
-
1000); /* kbytes */
670
-
671
-
return frequency;
672
-
}
673
-
674
-
static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel)
675
-
{
676
-
struct msm_dp_panel_private *panel;
677
-
struct device_node *of_node;
678
-
int cnt;
679
-
680
-
panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
681
-
of_node = panel->dev->of_node;
682
-
683
-
/*
684
-
* data-lanes is the property of msm_dp_out endpoint
685
-
*/
686
-
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
687
-
if (cnt < 0) {
688
-
/* legacy code, data-lanes is the property of mdss_dp node */
689
-
cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
690
-
}
691
-
692
-
if (cnt > 0)
693
-
msm_dp_panel->max_dp_lanes = cnt;
694
-
else
695
-
msm_dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
696
-
697
-
msm_dp_panel->max_dp_link_rate = msm_dp_panel_link_frequencies(of_node);
698
-
if (!msm_dp_panel->max_dp_link_rate)
699
-
msm_dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2;
700
-
701
-
return 0;
702
-
}
703
-
704
651
struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,
705
652
struct msm_dp_link *link,
706
653
void __iomem *link_base,
···
654
709
{
655
710
struct msm_dp_panel_private *panel;
656
711
struct msm_dp_panel *msm_dp_panel;
657
-
int ret;
658
712
659
713
if (!dev || !aux || !link) {
660
714
DRM_ERROR("invalid input\n");
···
672
728
673
729
msm_dp_panel = &panel->msm_dp_panel;
674
730
msm_dp_panel->max_bw_code = DP_LINK_BW_8_1;
675
-
676
-
ret = msm_dp_panel_parse_dt(msm_dp_panel);
677
-
if (ret)
678
-
return ERR_PTR(ret);
679
731
680
732
return msm_dp_panel;
681
733
}
-3
drivers/gpu/drm/msm/dp/dp_panel.h
-3
drivers/gpu/drm/msm/dp/dp_panel.h
+10
-7
drivers/gpu/drm/msm/msm_gem.c
+10
-7
drivers/gpu/drm/msm/msm_gem.c
···
701
701
struct drm_mode_create_dumb *args)
702
702
{
703
703
u32 fourcc;
704
-
const struct drm_format_info *info;
705
704
u64 pitch_align;
706
705
int ret;
707
706
···
710
711
* Use the result as pitch alignment.
711
712
*/
712
713
fourcc = drm_driver_color_mode_format(dev, args->bpp);
713
-
if (fourcc == DRM_FORMAT_INVALID)
714
-
return -EINVAL;
715
-
info = drm_format_info(fourcc);
716
-
if (!info)
717
-
return -EINVAL;
718
-
pitch_align = drm_format_info_min_pitch(info, 0, SZ_32);
714
+
if (fourcc != DRM_FORMAT_INVALID) {
715
+
const struct drm_format_info *info;
716
+
717
+
info = drm_format_info(fourcc);
718
+
if (!info)
719
+
return -EINVAL;
720
+
pitch_align = drm_format_info_min_pitch(info, 0, 32);
721
+
} else {
722
+
pitch_align = round_up(args->width, 32) * DIV_ROUND_UP(args->bpp, SZ_8);
723
+
}
719
724
if (!pitch_align || pitch_align > U32_MAX)
720
725
return -EINVAL;
721
726
ret = drm_mode_size_dumb(dev, args, pitch_align, 0);
+22
-6
drivers/gpu/drm/msm/msm_gem_vma.c
+22
-6
drivers/gpu/drm/msm/msm_gem_vma.c
···
462
462
bool kept;
463
463
};
464
464
465
-
static void
465
+
static int
466
466
vm_op_enqueue(struct op_arg *arg, struct msm_vm_op _op)
467
467
{
468
468
struct msm_vm_op *op = kmalloc(sizeof(*op), GFP_KERNEL);
469
+
if (!op)
470
+
return -ENOMEM;
471
+
469
472
*op = _op;
470
473
list_add_tail(&op->node, &arg->job->vm_ops);
471
474
472
475
if (op->obj)
473
476
drm_gem_object_get(op->obj);
477
+
478
+
return 0;
474
479
}
475
480
476
481
static struct drm_gpuva *
···
494
489
struct drm_gpuva *vma;
495
490
struct sg_table *sgt;
496
491
unsigned prot;
492
+
int ret;
497
493
498
494
if (arg->kept)
499
495
return 0;
···
506
500
vm_dbg("%p:%p:%p: %016llx %016llx", vma->vm, vma, vma->gem.obj,
507
501
vma->va.addr, vma->va.range);
508
502
509
-
vma->flags = ((struct op_arg *)arg)->flags;
510
-
511
503
if (obj) {
512
504
sgt = to_msm_bo(obj)->sgt;
513
505
prot = msm_gem_prot(obj);
···
514
510
prot = IOMMU_READ | IOMMU_WRITE;
515
511
}
516
512
517
-
vm_op_enqueue(arg, (struct msm_vm_op){
513
+
ret = vm_op_enqueue(arg, (struct msm_vm_op){
518
514
.op = MSM_VM_OP_MAP,
519
515
.map = {
520
516
.sgt = sgt,
···
527
523
.obj = vma->gem.obj,
528
524
});
529
525
526
+
if (ret)
527
+
return ret;
528
+
529
+
vma->flags = ((struct op_arg *)arg)->flags;
530
530
to_msm_vma(vma)->mapped = true;
531
531
532
532
return 0;
···
546
538
struct drm_gpuvm_bo *vm_bo = orig_vma->vm_bo;
547
539
bool mapped = to_msm_vma(orig_vma)->mapped;
548
540
unsigned flags;
541
+
int ret;
549
542
550
543
vm_dbg("orig_vma: %p:%p:%p: %016llx %016llx", vm, orig_vma,
551
544
orig_vma->gem.obj, orig_vma->va.addr, orig_vma->va.range);
···
556
547
557
548
drm_gpuva_op_remap_to_unmap_range(&op->remap, &unmap_start, &unmap_range);
558
549
559
-
vm_op_enqueue(arg, (struct msm_vm_op){
550
+
ret = vm_op_enqueue(arg, (struct msm_vm_op){
560
551
.op = MSM_VM_OP_UNMAP,
561
552
.unmap = {
562
553
.iova = unmap_start,
···
565
556
},
566
557
.obj = orig_vma->gem.obj,
567
558
});
559
+
560
+
if (ret)
561
+
return ret;
568
562
569
563
/*
570
564
* Part of this GEM obj is still mapped, but we're going to kill the
···
630
618
struct msm_vm_bind_job *job = arg->job;
631
619
struct drm_gpuva *vma = op->unmap.va;
632
620
struct msm_gem_vma *msm_vma = to_msm_vma(vma);
621
+
int ret;
633
622
634
623
vm_dbg("%p:%p:%p: %016llx %016llx", vma->vm, vma, vma->gem.obj,
635
624
vma->va.addr, vma->va.range);
···
663
650
if (!msm_vma->mapped)
664
651
goto out_close;
665
652
666
-
vm_op_enqueue(arg, (struct msm_vm_op){
653
+
ret = vm_op_enqueue(arg, (struct msm_vm_op){
667
654
.op = MSM_VM_OP_UNMAP,
668
655
.unmap = {
669
656
.iova = vma->va.addr,
···
672
659
},
673
660
.obj = vma->gem.obj,
674
661
});
662
+
663
+
if (ret)
664
+
return ret;
675
665
676
666
msm_vma->mapped = false;
677
667
+13
-8
drivers/gpu/drm/msm/msm_gpu.c
+13
-8
drivers/gpu/drm/msm/msm_gpu.c
···
287
287
288
288
state->bos = kcalloc(cnt, sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
289
289
290
-
drm_gpuvm_for_each_va (vma, submit->vm) {
291
-
bool dump = rd_full || (vma->flags & MSM_VMA_DUMP);
290
+
if (state->bos)
291
+
drm_gpuvm_for_each_va(vma, submit->vm) {
292
+
bool dump = rd_full || (vma->flags & MSM_VMA_DUMP);
292
293
293
-
/* Skip MAP_NULL/PRR VMAs: */
294
-
if (!vma->gem.obj)
295
-
continue;
294
+
/* Skip MAP_NULL/PRR VMAs: */
295
+
if (!vma->gem.obj)
296
+
continue;
296
297
297
-
msm_gpu_crashstate_get_bo(state, vma->gem.obj, vma->va.addr,
298
-
dump, vma->gem.offset, vma->va.range);
299
-
}
298
+
msm_gpu_crashstate_get_bo(state, vma->gem.obj, vma->va.addr,
299
+
dump, vma->gem.offset, vma->va.range);
300
+
}
300
301
301
302
drm_exec_fini(&exec);
302
303
} else {
···
349
348
350
349
state->vm_logs = kmalloc_array(
351
350
state->nr_vm_logs, sizeof(vm->log[0]), GFP_KERNEL);
351
+
if (!state->vm_logs) {
352
+
state->nr_vm_logs = 0;
353
+
}
354
+
352
355
for (int i = 0; i < state->nr_vm_logs; i++) {
353
356
int idx = (i + first) & vm_log_mask;
354
357
+2
drivers/gpu/drm/msm/msm_mdss.c
+2
drivers/gpu/drm/msm/msm_mdss.c
···
553
553
554
554
static const struct of_device_id mdss_dt_match[] = {
555
555
{ .compatible = "qcom,mdss", .data = &data_153k6 },
556
+
{ .compatible = "qcom,glymur-mdss", .data = &data_57k },
556
557
{ .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
557
558
{ .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
559
+
{ .compatible = "qcom,qcs8300-mdss", .data = &data_74k },
558
560
{ .compatible = "qcom,sa8775p-mdss", .data = &data_74k },
559
561
{ .compatible = "qcom,sar2130p-mdss", .data = &data_74k },
560
562
{ .compatible = "qcom,sdm670-mdss", .data = &data_76k8 },
+1637
-544
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+1637
-544
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
···
7
7
<import file="adreno/adreno_pm4.xml"/>
8
8
<import file="adreno/a6xx_enums.xml"/>
9
9
<import file="adreno/a7xx_enums.xml"/>
10
+
<import file="adreno/a8xx_enums.xml"/>
10
11
<import file="adreno/a6xx_perfcntrs.xml"/>
11
12
<import file="adreno/a7xx_perfcntrs.xml"/>
12
13
<import file="adreno/a6xx_descriptors.xml"/>
14
+
<import file="adreno/a8xx_descriptors.xml"/>
13
15
14
16
<!--
15
17
Each register that is actually being used by driver should have "usage" defined,
···
86
84
<bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
87
85
</bitset>
88
86
87
+
<bitset name="A8XX_CP_GLOBAL_INT_MASK" inline="no" varset="chip">
88
+
<bitfield name="HWFAULTBR" pos="0" type="boolean"/>
89
+
<bitfield name="HWFAULTBV" pos="1" type="boolean"/>
90
+
<bitfield name="HWFAULTLPAC" pos="2" type="boolean"/>
91
+
<bitfield name="HWFAULTAQE0" pos="3" type="boolean"/>
92
+
<bitfield name="HWFAULTAQE1" pos="4" type="boolean"/>
93
+
<bitfield name="HWFAULTDDEBR" pos="5" type="boolean"/>
94
+
<bitfield name="HWFAULTDDEBV" pos="6" type="boolean"/>
95
+
<bitfield name="SWFAULTBR" pos="16" type="boolean"/>
96
+
<bitfield name="SWFAULTBV" pos="17" type="boolean"/>
97
+
<bitfield name="SWFAULTLPAC" pos="18" type="boolean"/>
98
+
<bitfield name="SWFAULTAQE0" pos="19" type="boolean"/>
99
+
<bitfield name="SWFAULTAQE1" pos="20" type="boolean"/>
100
+
<bitfield name="SWFAULTDDEBR" pos="21" type="boolean"/>
101
+
<bitfield name="SWFAULTDDEBV" pos="22" type="boolean"/>
102
+
</bitset>
103
+
104
+
<bitset name="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" inline="no" varset="chip">
105
+
<bitfield name="CSFRBWRAP" pos="0" type="boolean"/>
106
+
<bitfield name="CSFIB1WRAP" pos="1" type="boolean"/>
107
+
<bitfield name="CSFIB2WRAP" pos="2" type="boolean"/>
108
+
<bitfield name="CSFIB3WRAP" pos="3" type="boolean"/>
109
+
<bitfield name="CSFSDSWRAP" pos="4" type="boolean"/>
110
+
<bitfield name="CSFMRBWRAP" pos="5" type="boolean"/>
111
+
<bitfield name="CSFVSDWRAP" pos="6" type="boolean"/>
112
+
<bitfield name="OPCODEERROR" pos="8" type="boolean"/>
113
+
<bitfield name="VSDPARITYERROR" pos="9" type="boolean"/>
114
+
<bitfield name="REGISTERPROTECTIONERROR" pos="10" type="boolean"/>
115
+
<bitfield name="ILLEGALINSTRUCTION" pos="11" type="boolean"/>
116
+
<bitfield name="SMMUFAULT" pos="12" type="boolean"/>
117
+
<bitfield name="VBIFRESPCLIENT" pos="13" type="boolean"/>
118
+
<bitfield name="VBIFRESPTYPE" pos="19" type="boolean"/>
119
+
<bitfield name="VBIFRESPREAD" pos="21" type="boolean"/>
120
+
<bitfield name="VBIFRESP" pos="22" type="boolean"/>
121
+
<bitfield name="RTWROVF" pos="23" type="boolean"/>
122
+
<bitfield name="LRZRTWROVF" pos="24" type="boolean"/>
123
+
<bitfield name="LRZRTREFCNTOVF" pos="25" type="boolean"/>
124
+
<bitfield name="LRZRTCLRRESMISS" pos="26" type="boolean"/>
125
+
</bitset>
126
+
127
+
<bitset name="A8XX_CP_HW_FAULT_STATUS_MASK_PIPE" inline="no" varset="chip">
128
+
<bitfield name="CSFRBFAULT" pos="0" type="boolean"/>
129
+
<bitfield name="CSFIB1FAULT" pos="1" type="boolean"/>
130
+
<bitfield name="CSFIB2FAULT" pos="2" type="boolean"/>
131
+
<bitfield name="CSFIB3FAULT" pos="3" type="boolean"/>
132
+
<bitfield name="CSFSDSFAULT" pos="4" type="boolean"/>
133
+
<bitfield name="CSFMRBFAULT" pos="5" type="boolean"/>
134
+
<bitfield name="CSFVSDFAULT" pos="6" type="boolean"/>
135
+
<bitfield name="SQEREADBURSTOVF" pos="8" type="boolean"/>
136
+
<bitfield name="EVENTENGINEOVF" pos="9" type="boolean"/>
137
+
<bitfield name="UCODEERROR" pos="10" type="boolean"/>
138
+
</bitset>
139
+
89
140
<reg64 offset="0x0800" name="CP_RB_BASE"/>
90
141
<reg32 offset="0x0802" name="CP_RB_CNTL"/>
142
+
<reg32 offset="0x0803" name="CP_RB_RPTR_WR" variants="A7XX-"/>
91
143
<reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
92
144
<reg32 offset="0x0806" name="CP_RB_RPTR"/>
93
145
<reg32 offset="0x0807" name="CP_RB_WPTR"/>
94
-
<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
95
-
<reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
146
+
<reg32 offset="0x0808" name="CP_RB_RPTR_ADDR_BV" variants="A8XX-"/>
147
+
<reg32 offset="0x080a" name="CP_RB_RPTR_BV" variants="A8XX-"/>
148
+
<reg64 offset="0x080b" name="CP_RB_BASE_LPAC" variants="A8XX-"/>
149
+
<reg32 offset="0x080d" name="CP_RB_CNTL_LPAC" variants="A8XX-"/>
150
+
<reg32 offset="0x080e" name="CP_RB_RPTR_WR_LPAC" variants="A8XX-"/>
151
+
<reg64 offset="0x080f" name="CP_RB_RPTR_ADDR_LPAC" variants="A8XX-"/>
152
+
<reg32 offset="0x0811" name="CP_RB_RPTR_LPAC" variants="A8XX-"/>
153
+
<reg32 offset="0x0812" name="CP_RB_WPTR_LPAC" variants="A8XX-"/>
154
+
<reg32 offset="0x0814" name="CP_SMMU_STREAM_ID_LPAC" variants="A8XX-"/>
155
+
<reg32 offset="0x0808" name="CP_SQE_CNTL" variants="A6XX-A7XX"/>
156
+
<reg32 offset="0x0815" name="CP_SQE_CNTL" variants="A8XX-"/>
157
+
<reg64 offset="0x0816" name="CP_SQE_INSTR_BASE" variants="A8XX-"/>
158
+
<reg64 offset="0x0818" name="CP_AQE_INSTR_BASE_0" variants="A8XX-"/>
159
+
<reg64 offset="0x081a" name="CP_AQE_INSTR_BASE_1" variants="A8XX-"/>
160
+
<reg32 offset="0x0812" name="CP_CP2GMU_STATUS" variants="A6XX-A7XX">
161
+
<!-- Note, layout defined by microcode -->
96
162
<bitfield name="IFPC" pos="0" type="boolean"/>
97
163
</reg32>
98
-
<reg32 offset="0x0821" name="CP_HW_FAULT"/>
99
-
<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
100
-
<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
101
-
<reg32 offset="0x0825" name="CP_STATUS_1"/>
102
-
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
103
-
<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
104
-
<reg32 offset="0x0844" name="CP_APRIV_CNTL">
164
+
<reg32 offset="0x0822" name="CP_CP2GMU_STATUS" variants="A8XX-">
165
+
<bitfield name="IFPC" pos="0" type="boolean"/>
166
+
</reg32>
167
+
<reg32 offset="0x0821" name="CP_HW_FAULT" variants="A6XX-A7XX"/>
168
+
<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT" variants="A6XX-A7XX"/>
169
+
170
+
<bitset name="a6xx_cp_protect_status" inline="yes">
171
+
<bitfield name="ADDR" low="0" high="17"/>
172
+
<bitfield name="READ" pos="20" type="boolean"/>
173
+
<bitfield name="CP_HALTED" pos="21" type="boolean"/>
174
+
<bitfield name="ACCESS_VIOLATION" pos="22" type="boolean"/>
175
+
</bitset>
176
+
177
+
<reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status" variants="A6XX-A7XX"/>
178
+
<reg32 offset="0x084f" name="CP_PROTECT_STATUS_PIPE" type="a6xx_cp_protect_status" variants="A8XX-"/>
179
+
<reg32 offset="0x0825" name="CP_STATUS_1" variants="A6XX-A7XX"/>
180
+
181
+
<reg32 offset="0x0825" name="CP_SEMAPHORE_REG_0" variants="A8XX-"/>
182
+
<array offset="0x082a" name="CP_SCRATCH_GLOBAL" stride="1" length="4" variants="A8XX-">
183
+
<reg32 offset="0x0" name="REG"/>
184
+
</array>
185
+
<array offset="0x0830" name="CP_SCRATCH_PIPE" stride="1" length="5" variants="A8XX-">
186
+
<reg32 offset="0x0" name="REG"/>
187
+
</array>
188
+
189
+
<reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-"/>
190
+
<reg32 offset="0x0841" name="CP_RL_ERROR_DETAILS_1" variants="A8XX-"/>
191
+
192
+
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/>
193
+
<reg32 offset="0x0840" name="CP_MISC_CNTL" variants="A6XX-A7XX"/>
194
+
<reg32 offset="0x084c" name="CP_MISC_CNTL" variants="A8XX-"/>
195
+
196
+
<reg32 offset="0x08b0" name="CP_SQE_ICACHE_CNTL_PIPE" variants="A8XX-"/>
197
+
<reg32 offset="0x08b1" name="CP_SQE_DCACHE_CNTL_PIPE" variants="A8XX-"/>
198
+
<reg32 offset="0x08b3" name="CP_HW_FAULT_STATUS_PIPE" variants="A8XX-"/>
199
+
<reg32 offset="0x08b4" name="CP_HW_FAULT_STATUS_MASK_PIPE" variants="A8XX-"/>
200
+
<reg32 offset="0x08b5" name="CP_INTERRUPT_STATUS_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/>
201
+
<reg32 offset="0x08b6" name="CP_INTERRUPT_STATUS_MASK_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/>
202
+
<reg32 offset="0x08b7" name="CP_INTERRUPT_STATUS_PIPE" type="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/>
203
+
<reg32 offset="0x08b8" name="CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/>
204
+
<reg32 offset="0x08b9" name="CP_PIPE_STATUS_PIPE" variants="A8XX-"/>
205
+
<reg32 offset="0x08ba" name="CP_GPU_BATCH_ID_PIPE" variants="A8XX-"/>
206
+
<reg32 offset="0x08bb" name="CP_SQE_STATUS_PIPE" variants="A8XX-"/>
207
+
208
+
<bitset name="a6xx_cp_apriv_cntl" inline="yes">
105
209
<!-- Crashdumper writes -->
106
210
<bitfield pos="6" name="CDWRITE" type="boolean"/>
107
211
<!-- Crashdumper reads -->
108
212
<bitfield pos="5" name="CDREAD" type="boolean"/>
109
-
110
-
<!-- 4 is unknown -->
111
-
213
+
<!-- CP Scratch reg copy to mem -->
214
+
<bitfield pos="4" name="SCRATCHWT" type="boolean"/>
112
215
<!-- RPTR shadow writes -->
113
216
<bitfield pos="3" name="RBRPWB" type="boolean"/>
114
217
<!-- Memory accesses from PM4 packets in the ringbuffer -->
···
222
115
<bitfield pos="1" name="RBFETCH" type="boolean"/>
223
116
<!-- Instruction cache fetches -->
224
117
<bitfield pos="0" name="ICACHE" type="boolean"/>
225
-
</reg32>
118
+
</bitset>
119
+
120
+
<reg32 offset="0x0844" name="CP_APRIV_CNTL" type="a6xx_cp_apriv_cntl" variants="A6XX-A7XX"/>
121
+
<reg32 offset="0x084d" name="CP_APRIV_CNTL_PIPE" type="a6xx_cp_apriv_cntl" variants="A8XX-"/>
122
+
226
123
<!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
227
-
<reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
124
+
<reg32 offset="0x08c0" name="CP_PREEMPT_THRESHOLD" variants="A6XX-A7XX"/>
125
+
<reg32 offset="0x08ec" name="CP_PREEMPT_THRESHOLD" variants="A8XX-"/>
228
126
<!-- all the threshold values seem to be in units of quad-dwords: -->
229
-
<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
127
+
<reg32 offset="0x08c1" name="CP_ROQ_THRESHOLDS_1" variants="A6XX">
230
128
<doc>
231
129
b0..7 identifies where MRB data starts (and RB data ends)
232
130
b8.15 identifies where VSD data starts (and MRB data ends)
···
243
131
<bitfield name="IB1_START" low="16" high="23" shr="2"/>
244
132
<bitfield name="IB2_START" low="24" high="31" shr="2"/>
245
133
</reg32>
246
-
<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
134
+
<reg32 offset="0x08c2" name="CP_ROQ_THRESHOLDS_2" variants="A6XX">
247
135
<doc>
248
136
low bits identify where CP_SET_DRAW_STATE stateobj
249
137
processing starts (and IB2 data ends). I'm guessing
···
259
147
<!-- total ROQ size: -->
260
148
<bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
261
149
</reg32>
262
-
<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
263
-
<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
264
-
<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
265
-
<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
266
-
<reg32 offset="0x084F" name="CP_PROTECT_CNTL">
150
+
<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE" variants="A6XX"/>
151
+
<reg32 offset="0x0841" name="CP_CHICKEN_DBG" variants="A6XX-A7XX"/>
152
+
<reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/>
153
+
<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
154
+
<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/>
155
+
<reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/>
156
+
157
+
<bitset name="a6xx_cp_protect_cntl" inline="yes">
267
158
<bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
268
159
<bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
269
160
<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
270
-
</reg32>
161
+
</bitset>
271
162
272
-
<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
163
+
<reg32 offset="0x084f" name="CP_PROTECT_CNTL" type="a6xx_cp_protect_cntl" variants="A6XX-A7XX"/>
164
+
<bitset name="a8xx_cp_protect_cntl" inline="yes">
165
+
<bitfield name="HALT_SQE_RANGE" low="16" high="31"/>
166
+
<bitfield name="LAST_SPAN_INF_RANGE" pos="3" type="boolean"/>
167
+
<bitfield name="ACCESS_FAULT_ON_VIOL_EN" pos="1" type="boolean"/>
168
+
<bitfield name="ACCESS_PROT_EN" pos="0" type="boolean"/>
169
+
</bitset>
170
+
171
+
<reg32 offset="0x084e" name="CP_PROTECT_CNTL_PIPE" type="a8xx_cp_protect_cntl" variants="A8XX-"/>
172
+
173
+
<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8" variants="A6XX-A7XX">
273
174
<reg32 offset="0x0" name="REG" type="uint"/>
274
175
</array>
275
-
<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
176
+
<array offset="0x0850" name="CP_PROTECT" stride="1" length="32" variants="A6XX-A7XX">
177
+
<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
178
+
</array>
179
+
<array offset="0x0850" name="CP_PROTECT_GLOBAL" stride="1" length="64" variants="A8XX-">
180
+
<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
181
+
</array>
182
+
<array offset="0x08a0" name="CP_PROTECT_PIPE" stride="1" length="16" variants="A8XX-">
276
183
<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
277
184
</array>
278
185
279
-
<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL">
186
+
<bitset name="a6xx_cp_context_switch_cntl" inline="yes">
280
187
<bitfield name="STOP" pos="0" type="boolean"/>
281
188
<bitfield name="LEVEL" low="6" high="7"/>
282
189
<bitfield name="USES_GMEM" pos="8" type="boolean"/>
283
190
<bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/>
284
-
</reg32>
285
-
<reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
286
-
<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
287
-
<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
288
-
<reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
289
-
<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
290
-
<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
291
-
<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
292
-
<reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE"/>
293
-
<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
294
-
<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
295
-
<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
296
-
<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
297
-
<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
298
-
<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
299
-
<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
300
-
<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
301
-
<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
302
-
<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
303
-
<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
304
-
<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
305
-
<reg64 offset="0x0928" name="CP_IB1_BASE"/>
306
-
<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
307
-
<reg64 offset="0x092B" name="CP_IB2_BASE"/>
308
-
<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
191
+
</bitset>
192
+
193
+
<reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A6XX-A7XX"/>
194
+
<reg32 offset="0x08c0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A8XX-"/>
195
+
196
+
<reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A6XX-A7XX"/>
197
+
<reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/>
198
+
<reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/>
199
+
<reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A6XX-A7XX"/>
200
+
<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX"/>
201
+
202
+
<reg64 offset="0x08c1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A8XX-"/>
203
+
<reg64 offset="0x08c3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A8XX-"/>
204
+
<reg64 offset="0x08c5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A8XX-"/>
205
+
<reg64 offset="0x08c7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A8XX-"/>
206
+
<reg32 offset="0x08cb" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A8XX-"/>
207
+
208
+
<array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14" variants="A6XX-A7XX"/>
209
+
<array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="21" variants="A8XX-"/>
210
+
<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX"/>
211
+
<reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A6XX-A7XX"/>
212
+
<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL" variants="A6XX-A7XX"/>
213
+
<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS" variants="A6XX-A7XX"/>
214
+
<reg64 offset="0x0842" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A8XX-"/>
215
+
<reg32 offset="0x0844" name="CP_CRASH_DUMP_CNTL" variants="A8XX-"/>
216
+
<reg32 offset="0x0845" name="CP_CRASH_DUMP_STATUS" variants="A8XX-"/>
217
+
<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR" variants="A6XX-A7XX"/>
218
+
<reg32 offset="0x0909" name="CP_SQE_STAT_DATA" variants="A6XX-A7XX"/>
219
+
<reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR" variants="A6XX-A7XX"/>
220
+
<reg32 offset="0x090b" name="CP_DRAW_STATE_DATA" variants="A6XX-A7XX"/>
221
+
<reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR" variants="A6XX-A7XX"/>
222
+
<reg32 offset="0x090d" name="CP_ROQ_DBG_DATA" variants="A6XX-A7XX"/>
223
+
<reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR" variants="A6XX-A7XX"/>
224
+
<reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA" variants="A6XX-A7XX"/>
225
+
<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR" variants="A6XX-A7XX"/>
226
+
<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA" variants="A6XX-A7XX"/>
227
+
228
+
<reg32 offset="0x08f0" name="CP_SQE_STAT_ADDR_PIPE" variants="A8XX-"/>
229
+
<reg32 offset="0x08f1" name="CP_SQE_STAT_DATA_PIPE" variants="A8XX-"/>
230
+
<reg32 offset="0x08f2" name="CP_DRAW_STATE_ADDR_PIPE" variants="A8XX-"/>
231
+
<reg32 offset="0x08f3" name="CP_DRAW_STATE_DATA_PIPE" variants="A8XX-"/>
232
+
<reg32 offset="0x08f4" name="CP_ROQ_DBG_ADDR_PIPE" variants="A8XX-"/>
233
+
<reg32 offset="0x08f5" name="CP_ROQ_DBG_DATA_PIPE" variants="A8XX-"/>
234
+
<reg32 offset="0x08f6" name="CP_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/>
235
+
<reg32 offset="0x08f7" name="CP_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/>
236
+
<reg32 offset="0x08f8" name="CP_SQE_UCODE_DBG_ADDR_PIPE" variants="A8XX-"/>
237
+
<reg32 offset="0x08f9" name="CP_SQE_UCODE_DBG_DATA_PIPE" variants="A8XX-"/>
238
+
<reg32 offset="0x08fa" name="CP_RESOURCE_TABLE_DBG_ADDR_BV" variants="A8XX-"/>
239
+
<reg32 offset="0x08fb" name="CP_RESOURCE_TABLE_DBG_DATA_BV" variants="A8XX-"/>
240
+
<reg32 offset="0x08fc" name="CP_FIFO_DBG_ADDR_LPAC" variants="A8XX-"/>
241
+
<reg32 offset="0x08fd" name="CP_FIFO_DBG_DATA_LPAC" variants="A8XX-"/>
242
+
<reg32 offset="0x08fe" name="CP_FIFO_DBG_ADDR_DDE_PIPE" variants="A8XX-"/>
243
+
<reg32 offset="0x08ff" name="CP_FIFO_DBG_DATA_DDE_PIPE" variants="A8XX-"/>
244
+
245
+
<reg32 offset="0x0b00" name="CP_SLICE_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/>
246
+
<reg32 offset="0x0b01" name="CP_SLICE_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/>
247
+
<reg32 offset="0x0b93" name="CP_SLICE_CHICKEN_DBG_PIPE" variants="A8XX-"/>
248
+
249
+
<reg64 offset="0x0928" name="CP_IB1_BASE" variants="A6XX-A7XX"/>
250
+
<reg32 offset="0x092a" name="CP_IB1_REM_SIZE" variants="A6XX-A7XX"/>
251
+
<reg64 offset="0x092b" name="CP_IB2_BASE" variants="A6XX-A7XX"/>
252
+
<reg32 offset="0x092d" name="CP_IB2_REM_SIZE" variants="A6XX-A7XX"/>
309
253
<!-- SDS == CP_SET_DRAW_STATE: -->
310
-
<reg64 offset="0x092e" name="CP_SDS_BASE"/>
311
-
<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
254
+
<reg64 offset="0x092e" name="CP_SDS_BASE" variants="A6XX-A7XX"/>
255
+
<reg32 offset="0x0930" name="CP_SDS_REM_SIZE" variants="A6XX-A7XX"/>
312
256
<!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
313
-
<reg64 offset="0x0931" name="CP_MRB_BASE"/>
314
-
<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
257
+
<reg64 offset="0x0931" name="CP_MRB_BASE" variants="A6XX-A7XX"/>
258
+
<reg32 offset="0x0933" name="CP_MRB_REM_SIZE" variants="A6XX-A7XX"/>
315
259
<!--
316
260
VSD == Visibility Stream Decode
317
261
This is used by CP to read the draw stream and skip empty draws
318
262
-->
319
-
<reg64 offset="0x0934" name="CP_VSD_BASE"/>
263
+
<reg64 offset="0x0934" name="CP_VSD_BASE" variants="A6XX-A7XX"/>
264
+
265
+
<reg64 offset="0x0900" name="CP_IB1_BASE" variants="A8XX-"/>
266
+
<reg32 offset="0x0902" name="CP_IB1_REM_SIZE" variants="A8XX-"/>
267
+
<reg32 offset="0x0903" name="CP_IB1_INIT_SIZE" variants="A8XX-"/>
268
+
<reg64 offset="0x0904" name="CP_IB2_BASE" variants="A8XX-"/>
269
+
<reg32 offset="0x0906" name="CP_IB2_REM_SIZE" variants="A8XX-"/>
270
+
<reg32 offset="0x0907" name="CP_IB2_INIT_SIZE" variants="A8XX-"/>
271
+
<reg64 offset="0x0908" name="CP_IB3_BASE" variants="A8XX-"/>
272
+
<reg32 offset="0x090a" name="CP_IB3_REM_SIZE" variants="A8XX-"/>
273
+
<reg32 offset="0x090b" name="CP_IB3_INIT_SIZE" variants="A8XX-"/>
274
+
<reg64 offset="0x090c" name="CP_SDS_BASE" variants="A8XX-"/>
275
+
<reg32 offset="0x090e" name="CP_SDS_REM_SIZE" variants="A8XX-"/>
276
+
<reg32 offset="0x090f" name="CP_SDS_INIT_SIZE" variants="A8XX-"/>
277
+
<reg64 offset="0x0910" name="CP_MRB_BASE" variants="A8XX-"/>
278
+
<reg32 offset="0x0912" name="CP_MRB_REM_SIZE" variants="A8XX-"/>
279
+
<reg32 offset="0x0913" name="CP_MRB_INIT_SIZE" variants="A8XX-"/>
280
+
<reg64 offset="0x0914" name="CP_VSD_BASE" variants="A8XX-"/>
281
+
<reg32 offset="0x0916" name="CP_VSD_REM_SIZE" variants="A8XX-"/>
282
+
<reg32 offset="0x0917" name="CP_VSD_INIT_SIZE" variants="A8XX-"/>
320
283
321
284
<bitset name="a6xx_roq_status" inline="yes">
322
285
<bitfield name="RPTR" low="0" high="9"/>
323
286
<bitfield name="WPTR" low="16" high="25"/>
324
287
</bitset>
325
-
<reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status"/>
326
-
<reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status"/>
327
-
<reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status"/>
328
-
<reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status"/>
329
-
<reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status"/>
330
-
<reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status"/>
288
+
<reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/>
289
+
<reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/>
290
+
<reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/>
291
+
<reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/>
292
+
<reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/>
293
+
<reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/>
331
294
332
-
<reg32 offset="0x0943" name="CP_IB1_INIT_SIZE"/>
333
-
<reg32 offset="0x0944" name="CP_IB2_INIT_SIZE"/>
334
-
<reg32 offset="0x0945" name="CP_SDS_INIT_SIZE"/>
335
-
<reg32 offset="0x0946" name="CP_MRB_INIT_SIZE"/>
336
-
<reg32 offset="0x0947" name="CP_VSD_INIT_SIZE"/>
295
+
<reg32 offset="0x0920" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
296
+
<reg32 offset="0x0921" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
297
+
<reg32 offset="0x0922" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
298
+
<reg32 offset="0x0923" name="CP_ROQ_IB3_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
299
+
<reg32 offset="0x0924" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
300
+
<reg32 offset="0x0925" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
301
+
<reg32 offset="0x0926" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A8XX-"/>
337
302
338
-
<reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">
303
+
<reg32 offset="0x0943" name="CP_IB1_INIT_SIZE" variants="A6XX-A7XX"/>
304
+
<reg32 offset="0x0944" name="CP_IB2_INIT_SIZE" variants="A6XX-A7XX"/>
305
+
<reg32 offset="0x0945" name="CP_SDS_INIT_SIZE" variants="A6XX-A7XX"/>
306
+
<reg32 offset="0x0946" name="CP_MRB_INIT_SIZE" variants="A6XX-A7XX"/>
307
+
<reg32 offset="0x0947" name="CP_VSD_INIT_SIZE" variants="A6XX-A7XX"/>
308
+
309
+
<bitset name="a6xx_cp_roq_avail" inline="yes">
339
310
<doc>number of remaining dwords incl current dword being consumed?</doc>
340
311
<bitfield name="REM" low="16" high="31"/>
341
-
</reg32>
342
-
<reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">
343
-
<doc>number of remaining dwords incl current dword being consumed?</doc>
344
-
<bitfield name="REM" low="16" high="31"/>
345
-
</reg32>
346
-
<reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">
347
-
<doc>number of remaining dwords incl current dword being consumed?</doc>
348
-
<bitfield name="REM" low="16" high="31"/>
349
-
</reg32>
350
-
<reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">
351
-
<doc>number of remaining dwords incl current dword being consumed?</doc>
352
-
<bitfield name="REM" low="16" high="31"/>
353
-
</reg32>
354
-
<reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">
355
-
<doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
356
-
<bitfield name="REM" low="16" high="31"/>
357
-
</reg32>
358
-
<reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">
359
-
<doc>number of remaining dwords incl current dword being consumed?</doc>
360
-
<bitfield name="REM" low="16" high="31"/>
361
-
</reg32>
312
+
</bitset>
313
+
314
+
<reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/>
315
+
<reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/>
316
+
<reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/>
317
+
<reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/>
318
+
<reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/>
319
+
<reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/>
320
+
321
+
<reg32 offset="0x0918" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A8XX-"/>
322
+
<reg32 offset="0x0919" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A8XX-"/>
323
+
<reg32 offset="0x091a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A8XX-"/>
324
+
<reg32 offset="0x091b" name="CP_ROQ_AVAIL_IB3" type="a6xx_cp_roq_avail" variants="A8XX-"/>
325
+
<reg32 offset="0x091c" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A8XX-"/>
326
+
<reg32 offset="0x091d" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A8XX-"/>
327
+
<reg32 offset="0x091e" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A8XX-"/>
362
328
363
329
<bitset name="a7xx_aperture_cntl" inline="yes">
364
-
<bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
330
+
<bitfield name="PIPE" low="12" high="13" type="adreno_pipe"/>
365
331
<bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
366
332
<bitfield name="CONTEXT" low="4" high="5"/>
367
333
</bitset>
368
-
<reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
369
-
<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
334
+
<reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER" variants="A6XX-A7XX"/>
335
+
<reg64 offset="0x0982" name="CP_ALWAYS_ON_CONTEXT" variants="A6XX-A7XX"/>
336
+
<reg64 offset="0x08e7" name="CP_ALWAYS_ON_COUNTER" variants="A8XX-"/>
337
+
<reg64 offset="0x08e9" name="CP_ALWAYS_ON_CONTEXT" variants="A8XX-"/>
338
+
<reg32 offset="0x098d" name="CP_AHB_CNTL" variants="A6XX-A7XX"/>
339
+
<reg32 offset="0x0838" name="CP_AHB_CNTL" variants="A8XX-"/>
370
340
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
371
-
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
341
+
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX"/>
372
342
<reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/>
373
343
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>
374
-
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
344
+
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX"/>
375
345
376
-
<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
377
-
<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
378
-
<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
379
-
<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
380
-
<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
381
-
<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
382
-
<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
383
-
<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
384
-
<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
385
-
<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
386
-
<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
387
-
<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
388
-
<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
346
+
<array offset="0x0a9c" name="CP_RESERVED_REG" stride="1" length="4" variants="A7XX"/>
347
+
<array offset="0x0958" name="CP_RESERVED_REG" stride="1" length="4" variants="A8XX-"/>
389
348
390
-
<reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX-"/>
391
-
<reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX-"/>
392
-
<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
393
-
<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
349
+
<bitset name="a8xx_aperture_cntl" inline="yes">
350
+
<bitfield name="CONTEXTID3D" low="4" high="5"/>
351
+
<bitfield name="CLUSTERID" low="8" high="11"/>
352
+
<bitfield name="PIPEID" low="12" high="15"/>
353
+
<bitfield name="SLICEID" low="16" high="18"/>
354
+
<bitfield name="USESLICEID" pos="23" type="boolean"/>
355
+
</bitset>
394
356
395
-
<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
396
-
<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
397
-
<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
398
-
<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
399
-
<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
400
-
<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
401
-
<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
357
+
<reg32 offset="0x081c" name="CP_APERTURE_CNTL_HOST" type="a8xx_aperture_cntl" variants="A8XX-"/>
358
+
<reg32 offset="0x081d" name="CP_APERTURE_CNTL_GMU" type="a8xx_aperture_cntl" variants="A8XX-"/>
359
+
<reg32 offset="0x081e" name="CP_APERTURE_CNTL_CD" type="a8xx_aperture_cntl" variants="A8XX-"/>
402
360
403
-
<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
404
-
<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
405
-
<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
406
-
<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
407
-
<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
408
-
<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
409
-
<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
361
+
<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX"/>
362
+
<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX"/>
363
+
<reg32 offset="0x0a66" name="CP_BV_RB_RPTR" variants="A7XX"/>
364
+
<reg64 offset="0x0a6d" name="CP_BV_IB1_BASE" variants="A7XX"/>
365
+
<reg32 offset="0x0a70" name="CP_BV_IB1_REM_SIZE" variants="A7XX"/>
366
+
<reg64 offset="0x0a71" name="CP_BV_IB2_BASE" variants="A7XX"/>
367
+
<reg32 offset="0x0a74" name="CP_BV_IB2_REM_SIZE" variants="A7XX"/>
368
+
<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX"/>
369
+
<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX"/>
370
+
<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX"/>
371
+
<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX"/>
372
+
<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX"/>
373
+
<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX"/>
374
+
<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX"/>
375
+
<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX"/>
410
376
411
-
<reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
412
-
<reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
413
-
<reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>
377
+
<reg32 offset="0x0a8f" name="CP_BV_ROQ_AVAIL_RB" variants="A7XX">
378
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
379
+
<bitfield name="REM" low="16" high="31"/>
380
+
</reg32>
381
+
<reg32 offset="0x0a90" name="CP_BV_ROQ_AVAIL_IB1" variants="A7XX">
382
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
383
+
<bitfield name="REM" low="16" high="31"/>
384
+
</reg32>
385
+
<reg32 offset="0x0a91" name="CP_BV_ROQ_AVAIL_IB2" variants="A7XX">
386
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
387
+
<bitfield name="REM" low="16" high="31"/>
388
+
</reg32>
414
389
415
-
<reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
416
-
<reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
417
-
<reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
418
-
<reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
419
-
<reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
420
-
<reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
421
-
<reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
422
-
<reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
423
-
<reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
424
-
<reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
425
-
<reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
426
-
<reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>
390
+
<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX"/>
391
+
<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX"/>
392
+
<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX"/>
427
393
428
-
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
429
-
<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
430
-
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
431
-
<reg32 offset="0x0210" name="RBBM_STATUS">
394
+
<reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX"/>
395
+
<reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX"/>
396
+
<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX"/>
397
+
<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX"/>
398
+
399
+
<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX"/>
400
+
<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX"/>
401
+
<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX"/>
402
+
<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX"/>
403
+
<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX"/>
404
+
<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX"/>
405
+
<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX"/>
406
+
407
+
<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX"/>
408
+
<reg32 offset="0x0b34" name="CP_LPAC_PROG_FIFO_SIZE" variants="A7XX"/>
409
+
<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX"/>
410
+
<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX"/>
411
+
<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX"/>
412
+
<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL" variants="A6XX-A7XX"/>
413
+
<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE" variants="A6XX-A7XX"/>
414
+
415
+
<reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX"/>
416
+
<reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX"/>
417
+
<reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX"/>
418
+
419
+
<reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX"/>
420
+
<reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX"/>
421
+
<reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX"/>
422
+
<reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX"/>
423
+
<reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX"/>
424
+
<reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX"/>
425
+
<reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX"/>
426
+
<reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX"/>
427
+
<reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX"/>
428
+
<reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX"/>
429
+
<reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX"/>
430
+
<reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX"/>
431
+
432
+
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
433
+
<reg32 offset="0x0018" name="RBBM_GPR0_CNTL" variants="A6XX"/>
434
+
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/>
435
+
<reg32 offset="0x006a" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/>
436
+
<reg32 offset="0x0210" name="RBBM_STATUS" variants="A6XX-A7XX">
432
437
<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
433
438
<bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
434
439
<bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
···
571
342
<bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
572
343
<bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
573
344
</reg32>
574
-
<reg32 offset="0x0211" name="RBBM_STATUS1"/>
575
-
<reg32 offset="0x0212" name="RBBM_STATUS2"/>
576
-
<reg32 offset="0x0213" name="RBBM_STATUS3">
345
+
<reg32 offset="0x0211" name="RBBM_STATUS1" variants="A6XX-A7XX"/>
346
+
<reg32 offset="0x0212" name="RBBM_STATUS2" variants="A6XX-A7XX"/>
347
+
<reg32 offset="0x0213" name="RBBM_STATUS3" variants="A6XX-A7XX">
577
348
<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
578
349
</reg32>
579
-
<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
580
350
581
-
<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
582
-
<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
583
-
<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
584
-
<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
585
-
<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
586
-
<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
351
+
<reg32 offset="0x012" name="RBBM_STATUS" variants="A8XX-">
352
+
<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
353
+
<bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
354
+
<bitfield pos="21" name="SLICE_BUSY_IGN_CP" type="boolean"/>
355
+
<bitfield pos="20" name="CP_SLICE_BUSY" type="boolean"/>
356
+
<bitfield pos="19" name="UNSLICE_BUSY_IGN_AHB" type="boolean"/>
357
+
<bitfield pos="18" name="UNSLICE_BUSY_IGN_AHB_CP" type="boolean"/>
358
+
<bitfield pos="17" name="CP_SLICE_RL_BUSY" type="boolean"/>
359
+
<bitfield pos="14" name="UNSLICE_TOP_BUSY" type="boolean"/>
360
+
<bitfield pos="13" name="UFC_BUSY" type="boolean"/>
361
+
<bitfield pos="12" name="HLSQ_BUSY" type="boolean"/>
362
+
<bitfield pos="11" name="VSC_BUSY" type="boolean"/>
363
+
<bitfield pos="10" name="UCHE_BUSY" type="boolean"/>
364
+
<bitfield pos="9" name="VPC_BUSY" type="boolean"/>
365
+
<bitfield pos="8" name="PC_BUSY" type="boolean"/>
366
+
<bitfield pos="7" name="CMP_BUSY" type="boolean"/>
367
+
<bitfield pos="6" name="DCMP_BUSY" type="boolean"/>
368
+
<bitfield pos="5" name="VBIF_GX_BUSY" type="boolean"/>
369
+
<bitfield pos="4" name="DBGC_PERF_BUSY" type="boolean"/>
370
+
<bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
371
+
<bitfield pos="2" name="CP_BUSY" type="boolean"/>
372
+
<bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
373
+
<bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
374
+
</reg32>
375
+
<reg32 offset="0x013" name="RBBM_STATUS1" variants="A8XX-"/>
376
+
<reg32 offset="0x015" name="RBBM_GFX_STATUS" variants="A8XX-"/>
377
+
<reg32 offset="0x016" name="RBBM_GFX_STATUS1" variants="A8XX-"/>
378
+
<reg32 offset="0x018" name="RBBM_LPAC_STATUS" variants="A8XX-"/>
379
+
<reg32 offset="0x01a" name="RBBM_GFX_BR_STATUS" variants="A8XX-"/>
380
+
<reg32 offset="0x01c" name="RBBM_GFX_BV_STATUS" variants="A8XX-"/>
381
+
<reg32 offset="0x01e" name="RBBM_MISC_STATUS" variants="A8XX-">
382
+
<bitfield pos="0" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
383
+
</reg32>
587
384
588
-
<reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
589
-
<reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
385
+
<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS" variants="A6XX"/>
386
+
387
+
<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX"/>
388
+
<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX"/>
389
+
<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX"/>
390
+
<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX"/>
391
+
<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX"/>
392
+
<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX"/>
393
+
394
+
<reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX"/>
395
+
<reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX"/>
396
+
<reg32 offset="0x0071" name="RBBM_SW_FUSE_INT_STATUS" variants="A8XX-"/>
397
+
<reg32 offset="0x0072" name="RBBM_SW_FUSE_INT_MASK" variants="A8XX-"/>
590
398
591
399
<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
592
400
<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
···
642
376
<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
643
377
<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>
644
378
645
-
<array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
646
-
<array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
647
-
<array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
648
-
<array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
649
-
<array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
650
-
<array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
651
-
<array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
652
-
<array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
653
-
<array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
654
-
<array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
655
-
<array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
656
-
<array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
657
-
<array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
658
-
<array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
659
-
<array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
660
-
<array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
661
-
<array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
662
-
<array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
663
-
<array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
664
-
<array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
665
-
<array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
666
-
<array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
667
-
<array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
668
-
<array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
669
-
<array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
670
-
<array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
671
-
<array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
672
-
<array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
379
+
<array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX"/>
380
+
<array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX"/>
381
+
<array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX"/>
382
+
<array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX"/>
383
+
<array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX"/>
384
+
<array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX"/>
385
+
<array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX"/>
386
+
<array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX"/>
387
+
<array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX"/>
388
+
<array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX"/>
389
+
<array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX"/>
390
+
<array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX"/>
391
+
<array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX"/>
392
+
<array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX"/>
393
+
<array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX"/>
394
+
<array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX"/>
395
+
<array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX"/>
396
+
<array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX"/>
397
+
<array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX"/>
398
+
<array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX"/>
399
+
<array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX"/>
400
+
<array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX"/>
401
+
<array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX"/>
402
+
<array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX"/>
403
+
<array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX"/>
404
+
<array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX"/>
405
+
<array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX"/>
406
+
<array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX"/>
673
407
674
-
<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
675
-
<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
676
-
<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
677
-
<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
678
-
<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
679
-
<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
680
-
<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
681
-
<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
682
-
<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
683
-
<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
684
-
<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
685
-
<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
686
-
<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/>
687
-
<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
408
+
<array offset="0x01b0" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A8XX"/>
409
+
<array offset="0x01cc" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A8XX"/>
410
+
<array offset="0x01d4" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A8XX"/>
411
+
<array offset="0x01e4" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A8XX"/>
412
+
<array offset="0x01f4" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A8XX"/>
413
+
<array offset="0x0200" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A8XX"/>
414
+
<array offset="0x020c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A8XX"/>
415
+
<array offset="0x0216" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A8XX"/>
416
+
<array offset="0x021e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A8XX"/>
417
+
<array offset="0x0226" name="RBBM_PERFCTR_UCHE" stride="2" length="24" variants="A8XX"/>
418
+
<array offset="0x0256" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A8XX"/>
419
+
<array offset="0x026e" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A8XX"/>
420
+
<array offset="0x029e" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A8XX"/>
421
+
<array offset="0x02ae" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A8XX"/>
422
+
<array offset="0x02b2" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A8XX"/>
423
+
<array offset="0x02ba" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A8XX"/>
424
+
<array offset="0x02c2" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A8XX"/>
425
+
<array offset="0x02e2" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A8XX"/>
426
+
<array offset="0x02ee" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A8XX"/>
427
+
<array offset="0x02fc" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A8XX"/>
428
+
<array offset="0x0314" name="RBBM_PERFCTR2_TP" stride="2" length="8" variants="A8XX"/>
429
+
<array offset="0x0324" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A8XX"/>
430
+
<array offset="0x0328" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A8XX"/>
431
+
<array offset="0x0338" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A8XX"/>
432
+
<array offset="0x0348" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A8XX"/>
433
+
<array offset="0x0354" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A8XX"/>
434
+
<array offset="0x035c" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A8XX"/>
435
+
<array offset="0x0364" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A8XX"/>
436
+
<array offset="0x036c" name="RBBM_PERFCTR_BV_CCU" stride="2" length="3" variants="A8XX"/>
437
+
<array offset="0x0372" name="RBBM_PERFCTR_BV_RB" stride="2" length="6" variants="A8XX"/>
438
+
439
+
<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL" variants="A6XX-A7XX"/>
440
+
<reg32 offset="0x0460" name="RBBM_PERFCTR_CNTL" variants="A8XX-"/>
441
+
<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0" variants="A6XX"/>
442
+
<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1" variants="A6XX"/>
443
+
<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2" variants="A6XX"/>
444
+
<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3" variants="A6XX"/>
445
+
<reg64 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE" variants="A6XX"/>
446
+
<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A6XX-A7XX"/>
447
+
<array offset="0x0441" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/>
448
+
<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A6XX-A7XX"/>
449
+
<reg32 offset="0x019e" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A8XX-"/>
450
+
<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A6XX-A7XX"/>
451
+
<reg32 offset="0x0449" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/>
452
+
<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A6XX-A7XX"/>
453
+
<reg32 offset="0x019f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A8XX-"/>
454
+
<reg32 offset="0x01a1" name="RBBM_PERFCTR_FLUSH_HOST_STATUS" variants="A8XX-"/>
455
+
<reg32 offset="0x044c" name="RBBM_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/>
456
+
<reg32 offset="0x0533" name="RBBM_ISDB_CNT" variants="A6XX-A7XX"/>
457
+
<reg32 offset="0x002d" name="RBBM_ISDB_CNT" variants="A8XX-"/>
458
+
<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A6XX-A7XX"/>
459
+
<reg32 offset="0x0440" name="RBBM_NC_MODE_CNTL" variants="A8XX-"/>
460
+
<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX"/>
461
+
<reg32 offset="0x002e" name="RBBM_SNAPSHOT_STATUS" variants="A8XX-"/>
462
+
463
+
<reg32 offset="0x500" name="RBBM_SLICE_PERFCTR_CNTL" variants="A8XX-"/>
464
+
<reg32 offset="0x58f" name="RBBM_SLICE_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/>
465
+
<array offset="0x5e0" name="RBBM_SLICE_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/>
466
+
<reg32 offset="0x5e8" name="RBBM_SLICE_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/>
467
+
<reg32 offset="0x5eb" name="RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/>
468
+
<reg32 offset="0x5ec" name="RBBM_SLICE_NC_MODE_CNTL" variants="A8XX-"/>
688
469
689
470
<!---
690
471
This block of registers aren't tied to perf counters. They
···
739
426
vertices in, number of primnitives assembled etc.
740
427
-->
741
428
742
-
<reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES"/>
743
-
<reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES"/>
744
-
<reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS"/>
745
-
<reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS"/>
746
-
<reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS"/>
747
-
<reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS"/>
748
-
<reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES"/>
749
-
<reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS"/>
750
-
<reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES"/>
751
-
<reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS"/>
752
-
<reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS"/>
429
+
<reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES" variants="A6XX-A7XX"/>
430
+
<reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A6XX-A7XX"/>
431
+
<reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A6XX-A7XX"/>
432
+
<reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A6XX-A7XX"/>
433
+
<reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A6XX-A7XX"/>
434
+
<reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A6XX-A7XX"/>
435
+
<reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A6XX-A7XX"/>
436
+
<reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A6XX-A7XX"/>
437
+
<reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A6XX-A7XX"/>
438
+
<reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A6XX-A7XX"/>
439
+
<reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A6XX-A7XX"/>
440
+
441
+
<reg64 offset="0x0380" name="RBBM_PIPESTAT_IAVERTICES" variants="A8XX-"/>
442
+
<reg64 offset="0x0382" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A8XX-"/>
443
+
<reg64 offset="0x0384" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A8XX-"/>
444
+
<reg64 offset="0x0386" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A8XX-"/>
445
+
<reg64 offset="0x0388" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A8XX-"/>
446
+
<reg64 offset="0x038a" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A8XX-"/>
447
+
<reg64 offset="0x038c" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A8XX-"/>
448
+
<reg64 offset="0x038e" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A8XX-"/>
449
+
<reg64 offset="0x0390" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A8XX-"/>
450
+
<reg64 offset="0x0392" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A8XX-"/>
451
+
<reg64 offset="0x0394" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A8XX-"/>
452
+
<reg64 offset="0x0396" name="RBBM_PIPESTAT_ASINVOCATIONS" variants="A8XX-"/>
453
+
<reg64 offset="0x0398" name="RBBM_PIPESTAT_MSINVOCATIONS" variants="A8XX-"/>
454
+
<reg64 offset="0x039a" name="RBBM_PIPESTAT_MSPRIMITIVES" variants="A8XX-"/>
753
455
754
456
<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
755
457
<reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
756
458
<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
757
459
<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
758
-
<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
460
+
<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
759
461
<reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
760
-
<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
761
-
<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
762
-
<reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
763
-
<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
764
-
<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
462
+
<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL" variants="A6XX"/>
463
+
<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/>
464
+
<reg32 offset="0x00008" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/>
465
+
<reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A6XX-A7XX"/>
466
+
<reg32 offset="0x0000a" name="RBBM_GBIF_HALT" variants="A8XX-"/>
467
+
<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A6XX-A7XX"/>
468
+
<reg32 offset="0x0000b" name="RBBM_GBIF_HALT_ACK" variants="A8XX-"/>
469
+
<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD" variants="A6XX">
765
470
<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
766
471
</reg32>
767
472
768
-
<reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
769
-
<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
770
-
<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
771
-
<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
772
-
<reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
773
-
<reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
774
-
<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
775
-
<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
776
-
<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
777
-
<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
778
-
<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
779
-
<reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
780
-
<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
781
-
<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
782
-
<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
783
-
<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
784
-
<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
785
-
<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
786
-
<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
787
-
<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
788
-
<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
789
-
<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
790
-
<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
791
-
<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
792
-
<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
793
-
<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
794
-
<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
795
-
<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
796
-
<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
797
-
<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
798
-
<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
799
-
<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
800
-
<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
801
-
<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
802
-
<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
803
-
<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
804
-
<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
805
-
<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
806
-
<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
807
-
<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
808
-
<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
809
-
<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
810
-
<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
811
-
<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
812
-
<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
813
-
<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
814
-
<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
815
-
<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
816
-
<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
817
-
<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
818
-
<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
819
-
<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
820
-
<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
821
-
<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
822
-
<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
823
-
<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
824
-
<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
825
-
<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
826
-
<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
827
-
<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
828
-
<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
829
-
<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
830
-
<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
831
-
<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
832
-
<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
833
-
<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
834
-
<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
835
-
<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
836
-
<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
837
-
<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
838
-
<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
839
-
<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
840
-
<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
841
-
<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
842
-
<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
843
-
<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
844
-
<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
845
-
<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
846
-
<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
847
-
<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
848
-
<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
849
-
<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
850
-
<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
851
-
<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
852
-
<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
853
-
<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
854
-
<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
855
-
<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
856
-
<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
857
-
<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
858
-
<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
859
-
<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
860
-
<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
861
-
<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
862
-
<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
863
-
<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
864
-
<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
865
-
<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
866
-
<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
867
-
<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
868
-
<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
869
-
<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
870
-
<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
871
-
<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
872
-
<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
873
-
<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
874
-
<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
875
-
<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
876
-
<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
877
-
<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
878
-
<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
879
-
<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
880
-
<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
881
-
<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
882
-
<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
883
-
<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
884
-
<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
885
-
<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
886
-
<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
887
-
<reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
888
-
<reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
889
-
<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
890
-
<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
473
+
<reg32 offset="0x01a" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A6XX-A7XX"/>
474
+
<reg32 offset="0x01b" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A6XX-A7XX"/>
475
+
<reg32 offset="0x010" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/>
476
+
<reg32 offset="0x011" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A8XX-"/>
477
+
478
+
<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A6XX-A7XX"/>
479
+
<reg32 offset="0x0002f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/>
480
+
<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/>
481
+
<reg32 offset="0x00061" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/>
482
+
<reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/>
483
+
<reg32 offset="0x00062" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/>
484
+
<reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX"/>
485
+
<reg32 offset="0x00064" name="RBBM_INT_2_MASK" variants="A8XX-"/>
486
+
<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT" variants="A6XX-A7XX"/>
487
+
<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD" variants="A6XX-A7XX"/>
488
+
<reg32 offset="0x00073" name="RBBM_SW_RESET_CMD" variants="A8XX-"/>
489
+
<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT" variants="A6XX-A7XX"/>
490
+
<reg32 offset="0x00029" name="RBBM_RAC_THRESHOLD_CNT" variants="A8XX-"/>
491
+
<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD" variants="A6XX"/>
492
+
<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2" variants="A6XX"/>
493
+
<reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX"/>
494
+
<reg32 offset="0x0009a" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A8XX-"/>
495
+
<reg32 offset="0x07d" name="RBBM_POWER_UP_RESET_SW_OVERRIDE" variants="A8XX-"/>
496
+
<reg32 offset="0x07e" name="RBBM_POWER_UP_RESET_SW_BV_OVERRIDE" variants="A8XX-"/>
497
+
<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL" variants="A6XX-A7XX"/>
498
+
<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0" variants="A6XX-A7XX"/>
499
+
<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1" variants="A6XX-A7XX"/>
500
+
<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2" variants="A6XX-A7XX"/>
501
+
<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3" variants="A6XX-A7XX"/>
502
+
<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0" variants="A6XX-A7XX"/>
503
+
<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1" variants="A6XX-A7XX"/>
504
+
<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2" variants="A6XX-A7XX"/>
505
+
<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3" variants="A6XX-A7XX"/>
506
+
<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0" variants="A6XX-A7XX"/>
507
+
<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1" variants="A6XX-A7XX"/>
508
+
<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2" variants="A6XX-A7XX"/>
509
+
<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3" variants="A6XX-A7XX"/>
510
+
<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0" variants="A6XX-A7XX"/>
511
+
<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1" variants="A6XX-A7XX"/>
512
+
<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2" variants="A6XX-A7XX"/>
513
+
<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3" variants="A6XX-A7XX"/>
514
+
<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0" variants="A6XX-A7XX"/>
515
+
<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1" variants="A6XX-A7XX"/>
516
+
<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2" variants="A6XX-A7XX"/>
517
+
<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3" variants="A6XX-A7XX"/>
518
+
<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0" variants="A6XX-A7XX"/>
519
+
<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1" variants="A6XX-A7XX"/>
520
+
<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2" variants="A6XX-A7XX"/>
521
+
<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3" variants="A6XX-A7XX"/>
522
+
<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0" variants="A6XX-A7XX"/>
523
+
<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1" variants="A6XX-A7XX"/>
524
+
<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2" variants="A6XX-A7XX"/>
525
+
<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3" variants="A6XX-A7XX"/>
526
+
<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0" variants="A6XX-A7XX"/>
527
+
<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1" variants="A6XX-A7XX"/>
528
+
<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2" variants="A6XX-A7XX"/>
529
+
<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3" variants="A6XX-A7XX"/>
530
+
<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0" variants="A6XX-A7XX"/>
531
+
<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1" variants="A6XX-A7XX"/>
532
+
<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2" variants="A6XX-A7XX"/>
533
+
<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3" variants="A6XX-A7XX"/>
534
+
<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0" variants="A6XX-A7XX"/>
535
+
<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1" variants="A6XX-A7XX"/>
536
+
<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2" variants="A6XX-A7XX"/>
537
+
<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3" variants="A6XX-A7XX"/>
538
+
<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0" variants="A6XX-A7XX"/>
539
+
<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1" variants="A6XX-A7XX"/>
540
+
<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2" variants="A6XX-A7XX"/>
541
+
<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3" variants="A6XX-A7XX"/>
542
+
<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0" variants="A6XX-A7XX"/>
543
+
<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1" variants="A6XX-A7XX"/>
544
+
<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2" variants="A6XX-A7XX"/>
545
+
<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3" variants="A6XX-A7XX"/>
546
+
<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0" variants="A6XX-A7XX"/>
547
+
<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1" variants="A6XX-A7XX"/>
548
+
<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2" variants="A6XX-A7XX"/>
549
+
<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3" variants="A6XX-A7XX"/>
550
+
<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0" variants="A6XX-A7XX"/>
551
+
<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1" variants="A6XX-A7XX"/>
552
+
<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2" variants="A6XX-A7XX"/>
553
+
<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3" variants="A6XX-A7XX"/>
554
+
<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0" variants="A6XX-A7XX"/>
555
+
<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1" variants="A6XX-A7XX"/>
556
+
<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2" variants="A6XX-A7XX"/>
557
+
<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3" variants="A6XX-A7XX"/>
558
+
<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0" variants="A6XX-A7XX"/>
559
+
<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1" variants="A6XX-A7XX"/>
560
+
<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2" variants="A6XX-A7XX"/>
561
+
<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3" variants="A6XX-A7XX"/>
562
+
<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0" variants="A6XX-A7XX"/>
563
+
<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1" variants="A6XX-A7XX"/>
564
+
<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2" variants="A6XX-A7XX"/>
565
+
<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3" variants="A6XX-A7XX"/>
566
+
<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0" variants="A6XX-A7XX"/>
567
+
<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1" variants="A6XX-A7XX"/>
568
+
<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2" variants="A6XX-A7XX"/>
569
+
<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3" variants="A6XX-A7XX"/>
570
+
<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0" variants="A6XX-A7XX"/>
571
+
<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1" variants="A6XX-A7XX"/>
572
+
<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2" variants="A6XX-A7XX"/>
573
+
<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3" variants="A6XX-A7XX"/>
574
+
<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0" variants="A6XX-A7XX"/>
575
+
<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1" variants="A6XX-A7XX"/>
576
+
<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2" variants="A6XX-A7XX"/>
577
+
<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3" variants="A6XX-A7XX"/>
578
+
<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC" variants="A6XX-A7XX"/>
579
+
<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC" variants="A6XX-A7XX"/>
580
+
<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC" variants="A6XX-A7XX"/>
581
+
<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC" variants="A6XX-A7XX"/>
582
+
<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM" variants="A6XX-A7XX"/>
583
+
<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM" variants="A6XX-A7XX"/>
584
+
<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM" variants="A6XX-A7XX"/>
585
+
<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE" variants="A6XX-A7XX"/>
586
+
<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE" variants="A6XX-A7XX"/>
587
+
<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE" variants="A6XX-A7XX"/>
588
+
<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE" variants="A6XX-A7XX"/>
589
+
<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE" variants="A6XX-A7XX"/>
590
+
<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE" variants="A6XX-A7XX"/>
591
+
<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD" variants="A6XX-A7XX"/>
592
+
<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD" variants="A6XX-A7XX"/>
593
+
<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD" variants="A6XX-A7XX"/>
594
+
<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC" variants="A6XX-A7XX"/>
595
+
<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC" variants="A6XX-A7XX"/>
596
+
<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC" variants="A6XX-A7XX"/>
597
+
<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2" variants="A6XX-A7XX"/>
598
+
<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX" variants="A6XX-A7XX"/>
599
+
<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX" variants="A6XX-A7XX"/>
600
+
<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX" variants="A6XX-A7XX"/>
601
+
<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ" variants="A6XX-A7XX"/>
602
+
<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ" variants="A6XX-A7XX"/>
603
+
<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ" variants="A6XX-A7XX"/>
604
+
<reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX"/>
605
+
<reg32 offset="0x0009b" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A8XX-"/>
606
+
<reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX"/>
607
+
<reg32 offset="0x0009c" name="RBBM_CGC_P2S_TRIG_CMD" variants="A8XX-"/>
608
+
<reg32 offset="0x00120" name="RBBM_CGC_P2S_CNTL" variants="A7XX"/>
609
+
<reg32 offset="0x0009d" name="RBBM_CGC_P2S_CNTL" variants="A8XX-"/>
610
+
<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE" variants="A6XX"/>
611
+
<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE" variants="A6XX-A7XX"/>
891
612
<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/>
892
-
<reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
613
+
<reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX">
893
614
<bitfield name="TXDONE" pos="0" type="boolean"/>
894
615
</reg32>
895
-
<reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>
896
-
<reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>
897
-
<reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>
898
-
<reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>
899
-
<reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>
900
-
<reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>
901
-
<reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>
902
-
<reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>
903
-
<reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>
904
-
<reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
905
-
<reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>
616
+
<reg32 offset="0x09f" name="RBBM_CGC_P2S_STATUS" variants="A8XX-">
617
+
<bitfield name="TXDONE" pos="0" type="boolean"/>
618
+
</reg32>
619
+
<reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE" variants="A6XX-A7XX"/>
620
+
<reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE" variants="A6XX-A7XX"/>
621
+
<reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE" variants="A6XX-A7XX"/>
622
+
<reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB" variants="A6XX-A7XX"/>
623
+
<reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB" variants="A6XX-A7XX"/>
624
+
<reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB" variants="A6XX-A7XX"/>
625
+
<reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC" variants="A6XX-A7XX"/>
626
+
<reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC" variants="A6XX-A7XX"/>
627
+
<reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC" variants="A6XX-A7XX"/>
628
+
<reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX"/>
629
+
<reg32 offset="0x00195" name="RBBM_CGC_0_PC" variants="A7XX"/>
630
+
<reg32 offset="0x0010b" name="RBBM_CGC_0_PC" variants="A8XX-"/>
631
+
632
+
<reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/>
633
+
<reg32 offset="0x00009" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/>
906
634
907
635
<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
908
636
<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
···
964
610
<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
965
611
<bitfield high="27" low="24" name="ENABLE"/>
966
612
</reg32>
613
+
<reg32 offset="0x0606" name="DBGC_CFG_DBGBUS_OPL"/>
614
+
<reg32 offset="0x0607" name="DBGC_CFG_DBGBUS_OPE"/>
967
615
<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
968
616
<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
969
617
<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
···
994
638
<bitfield high="27" low="24" name="BYTEL14"/>
995
639
<bitfield high="31" low="28" name="BYTEL15"/>
996
640
</reg32>
641
+
<reg32 offset="0x0612" name="DBGC_CFG_DBGBUS_IVTE_0"/>
642
+
<reg32 offset="0x0613" name="DBGC_CFG_DBGBUS_IVTE_1"/>
643
+
<reg32 offset="0x0614" name="DBGC_CFG_DBGBUS_IVTE_2"/>
644
+
<reg32 offset="0x0615" name="DBGC_CFG_DBGBUS_IVTE_3"/>
645
+
<reg32 offset="0x0616" name="DBGC_CFG_DBGBUS_MASKE_0"/>
646
+
<reg32 offset="0x0617" name="DBGC_CFG_DBGBUS_MASKE_1"/>
647
+
<reg32 offset="0x0618" name="DBGC_CFG_DBGBUS_MASKE_2"/>
648
+
<reg32 offset="0x0619" name="DBGC_CFG_DBGBUS_MASKE_3"/>
649
+
<reg32 offset="0x061a" name="DBGC_CFG_DBGBUS_NIBBLEE"/>
650
+
<reg32 offset="0x061b" name="DBGC_CFG_DBGBUS_PTRC0"/>
651
+
<reg32 offset="0x061c" name="DBGC_CFG_DBGBUS_PTRC1"/>
652
+
<reg32 offset="0x061d" name="DBGC_CFG_DBGBUS_LOADREG"/>
653
+
<reg32 offset="0x061e" name="DBGC_CFG_DBGBUS_IDX"/>
654
+
<reg32 offset="0x061f" name="DBGC_CFG_DBGBUS_CLRC"/>
655
+
<reg32 offset="0x0620" name="DBGC_CFG_DBGBUS_LOADIVT"/>
656
+
<reg32 offset="0x0621" name="DBGC_VBIF_DBG_CNTL"/>
657
+
<reg32 offset="0x0622" name="DBGC_DBG_LO_HI_GPIO"/>
658
+
<reg32 offset="0x0623" name="DBGC_EXT_TRACE_BUS_CNTL"/>
659
+
<reg32 offset="0x0624" name="DBGC_READ_AHB_THROUGH_DBG"/>
660
+
<reg32 offset="0x0625" name="DBGC_CFG_DBGBUS_EVENT_LOGIC"/>
661
+
<reg32 offset="0x0626" name="DBGC_CFG_DBGBUS_OVER"/>
662
+
<reg32 offset="0x0627" name="DBGC_CFG_DBGBUS_COUNT0"/>
663
+
<reg32 offset="0x0628" name="DBGC_CFG_DBGBUS_COUNT1"/>
664
+
<reg32 offset="0x0629" name="DBGC_CFG_DBGBUS_COUNT2"/>
665
+
<reg32 offset="0x062a" name="DBGC_CFG_DBGBUS_COUNT3"/>
666
+
<reg32 offset="0x062b" name="DBGC_CFG_DBGBUS_COUNT4"/>
667
+
<reg32 offset="0x062c" name="DBGC_CFG_DBGBUS_COUNT5"/>
668
+
<reg32 offset="0x062d" name="DBGC_CFG_DBGBUS_TRACE_ADDR"/>
669
+
<reg32 offset="0x062e" name="DBGC_CFG_DBGBUS_TRACE_BUF0"/>
997
670
<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
998
671
<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
999
-
<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2" variants="A6XX"/>
1000
-
<reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">
1001
-
<doc>
1002
-
Set to true when binning, isn't changed afterwards
1003
-
</doc>
1004
-
<bitfield name="BINNING" pos="0" type="boolean"/>
1005
-
</reg32>
672
+
<reg32 offset="0x0631" name="DBGC_CFG_DBGBUS_TRACE_BUF3"/>
673
+
<reg32 offset="0x0632" name="DBGC_CFG_DBGBUS_TRACE_BUF4"/>
674
+
<reg32 offset="0x0633" name="DBGC_CFG_DBGBUS_MISR0"/>
675
+
<reg32 offset="0x0634" name="DBGC_CFG_DBGBUS_MISR1"/>
676
+
<reg32 offset="0x0635" name="DBGC_EVT_CFG"/>
677
+
<reg32 offset="0x0636" name="DBGC_EVT_INTF_SEL_0"/>
678
+
<reg32 offset="0x0637" name="DBGC_EVT_INTF_SEL_1"/>
679
+
<reg32 offset="0x0638" name="DBGC_EVT_SLICE_CFG"/>
680
+
<reg32 offset="0x0639" name="DBGC_QDSS_TIMESTAMP_0"/>
681
+
<reg32 offset="0x063a" name="DBGC_QDSS_TIMESTAMP_1"/>
682
+
<reg32 offset="0x063b" name="DBGC_ECO_CNTL"/>
683
+
<reg32 offset="0x063c" name="DBGC_AHB_DBG_CNTL"/>
684
+
<reg32 offset="0x063d" name="DBGC_EVT_INTF_SEL_2"/>
685
+
<reg32 offset="0x0640" name="DBGC_CFG_DBGBUS_PONG_SEL_A"/>
686
+
<reg32 offset="0x0641" name="DBGC_CFG_DBGBUS_PONG_SEL_B"/>
687
+
<reg32 offset="0x0642" name="DBGC_CFG_DBGBUS_PONG_SEL_C"/>
688
+
<reg32 offset="0x0643" name="DBGC_CFG_DBGBUS_PONG_SEL_D"/>
689
+
<reg32 offset="0x0644" name="DBGC_CFG_DBGBUS_MISC_MODE"/>
690
+
<reg32 offset="0x0650" name="DBGC_EVT_INTF_SEL_3_0"/>
691
+
<reg32 offset="0x0651" name="DBGC_EVT_INTF_SEL_3_1"/>
692
+
<reg32 offset="0x0652" name="DBGC_EVT_INTF_SEL_3_2"/>
693
+
<reg32 offset="0x0653" name="DBGC_EVT_INTF_SEL_3_3"/>
694
+
<reg32 offset="0x0654" name="DBGC_EVT_INTF_SEL_3_4"/>
695
+
<reg32 offset="0x0655" name="DBGC_EVT_INTF_SEL_3_5"/>
696
+
<reg32 offset="0x0660" name="DBGC_TRACE_BUFFER_STATUS"/>
697
+
<reg32 offset="0x0661" name="DBGC_TRACE_BUFFER_CMD"/>
698
+
<reg32 offset="0x0662" name="DBGC_DBG_TRACE_BUFFER_RD_ADDR"/>
699
+
<reg32 offset="0x0663" name="DBGC_DBG_TRACE_BUFFER_RD_DATA"/>
700
+
<reg32 offset="0x0664" name="DBGC_TRACE_BUFFER_ATB_RD_STATUS"/>
701
+
<reg32 offset="0x0665" name="DBGC_SMMU_FAULT_BLOCK_HALT_CFG"/>
702
+
<reg32 offset="0x0666" name="DBGC_DBG_LOPC_SB_RD_ADDR"/>
703
+
<reg32 offset="0x0667" name="DBGC_DBG_LOPC_SB_RD_DATA"/>
704
+
<reg32 offset="0x0668" name="DBGC_DBG_LOPC_SB_WR_ADDR"/>
705
+
<reg32 offset="0x0669" name="DBGC_DBG_LOPC_SB_WR_DATA"/>
706
+
<reg32 offset="0x066a" name="DBGC_INTERRUPT_STATUS"/>
707
+
<reg64 offset="0x0680" name="DBGC_GBIF_DBG_BASE"/>
708
+
<reg32 offset="0x0682" name="DBGC_GBIF_DBG_BUFF_SIZE"/>
709
+
<reg32 offset="0x0683" name="DBGC_GBIF_DBG_CNTL"/>
710
+
<reg32 offset="0x0684" name="DBGC_GBIF_DBG_CMD"/>
711
+
<reg32 offset="0x0685" name="DBGC_GBIF_DBG_STATUS"/>
712
+
713
+
<reg32 offset="0x0700" name="DBGC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/>
714
+
<reg32 offset="0x0701" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/>
715
+
<reg32 offset="0x0702" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/>
716
+
<reg32 offset="0x0703" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/>
717
+
<reg32 offset="0x0704" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS_US" variants="A8XX-"/>
718
+
<reg32 offset="0x0707" name="DBGC_CFG_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/>
719
+
<reg32 offset="0x0708" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/>
720
+
<reg32 offset="0x0709" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/>
721
+
<reg32 offset="0x070a" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/>
722
+
<reg32 offset="0x070f" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/>
723
+
<reg32 offset="0x0710" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/>
724
+
<reg32 offset="0x0711" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/>
725
+
<reg32 offset="0x0712" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/>
726
+
<reg32 offset="0x0713" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/>
727
+
<reg32 offset="0x0714" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/>
728
+
<reg32 offset="0x0715" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/>
729
+
<reg32 offset="0x0716" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_US" variants="A8XX-"/>
730
+
<reg32 offset="0x0720" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/>
731
+
<reg32 offset="0x0721" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US_1" variants="A8XX-"/>
732
+
<reg32 offset="0x0722" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/>
733
+
<reg32 offset="0x0723" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/>
734
+
<reg32 offset="0x0724" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/>
735
+
<reg32 offset="0x0730" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/>
736
+
<reg32 offset="0x0731" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/>
737
+
<reg32 offset="0x0732" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/>
738
+
<reg32 offset="0x0740" name="DBGC_CFG_BV_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/>
739
+
<reg32 offset="0x0742" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/>
740
+
<reg32 offset="0x0743" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/>
741
+
<reg64 offset="0x0744" name="DBGC_CFG_GBIF_BR_PERF_CNTR_BASE" variants="A8XX-"/>
742
+
<reg32 offset="0x0746" name="DBGC_CFG_GBIF_BR_BUFFER_SIZE" variants="A8XX-"/>
743
+
<reg64 offset="0x0747" name="DBGC_CFG_GBIF_BV_PERF_CNTR_BASE" variants="A8XX-"/>
744
+
<reg32 offset="0x0749" name="DBGC_CFG_GBIF_BV_BUFFER_SIZE" variants="A8XX-"/>
745
+
<reg32 offset="0x074a" name="DBGC_CFG_GBIF_QOS_CTRL" variants="A8XX-"/>
746
+
<reg32 offset="0x0750" name="DBGC_GBIF_BR_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/>
747
+
<reg32 offset="0x0751" name="DBGC_GBIF_BV_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/>
748
+
<reg32 offset="0x0752" name="DBGC_PERF_COUNTER_FE_LOCAL_BATCH_ID" variants="A8XX-"/>
749
+
<reg32 offset="0x0753" name="DBGC_CFG_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/>
750
+
<reg32 offset="0x0754" name="DBGC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/>
751
+
<reg32 offset="0x0755" name="DBGC_PERF_SKEW_BUFFER_INIT_CMD" variants="A8XX-"/>
752
+
<reg32 offset="0x0759" name="DBGC_LOPC_INTERRUPT_STATUS" variants="A8XX-"/>
753
+
<reg32 offset="0x075a" name="DBGC_LOPC_BUFFER_PTR_STATUS" variants="A8XX-"/>
754
+
<reg32 offset="0x075b" name="DBGC_PERF_SCOPING_STATUS" variants="A8XX-"/>
755
+
<reg32 offset="0x075c" name="DBGC_PERF_COUNTER_PKT_STATUS" variants="A8XX-"/>
756
+
<reg32 offset="0x0760" name="DBGC_GC_LIVE_MBX_PKT_STATUS" variants="A8XX-"/>
757
+
<reg32 offset="0x0761" name="DBGC_GC_ALW_MBX_PKT_STATUS" variants="A8XX-"/>
758
+
<reg32 offset="0x0762" name="DBGC_AO_CNTR_LO_STATUS" variants="A8XX-"/>
759
+
<reg32 offset="0x0763" name="DBGC_AO_CNTR_HI_STATUS" variants="A8XX-"/>
760
+
<reg32 offset="0x0770" name="DBGC_LOPC_GC_SB_DEPTH_STATUS" variants="A8XX-"/>
761
+
<reg32 offset="0x0780" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/>
762
+
<reg32 offset="0x0781" name="DBGC_CFG_PERF_TRIG_LPAC_US" variants="A8XX-"/>
763
+
<reg32 offset="0x0782" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US" variants="A8XX-"/>
764
+
<reg32 offset="0x0783" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_1" variants="A8XX-"/>
765
+
<reg32 offset="0x0784" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_2" variants="A8XX-"/>
766
+
<reg32 offset="0x0785" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_US" variants="A8XX-"/>
767
+
<reg64 offset="0x0786" name="DBGC_CFG_GBIF_LPAC_PERF_CNTR_BASE" variants="A8XX-"/>
768
+
<reg32 offset="0x0788" name="DBGC_CFG_GBIF_LPAC_BUFFER_SIZE" variants="A8XX-"/>
769
+
<reg32 offset="0x0789" name="DBGC_GBIF_LPAC_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/>
770
+
<reg32 offset="0x078a" name="DBGC_CFG_LPAC_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/>
771
+
<reg32 offset="0x078b" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/>
772
+
<reg32 offset="0x078c" name="DBGC_LPAC_MBX_PKT_STATUS" variants="A8XX-"/>
773
+
<reg32 offset="0x078d" name="DBGC_LPAC_PERF_SCOPING_STATUS" variants="A8XX-"/>
774
+
<reg32 offset="0x0790" name="DBGC_LOPC_LPAC_SB_DEPTH_STATUS" variants="A8XX-"/>
775
+
<reg32 offset="0x07a0" name="DBGC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/>
776
+
<reg32 offset="0x07a1" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/>
777
+
<reg32 offset="0x07a2" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/>
778
+
<reg32 offset="0x07a3" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/>
779
+
<reg32 offset="0x07a4" name="DBGC_CFG_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/>
780
+
<reg32 offset="0x07a5" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS" variants="A8XX-"/>
781
+
<reg32 offset="0x07a6" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/>
782
+
<reg32 offset="0x07a7" name="DBGC_CFG_PERF_TRIG_CLUSTER_PS" variants="A8XX-"/>
783
+
<reg32 offset="0x07a8" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/>
784
+
<reg32 offset="0x07a9" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/>
785
+
<reg32 offset="0x07aa" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/>
786
+
<reg32 offset="0x07ab" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/>
787
+
<reg32 offset="0x07ac" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/>
788
+
<reg32 offset="0x07ad" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/>
789
+
<reg32 offset="0x07ae" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/>
790
+
<reg32 offset="0x07af" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/>
791
+
<reg32 offset="0x07b0" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/>
792
+
<reg32 offset="0x07b1" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/>
793
+
<reg32 offset="0x07b2" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/>
794
+
<reg32 offset="0x07b3" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/>
795
+
<reg32 offset="0x07b4" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/>
796
+
<reg32 offset="0x07b5" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/>
797
+
<reg32 offset="0x07b6" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/>
798
+
<reg32 offset="0x07b7" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/>
799
+
<reg32 offset="0x07b8" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/>
800
+
<reg32 offset="0x07b9" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/>
801
+
<reg32 offset="0x07ba" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS" variants="A8XX-"/>
802
+
<reg32 offset="0x07bb" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_1" variants="A8XX-"/>
803
+
<reg32 offset="0x07bc" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_2" variants="A8XX-"/>
804
+
<reg32 offset="0x07bd" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_3" variants="A8XX-"/>
805
+
<reg32 offset="0x07be" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/>
806
+
<reg32 offset="0x07bf" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/>
807
+
<reg32 offset="0x07c0" name="DBGC_CFG_PERF_COUNTER_SEL_PS" variants="A8XX-"/>
808
+
<reg32 offset="0x07c1" name="DBGC_CFG_PERF_COUNTER_SEL_PS_1" variants="A8XX-"/>
809
+
<reg32 offset="0x07c2" name="DBGC_CFG_PERF_COUNTER_SEL_PS_2" variants="A8XX-"/>
810
+
<reg32 offset="0x07c3" name="DBGC_CFG_PERF_COUNTER_SEL_PS_3" variants="A8XX-"/>
811
+
<reg32 offset="0x07c4" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/>
812
+
<reg32 offset="0x07c5" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/>
813
+
<reg32 offset="0x07c6" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/>
814
+
<reg32 offset="0x07c7" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/>
815
+
<reg32 offset="0x07c8" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/>
816
+
<reg32 offset="0x07c9" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/>
817
+
<reg32 offset="0x07ca" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/>
818
+
<reg32 offset="0x07cb" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/>
819
+
<reg32 offset="0x07cc" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/>
820
+
<reg32 offset="0x07cd" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/>
821
+
<reg32 offset="0x07ce" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/>
822
+
<reg32 offset="0x07cf" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/>
823
+
<reg32 offset="0x07d0" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/>
824
+
<reg32 offset="0x07d1" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/>
825
+
<reg32 offset="0x07d2" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/>
826
+
<reg32 offset="0x07d3" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/>
827
+
<reg32 offset="0x07d4" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/>
828
+
<reg32 offset="0x07d5" name="DBGC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/>
829
+
<reg32 offset="0x07e0" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/>
830
+
<reg32 offset="0x07e1" name="DBGC_CFG_PERF_TRIG_LPAC_S" variants="A8XX-"/>
831
+
<reg32 offset="0x07e2" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S" variants="A8XX-"/>
832
+
<reg32 offset="0x07e3" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_1" variants="A8XX-"/>
833
+
<reg32 offset="0x07e4" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_2" variants="A8XX-"/>
834
+
<reg32 offset="0x07e5" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_S" variants="A8XX-"/>
835
+
<reg32 offset="0x07e6" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/>
836
+
837
+
<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
1006
838
<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1007
839
<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1008
-
<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
840
+
<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
1009
841
<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1010
-
<reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>
1011
-
<reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>
1012
-
<reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>
1013
-
<reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>
1014
-
<reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
1015
-
<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>
842
+
<reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX" variants="A6XX"/>
843
+
<reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE" variants="A6XX-A7XX"/>
844
+
<reg64 offset="0x0E06" name="UCHE_WRITE_THRU_BASE" variants="A8XX-"/>
845
+
<reg64 offset="0x0E09" name="UCHE_TRAP_BASE" variants="A6XX-A7XX"/>
846
+
<reg64 offset="0x0E08" name="UCHE_TRAP_BASE" variants="A8XX-"/>
847
+
<reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN" variants="A6XX-A7XX"/>
848
+
<reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX" variants="A6XX-A7XX"/>
849
+
<reg32 offset="0x0e17" name="UCHE_CACHE_WAYS" variants="A6XX-A7XX" usage="init"/>
850
+
<reg32 offset="0x0e04" name="UCHE_CACHE_WAYS" variants="A8XX-"/>
1016
851
<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1017
-
<reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">
852
+
<reg32 offset="0x0e19" name="UCHE_CLIENT_PF" variants="A6XX-A7XX" usage="init">
1018
853
<bitfield high="7" low="0" name="PERFSEL"/>
1019
854
</reg32>
1020
-
<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
1021
-
<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
1022
-
<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
855
+
<array offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12" variants="A6XX-A7XX"/>
856
+
<array offset="0x0e20" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="24" variants="A8XX-"/>
857
+
<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG" variants="A6XX-A7XX"/>
858
+
<reg32 offset="0x0e12" name="UCHE_GBIF_GX_CONFIG" variants="A8XX-"/>
859
+
<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG" variants="A6XX-A7XX"/>
1023
860
1024
-
<reg32 offset="0x3000" name="VBIF_VERSION"/>
1025
-
<reg32 offset="0x3001" name="VBIF_CLKON">
861
+
<reg32 offset="0x0f01" name="UCHE_CCHE_MODE_CNTL" variants="A8XX-"/>
862
+
<reg32 offset="0x0f02" name="UCHE_CCHE_CACHE_WAYS" variants="A8XX-"/>
863
+
<reg64 offset="0x0f04" name="UCHE_CCHE_WRITE_THRU_BASE" variants="A8XX-"/>
864
+
<reg64 offset="0x0f06" name="UCHE_CCHE_TRAP_BASE" variants="A8XX-"/>
865
+
<reg64 offset="0x0f08" name="UCHE_CCHE_GC_GMEM_RANGE_MIN" variants="A8XX-"/>
866
+
<reg64 offset="0x0f0a" name="UCHE_CCHE_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/>
867
+
<reg32 offset="0x0f0c" name="UCHE_CCHE_HW_DBG_CNTL" variants="A8XX-"/>
868
+
869
+
<!-- VBIF only existed on early a6xx, and was later replaced with GBIF -->
870
+
871
+
<reg32 offset="0x3000" name="VBIF_VERSION" variants="A6XX"/>
872
+
<reg32 offset="0x3001" name="VBIF_CLKON" variants="A6XX">
1026
873
<bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
1027
874
</reg32>
1028
-
<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1029
-
<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1030
-
<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1031
-
<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1032
-
<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1033
-
<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
875
+
<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN" variants="A6XX"/>
876
+
<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0" variants="A6XX"/>
877
+
<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1" variants="A6XX"/>
878
+
<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL" variants="A6XX"/>
879
+
<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0" variants="A6XX"/>
880
+
<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1" variants="A6XX">
1034
881
<bitfield low="0" high="3" name="DATA_SEL"/>
1035
882
</reg32>
1036
-
<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1037
-
<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
883
+
<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0" variants="A6XX"/>
884
+
<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1" variants="A6XX">
1038
885
<bitfield low="0" high="8" name="DATA_SEL"/>
1039
886
</reg32>
1040
-
<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1041
-
<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1042
-
<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1043
-
<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1044
-
<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1045
-
<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1046
-
<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1047
-
<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1048
-
<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1049
-
<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1050
-
<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1051
-
<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1052
-
<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1053
-
<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1054
-
<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1055
-
<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1056
-
<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1057
-
<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1058
-
<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1059
-
<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1060
-
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1061
-
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
887
+
<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT" variants="A6XX"/>
888
+
<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" variants="A6XX"/>
889
+
<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" variants="A6XX"/>
890
+
<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" variants="A6XX"/>
891
+
<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" variants="A6XX"/>
892
+
<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0" variants="A6XX"/>
893
+
<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1" variants="A6XX"/>
894
+
<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2" variants="A6XX"/>
895
+
<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3" variants="A6XX"/>
896
+
<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0" variants="A6XX"/>
897
+
<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1" variants="A6XX"/>
898
+
<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2" variants="A6XX"/>
899
+
<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3" variants="A6XX"/>
900
+
<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0" variants="A6XX"/>
901
+
<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1" variants="A6XX"/>
902
+
<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2" variants="A6XX"/>
903
+
<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0" variants="A6XX"/>
904
+
<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1" variants="A6XX"/>
905
+
<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2" variants="A6XX"/>
906
+
<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0" variants="A6XX"/>
907
+
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1" variants="A6XX"/>
908
+
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2" variants="A6XX"/>
1062
909
910
+
<reg32 offset="0x3c00" name="GBIF_CX_CONFIG" variants="A8XX-"/>
1063
911
<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
1064
912
<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1065
913
<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
···
1272
712
<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1273
713
<reg32 offset="0x3c45" name="GBIF_HALT"/>
1274
714
<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
715
+
<reg32 offset="0x3c49" name="GBIF_REINIT_ENABLE" variants="A8XX-"/>
716
+
<reg32 offset="0x3c4a" name="GBIF_REINIT_DONE" variants="A8XX-"/>
1275
717
<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1276
718
<reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
1277
719
<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1278
-
<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1279
-
<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1280
-
<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1281
-
<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1282
-
<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1283
-
<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1284
-
<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1285
-
<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1286
-
<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1287
-
<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1288
-
<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1289
-
<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1290
-
<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1291
-
<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1292
-
<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
720
+
<reg32 offset="0x3cc3" name="GBIF_PERF_CNT_SEL_1" variants="A8XX-"/>
721
+
722
+
<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL" variants="A6XX-A7XX"/>
723
+
<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0" variants="A6XX-A7XX"/>
724
+
<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1" variants="A6XX-A7XX"/>
725
+
<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2" variants="A6XX-A7XX"/>
726
+
<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3" variants="A6XX-A7XX"/>
727
+
<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0" variants="A6XX-A7XX"/>
728
+
<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1" variants="A6XX-A7XX"/>
729
+
<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2" variants="A6XX-A7XX"/>
730
+
<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3" variants="A6XX-A7XX"/>
731
+
<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0" variants="A6XX-A7XX"/>
732
+
<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1" variants="A6XX-A7XX"/>
733
+
<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2" variants="A6XX-A7XX"/>
734
+
<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0" variants="A6XX-A7XX"/>
735
+
<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1" variants="A6XX-A7XX"/>
736
+
<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2" variants="A6XX-A7XX"/>
737
+
738
+
<reg32 offset="0x3cc4" name="GBIF_PWR_CNT_SEL" variants="A8XX"/>
739
+
<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LO_0" variants="A8XX"/>
740
+
<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_HI_0" variants="A8XX"/>
741
+
<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_LO_1" variants="A8XX"/>
742
+
<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HI_1" variants="A8XX"/>
743
+
<reg32 offset="0x3cca" name="GBIF_PERF_CNT_LO_2" variants="A8XX"/>
744
+
<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HI_2" variants="A8XX"/>
745
+
<reg32 offset="0x3ccc" name="GBIF_PERF_CNT_LO_3" variants="A8XX"/>
746
+
<reg32 offset="0x3ccd" name="GBIF_PERF_CNT_HI_3" variants="A8XX"/>
747
+
<reg32 offset="0x3cce" name="GBIF_PERF_CNT_LO_4" variants="A8XX"/>
748
+
<reg32 offset="0x3ccf" name="GBIF_PERF_CNT_HI_4" variants="A8XX"/>
749
+
<reg32 offset="0x3cd0" name="GBIF_PERF_CNT_LO_5" variants="A8XX"/>
750
+
<reg32 offset="0x3cd1" name="GBIF_PERF_CNT_HI_5" variants="A8XX"/>
751
+
<reg32 offset="0x3cd2" name="GBIF_PERF_CNT_LO_6" variants="A8XX"/>
752
+
<reg32 offset="0x3cd3" name="GBIF_PERF_CNT_HI_6" variants="A8XX"/>
753
+
<reg32 offset="0x3cd4" name="GBIF_PERF_CNT_LO_7" variants="A8XX"/>
754
+
<reg32 offset="0x3cd5" name="GBIF_PERF_CNT_HI_7" variants="A8XX"/>
755
+
<reg32 offset="0x3ce0" name="GBIF_PWR_CNT_LO_0" variants="A8XX"/>
756
+
<reg32 offset="0x3ce1" name="GBIF_PWR_CNT_LO_1" variants="A8XX"/>
757
+
<reg32 offset="0x3ce2" name="GBIF_PWR_CNT_LO_2" variants="A8XX"/>
758
+
<reg32 offset="0x3ce3" name="GBIF_PWR_CNT_HI_0" variants="A8XX"/>
759
+
<reg32 offset="0x3ce4" name="GBIF_PWR_CNT_HI_1" variants="A8XX"/>
760
+
<reg32 offset="0x3ce5" name="GBIF_PWR_CNT_HI_2" variants="A8XX"/>
1293
761
1294
762
<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
1295
-
<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">
1296
-
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1297
-
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
763
+
<reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/>
764
+
<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit" variants="A6XX-A7XX">
765
+
<bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
766
+
<bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1298
767
</reg32>
768
+
769
+
<bitset name="a8xx_bin_size" inline="yes">
770
+
<bitfield name="BINW" low="0" high="9" shr="5" type="uint"/>
771
+
<bitfield name="BINH" low="16" high="26" shr="4" type="uint"/>
772
+
</bitset>
773
+
774
+
<reg32 offset="0x0c02" name="VSC_BIN_SIZE" type="a8xx_bin_size" usage="rp_blit" variants="A8XX"/>
1299
775
<reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/>
1300
776
<reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit">
1301
777
<bitfield name="NX" low="1" high="10" type="uint"/>
···
1399
803
1400
804
<reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
1401
805
1402
-
<reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
1403
-
<reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
806
+
<reg32 offset="0x0e10" name="UCHE_UNKNOWN_0E10" variants="A7XX" usage="init"/>
807
+
<reg32 offset="0x0e10" name="UCHE_VARB_IDLE_TIMEOUT" variants="A8XX-"/>
808
+
<reg32 offset="0x0e11" name="UCHE_UNKNOWN_0E11" variants="A7XX" usage="init"/>
809
+
<reg32 offset="0x0e11" name="UCHE_CLIENT_PF" variants="A8XX-"/>
1404
810
<!-- always 0x03200000 ? -->
1405
-
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/>
811
+
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" variants="A6XX-A7XX" usage="init"/>
812
+
<reg32 offset="0x0e15" name="UCHE_DBG_ECO_CNTL_0" variants="A8XX-"/>
813
+
<reg32 offset="0x0e16" name="UCHE_HW_DBG_CNTL" variants="A8XX-"/>
1406
814
1407
815
<!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1408
816
<bitset name="a6xx_reg_xy" inline="yes">
···
1429
829
</bitset>
1430
830
1431
831
<reg32 offset="0x8000" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
832
+
<reg32 offset="0x8200" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A8XX-" usage="rp_blit"/>
1432
833
1433
834
<bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes">
1434
835
<bitfield name="CLIP_MASK" low="0" high="7"/>
···
1439
838
<reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" />
1440
839
<reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" />
1441
840
<reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A6XX-A7XX" />
841
+
842
+
<reg32 offset="0x8201" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" />
843
+
<reg32 offset="0x8202" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" />
844
+
<reg32 offset="0x8203" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" />
845
+
<reg32 offset="0x8204" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A8XX" />
846
+
847
+
<reg32 offset="0x8228" name="GRAS_UNKNOWN_8228" variants="A8XX-"/>
848
+
<reg32 offset="0x8229" name="GRAS_UNKNOWN_8229" variants="A8XX-"/>
849
+
<reg32 offset="0x822a" name="GRAS_UNKNOWN_822A" variants="A8XX-"/>
850
+
<reg32 offset="0x822b" name="GRAS_UNKNOWN_822B" variants="A8XX-"/>
851
+
<reg32 offset="0x822c" name="GRAS_UNKNOWN_822C" variants="A8XX-"/>
852
+
<reg32 offset="0x822d" name="GRAS_UNKNOWN_822D" variants="A8XX-"/>
1442
853
1443
854
<bitset name="a6xx_gras_cl_interp_cntl" inline="yes">
1444
855
<!-- see also RB_INTERP_CNTL -->
···
1466
853
</bitset>
1467
854
1468
855
<reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
856
+
<reg32 offset="0x8080" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A8XX-" usage="rp_blit"/>
1469
857
1470
858
<bitset name="a6xx_gras_cl_guardband_clip_adj" inline="true">
1471
859
<bitfield name="HORZ" low="0" high="8" type="uint"/>
···
1474
860
</bitset>
1475
861
1476
862
<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A6XX-A7XX" usage="rp_blit"/>
1477
-
1478
-
<!-- Something connected to depth-stencil attachment size -->
1479
-
<reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
863
+
<reg32 offset="0x8205" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A8XX-" usage="rp_blit"/>
1480
864
1481
865
<!-- the scale/offset is per view, with up to 6 views -->
1482
866
<bitset name="a6xx_gras_bin_foveat" inline="yes">
···
1499
887
</bitset>
1500
888
1501
889
<reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/>
890
+
<reg32 offset="0x8206" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A8XX-" usage="cmd"/>
1502
891
1503
892
<reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd">
1504
893
<bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/>
···
1534
921
<reg32 offset="5" name="ZSCALE" type="float"/>
1535
922
</array>
1536
923
924
+
<array offset="0x82d0" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A8XX-" usage="rp_blit">
925
+
<reg32 offset="0" name="XOFFSET" type="float"/>
926
+
<reg32 offset="1" name="XSCALE" type="float"/>
927
+
<reg32 offset="2" name="YOFFSET" type="float"/>
928
+
<reg32 offset="3" name="YSCALE" type="float"/>
929
+
<reg32 offset="4" name="ZOFFSET" type="float"/>
930
+
<reg32 offset="5" name="ZSCALE" type="float"/>
931
+
</array>
932
+
1537
933
<array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit">
934
+
<reg32 offset="0" name="MIN" type="float"/>
935
+
<reg32 offset="1" name="MAX" type="float"/>
936
+
</array>
937
+
<array offset="0x80c0" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A8XX-" usage="rp_blit">
1538
938
<reg32 offset="0" name="MIN" type="float"/>
1539
939
<reg32 offset="1" name="MAX" type="float"/>
1540
940
</array>
···
1577
951
<bitfield name="UNK20" low="20" high="22" variants="A6XX-A7XX"/>
1578
952
</bitset>
1579
953
<reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
954
+
<reg32 offset="0x8209" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A8XX-" usage="rp_blit"/>
955
+
956
+
<!-- Fields moved from GRAS_SU_CNTL on earlier gens: -->
957
+
<reg32 offset="0x820c" name="GRAS_SU_STEREO_CNTL" variants="A8XX-" usage="rp_blit">
958
+
<bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
959
+
<bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
960
+
</reg32>
1580
961
1581
962
<bitset name="a6xx_gras_su_point_minmax" inline="yes">
1582
963
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
···
1591
958
</bitset>
1592
959
1593
960
<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A6XX-A7XX" usage="rp_blit"/>
961
+
<reg32 offset="0x820a" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A8XX-" usage="rp_blit"/>
962
+
1594
963
<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A6XX-A7XX" usage="rp_blit"/>
964
+
<reg32 offset="0x820b" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A8XX-" usage="rp_blit"/>
1595
965
1596
966
<bitset name="a6xx_gras_su_depth_cntl" inline="yes">
1597
967
<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
1598
968
</bitset>
1599
969
1600
970
<reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" variants="A6XX-A7XX" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/>
971
+
<reg32 offset="0x8086" name="GRAS_SU_DEPTH_CNTL" variants="A8XX-" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/>
1601
972
1602
973
<bitset name="a6xx_gras_su_stencil_cntl" inline="yes">
1603
974
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1604
975
</bitset>
1605
976
1606
977
<reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
978
+
<reg32 offset="0x8087" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A8XX-" usage="rp_blit"/>
1607
979
1608
980
<bitset name="a6xx_gras_su_render_cntl" inline="yes">
1609
981
<bitfield name="FS_DISABLE" pos="7" type="boolean"/>
1610
982
</bitset>
1611
983
1612
984
<reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A7XX" usage="rp_blit"/>
985
+
<reg32 offset="0x8088" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A8XX-" usage="rp_blit"/>
1613
986
1614
987
<!-- 0x8093 invalid -->
1615
988
<bitset name="a6xx_depth_plane_cntl" inline="yes">
···
1623
984
</bitset>
1624
985
1625
986
<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
987
+
<reg32 offset="0x8089" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A8XX-" usage="rp_blit"/>
988
+
1626
989
<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A6XX-A7XX" usage="rp_blit"/>
990
+
<reg32 offset="0x808a" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A8XX-" usage="rp_blit"/>
991
+
1627
992
<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A6XX-A7XX" usage="rp_blit"/>
993
+
<reg32 offset="0x808b" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A8XX-" usage="rp_blit"/>
994
+
1628
995
<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A6XX-A7XX" usage="rp_blit"/>
996
+
<reg32 offset="0x808c" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A8XX-" usage="rp_blit"/>
997
+
1629
998
<bitset name="a6xx_depth_buffer_info" inline="yes">
1630
999
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1631
-
<bitfield name="UNK3" pos="3"/>
1000
+
<bitfield name="READ_ONLY" pos="3" type="boolean"/>
1632
1001
</bitset>
1633
1002
1634
1003
<!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1635
1004
<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A6XX-A7XX" usage="rp_blit"/>
1005
+
<reg32 offset="0x808d" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX-" usage="rp_blit"/>
1636
1006
1637
1007
<bitset name="a6xx_gras_su_conservative_ras_cntl" inline="yes">
1638
1008
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
···
1656
1008
</bitset>
1657
1009
1658
1010
<reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A6XX-A7XX" usage="cmd"/>
1011
+
<reg32 offset="0x820d" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A8XX-" usage="cmd"/>
1659
1012
1660
1013
<reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
1661
1014
<bitfield name="UNK0" pos="0" type="boolean"/>
···
1671
1022
<reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1672
1023
<reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1673
1024
1025
+
<reg32 offset="0x820e" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/>
1026
+
<reg32 offset="0x820f" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/>
1027
+
<reg32 offset="0x8210" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/>
1028
+
1674
1029
<bitset name="a6xx_rast_cntl" inline="yes">
1675
1030
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
1676
1031
</bitset>
1032
+
1033
+
<reg32 offset="0x8211" name="GRAS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/>
1677
1034
1678
1035
<enum name="a6xx_sequenced_thread_dist">
1679
1036
<value value="0x0" name="DIST_SCREEN_COORD"/>
···
1728
1073
</enum>
1729
1074
1730
1075
<bitset name="a6xx_gras_sc_cntl" inline="yes">
1731
-
<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
1732
1076
<bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
1733
1077
<bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
1734
1078
<bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
···
1738
1084
<bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
1739
1085
</bitset>
1740
1086
1741
-
<reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1087
+
<reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit">
1088
+
<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2" variants="A6XX-A7XX"/>
1089
+
</reg32>
1090
+
<reg32 offset="0x8230" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A8XX-" usage="rp_blit"/>
1742
1091
1743
1092
<enum name="a6xx_render_mode">
1744
1093
<value value="0x0" name="RENDERING_PASS"/>
···
1780
1123
1781
1124
<reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" type="a6xx_bin_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1782
1125
1126
+
<!-- Common fields for RB_CNTL and GRAS_SC_BIN_CNTL -->
1127
+
<bitset name="a8xx_bin_cntl" inline="yes">
1128
+
<bitfield name="BINW" low="0" high="9" shr="5" type="uint"/>
1129
+
<bitfield name="BINH" low="16" high="26" shr="4" type="uint"/>
1130
+
<bitfield name="RENDER_MODE" low="11" high="13" type="a6xx_render_mode"/>
1131
+
<doc>
1132
+
Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have
1133
+
GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass.
1134
+
In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered.
1135
+
</doc>
1136
+
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="28" high="30" type="a6xx_lrz_feedback_mask"/>
1137
+
<doc>Disable LRZ feedback writes</doc>
1138
+
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="31" type="boolean"/>
1139
+
</bitset>
1140
+
1141
+
<reg32 offset="0x8231" name="GRAS_SC_BIN_CNTL" type="a8xx_bin_cntl" variants="A8XX-" usage="rp_blit">
1142
+
<bitfield name="CONS_VIS_IN_BINNING" pos="10" type="boolean"/>
1143
+
<bitfield name="FORCE_BI_DIR_LRZ_DISABLE" pos="14" type="boolean"/>
1144
+
<bitfield name="FORCE_LRZ_DIS" pos="15" type="boolean"/>
1145
+
<bitfield name="BIN_VRS_DIS" pos="27" type="boolean"/>
1146
+
</reg32>
1147
+
1783
1148
<bitset name="a6xx_gras_sc_ras_msaa_cntl" inline="yes">
1784
1149
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1785
1150
<bitfield name="UNK2" pos="2"/>
···
1809
1130
</bitset>
1810
1131
1811
1132
<reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1133
+
<reg32 offset="0x8232" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A8XX-" usage="rp_blit"/>
1812
1134
1813
1135
<bitset name="a6xx_gras_sc_dest_msaa_cntl" inline="yes">
1814
1136
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
···
1817
1137
</bitset>
1818
1138
1819
1139
<reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1140
+
<reg32 offset="0x8233" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A8XX-" usage="rp_blit"/>
1820
1141
1821
1142
<bitset name="a6xx_msaa_sample_pos_cntl" inline="yes">
1822
1143
<bitfield name="UNK0" pos="0"/>
···
1839
1158
<reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/>
1840
1159
<reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/>
1841
1160
1161
+
<reg32 offset="0x8237" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A8XX-" usage="rp_blit"/>
1162
+
<reg32 offset="0x8238" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/>
1163
+
<reg32 offset="0x8239" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/>
1164
+
<reg32 offset="0x823a" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/>
1165
+
<reg32 offset="0x823b" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/>
1166
+
1842
1167
<reg32 offset="0x80a7" name="GRAS_ROTATION_CNTL" variants="A7XX" usage="cmd"/>
1168
+
<reg32 offset="0x8207" name="GRAS_ROTATION_CNTL" variants="A8XX-" usage="cmd"/>
1843
1169
1844
1170
<bitset name="a6xx_screen_scissor_cntl" inline="yes">
1845
1171
<bitfield name="SCISSOR_DISABLE" pos="0" type="boolean"/>
1846
1172
</bitset>
1847
1173
1848
1174
<reg32 offset="0x80af" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A6XX-A7XX" pos="0" usage="cmd"/>
1175
+
<reg32 offset="0x8234" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A8XX-" pos="0" usage="cmd"/>
1849
1176
1850
1177
<bitset name="a6xx_scissor_xy" inline="yes">
1851
1178
<bitfield name="X" low="0" high="15" type="uint"/>
···
1865
1176
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1866
1177
</array>
1867
1178
1179
+
<array offset="0x8240" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A8XX-" usage="rp_blit">
1180
+
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1181
+
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1182
+
</array>
1183
+
1868
1184
<array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit">
1185
+
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1186
+
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1187
+
</array>
1188
+
<array offset="0x8270" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A8XX-" usage="rp_blit">
1869
1189
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1870
1190
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1871
1191
</array>
1872
1192
1873
1193
<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
1874
1194
<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
1195
+
1196
+
<reg32 offset="0x8235" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
1197
+
<reg32 offset="0x8236" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
1875
1198
1876
1199
<enum name="a6xx_fsr_combiner">
1877
1200
<value value="0" name="FSR_COMBINER_OP_KEEP"/>
···
1904
1203
</bitset>
1905
1204
1906
1205
<reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A7XX" usage="rp_blit"/>
1206
+
<reg32 offset="0x8208" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A8XX-" usage="rp_blit"/>
1907
1207
1908
1208
<bitset name="a6xx_gras_quality_buffer_info" inline="yes">
1909
1209
<bitfield name="LAYERED" pos="0" type="boolean"/>
···
1912
1210
</bitset>
1913
1211
1914
1212
<reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A7XX" usage="rp_blit"/>
1213
+
<reg32 offset="0x808e" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A8XX-" usage="rp_blit"/>
1915
1214
1916
1215
<bitset name="a6xx_gras_quality_buffer_dimension" inline="yes">
1917
1216
<bitfield name="WIDTH" low="0" high="15" type="uint"/>
···
1920
1217
</bitset>
1921
1218
1922
1219
<reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A7XX" usage="rp_blit"/>
1220
+
<reg32 offset="0x808f" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A8XX-" usage="rp_blit"/>
1923
1221
1924
1222
<reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX" type="waddress" usage="rp_blit"/>
1223
+
<reg64 offset="0x8090" name="GRAS_QUALITY_BUFFER_BASE" variants="A8XX-" type="waddress" usage="rp_blit"/>
1925
1224
1926
1225
<bitset name="a6xx_gras_quality_buffer_pitch" inline="yes">
1927
1226
<bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/>
···
1931
1226
</bitset>
1932
1227
1933
1228
<reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A7XX" usage="rp_blit"/>
1229
+
<reg32 offset="0x8092" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A8XX-" usage="rp_blit"/>
1934
1230
1935
1231
<enum name="a6xx_lrz_dir_status">
1936
1232
<value value="0x1" name="LRZ_DIR_LE"/>
···
1950
1244
- 0.0 if GREATER
1951
1245
- 1.0 if LESS
1952
1246
</doc>
1953
-
<bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>
1954
1247
<!-- set when depth-test + depth-write enabled -->
1955
1248
<bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/>
1956
1249
<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
···
1963
1258
Disable LRZ based on previous direction and the current one.
1964
1259
If DIR_WRITE is not enabled - there is no write to direction buffer.
1965
1260
</doc>
1966
-
<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>
1967
1261
<bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
1968
1262
</bitset>
1969
1263
1970
-
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX-A7XX"/>
1264
+
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX">
1265
+
<bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>
1266
+
<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>
1267
+
</reg32>
1268
+
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A7XX"/>
1269
+
<reg32 offset="0x8212" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A8XX-"/>
1270
+
1271
+
<reg32 offset="0x8007" name="GRAS_LRZ_CB_CNTL" variants="A7XX" usage="rp_blit">
1272
+
<doc>
1273
+
The total size of the LRZ image array (not including
1274
+
fast clear buffer), used as a stride for double
1275
+
buffering used with concurrent binning.
1276
+
</doc>
1277
+
<bitfield name="DOUBLE_BUFFER_STRIDE" low="8" high="31" shr="8"/>
1278
+
</reg32>
1279
+
<reg32 offset="0x8101" name="GRAS_LRZ_CB_CNTL" usage="rp_blit" variants="A8XX-">
1280
+
<bitfield name="DOUBLE_BUFFER_PITCH" low="8" high="31" shr="8"/>
1281
+
</reg32>
1971
1282
1972
1283
<enum name="a6xx_fragcoord_sample_mode">
1973
1284
<value value="0" name="FRAGCOORD_CENTER"/>
···
1996
1275
</bitset>
1997
1276
1998
1277
<reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A6XX-A7XX"/>
1278
+
<reg32 offset="0x8102" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A8XX-"/>
1999
1279
2000
1280
<bitset name="a6xx_gras_lrz_mrt_buffer_info_0" inline="yes">
2001
1281
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2002
1282
</bitset>
2003
1283
2004
1284
<reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A6XX-A7XX"/>
1285
+
<reg32 offset="0x8103" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A8XX-"/>
2005
1286
2006
1287
<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A6XX-A7XX"/>
1288
+
<reg64 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A8XX-"/>
2007
1289
2008
1290
<bitset name="a6xx_gras_lrz_buffer_pitch" inline="yes">
2009
1291
<bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
···
2014
1290
</bitset>
2015
1291
2016
1292
<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A6XX-A7XX"/>
1293
+
<reg32 offset="0x8108" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A8XX-"/>
1294
+
1295
+
<reg32 offset="0x810e" name="GRAS_LRZ_BUFFER_STRIDE" usage="rp_blit" low="0" high="16" shr="12" variants="A8XX-"/>
2017
1296
2018
1297
<!--
2019
1298
The LRZ "fast clear" buffer is initialized to zero's by blob, and
···
2073
1346
2074
1347
<!-- 0x810c-0x810f invalid -->
2075
1348
1349
+
<reg32 offset="0x8110" name="GRAS_LRZ_BUFFER_SLICE_PITCH" low="0" high="31" shr="8" type="uint" variants="A8XX-"/>
1350
+
2076
1351
<reg32 offset="0x8110" name="GRAS_MODE_CNTL" low="0" high="1" variants="A6XX-A7XX" usage="cmd"/>
1352
+
<reg32 offset="0x8213" name="GRAS_MODE_CNTL" low="0" high="1" variants="A8XX-" usage="cmd"/>
2077
1353
2078
1354
<!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
2079
1355
<reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX"/>
1356
+
<reg32 offset="0x810d" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A8XX-"/>
2080
1357
2081
-
<bitset name="a6xx_gras_lrz_depth_buffer_info" inline="yes">
2082
-
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2083
-
<bitfield name="UNK3" pos="3"/>
2084
-
</bitset>
2085
-
2086
-
<reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_gras_lrz_depth_buffer_info" variants="A7XX" usage="rp_blit"/>
1358
+
<reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX" usage="rp_blit"/>
1359
+
<reg32 offset="0x810f" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX" usage="rp_blit"/>
2087
1360
2088
1361
<doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc>
2089
-
<array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX-" stride="1" length="2"/>
1362
+
<array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX" stride="1" length="2"/>
1363
+
<array offset="0x8130" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A8XX-" stride="1" length="2"/>
2090
1364
2091
-
<!-- 0x8112-0x83ff invalid -->
1365
+
<reg32 offset="0x810c" name="GRAS_LRZ_COLOR_COMP_MASK" variants="A8XX-">
1366
+
<bitfield name="MRT0" low="0" high="3"/>
1367
+
<bitfield name="MRT1" low="4" high="7"/>
1368
+
<bitfield name="MRT2" low="8" high="11"/>
1369
+
<bitfield name="MRT3" low="12" high="15"/>
1370
+
<bitfield name="MRT4" low="16" high="19"/>
1371
+
<bitfield name="MRT5" low="20" high="23"/>
1372
+
<bitfield name="MRT6" low="24" high="27"/>
1373
+
<bitfield name="MRT7" low="28" high="31"/>
1374
+
</reg32>
2092
1375
2093
1376
<enum name="a6xx_rotation">
2094
1377
<value value="0x0" name="ROTATE_0"/>
···
2109
1372
<value value="0x5" name="ROTATE_VFLIP"/>
2110
1373
</enum>
2111
1374
2112
-
<bitset name="a6xx_a2d_bit_cntl" inline="yes">
1375
+
<bitset name="a6xx_a2d_blt_cntl" inline="yes">
2113
1376
<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2114
1377
<bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
2115
1378
<bitfield name="UNK4" low="4" high="6"/>
···
2128
1391
<bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/>
2129
1392
</bitset>
2130
1393
2131
-
<reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
1394
+
<reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2132
1395
<!-- note: the low 8 bits for src coords are valid, probably fixed point
2133
1396
it would be a bit weird though, since we subtract 1 from BR coords
2134
1397
apparently signed, gallium driver uses negative coords and it works?
···
2145
1408
<reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
2146
1409
<reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
2147
1410
1411
+
<reg32 offset="0x8500" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A8XX-" usage="rp_blit"/>
1412
+
<reg32 offset="0x8501" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/>
1413
+
<reg32 offset="0x8502" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/>
1414
+
<reg32 offset="0x8503" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/>
1415
+
<reg32 offset="0x8504" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/>
1416
+
<reg32 offset="0x8505" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
1417
+
<reg32 offset="0x8506" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
1418
+
<reg32 offset="0x8507" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
1419
+
<reg32 offset="0x8508" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
1420
+
2148
1421
<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
2149
-
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd">
1422
+
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="init" variants="A6XX-A7XX">
2150
1423
<bitfield name="UNK7" pos="7" type="boolean"/>
2151
1424
<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
2152
1425
</reg32>
2153
-
<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2154
-
<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
2155
-
<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
2156
-
<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
2157
-
<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
1426
+
<reg32 offset="0x8600" name="GRAS_TSEFE_DBG_ECO_CNTL" variants="A8XX-"/>
1427
+
<reg32 offset="0x8702" name="GRAS_DBG_ECO_CNTL" variants="A8XX"/>
1428
+
<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/>
1429
+
<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX"/>
1430
+
<reg32 offset="0x8700" name="GRAS_NC_MODE_CNTL" variants="A8XX-"/>
1431
+
<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4" variants="A6XX-A7XX"/>
1432
+
<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A6XX-A7XX"/>
1433
+
<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4" variants="A6XX-A7XX"/>
1434
+
1435
+
<array offset="0x8610" name="GRAS_PERFCTR_TSEFE_SEL" stride="1" length="6" variants="A8XX-"/>
1436
+
<array offset="0x8710" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="6" variants="A8XX-"/>
1437
+
<array offset="0x8720" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A8XX-"/>
1438
+
<array offset="0x8730" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="6" variants="A8XX-"/>
1439
+
2158
1440
2159
1441
<!-- note 0x8620-0x87ff are not all invalid
2160
1442
(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
···
2181
1425
2182
1426
<!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
2183
1427
<reg32 offset="0x8800" name="RB_CNTL" variants="A6XX-A7XX" type="a6xx_bin_cntl" usage="rp_blit"/>
1428
+
<reg32 offset="0x8800" name="RB_CNTL" variants="A8XX-" type="a8xx_bin_cntl" usage="rp_blit"/>
2184
1429
2185
1430
<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">
2186
1431
<bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
···
2219
1462
<reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/>
2220
1463
<reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/>
2221
1464
<reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/>
2222
-
<!-- 0x8807-0x8808 invalid -->
1465
+
<reg32 offset="0x8807" name="RB_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A8XX-"/>
1466
+
<reg32 offset="0x8808" name="RB_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A8XX-"/>
2223
1467
<!--
2224
1468
note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2225
1469
name comes from kernel and is probably right)
···
2234
1476
<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
2235
1477
<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
2236
1478
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2237
-
<bitfield name="UNK10" pos="10" type="boolean"/>
1479
+
<bitfield name="INTERP_EN" pos="10" type="boolean"/>
2238
1480
</reg32>
2239
1481
<reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="rp_blit">
2240
1482
<!-- enable bits for various FS sysvalue regs: -->
···
2292
1534
<reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="rp_blit">
2293
1535
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2294
1536
</reg32>
2295
-
<reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>
2296
-
<reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
1537
+
<reg32 offset="0x8811" name="RB_MODE_CNTL" low="4" high="6" usage="cmd"/>
1538
+
<reg32 offset="0x8812" name="RB_BUFFER_CNTL" variants="A7XX-" usage="rp_blit">
1539
+
<bitfield name="Z_SYSMEM" pos="0" type="boolean"/>
1540
+
<bitfield name="S_SYSMEM" pos="1" type="boolean"/>
1541
+
<bitfield name="RT0_SYSMEM" pos="2" type="boolean"/>
1542
+
<bitfield name="RT1_SYSMEM" pos="3" type="boolean"/>
1543
+
<bitfield name="RT2_SYSMEM" pos="4" type="boolean"/>
1544
+
<bitfield name="RT3_SYSMEM" pos="5" type="boolean"/>
1545
+
<bitfield name="RT4_SYSMEM" pos="6" type="boolean"/>
1546
+
<bitfield name="RT5_SYSMEM" pos="7" type="boolean"/>
1547
+
<bitfield name="RT6_SYSMEM" pos="8" type="boolean"/>
1548
+
<bitfield name="RT7_SYSMEM" pos="9" type="boolean"/>
1549
+
<bitfield name="Z_FULL_IN_GMEM" pos="10" type="boolean" variants="A8XX-"/>
1550
+
<bitfield name="S_FULL_IN_GMEM" pos="11" type="boolean" variants="A8XX-"/>
1551
+
<bitfield name="RT0_FULL_IN_GMEM" pos="12" type="boolean" variants="A8XX-"/>
1552
+
<bitfield name="RT1_FULL_IN_GMEM" pos="13" type="boolean" variants="A8XX-"/>
1553
+
<bitfield name="RT2_FULL_IN_GMEM" pos="14" type="boolean" variants="A8XX-"/>
1554
+
<bitfield name="RT3_FULL_IN_GMEM" pos="15" type="boolean" variants="A8XX-"/>
1555
+
<bitfield name="RT4_FULL_IN_GMEM" pos="16" type="boolean" variants="A8XX-"/>
1556
+
<bitfield name="RT5_FULL_IN_GMEM" pos="17" type="boolean" variants="A8XX-"/>
1557
+
<bitfield name="RT6_FULL_IN_GMEM" pos="18" type="boolean" variants="A8XX-"/>
1558
+
<bitfield name="RT7_FULL_IN_GMEM" pos="19" type="boolean" variants="A8XX-"/>
1559
+
</reg32>
1560
+
1561
+
<reg32 offset="0x8816" name="RB_RESOLVE_CR_CNTL" variants="A8XX-" usage="rp_blit"/>
1562
+
2297
1563
<!-- 0x8813-0x8817 invalid -->
2298
1564
<!-- always 0x0 ? -->
2299
1565
<reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>
···
2328
1546
<reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/>
2329
1547
<reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/>
2330
1548
<reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/>
2331
-
<!-- 0x881f invalid -->
1549
+
1550
+
<!-- Duplicates fields from SP_PS_CNTL_0 -->
1551
+
<reg32 offset="0x881f" name="RB_PS_CNTL" variants="A8XX-" usage="rp_blit">
1552
+
<bitfield name="PIXLODENABLE" pos="0" type="boolean"/>
1553
+
<bitfield name="LODPIXMASK" pos="1" type="boolean"/>
1554
+
</reg32>
1555
+
2332
1556
<array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit">
2333
1557
<reg32 offset="0x0" name="CONTROL">
2334
-
<bitfield name="BLEND" pos="0" type="boolean"/>
2335
-
<bitfield name="BLEND2" pos="1" type="boolean"/>
1558
+
<bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/>
1559
+
<bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/>
2336
1560
<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2337
1561
<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2338
1562
<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
···
2401
1613
<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2402
1614
<bitfield name="SAMPLE_MASK" low="16" high="31"/>
2403
1615
</reg32>
2404
-
<!-- 0x8866-0x886f invalid -->
1616
+
<reg32 offset="0x8866" name="RB_LB_PARAM_LIMIT" variants="A8XX-" usage="rp_blit">
1617
+
<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
1618
+
</reg32>
2405
1619
<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" usage="rp_blit"/>
2406
1620
2407
1621
<reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit">
···
2417
1627
</doc>
2418
1628
<bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
2419
1629
<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
1630
+
<!-- clamp shader depth out to [0, 1] (instead of RB_VIEWPORT_ZCLAMP_MIN/MAX)-->
1631
+
<bitfield name="O_DEPTH_01_CLAMP_EN" pos="8" type="boolean" variants="A8XX-"/>
2420
1632
</reg32>
2421
1633
2422
1634
<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2423
1635
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" type="a6xx_depth_buffer_info" usage="rp_blit"/>
2424
1636
<!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
2425
-
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
2426
-
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2427
-
<bitfield name="UNK3" low="3" high="4"/>
1637
+
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX-" usage="rp_blit">
1638
+
<bitfield name="PRT" low="3" high="4"/>
2428
1639
<bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>
2429
1640
<bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/>
2430
1641
</reg32>
···
2493
1702
<reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">
2494
1703
<bitfield name="ENABLE" pos="0" type="boolean"/>
2495
1704
</reg32>
2496
-
<reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
1705
+
<reg32 offset="0x8899" name="RB_LRZ_CNTL2" variants="A7XX-" usage="cmd">
1706
+
<bitfield name="ENABLE_BIDIRECTIONAL_LRZ" pos="0" type="boolean"/>
1707
+
</reg32>
2497
1708
<!-- 0x8899-0x88bf invalid -->
2498
1709
<!-- clamps depth value for depth test/write -->
2499
1710
<reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit" variants="A6XX-A7XX"/>
2500
1711
<reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit" variants="A6XX-A7XX"/>
1712
+
1713
+
<!-- todo allow type="float" on an <array/> -->
1714
+
<array offset="0x88b0" name="RB_VIEWPORT_ZCLAMP_MIN" stride="1" length="16" usage="rp_blit" variants="A8XX-">
1715
+
<reg32 offset="0" name="REG" type="float"/>
1716
+
</array>
1717
+
<array offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MAX" stride="1" length="16" usage="rp_blit" variants="A8XX-">
1718
+
<reg32 offset="0" name="REG" type="float"/>
1719
+
</array>
2501
1720
2502
1721
<!-- 0x88c2-0x88cf invalid-->
2503
1722
<reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit">
···
2521
1720
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2522
1721
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2523
1722
</reg32>
1723
+
1724
+
<reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/>
1725
+
<reg32 offset="0x88f0" name="RB_RESOLVE_CNTL_4" variants="A8XX-" usage="rp_blit"/>
1726
+
<reg32 offset="0x88f1" name="RB_RESOLVE_CNTL_5" variants="A8XX-" usage="rp_blit"/>
1727
+
2524
1728
<reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
2525
1729
<reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="rp_blit">
2526
1730
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
···
2604
1798
<value value="0x1" name="CCU_CACHE_SIZE_HALF"/>
2605
1799
<value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>
2606
1800
<value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>
1801
+
<!-- for DEPTH_CACHE_SIZE 3 == THREE_QUARTER from KNP -->
1802
+
<value value="0x3" name="CCU_CACHE_SIZE_THREE_QUARTER"/>
2607
1803
</enum>
2608
-
<reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX-" usage="cmd">
1804
+
<reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX" usage="cmd">
2609
1805
<bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
2610
1806
<bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>
2611
1807
<bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
···
2622
1814
-->
2623
1815
<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
2624
1816
</reg32>
2625
-
<!-- 0x88e6-0x88ef invalid -->
1817
+
1818
+
<reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A8XX-" usage="cmd">
1819
+
<!--
1820
+
For color cache, full is 128KB per CCU. For depth cache,
1821
+
full is 256KB per CCU.
1822
+
1823
+
For attr/pos caches (see VPC_{ATTR,POS,BV_POS}_BUF_GMEM_SIZE),
1824
+
the sizes are per CCU
1825
+
-->
1826
+
<bitfield name="COLOR_OFFSET" low="0" high="13" shr="12" type="hex"/>
1827
+
<bitfield name="COLOR_CACHE_SIZE" low="14" high="15" type="a6xx_ccu_cache_size"/>
1828
+
<bitfield name="DEPTH_OFFSET" low="16" high="29" shr="12" type="hex"/>
1829
+
<bitfield name="DEPTH_CACHE_SIZE" low="30" high="31" type="a6xx_ccu_cache_size"/>
1830
+
</reg32>
1831
+
1832
+
<reg32 offset="0x88e6" name="RB_RESOLVE_GMEM_BUFFER_CNTL" variants="A8XX-">
1833
+
<bitfield name="FULL_IN_GMEM" pos="0" type="boolean"/>
1834
+
</reg32>
1835
+
2626
1836
<!-- always 0x0 ? -->
2627
-
<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>
1837
+
<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" variants="A6XX" usage="cmd"/>
2628
1838
<!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2629
-
<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2630
-
<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch"/>
1839
+
<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64" variants="A6XX"/>
1840
+
<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" variants="A6XX"/>
2631
1841
2632
1842
<reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit">
2633
1843
<bitfield name="UNK2" pos="2" type="boolean"/>
···
2675
1849
the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT.
2676
1850
</doc>
2677
1851
<reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/>
2678
-
<!-- 0x8929-0x89ff invalid -->
2679
1852
2680
-
<!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
1853
+
<bitset name="a8xx_gmem_dimension" inline="yes">
1854
+
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
1855
+
<bitfield name="HEIGHT" low="16" high="30" type="uint"/>
1856
+
</bitset>
1857
+
1858
+
<reg32 offset="0x8813" name="RB_DEPTH_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/>
1859
+
<reg32 offset="0x8814" name="RB_STENCIL_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/>
1860
+
<reg32 offset="0x8815" name="RB_RESOLVE_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/>
1861
+
1862
+
<array offset="0x8930" name="RB_MRT_GMEM_DIMENSION" variants="A8XX-" stride="1" length="8">
1863
+
<reg32 offset="0" name="REG" type="a8xx_gmem_dimension"/>
1864
+
</array>
2681
1865
2682
1866
<!--
2683
1867
These show up in a6xx gen3+ but so far haven't found an example of
···
2698
1862
<reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/>
2699
1863
<reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/>
2700
1864
2701
-
<reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/>
1865
+
<reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" usage="rp_blit"/>
2702
1866
<reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="rp_blit"/>
2703
1867
2704
1868
<bitset name="a6xx_a2d_src_texture_info" inline="yes">
···
2757
1921
<!-- 0x8c35-0x8dff invalid -->
2758
1922
2759
1923
<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2760
-
<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>
1924
+
<reg32 offset="0x8e01" name="RB_RBP_CNTL" usage="cmd"/>
2761
1925
<!-- 0x8e00-0x8e03 invalid -->
2762
1926
<reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
2763
-
<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
1927
+
<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/>
2764
1928
<!-- 0x02080000 in GMEM, zero otherwise? -->
2765
1929
<reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/>
2766
1930
···
2799
1963
<bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/>
2800
1964
<!-- rest of the bits were moved to RB_CCU_CACHE_CNTL -->
2801
1965
</reg32>
2802
-
<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
1966
+
<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL" variants="A6XX-A7XX">
2803
1967
<bitfield name="MODE" pos="0" type="boolean"/>
2804
1968
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
2805
1969
<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
···
2808
1972
<bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
2809
1973
<bitfield name="UNK12" low="12" high="13"/>
2810
1974
</reg32>
2811
-
<reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
1975
+
<reg32 offset="0x8e08" name="RB_CCU_NC_MODE_CNTL" variants="A8XX-"/>
1976
+
1977
+
<reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX" usage="cmd"/>
1978
+
<reg32 offset="0x8e09" name="RB_GC_GMEM_PROTECT" variants="A8XX-"/>
1979
+
<reg32 offset="0x8e0a" name="RB_LPAC_GMEM_PROTECT" variants="A8XX-"/>
2812
1980
<!-- 0x8e09-0x8e0f invalid -->
2813
1981
<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
2814
1982
<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
2815
1983
<!-- 0x8e1d-0x8e1f invalid -->
2816
1984
<!-- 0x8e20-0x8e25 more perfcntr sel? -->
2817
1985
<!-- 0x8e26-0x8e27 invalid -->
2818
-
<reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/>
1986
+
1987
+
<reg32 offset="0x8f00" name="RB_CMP_NC_MODE_CNTL" variants="A8XX-"/>
1988
+
<reg32 offset="0x8f01" name="RB_RESOLVE_PREFETCH_CNTL" variants="A8XX-"/>
1989
+
<reg32 offset="0x8f02" name="RB_CMP_DBG_ECO_CNTL" variants="A8XX-"/>
1990
+
1991
+
<reg32 offset="0x8f03" name="RB_UNSLICE_STATUS" variants="A8XX-"/>
1992
+
<reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL" variants="A6XX-A7XX"/>
2819
1993
<!-- 0x8e29-0x8e2b invalid -->
2820
-
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
2821
-
<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
2822
-
<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
2823
-
<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1994
+
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A6XX-A7XX"/>
1995
+
<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX"/>
1996
+
<array offset="0x8f04" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A8XX-"/>
1997
+
<array offset="0x8f10" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A8XX-"/>
1998
+
<reg32 offset="0x8e3b" name="RB_SUB_BLOCK_SEL_CNTL_HOST"/>
1999
+
<reg32 offset="0x8e3d" name="RB_SUB_BLOCK_SEL_CNTL_CD"/>
2000
+
<reg32 offset="0x8f29" name="RB_UFC_DBG_CNTL" variants="A8XX-"/>
2824
2001
<!-- 0x8e3e-0x8e4f invalid -->
2825
2002
<!-- GMEM save/restore for preemption: -->
2826
2003
<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/>
2827
2004
<!-- address for GMEM save/restore? -->
2828
2005
<reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/>
2829
-
<!-- 0x8e53-0x8e7f invalid -->
2830
-
<reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
2006
+
<reg32 offset="0x8e77" name="RB_SLICE_UFC_PREFETCH_CNTL" variants="A8XX-"/>
2007
+
<reg32 offset="0x8e78" name="RB_SLICE_UFC_DBG_CNTL" variants="A8XX-"/>
2008
+
<reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX" usage="init"/>
2831
2009
<!-- 0x8e80-0x8e83 are valid -->
2832
2010
<!-- 0x8e84-0x90ff invalid -->
2833
2011
···
2864
2014
<reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2865
2015
<reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2866
2016
2017
+
<reg32 offset="0x9307" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/>
2018
+
<reg32 offset="0x9308" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/>
2019
+
<reg32 offset="0x9309" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/>
2020
+
2867
2021
<reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2868
2022
<reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2869
2023
<reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
···
2882
2028
<reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2883
2029
<reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2884
2030
2031
+
<reg32 offset="0x930a" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/>
2032
+
<reg32 offset="0x930b" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/>
2033
+
<reg32 offset="0x930c" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/>
2885
2034
2886
2035
<reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2887
2036
<reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
···
2899
2042
2900
2043
<reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="rp_blit"/>
2901
2044
<reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/>
2045
+
<reg32 offset="0x930d" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A8XX-" usage="rp_blit"/>
2902
2046
<reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/>
2903
2047
2904
2048
<reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit">
···
2909
2051
</reg32>
2910
2052
2911
2053
<reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2054
+
<reg32 offset="0x930e" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/>
2912
2055
<bitset name="a6xx_pc_cntl" inline="yes">
2913
2056
<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2914
2057
<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
···
2950
2091
</bitset>
2951
2092
2952
2093
<reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX" usage="rp_blit"/>
2094
+
<reg32 offset="0x930f" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="rp_blit"/>
2953
2095
<reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX" usage="rp_blit"/>
2096
+
<reg32 offset="0x90c0" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="rp_blit"/>
2954
2097
<reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX" usage="rp_blit"/>
2098
+
<reg32 offset="0x90c1" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="rp_blit"/>
2955
2099
<reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX" usage="rp_blit"/>
2100
+
<reg32 offset="0x931a" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="rp_blit"/>
2956
2101
2957
2102
<enum name="a6xx_varying_interp_mode">
2958
2103
<value value="0" name="INTERP_SMOOTH"/>
···
2982
2119
<reg32 offset="0x0" name="MODE"/>
2983
2120
</array>
2984
2121
2122
+
<array offset="0x9240" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A8XX-" usage="rp_blit">
2123
+
<doc>Packed array of a6xx_varying_interp_mode</doc>
2124
+
<reg32 offset="0x0" name="MODE"/>
2125
+
</array>
2126
+
<array offset="0x9248" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A8XX-" usage="rp_blit">
2127
+
<doc>Packed array of a6xx_varying_ps_repl_mode</doc>
2128
+
<reg32 offset="0x0" name="MODE"/>
2129
+
</array>
2130
+
2985
2131
<!-- always 0x0 -->
2986
2132
<reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>
2987
2133
<reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>
2988
2134
2989
2135
<array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A6XX-A7XX" usage="rp_blit">
2136
+
<!-- one bit per varying component: -->
2137
+
<reg32 offset="0" name="DISABLE"/>
2138
+
</array>
2139
+
2140
+
<array offset="0x9252" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A8XX-" usage="rp_blit">
2990
2141
<!-- one bit per varying component: -->
2991
2142
<reg32 offset="0" name="DISABLE"/>
2992
2143
</array>
···
3035
2158
</bitset>
3036
2159
3037
2160
<reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A6XX-A7XX" usage="rp_blit"/>
2161
+
<reg32 offset="0x9180" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A8XX-" usage="rp_blit"/>
3038
2162
3039
2163
<bitset name="a6xx_vpc_so_mapping_port" inline="yes">
3040
2164
<bitfield name="A_BUF" low="0" high="1" type="uint"/>
···
3048
2170
3049
2171
<!-- special register, write multiple times to load SO program (not readable) -->
3050
2172
<reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A6XX-A7XX" usage="rp_blit"/>
2173
+
<reg32 offset="0x9181" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A8XX-" usage="rp_blit"/>
3051
2174
3052
2175
<reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A6XX-A7XX" usage="cmd"/>
2176
+
<reg64 offset="0x9182" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A8XX-" usage="cmd"/>
3053
2177
3054
2178
<array offset="0x921a" name="VPC_SO" stride="7" length="4" variants="A6XX-A7XX" usage="cmd">
2179
+
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
2180
+
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
2181
+
<reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
2182
+
<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
2183
+
<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
2184
+
</array>
2185
+
2186
+
<array offset="0x9184" name="VPC_SO" stride="7" length="4" variants="A8XX-" usage="cmd">
3055
2187
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
3056
2188
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
3057
2189
<reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
···
3074
2186
</bitset>
3075
2187
3076
2188
<reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A6XX-A7XX" usage="cmd"/>
2189
+
<reg32 offset="0x9310" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A8XX-" usage="cmd"/>
3077
2190
3078
2191
<reg32 offset="0x9300" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A6XX-A7XX" usage="cmd"/>
2192
+
<reg32 offset="0x9312" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A8XX-" usage="cmd"/>
3079
2193
3080
2194
<bitset name="a6xx_vpc_xs_cntl" inline="yes">
3081
2195
<doc>
···
3101
2211
<reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
3102
2212
<reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
3103
2213
2214
+
<reg32 offset="0x9300" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2215
+
<reg32 offset="0x9301" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2216
+
<reg32 offset="0x9302" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2217
+
3104
2218
<bitset name="a6xx_vpc_ps_cntl" inline="yes">
3105
2219
<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
3106
2220
<!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
···
3125
2231
</bitset>
3126
2232
3127
2233
<reg32 offset="0x9304" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2234
+
<reg32 offset="0x9303" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A8XX-" usage="rp_blit"/>
3128
2235
3129
2236
<bitset name="a6xx_vpc_so_cntl" inline="yes">
3130
2237
<!--
···
3139
2244
</bitset>
3140
2245
3141
2246
<reg32 offset="0x9305" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2247
+
<reg32 offset="0x9304" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A8XX-" usage="rp_blit"/>
3142
2248
3143
2249
<bitset name="a6xx_so_override" inline="yes">
3144
2250
<bitfield name="DISABLE" pos="0" type="boolean"/>
3145
2251
</bitset>
3146
2252
3147
2253
<reg32 offset="0x9306" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A6XX-A7XX" usage="rp_blit"/>
2254
+
<reg32 offset="0x9305" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="rp_blit"/>
3148
2255
3149
2256
<reg32 offset="0x9807" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A7XX" usage="rp_blit"/>
2257
+
<reg32 offset="0x9b0a" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="rp_blit"/>
3150
2258
3151
2259
<reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2260
+
<reg32 offset="0x9306" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/>
3152
2261
3153
-
<reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/>
3154
-
<reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="uint" usage="rp_blit"/>
2262
+
<reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/>
2263
+
<reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="hex" usage="cmd"/>
3155
2264
3156
-
<reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/>
2265
+
<reg32 offset="0x9314" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
2266
+
<reg32 offset="0x9315" name="VPC_ATTR_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/>
2267
+
2268
+
<reg32 offset="0x9316" name="VPC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
2269
+
<reg32 offset="0x9317" name="VPC_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/>
2270
+
2271
+
<reg32 offset="0x9318" name="VPC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
2272
+
<reg32 offset="0x9319" name="VPC_BV_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/>
2273
+
2274
+
<reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/>
2275
+
<reg32 offset="0x9b16" name="PC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
2276
+
2277
+
<reg32 offset="0x9b17" name="PC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
2278
+
<reg32 offset="0x9b18" name="PC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
3157
2279
3158
2280
<reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/>
3159
2281
2282
+
<reg32 offset="0x9313" name="VPC_UNKNOWN_9313" variants="A8XX-"/>
2283
+
<reg32 offset="0x9e17" name="PC_UNKNOWN_9E17" variants="A8XX-"/>
2284
+
3160
2285
<reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/>
2286
+
<reg32 offset="0x9741" name="VPC_FLATSHADE_MODE_CNTL" variants="A8XX-"/>
3161
2287
3162
2288
<!-- 0x9307-0x95ff invalid -->
3163
2289
3164
2290
<!-- TODO: 0x9600-0x97ff range -->
3165
-
<reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
3166
-
<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/>
3167
-
<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
3168
-
<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
2291
+
<reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" variants="A6XX-A7XX" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2292
+
<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd" variants="A6XX"/>
2293
+
<reg32 offset="0x9680" name="VPC_DBG_ECO_CNTL" variants="A8XX-"/>
2294
+
<reg32 offset="0x9604" name="VPC_DBG_ECO_CNTL_2" variants="A8XX-"/>
2295
+
<reg32 offset="0x9742" name="VPC_DBG_ECO_CNTL_1" variants="A8XX-"/>
2296
+
<reg32 offset="0x9745" name="VPC_DBG_ECO_CNTL_3" variants="A8XX-"/>
2297
+
<reg32 offset="0x9602" name="VPC_LB_MODE_CNTL" pos="0" variants="A6XX-A7XX" usage="init"/> <!-- always 0x0 ? -->
2298
+
<reg32 offset="0x9740" name="VPC_LB_MODE_CNTL" pos="0" variants="A8XX-"/>
2299
+
<reg32 offset="0x9603" name="VPC_STATUS" low="0" high="26" variants="A6XX-A7XX"/>
2300
+
<reg32 offset="0x9600" name="VPC_STATUS" low="0" high="26" variants="A8XX-"/>
3169
2301
<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>
3170
-
<array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
3171
-
<!-- 0x960a-0x9623 invalid -->
3172
-
<!-- TODO: regs from 0x9624-0x963a -->
3173
-
<!-- 0x963b-0x97ff invalid -->
2302
+
<array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX"/>
2303
+
<array offset="0x9670" name="VPC_PERFCTR_VPC_SEL_2" stride="1" length="12" variants="A8XX-"/>
2304
+
<array offset="0x9690" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A8XX-"/>
2305
+
<array offset="0x9750" name="VPC_PERFCTR_VPC_SEL_1" stride="1" length="12" variants="A8XX-"/>
2306
+
2307
+
<reg64 offset="0x9634" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A6XX-A7XX"/>
2308
+
<reg64 offset="0x9602" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A8XX-"/>
2309
+
2310
+
<reg32 offset="0x980b" name="PC_UNKNOWN_980B" variants="A8XX-"/>
3174
2311
3175
2312
<reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A6XX-A7XX" usage="rp_blit"/>
2313
+
<reg32 offset="0x9b10" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A8XX-" usage="rp_blit"/>
3176
2314
3177
2315
<bitset name="a6xx_pc_hs_param_1" inline="yes">
3178
2316
<bitfield name="SIZE" low="0" high="10" type="uint"/>
···
3213
2285
</bitset>
3214
2286
3215
2287
<reg32 offset="0x9801" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A6XX-A7XX" usage="rp_blit"/>
2288
+
<reg32 offset="0x9b11" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A8XX-" usage="rp_blit"/>
3216
2289
3217
2290
<bitset name="a6xx_pc_ds_param" inline="yes">
3218
2291
<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
···
3221
2292
</bitset>
3222
2293
3223
2294
<reg32 offset="0x9802" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A6XX-A7XX" usage="rp_blit"/>
2295
+
<reg32 offset="0x9b12" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A8XX-" usage="rp_blit"/>
3224
2296
3225
2297
<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="rp_blit"/>
2298
+
<reg32 offset="0x9b15" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A8XX-" usage="rp_blit"/>
3226
2299
3227
2300
<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="rp_blit"/>
2301
+
<reg32 offset="0x9b00" name="PC_MODE_CNTL" low="0" high="14" variants="A8XX" usage="rp_blit"/>
3228
2302
3229
2303
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
3230
2304
···
3236
2304
</bitset>
3237
2305
3238
2306
<reg32 offset="0x9806" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2307
+
<reg32 offset="0x9b06" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A8XX-" usage="rp_blit"/>
3239
2308
3240
2309
<bitset name="a6xx_pc_dgen_so_cntl" inline="yes">
3241
2310
<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
···
3244
2311
3245
2312
<!-- New in a6xx gen3+ -->
3246
2313
<reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2314
+
<reg32 offset="0x9b0b" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A8XX-" usage="rp_blit"/>
3247
2315
3248
2316
<bitset name="a6xx_pc_dgen_su_conservative_ras_cntl" inline="yes">
3249
2317
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
3250
2318
</bitset>
3251
2319
3252
2320
<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A6XX-A7XX"/>
2321
+
<reg32 offset="0x9b08" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A8XX-"/>
2322
+
2323
+
<reg32 offset="0x9b0c" name="PC_VS_INPUT_CNTL" variants="A8XX-" usage="rp_blit">
2324
+
<bitfield name="INSTR_CNT" low="0" high="5" type="uint"/>
2325
+
<bitfield name="SIDEBAND_CNT" low="6" high="8" type="uint"/>
2326
+
</reg32>
3253
2327
3254
2328
<!-- 0x9840 - 0x9842 are not readable -->
3255
2329
<bitset name="a6xx_draw_initiator" inline="yes">
···
3266
2326
<reg32 offset="0x9840" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/>
3267
2327
<reg32 offset="0x9841" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/>
3268
2328
2329
+
<reg32 offset="0x9800" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/>
2330
+
<reg32 offset="0x9801" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/>
2331
+
3269
2332
<bitset name="a6xx_event_initiator" inline="yes">
3270
2333
<!-- I think only the low bit is actually used? -->
3271
2334
<bitfield name="STATE_ID" low="16" high="23"/>
···
3276
2333
</bitset>
3277
2334
3278
2335
<reg32 offset="0x9842" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A6XX-A7XX"/>
2336
+
<reg32 offset="0x9802" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A8XX-"/>
3279
2337
3280
2338
<!--
3281
2339
0x9880 written in a lot of places by SQE, same value gets written
···
3289
2345
3290
2346
<reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX" usage="rp_blit"/>
3291
2347
<reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A7XX" usage="rp_blit"/>
2348
+
<reg32 offset="0x9812" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX" usage="rp_blit"/>
3292
2349
3293
2350
<!-- Both are a750+.
3294
2351
Probably needed to correctly overlap execution of several draws.
3295
2352
-->
3296
2353
<reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX" usage="cmd"/>
2354
+
<reg32 offset="0x9814" name="PC_HS_BUFFER_SIZE" variants="A8XX-" usage="cmd"/>
3297
2355
<!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
3298
2356
this additional space is not known.
3299
2357
-->
3300
2358
<reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/>
2359
+
<reg32 offset="0x9815" name="PC_TF_BUFFER_SIZE" variants="A8XX-" usage="cmd"/>
3301
2360
3302
2361
<!-- 0x9982-0x9aff invalid -->
3303
2362
3304
2363
<reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2364
+
<reg32 offset="0x9b01" name="PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="rp_blit"/>
3305
2365
3306
2366
<bitset name="a6xx_pc_xs_cntl" inline="yes">
3307
2367
<doc>
···
3329
2381
<reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
3330
2382
<reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
3331
2383
2384
+
<reg32 offset="0x9b02" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2385
+
<reg32 offset="0x9b03" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2386
+
<reg32 offset="0x9b04" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2387
+
<reg32 offset="0x9b05" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/>
2388
+
3332
2389
<reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A6XX-A7XX" usage="rp_blit"/>
2390
+
<reg32 offset="0x9b13" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="rp_blit"/>
3333
2391
3334
2392
<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit">
3335
2393
<doc>
···
3345
2391
</reg32>
3346
2392
3347
2393
<reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2394
+
<reg32 offset="0x9b09" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="rp_blit"/>
3348
2395
<!-- mask of enabled views, doesn't exist on A630 -->
3349
2396
<reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A6XX-A7XX" usage="rp_blit"/>
2397
+
<reg32 offset="0x9b0d" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="rp_blit"/>
3350
2398
<!-- 0x9b09-0x9bff invalid -->
3351
2399
<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
3352
2400
<!-- special register (but note first 8 bits can be written/read) -->
3353
2401
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3354
2402
<bitfield name="STATE_ID" low="8" high="15"/>
3355
2403
</reg32>
3356
-
<!-- 0x9c01-0x9dff invalid -->
3357
-
<!-- TODO: 0x9e00-0xa000 range incomplete -->
3358
-
<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
3359
-
<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2404
+
2405
+
<reg32 offset="0x9e50" name="PC_CHICKEN_BITS_1" variants="A8XX-"/>
2406
+
<reg32 offset="0x9f20" name="PC_CHICKEN_BITS_2" variants="A8XX-"/>
2407
+
<reg32 offset="0x9e22" name="PC_CHICKEN_BITS_3" variants="A8XX-"/>
2408
+
<reg32 offset="0x9e23" name="PC_CHICKEN_BITS_4" variants="A8XX-"/>
2409
+
<reg32 offset="0x9f23" name="PC_CHICKEN_BITS_5" variants="A8XX-"/>
2410
+
2411
+
<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL" variants="A6XX-A7XX"/>
2412
+
<reg32 offset="0x9e53" name="PC_DBG_ECO_CNTL" variants="A8XX-"/>
2413
+
<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
3360
2414
<reg64 offset="0x9e04" name="PC_DMA_BASE" type="address" variants="A6XX-A7XX"/>
3361
2415
<reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint" variants="A6XX-A7XX"/>
3362
2416
<reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint" variants="A6XX-A7XX"/>
3363
2417
2418
+
<reg64 offset="0x9e06" name="PC_DMA_BASE" type="address" variants="A8XX-"/>
2419
+
<reg32 offset="0x9e08" name="PC_DMA_OFFSET" type="uint" variants="A8XX-"/>
2420
+
<reg32 offset="0x9e09" name="PC_DMA_SIZE" type="uint" variants="A8XX-"/>
2421
+
3364
2422
<reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/>
3365
2423
<reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX" type="waddress" align="32" usage="cmd"/>
2424
+
<reg64 offset="0x9816" name="PC_TESS_BASE" variants="A8XX-" type="waddress" align="32" usage="cmd"/>
3366
2425
3367
2426
<reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A6XX-A7XX">
3368
2427
<doc>
···
3385
2418
</reg32>
3386
2419
<reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A6XX-A7XX"/>
3387
2420
<reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint" variants="A6XX-A7XX"/>
2421
+
2422
+
<reg32 offset="0x9e00" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A8XX-"/>
2423
+
<reg32 offset="0x9e01" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A8XX-"/>
2424
+
<reg32 offset="0x9e02" name="PC_DRAWCALL_SIZE" type="uint" variants="A8XX-"/>
3388
2425
3389
2426
<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
3390
2427
<bitset name="a6xx_pc_vis_stream_cntl" inline="yes">
···
3401
2430
<reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/>
3402
2431
<reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/>
3403
2432
2433
+
<reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE"/>
2434
+
<reg32 offset="0x9e0d" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A8XX-"/>
2435
+
<reg64 offset="0x9e0e" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/>
2436
+
<reg64 offset="0x9e10" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/>
2437
+
3404
2438
<bitset name="a6xx_pc_drawcall_cntl_override" inline="yes">
3405
2439
<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
3406
2440
<bitfield name="OVERRIDE" pos="0" type="boolean"/>
3407
2441
</bitset>
3408
2442
3409
2443
<reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A6XX-A7XX"/>
2444
+
<reg32 offset="0x9e04" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A8XX-"/>
3410
2445
3411
-
<reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
2446
+
<reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="init"/>
3412
2447
3413
2448
<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>
3414
-
<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
2449
+
<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX"/>
2450
+
<array offset="0x9e30" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/>
2451
+
<array offset="0x9f00" name="PC_SLICE_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/>
3415
2452
3416
2453
<!-- always 0x0 -->
3417
-
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/>
2454
+
<reg32 offset="0x9e72" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A6XX-A7XX" usage="init"/>
2455
+
<reg32 offset="0x9e63" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A8XX-"/>
2456
+
<reg32 offset="0x9e64" name="PC_CONTEXT_SWITCH_STABILIZE_CNTL_1" variants="A8XX-"/>
3418
2457
3419
2458
<reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit">
3420
2459
<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
···
3511
2530
3512
2531
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
3513
2532
3514
-
<reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/>
2533
+
<reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="init"/>
3515
2534
3516
-
<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2535
+
<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
3517
2536
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>
3518
2537
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
2538
+
<reg32 offset="0xa639" name="VFD_CB_BV_THRESHOLD" variants="A8XX-"/>
2539
+
<reg32 offset="0xa63a" name="VFD_CB_BR_THRESHOLD" variants="A8XX-"/>
2540
+
<reg32 offset="0xa63b" name="VFD_CB_BUSY_REQ_CNT" variants="A8XX-"/>
2541
+
<reg32 offset="0xa63c" name="VFD_CB_LP_REQ_CNT" variants="A8XX-"/>
3519
2542
3520
2543
<!--
3521
2544
Note: this seems to always be paired with another bit in another
···
3578
2593
<bitset name="a6xx_sp_xs_output_cntl" inline="yes">
3579
2594
<!-- # of VS outputs including pos/psize -->
3580
2595
<bitfield name="OUT" low="0" high="5" type="uint"/>
3581
-
<!-- FLAGS_REGID only for GS -->
3582
-
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
3583
2596
</bitset>
3584
2597
3585
2598
<reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
···
3703
2720
<bitfield name="OFFSET" low="0" high="18" shr="11"/>
3704
2721
</bitset>
3705
2722
2723
+
<bitset name="a6xx_sp_xs_hysteresis" inline="yes">
2724
+
<doc>Same on a6xx/a7xx, UMD should not need to write this</doc>
2725
+
</bitset>
2726
+
2727
+
<bitset name="a8xx_sp_xs_hysteresis" inline="yes">
2728
+
<doc>UMD needs to write in some cases</doc>
2729
+
<!-- seen 0x400, 0xc00, 0x1000, 0x1c00, 0x1000, 0x2000, 0x3000 -->
2730
+
</bitset>
2731
+
3706
2732
<reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/>
3707
2733
<reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/>
3708
2734
<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
···
3721
2729
<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3722
2730
<reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
3723
2731
<reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
2732
+
<reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
2733
+
<reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/>
3724
2734
<reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
3725
2735
3726
2736
<reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
···
3748
2754
<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3749
2755
<reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
3750
2756
<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
2757
+
<reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
2758
+
<reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/>
3751
2759
<reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
3752
2760
3753
2761
<reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
···
3787
2791
<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3788
2792
<reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
3789
2793
<reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
2794
+
<reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
2795
+
<reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/>
3790
2796
<reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
3791
2797
3792
2798
<reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
···
3812
2814
<reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/>
3813
2815
3814
2816
<!-- TODO: exact same layout as 0xa802-0xa81a -->
3815
-
<reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/>
2817
+
<reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit">
2818
+
<!-- FLAGS_REGID only for GS -->
2819
+
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2820
+
</reg32>
3816
2821
<array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit">
3817
2822
<reg32 offset="0x0" name="REG">
3818
2823
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
···
3844
2843
<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3845
2844
<reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
3846
2845
<reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
2846
+
<reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
2847
+
<reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/>
3847
2848
<reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
3848
2849
3849
2850
<reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/>
···
3889
2886
<reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/>
3890
2887
<reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
3891
2888
3892
-
<reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit">
2889
+
<bitset name="a6xx_sp_blend_cntl" inline="yes">
3893
2890
<!-- per-mrt enable bit -->
3894
2891
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
3895
-
<bitfield name="UNK8" pos="8" type="boolean"/>
2892
+
<bitfield name="INDEPENDENT_BLEND_EN" pos="8" type="boolean"/>
3896
2893
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3897
2894
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2895
+
</bitset>
2896
+
2897
+
<reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
2898
+
<reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A8XX-" usage="rp_blit">
2899
+
<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean" variants="A8XX-"/>
3898
2900
</reg32>
2901
+
3899
2902
<reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit">
3900
2903
<!-- Same as RB_SRGB_CNTL -->
3901
2904
<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
···
4002
2993
<reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/>
4003
2994
<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
4004
2995
<reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
4005
-
<reg32 offset="0xa9ab" name="SP_PS_UNKNOWN_A9AB" variants="A7XX-" usage="cmd"/>
2996
+
<reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
2997
+
<reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/>
4006
2998
4007
2999
<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
4008
-
4009
-
4010
-
4011
3000
4012
3001
<reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="cmd">
4013
3002
<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
···
4043
3036
must be at least the actual CONSTLEN.
4044
3037
</doc>
4045
3038
</bitfield>
3039
+
<bitfield name="ALT_LM_ENCODE" pos="26" type="boolean"/>
4046
3040
</reg32>
4047
3041
<reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="cmd"/>
4048
3042
<reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/>
···
4055
3047
<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>
4056
3048
<reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/>
4057
3049
<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/>
4058
-
<reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
3050
+
<reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
3051
+
<reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/>
4059
3052
<reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
4060
3053
4061
3054
<!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 -->
···
4167
3158
<bitfield name="RT7" low="28" high="31"/>
4168
3159
</reg32>
4169
3160
3161
+
<array offset="0xaa04" name="SP_MRT_BLEND_CNTL" stride="1" length="8" variants="A8XX-">
3162
+
<reg32 offset="0" name="REG">
3163
+
<bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/>
3164
+
<bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/>
3165
+
<bitfield name="COMPONENT_WRITE_MASK" low="7" high="10"/>
3166
+
</reg32>
3167
+
</array>
3168
+
3169
+
<reg32 offset="0xaa0c" name="SP_ALPHA_TEST_CNTL" variants="A8XX-">
3170
+
<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
3171
+
</reg32>
3172
+
4170
3173
<reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/>
4171
3174
4172
3175
<!--
···
4203
3182
-->
4204
3183
<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
4205
3184
<bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
4206
-
<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
3185
+
<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see SP_SHARED_CONSTANT -->
4207
3186
</reg32>
4208
3187
4209
3188
<reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
4210
-
<reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
3189
+
<reg32 offset="0xab02" name="SP_HLSQ_MODE_CNTL" variants="A7XX-" usage="cmd">
3190
+
<bitfield name="SHARED_CONSTS_ENABLE" pos="0" type="boolean"/> <!-- see SP_SHARED_CONSTANT -->
3191
+
</reg32>
4211
3192
4212
3193
<reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
4213
3194
<reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
3195
+
3196
+
<reg32 offset="0xab06" name="SP_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/>
4214
3197
4215
3198
<array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
4216
3199
<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
···
4235
3210
-->
4236
3211
<reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/>
4237
3212
<reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A6XX-A7XX" usage="cmd"/>
3213
+
<reg32 offset="0xab09" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A8XX-" usage="cmd"/>
4238
3214
4239
3215
<reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX" usage="cmd"/>
3216
+
3217
+
<reg32 offset="0xab23" name="SP_UNKNOWN_AB23" variants="A8XX-"/>
4240
3218
4241
3219
<enum name="a6xx_sp_a2d_output_ifmt_type">
4242
3220
<value name="OUTPUT_IFMT_2D_FLOAT" value="0"/>
···
4262
3234
<reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="rp_blit"/>
4263
3235
<reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="rp_blit"/>
4264
3236
4265
-
<reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/>
4266
-
<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
3237
+
<reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="init"/>
3238
+
<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/>
3239
+
<reg32 offset="0xae01" name="SP_SHADER_PROFILING" variants="A8XX-"/>
4267
3240
<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
4268
3241
<!-- TODO: valid bits 0x3c3f, see kernel -->
4269
3242
</reg32>
4270
-
<reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/>
4271
-
<reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="cmd">
3243
+
<reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="init"/>
3244
+
<reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="init">
4272
3245
<bitfield name="F16_NO_INF" pos="3" type="boolean"/>
4273
3246
</reg32>
4274
3247
4275
-
<reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
4276
-
<reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="cmd"/>
4277
-
<reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="cmd"/>
4278
-
<reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="cmd"/>
3248
+
<reg32 offset="0xae05" name="SP_SS_CHICKEN_BITS_0" variants="A8XX-"/>
3249
+
<reg32 offset="0xae06" name="SP_ISDB_CNTL" variants="A7XX-" usage="init"/>
3250
+
<reg32 offset="0xae07" name="SP_PERFCTR_CNTL"/>
3251
+
<reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="init"/>
3252
+
<reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="init"/>
3253
+
<reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/>
3254
+
<reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/>
3255
+
<reg32 offset="0xae0c" name="SP_STATUS"/>
4279
3256
4280
-
<reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="cmd">
3257
+
<reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init">
4281
3258
<!-- some perfcntrs are affected by a per-stage enable bit
4282
3259
(PERF_SP_ALU_WORKING_CYCLES for example)
4283
3260
TODO: verify position of HS/DS/GS bits -->
···
4293
3260
<bitfield name="FS" pos="4" type="boolean"/>
4294
3261
<bitfield name="CS" pos="5" type="boolean"/>
4295
3262
</reg32>
4296
-
<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
3263
+
<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24" variants="A6XX"/>
4297
3264
<array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
4298
-
<reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
4299
-
<reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
4300
-
<reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/>
3265
+
<reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="init"/>
3266
+
<reg32 offset="0xae6b" name="SP_HLSQ_TIMEOUT_THRESHOLD_DP" variants="A7XX-" usage="init"/>
3267
+
<reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="init"/>
4301
3268
<reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
3269
+
<bitfield name="CONTEXT" low="26" high="30"/>
3270
+
<bitfield name="SLICE" low="21" high="25"/>
4302
3271
<bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/>
4303
-
<bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>
3272
+
<bitfield name="PIPE" low="16" high="17" type="adreno_pipe"/>
4304
3273
<bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>
4305
3274
<bitfield name="USPTP" low="4" high="7"/>
4306
3275
<bitfield name="SPTP" low="0" high="3"/>
4307
3276
</reg32>
4308
3277
<reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
4309
-
<reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
3278
+
<reg32 offset="0xae73" name="SP_HLSQ_DBG_ECO_CNTL_1" variants="A7XX-"/>
3279
+
<reg32 offset="0xae74" name="SP_HLSQ_DBG_ECO_CNTL_2" variants="A7XX-"/>
3280
+
<reg32 offset="0xae76" name="SP_HLSQ_DBG_ECO_CNTL_3" variants="A8XX-"/>
4310
3281
<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
4311
3282
<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
4312
3283
<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
4313
-
<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
3284
+
<reg32 offset="0xae52" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
3285
+
3286
+
<reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/>
3287
+
<reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/>
3288
+
<reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/>
3289
+
<reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/>
3290
+
<reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/>
3291
+
<reg32 offset="0xae18" name="SP_LPAC_ISDB_BATCH_COUNT_INCR_EN" variants="A8XX-"/>
3292
+
<reg32 offset="0xae19" name="SP_LPAC_ISDB_BATCH_COUNT_SHADERS" variants="A8XX-"/>
3293
+
<reg32 offset="0xae30" name="SP_ISDB_BATCH_COUNT" variants="A7XX-"/>
3294
+
<reg32 offset="0xae31" name="SP_ISDB_BATCH_COUNT_INCR_EN" variants="A7XX-"/>
3295
+
<reg32 offset="0xae32" name="SP_ISDB_BATCH_COUNT_SHADERS" variants="A7XX-"/>
3296
+
<reg32 offset="0xae35" name="SP_ISDB_DEBUG_CONFIG" variants="A7XX-"/>
3297
+
3298
+
<reg32 offset="0xae3a" name="SP_SELF_THROTTLE_CONTROL" variants="A7XX-"/>
3299
+
<reg32 offset="0xae3b" name="SP_DISPATCH_CNTL" variants="A7XX-"/>
3300
+
<reg64 offset="0xae3c" name="SP_SW_DEBUG_ADDR" variants="A7XX-"/>
3301
+
<reg64 offset="0xae3e" name="SP_ISDB_DEBUG_ADDR" variants="A7XX-"/>
3302
+
3303
+
<array offset="0xaec0" name="SP_PERFCTR_HLSQ_SEL_2_0" stride="1" length="6" variants="A7XX-"/>
4314
3304
4315
3305
<!--
4316
3306
The downstream kernel calls the debug cluster of registers
···
4341
3285
color base for compute shaders.
4342
3286
-->
4343
3287
<reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/>
4344
-
<reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>
4345
-
<reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>
3288
+
<reg32 offset="0xb182" name="TPL1_PS_ROTATION_CNTL" low="0" high="2" usage="cmd"/>
3289
+
<reg32 offset="0xb183" name="TPL1_PS_SWIZZLE_CNTL" low="0" high="23" usage="cmd"/>
4346
3290
4347
3291
<reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
4348
3292
<reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
3293
+
3294
+
<reg32 offset="0xb2d6" name="TPL1_A2D_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/>
3295
+
<reg32 offset="0xb2d7" name="TPL1_A2D_FILTER_CNTL" variants="A8XX-" usage="rp_blit"/>
4349
3296
4350
3297
<reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="rp_blit">
4351
3298
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
···
4362
3303
<!-- looks to work in the same way as a5xx: -->
4363
3304
<reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/>
4364
3305
<reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
4365
-
<reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/>
4366
-
<reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/>
3306
+
<reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A6XX-A7XX" />
3307
+
<reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A6XX-A7XX" />
4367
3308
<reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
3309
+
3310
+
<reg32 offset="0xb304" name="TPL1_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/>
4368
3311
4369
3312
<enum name="a6xx_coord_round">
4370
3313
<value value="0" name="COORD_TRUNCATE"/>
···
4376
3315
<enum name="a6xx_nearest_mode">
4377
3316
<value value="0" name="ROUND_CLAMP_TRUNCATE"/>
4378
3317
<value value="1" name="CLAMP_ROUND_TRUNCATE"/>
3318
+
<value value="2" name="ROUND_FLOAT_TO_INT"/> <!-- only ARRAYCOORDROUNDMODE -->
4379
3319
</enum>
4380
3320
4381
3321
<reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd">
4382
3322
<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
4383
3323
<bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/>
3324
+
<bitfield name="ARRAYCOORDROUNDMODE" low="3" high="4" type="a6xx_coord_round"/>
4384
3325
<bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/>
3326
+
<bitfield name="SAMPLEREPLICATE" pos="6" type="boolean"/>
4385
3327
<bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/>
3328
+
<bitfield name="PACK_SAMP_REDUCED_PRECISION" pos="8" type="boolean"/>
4386
3329
</reg32>
4387
3330
<reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
4388
3331
···
4452
3387
<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
4453
3388
</reg32>
4454
3389
<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX" usage="rp_blit"/>
3390
+
<reg32 offset="0xab07" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/>
4455
3391
4456
3392
<!-- always 0x100000 or 0x1000000? -->
4457
-
<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
4458
-
<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
4459
-
<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd">
3393
+
<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="init"/>
3394
+
<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
3395
+
<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="init">
4460
3396
<!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set
4461
3397
and if other blit is done without it - UBWC image may be copied incorrectly.
4462
3398
-->
···
4470
3404
<bitfield name="UPPER_BIT" pos="4" type="uint"/>
4471
3405
<bitfield name="UNK6" low="6" high="7"/>
4472
3406
</reg32>
4473
-
<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->
3407
+
<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="init"/> <!-- always 0x0 or 0x44 ? -->
4474
3408
4475
3409
<array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX">
4476
3410
<reg32 offset="0" name="REG" low="0" high="29"/>
···
4480
3414
<reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/>
4481
3415
</array>
4482
3416
3417
+
<array offset="0xb606" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="25" variants="A8XX">
3418
+
<reg32 offset="0" name="REG" low="0" high="29"/>
3419
+
</array>
3420
+
4483
3421
<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/>
4484
3422
<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/>
3423
+
<array offset="0xb620" name="TPL1_PERFCTR_TP_SEL" stride="1" length="20" variants="A8XX"/>
4485
3424
4486
3425
<!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
4487
3426
···
4529
3458
4530
3459
<reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="rp_blit">
4531
3460
<bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
4532
-
<!-- UNK8 is set on a730/a740 -->
4533
-
<bitfield name="UNK8" pos="8" type="boolean"/>
4534
-
<!-- UNK9 is set on a750 -->
4535
-
<bitfield name="UNK9" pos="9" type="boolean"/>
3461
+
<bitfield name="DEFER_WAVE_ALLOC_DIS" pos="8" type="boolean"/>
3462
+
<bitfield name="EVICT_BUF_MODE" low="9" high="10"/>
4536
3463
</reg32>
4537
3464
4538
3465
<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
···
4581
3512
<reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="rp_blit"/>
4582
3513
<reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="rp_blit"/>
4583
3514
<reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="cmd"/>
4584
-
<reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX-" usage="rp_blit"/>
3515
+
<reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX" usage="rp_blit"/>
3516
+
<reg32 offset="0xa9c6" name="SP_PS_WAVE_CNTL" variants="A8XX-" usage="rp_blit">
3517
+
<bitfield name="VARYINGS" pos="1" type="boolean"/>
3518
+
</reg32>
4585
3519
<reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="rp_blit">
4586
-
<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
3520
+
<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
4587
3521
</reg32>
4588
3522
<reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="rp_blit">
4589
3523
<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
···
4790
3718
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4791
3719
</reg32>
4792
3720
4793
-
<reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX-" usage="cmd">
3721
+
<reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX" usage="cmd">
4794
3722
<doc>
4795
3723
This register clears pending loads queued up by
4796
3724
CP_LOAD_STATE6. Each bit resets a particular kind(s) of
···
4813
3741
<bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>
4814
3742
</reg32>
4815
3743
3744
+
<reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A8XX" usage="cmd">
3745
+
<doc>
3746
+
This register clears pending loads queued up by
3747
+
CP_LOAD_STATE6. Each bit resets a particular kind(s) of
3748
+
CP_LOAD_STATE6.
3749
+
</doc>
3750
+
3751
+
<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
3752
+
<bitfield name="VS_STATE" pos="0" type="boolean"/>
3753
+
<bitfield name="HS_STATE" pos="1" type="boolean"/>
3754
+
<bitfield name="DS_STATE" pos="2" type="boolean"/>
3755
+
<bitfield name="GS_STATE" pos="3" type="boolean"/>
3756
+
<bitfield name="FS_STATE" pos="4" type="boolean"/>
3757
+
<bitfield name="CS_STATE" pos="5" type="boolean"/>
3758
+
</reg32>
3759
+
3760
+
<reg32 offset="0xa9c0" name="SP_CS_BINDLESS_INVALIDATE"/>
3761
+
<reg32 offset="0xab08" name="SP_GFX_BINDLESS_INVALIDATE"/>
3762
+
4816
3763
<reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/>
4817
3764
<reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/>
4818
3765
4819
3766
<array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX"/>
3767
+
<array offset="0xab30" name="SP_SHARED_CONSTANT_GFX" stride="1" length="128" variants="A8XX-"/>
4820
3768
4821
3769
<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd">
4822
3770
<doc>
···
4873
3781
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4874
3782
</reg32>
4875
3783
4876
-
<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
4877
-
<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>
4878
-
<reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/>
4879
-
<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3784
+
<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="init"/> <!-- all bits valid except bit 29 -->
3785
+
<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="init"/>
3786
+
<reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="init"/>
3787
+
<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
4880
3788
<reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
4881
3789
<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
4882
3790
4883
3791
<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
4884
-
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
3792
+
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE" variants="A6XX"/>
4885
3793
4886
3794
<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
4887
3795
···
5010
3918
<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
5011
3919
<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
5012
3920
<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
3921
+
<reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/>
5013
3922
<reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
5014
3923
<bitfield pos="0" name="FASTBLEND" type="boolean"/>
5015
3924
<bitfield pos="1" name="LPAC" type="boolean"/>
+1
-1
drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml
+1
-1
drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml
···
303
303
</enum>
304
304
305
305
<!--
306
-
Used in a6xx_a2d_bit_cntl.. the value mostly seems to correlate to the
306
+
Used in a6xx_a2d_blt_cntl.. the value mostly seems to correlate to the
307
307
component type/size, so I think it relates to internal format used for
308
308
blending? The one exception is that 16b unorm and 32b float use the
309
309
same value... maybe 16b unorm is uncommon enough that it was just easier
+153
-130
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+153
-130
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
···
40
40
<bitfield name="IRQ_MASK_BIT" pos="0" />
41
41
</bitset>
42
42
43
-
<reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44
-
<reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45
-
<reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
46
-
<reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
47
-
<reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
48
-
<reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
49
-
<reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
50
-
<reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
51
-
<reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
52
-
<reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
53
-
<reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
54
-
<reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
55
-
<reg32 offset="0x2bf8" name="GMU_CORE_FW_VERSION">
43
+
<reg32 offset="0x1a880" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44
+
<reg32 offset="0x1a881" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45
+
<reg32 offset="0x1b400" name="GMU_CM3_ITCM_START"/>
46
+
<reg32 offset="0x1c400" name="GMU_CM3_DTCM_START"/>
47
+
<reg32 offset="0x1cbf0" name="GMU_NMI_CONTROL_STATUS"/>
48
+
<reg32 offset="0x1cbf8" name="GMU_BOOT_SLUMBER_OPTION"/>
49
+
<reg32 offset="0x1cbf9" name="GMU_GX_VOTE_IDX"/>
50
+
<reg32 offset="0x1cbfa" name="GMU_MX_VOTE_IDX"/>
51
+
<reg32 offset="0x1cbfc" name="GMU_DCVS_ACK_OPTION"/>
52
+
<reg32 offset="0x1cbfd" name="GMU_DCVS_PERF_SETTING"/>
53
+
<reg32 offset="0x1cbfe" name="GMU_DCVS_BW_SETTING"/>
54
+
<reg32 offset="0x1cbff" name="GMU_DCVS_RETURN"/>
55
+
<reg32 offset="0x1d3f8" name="GMU_CORE_FW_VERSION">
56
56
<bitfield name="MAJOR" low="28" high="31"/>
57
57
<bitfield name="MINOR" low="16" high="27"/>
58
58
<bitfield name="STEP" low="0" high="15"/>
59
59
</reg32>
60
-
<reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
61
-
<reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
62
-
<reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
63
-
<reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
64
-
<reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
65
-
<reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
66
-
<reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
67
-
<reg32 offset="0x502d" name="GMU_CM3_CFG"/>
68
-
<reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
69
-
<reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
70
-
<reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
71
-
<reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
72
-
<reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
73
-
<reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
74
-
<reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
75
-
<reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
76
-
<reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
77
-
<reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
78
-
<reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
79
-
<reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
80
-
<reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
81
-
<reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
82
-
<reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
83
-
<reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
60
+
<reg32 offset="0x1f400" name="GMU_ICACHE_CONFIG"/>
61
+
<reg32 offset="0x1f401" name="GMU_DCACHE_CONFIG"/>
62
+
<reg32 offset="0x1f40f" name="GMU_SYS_BUS_CONFIG"/>
63
+
<reg32 offset="0x1f50b" name="GMU_MRC_GBIF_QOS_CTRL"/>
64
+
<reg32 offset="0x1f800" name="GMU_CM3_SYSRESET"/>
65
+
<reg32 offset="0x1f801" name="GMU_CM3_BOOT_CONFIG"/>
66
+
<reg32 offset="0x1f81a" name="GMU_CM3_FW_BUSY"/>
67
+
<reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/>
68
+
<reg32 offset="0x1f82d" name="GMU_CM3_CFG"/>
69
+
<reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
70
+
<reg32 offset="0x1fc10" name="GMU_CX_GMU_POWER_COUNTER_ENABLE" variants="A8XX"/>
71
+
<reg32 offset="0x1f841" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
72
+
<reg32 offset="0x1f842" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
73
+
<reg32 offset="0x1fc40" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0" variants="A8XX-"/>
74
+
<reg32 offset="0x1fc41" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1" variants="A8XX-"/>
75
+
<reg32 offset="0x1f844" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
76
+
<reg32 offset="0x1fca0" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L" variants="A8XX-"/>
77
+
<reg32 offset="0x1f845" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
78
+
<reg32 offset="0x1fca1" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H" variants="A8XX-"/>
79
+
<reg32 offset="0x1f846" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
80
+
<reg32 offset="0x1f847" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
81
+
<reg32 offset="0x1f848" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
82
+
<reg32 offset="0x1f849" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
83
+
<reg32 offset="0x1f84a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
84
+
<reg32 offset="0x1f84b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
85
+
<reg32 offset="0x1f84c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
86
+
<reg32 offset="0x1f84d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
87
+
<reg32 offset="0x1f84e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
88
+
<reg32 offset="0x1f84f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
89
+
<reg32 offset="0x1f8c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
84
90
<bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
85
91
<bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
86
92
<bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
87
93
<bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
88
94
<bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
89
95
</reg32>
90
-
<reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
91
-
<reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
92
-
<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
96
+
<reg32 offset="0x1f8c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
97
+
<reg32 offset="0x1f8c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
98
+
<reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A6XX">
93
99
<bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
94
100
<bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
95
101
<bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
···
105
99
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
106
100
<bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
107
101
</reg32>
108
-
<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
102
+
<reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
109
103
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
110
104
<bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
111
105
</reg32>
112
-
<reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
106
+
<reg32 offset="0x1f7e8" name="GMU_PWR_CLK_STATUS" variants="A8XX-">
107
+
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
108
+
<bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
109
+
</reg32>
110
+
<reg32 offset="0x1f8e4" name="GMU_GPU_NAP_CTRL">
113
111
<bitfield name="HW_NAP_ENABLE" pos="0"/>
114
112
<bitfield name="SID" low="4" high="8"/>
115
113
</reg32>
116
-
<reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
114
+
<reg32 offset="0x1f8e8" name="GMU_RPMH_CTRL">
117
115
<bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
118
116
<bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
119
117
<bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
···
129
119
<bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
130
120
<bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
131
121
</reg32>
132
-
<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
133
-
<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
134
-
<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
135
-
<reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
136
-
<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
137
-
<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
138
-
<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
139
-
<reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
140
-
<reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
141
-
<reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
142
-
<reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
143
-
<reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
144
-
<reg32 offset="0x50c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/>
145
-
<reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
146
-
<reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
147
-
<reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
148
-
<reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
149
-
<reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
150
-
<reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
151
-
<reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
152
-
<reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
153
-
<reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
154
-
<reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
122
+
<reg32 offset="0x1f8e9" name="GMU_RPMH_HYST_CTRL"/>
123
+
<reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A6XX"/>
124
+
<reg32 offset="0x1f7e9" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A8XX-"/>
125
+
<reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A6XX"/>
126
+
<reg32 offset="0x1f7ec" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A8XX-"/>
127
+
<reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A6XX"/>
128
+
<reg32 offset="0x1f7ed" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A8XX-"/>
129
+
<reg32 offset="0x1f900" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
130
+
<reg32 offset="0x1f901" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
131
+
<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
132
+
<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
133
+
<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
134
+
<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L"/>
135
+
<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H"/>
136
+
<reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/>
137
+
<reg32 offset="0x1f7e4" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A8XX-"/>
138
+
<reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/>
139
+
<reg32 offset="0x1f7e5" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A8XX-"/>
140
+
<reg32 offset="0x1f980" name="GMU_HFI_CTRL_STATUS"/>
141
+
<reg32 offset="0x1f981" name="GMU_HFI_VERSION_INFO"/>
142
+
<reg32 offset="0x1f982" name="GMU_HFI_SFR_ADDR"/>
143
+
<reg32 offset="0x1f983" name="GMU_HFI_MMAP_ADDR"/>
144
+
<reg32 offset="0x1f984" name="GMU_HFI_QTBL_INFO"/>
145
+
<reg32 offset="0x1f985" name="GMU_HFI_QTBL_ADDR"/>
146
+
<reg32 offset="0x1f986" name="GMU_HFI_CTRL_INIT"/>
147
+
<reg32 offset="0x1f990" name="GMU_GMU2HOST_INTR_SET"/>
148
+
<reg32 offset="0x1f991" name="GMU_GMU2HOST_INTR_CLR"/>
149
+
<reg32 offset="0x1f992" name="GMU_GMU2HOST_INTR_INFO">
155
150
<bitfield name="MSGQ" pos="0" type="boolean"/>
156
151
<bitfield name="CM3_FAULT" pos="23" type="boolean"/>
157
152
</reg32>
158
-
<reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
159
-
<reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
160
-
<reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
161
-
<reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
162
-
<reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
163
-
<reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
164
-
<reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
165
-
<reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
166
-
<reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
167
-
<reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
168
-
<reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
169
-
<reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
170
-
<reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
171
-
<reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
172
-
<reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
173
-
<reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
174
-
<reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
175
-
<reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
176
-
<reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
177
-
<reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
178
-
<reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
179
-
<reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
180
-
<reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
181
-
<reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
182
-
<reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
183
-
<reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
184
-
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
185
-
<reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
186
-
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
187
-
<reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
188
-
<reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
189
-
<reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
190
-
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
191
-
<reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
192
-
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
193
-
<reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
194
-
<reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
195
-
<reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
196
-
<reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
153
+
<reg32 offset="0x1f993" name="GMU_GMU2HOST_INTR_MASK"/>
154
+
<reg32 offset="0x1f994" name="GMU_HOST2GMU_INTR_SET"/>
155
+
<reg32 offset="0x1f995" name="GMU_HOST2GMU_INTR_CLR"/>
156
+
<reg32 offset="0x1f996" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
157
+
<reg32 offset="0x1f997" name="GMU_HOST2GMU_INTR_EN_0"/>
158
+
<reg32 offset="0x1f998" name="GMU_HOST2GMU_INTR_EN_1"/>
159
+
<reg32 offset="0x1f999" name="GMU_HOST2GMU_INTR_EN_2"/>
160
+
<reg32 offset="0x1f99a" name="GMU_HOST2GMU_INTR_EN_3"/>
161
+
<reg32 offset="0x1f99b" name="GMU_HOST2GMU_INTR_INFO_0"/>
162
+
<reg32 offset="0x1f99c" name="GMU_HOST2GMU_INTR_INFO_1"/>
163
+
<reg32 offset="0x1f99d" name="GMU_HOST2GMU_INTR_INFO_2"/>
164
+
<reg32 offset="0x1f99e" name="GMU_HOST2GMU_INTR_INFO_3"/>
165
+
<reg32 offset="0x1f9c5" name="GMU_GENERAL_0"/>
166
+
<reg32 offset="0x1f9c6" name="GMU_GENERAL_1"/>
167
+
<reg32 offset="0x1f9cb" name="GMU_GENERAL_6"/>
168
+
<reg32 offset="0x1f9cc" name="GMU_GENERAL_7"/>
169
+
<reg32 offset="0x1f9cd" name="GMU_GENERAL_8" variants="A7XX"/>
170
+
<reg32 offset="0x1f9ce" name="GMU_GENERAL_9" variants="A7XX"/>
171
+
<reg32 offset="0x1f9cf" name="GMU_GENERAL_10" variants="A7XX"/>
172
+
<reg32 offset="0x1f9c0" name="GMU_GENERAL_0" variants="A8XX"/>
173
+
<reg32 offset="0x1f9c1" name="GMU_GENERAL_1" variants="A8XX"/>
174
+
<reg32 offset="0x1f9c6" name="GMU_GENERAL_6" variants="A8XX"/>
175
+
<reg32 offset="0x1f9c7" name="GMU_GENERAL_7" variants="A8XX"/>
176
+
<reg32 offset="0x1f9c8" name="GMU_GENERAL_8" variants="A8XX"/>
177
+
<reg32 offset="0x1f9c9" name="GMU_GENERAL_9" variants="A8XX"/>
178
+
<reg32 offset="0x1f9ca" name="GMU_GENERAL_10" variants="A8XX"/>
179
+
<reg32 offset="0x1f9cb" name="GMU_GENERAL_11" variants="A8XX"/>
180
+
<reg32 offset="0x1f95d" name="GMU_ISENSE_CTRL"/>
181
+
<reg32 offset="0x23120" name="GPU_CS_ENABLE_REG"/>
182
+
<reg32 offset="0x1f95d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
183
+
<reg32 offset="0x22d78" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
184
+
<reg32 offset="0x22d58" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
185
+
<reg32 offset="0x22d80" name="GPU_CS_A_SENSOR_CTRL_0"/>
186
+
<reg32 offset="0x422da" name="GPU_CS_A_SENSOR_CTRL_2"/>
187
+
<reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
188
+
<reg32 offset="0x23157" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
189
+
<reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
190
+
<reg32 offset="0x2301d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
191
+
<reg32 offset="0x2301f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
192
+
<reg32 offset="0x23021" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
193
+
<reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/>
194
+
<reg32 offset="0x2316d" name="GPU_CS_AMP_PERIOD_CTRL"/>
195
+
<reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/>
196
+
<reg32 offset="0x1f94d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
197
+
<reg32 offset="0x23b03" name="GMU_AO_INTERRUPT_EN"/>
198
+
<reg32 offset="0x23b04" name="GMU_AO_HOST_INTERRUPT_CLR"/>
199
+
<reg32 offset="0x23b05" name="GMU_AO_HOST_INTERRUPT_STATUS">
197
200
<bitfield name="WDOG_BITE" pos="0" type="boolean"/>
198
201
<bitfield name="RSCC_COMP" pos="1" type="boolean"/>
199
202
<bitfield name="VDROOP" pos="2" type="boolean"/>
···
214
191
<bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
215
192
<bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
216
193
</reg32>
217
-
<reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
218
-
<reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
219
-
<reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
220
-
<reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
221
-
<reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
194
+
<reg32 offset="0x23b06" name="GMU_AO_HOST_INTERRUPT_MASK"/>
195
+
<reg32 offset="0x23b09" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
196
+
<reg32 offset="0x23b0a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
197
+
<reg32 offset="0x23b0b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
198
+
<reg32 offset="0x23b0c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
222
199
<bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
223
200
</reg32>
224
-
<reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
225
-
<reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
226
-
<reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
227
-
<reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
228
-
<reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
229
-
<reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
230
-
<reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
231
-
<reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
232
-
<reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
233
-
<reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
234
-
<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
235
-
<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
236
-
<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
237
-
<reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
201
+
<reg32 offset="0x23b0d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
202
+
<reg32 offset="0x23b0e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
203
+
<reg32 offset="0x23b10" name="GMU_AO_AHB_FENCE_CTRL"/>
204
+
<reg32 offset="0x23b13" name="GMU_AHB_FENCE_STATUS"/>
205
+
<reg32 offset="0x23b14" name="GMU_AHB_FENCE_STATUS_CLR"/>
206
+
<reg32 offset="0x23b15" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
207
+
<reg32 offset="0x23b16" name="GMU_AO_SPARE_CNTL"/>
208
+
<reg32 offset="0x23b07" name="GMU_RSCC_CONTROL_REQ"/>
209
+
<reg32 offset="0x23b08" name="GMU_RSCC_CONTROL_ACK"/>
210
+
<reg32 offset="0x23b11" name="GMU_AHB_FENCE_RANGE_0"/>
211
+
<reg32 offset="0x23b12" name="GMU_AHB_FENCE_RANGE_1"/>
212
+
<reg32 offset="0x24403" name="GPU_CC_GX_GDSCR"/>
213
+
<reg32 offset="0x24542" name="GPU_CC_GX_DOMAIN_MISC"/>
214
+
<reg32 offset="0x26801" name="GPU_CPR_FSM_CTL"/>
238
215
239
216
<!-- starts at offset 0x8c00 on most gpus -->
240
217
<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
···
256
233
<reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
257
234
<reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
258
235
<reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
259
-
<reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX"/>
260
-
<reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX"/>
261
-
<reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX"/>
262
-
<reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX"/>
263
-
<reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX"/>
264
-
<reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX"/>
236
+
<reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX-"/>
237
+
<reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX-"/>
238
+
<reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX-"/>
239
+
<reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX-"/>
240
+
<reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX-"/>
241
+
<reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX-"/>
265
242
</domain>
266
243
267
244
</database>
-7
drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml
-7
drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml
···
93
93
<value value="4" name="A7XX_HLSQ_DP_STR"/>
94
94
</enum>
95
95
96
-
<enum name="a7xx_pipe">
97
-
<value value="0" name="A7XX_PIPE_NONE"/>
98
-
<value value="1" name="A7XX_PIPE_BR"/>
99
-
<value value="2" name="A7XX_PIPE_BV"/>
100
-
<value value="3" name="A7XX_PIPE_LPAC"/>
101
-
</enum>
102
-
103
96
<enum name="a7xx_cluster">
104
97
<value value="0" name="A7XX_CLUSTER_NONE"/>
105
98
<value value="1" name="A7XX_CLUSTER_FE"/>
+121
drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml
+121
drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
<import file="adreno/adreno_pm4.xml"/>
8
+
<import file="adreno/a6xx_enums.xml"/>
9
+
<import file="adreno/a8xx_enums.xml"/>
10
+
11
+
<domain name="A8XX_TEX_SAMP" width="32">
12
+
<doc>Texture sampler dwords</doc>
13
+
<reg32 offset="0" name="0">
14
+
<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
15
+
<bitfield name="MIPMAPING_DIS" pos="1" type="boolean"/>
16
+
<bitfield name="XY_MAG" low="2" high="3" type="a6xx_tex_filter"/>
17
+
<bitfield name="XY_MIN" low="4" high="5" type="a6xx_tex_filter"/>
18
+
<bitfield name="WRAP_S" low="6" high="8" type="a6xx_tex_clamp"/>
19
+
<bitfield name="WRAP_T" low="9" high="11" type="a6xx_tex_clamp"/>
20
+
<bitfield name="WRAP_R" low="12" high="14" type="a6xx_tex_clamp"/>
21
+
<bitfield name="MSAA_BOX_FILTERING" pos="15" type="boolean"/>
22
+
<bitfield name="LOD_BIAS" low="16" high="28" type="fixed" radix="8"/>
23
+
<bitfield name="ANISO" low="29" high="31" type="a6xx_tex_aniso"/>
24
+
</reg32>
25
+
<reg32 offset="1" name="1">
26
+
<bitfield name="MAX_LOD" low="0" high="11" type="ufixed" radix="8"/>
27
+
<bitfield name="MIN_LOD" low="12" high="23" type="ufixed" radix="8"/>
28
+
<bitfield name="REDUCTION_MODE" low="24" high="25" type="a6xx_reduction_mode"/>
29
+
<bitfield name="COMPARE_FUNC" low="26" high="28" type="adreno_compare_func"/>
30
+
<bitfield name="CHROMA_LINEAR" pos="29" type="boolean"/>
31
+
<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="30" type="boolean"/>
32
+
<bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
33
+
</reg32>
34
+
<reg32 offset="2" name="2">
35
+
<bitfield name="FASTBORDERCOLOREN" pos="0" type="boolean"/>
36
+
<bitfield name="FASTBORDERCOLOR" low="1" high="2" type="a6xx_fast_border_color"/>
37
+
<bitfield name="BCOLOR" low="7" high="31"/>
38
+
</reg32>
39
+
<reg32 offset="3" name="3"/>
40
+
</domain>
41
+
42
+
<domain name="A8XX_TEX_MEMOBJ" width="32" varset="chip">
43
+
<doc>Texture memobj dwords</doc>
44
+
<reg32 offset="0" name="0">
45
+
<bitfield name="BASE_LO" low="6" high="31" shr="6"/>
46
+
</reg32>
47
+
<reg32 offset="1" name="1">
48
+
<bitfield name="BASE_HI" low="0" high="16"/>
49
+
<bitfield name="TYPE" low="17" high="19" type="a6xx_tex_type"/>
50
+
<bitfield name="DEPTH" low="20" high="31" type="uint"/>
51
+
</reg32>
52
+
<reg32 offset="2" name="2">
53
+
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
54
+
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
55
+
<bitfield name="SAMPLES" low="30" high="31" type="a3xx_msaa_samples"/>
56
+
</reg32>
57
+
<reg32 offset="3" name="3">
58
+
<bitfield name="FMT" low="0" high="7" type="a6xx_format"/>
59
+
<bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
60
+
<bitfield name="SWIZ_X" low="10" high="12" type="a8xx_tex_swiz"/>
61
+
<bitfield name="SWIZ_Y" low="13" high="15" type="a8xx_tex_swiz"/>
62
+
<bitfield name="SWIZ_Z" low="16" high="18" type="a8xx_tex_swiz"/>
63
+
<bitfield name="SWIZ_W" low="19" high="21" type="a8xx_tex_swiz"/>
64
+
</reg32>
65
+
<reg32 offset="4" name="4">
66
+
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
67
+
<bitfield name="FLAG" pos="2" type="boolean"/>
68
+
<bitfield name="PRT_EN" pos="3" type="boolean"/>
69
+
<bitfield name="TILE_ALL" pos="4" type="boolean"/>
70
+
<bitfield name="SRGB" pos="5" type="boolean"/>
71
+
<bitfield name="FLAG_LO" low="6" high="31" shr="6"/>
72
+
<!-- For multiplanar: -->
73
+
<bitfield name="BASE_U_LO" low="6" high="31" shr="6"/>
74
+
</reg32>
75
+
<reg32 offset="5" name="5">
76
+
<bitfield name="FLAG_HI" low="0" high="16"/>
77
+
<!-- For multiplanar: -->
78
+
<bitfield name="BASE_U_HI" low="0" high="16"/>
79
+
<bitfield name="FLAG_BUFFER_PITCH" low="17" high="24" shr="6" type="uint"/>
80
+
<bitfield name="ALL_SAMPLES_CENTER" pos="29" type="boolean"/>
81
+
<bitfield name="MUTABLEEN" pos="31" type="boolean"/>
82
+
</reg32>
83
+
<reg32 offset="6" name="6">
84
+
<bitfield name="TEX_LINE_OFFSET" low="0" high="23" type="uint"/> <!-- PITCH -->
85
+
<bitfield name="MIN_LINE_OFFSET" low="24" high="27" type="uint"/> <!-- PITCHALIGN -->
86
+
<bitfield name="MIPLVLS" low="28" high="31" type="uint"/>
87
+
</reg32>
88
+
<reg32 offset="7" name="7">
89
+
<bitfield name="ARRAY_SLICE_OFFSET" low="0" high="22" shr="12" type="uint"/> <!-- ARRAY_PITCH -->
90
+
<bitfield name="ASO_UNIT" pos="23"/> <!-- 4KB or 32B ? -->
91
+
<bitfield name="MIN_ARRAY_SLIZE_OFFSET" low="24" high="27" shr="12"/> <!-- MIN_LAYERSZ -->
92
+
<bitfield name="GMEM_TILING_FALLBACK_EN" pos="28" type="boolean"/>
93
+
<bitfield name="CORNER_BASED_EN" pos="30" type="boolean"/>
94
+
<bitfield name="GMEM_FULL_SURF" pos="31" type="boolean"/>
95
+
<!-- For multiplanar. This overlaps other single-planar fields: -->
96
+
<bitfield name="UV_OFFSET_H" low="24" high="25" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_X -->
97
+
<bitfield name="UV_OFFSET_V" low="26" high="27" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_Y -->
98
+
</reg32>
99
+
<reg32 offset="8" name="8">
100
+
<bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="12" type="uint"/> <!-- FLAG_BUFFER_ARRAY_PITCH -->
101
+
<!-- log2 size of the first level, required for mipmapping -->
102
+
<bitfield name="FLAG_BUFFER_LOGW" low="24" high="27" type="uint"/>
103
+
<bitfield name="FLAG_BUFFER_LOGH" low="28" high="31" type="uint"/>
104
+
<!-- For multiplanar. This overlaps other single-planar fields: -->
105
+
<bitfield name="BASE_V_LO" low="6" high="31" shr="6"/>
106
+
</reg32>
107
+
<reg32 offset="9" name="9">
108
+
<bitfield name="MIN_LOD_CLAMP" low="19" high="30" type="ufixed" radix="8"/>
109
+
<!-- For multiplanar, this overlaps other fields: -->
110
+
<bitfield name="BASE_V_HI" low="0" high="16"/>
111
+
<bitfield name="UV_PITCH" low="17" high="26"/> <!-- PLANE_PITCH -->
112
+
</reg32>
113
+
<reg32 offset="10" name="10"/>
114
+
<reg32 offset="11" name="11"/>
115
+
<reg32 offset="12" name="12"/>
116
+
<reg32 offset="13" name="13"/>
117
+
<reg32 offset="14" name="14"/>
118
+
<reg32 offset="15" name="15"/>
119
+
</domain>
120
+
121
+
</database>
+299
drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml
+299
drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
<import file="adreno/adreno_pm4.xml"/>
8
+
9
+
<enum name="a8xx_statetype_id">
10
+
<value value="0" name="A8XX_TP0_NCTX_REG"/>
11
+
<value value="1" name="A8XX_TP0_CTX0_3D_CVS_REG"/>
12
+
<value value="2" name="A8XX_TP0_CTX0_3D_CPS_REG"/>
13
+
<value value="3" name="A8XX_TP0_CTX1_3D_CVS_REG"/>
14
+
<value value="4" name="A8XX_TP0_CTX1_3D_CPS_REG"/>
15
+
<value value="5" name="A8XX_TP0_CTX2_3D_CPS_REG"/>
16
+
<value value="6" name="A8XX_TP0_CTX3_3D_CPS_REG"/>
17
+
<value value="9" name="A8XX_TP0_TMO_DATA"/>
18
+
<value value="10" name="A8XX_TP0_SMO_DATA"/>
19
+
<value value="11" name="A8XX_TP0_MIPMAP_BASE_DATA"/>
20
+
<value value="12" name="A8XX_TP_3D_CVS_REG"/>
21
+
<value value="13" name="A8XX_TP_3D_CPS_REG"/>
22
+
<value value="16" name="A8XX_SP_3D_CVS_REG"/>
23
+
<value value="17" name="A8XX_SP_3D_CPS_REG"/>
24
+
<value value="22" name="A8XX_SP_LB_DATA_RAM"/>
25
+
<value value="23" name="A8XX_SP_INST_DATA_RAM"/>
26
+
<value value="24" name="A8XX_SP_STH"/>
27
+
<value value="25" name="A8XX_SP_EVQ"/>
28
+
<value value="26" name="A8XX_SP_CONSMNG"/>
29
+
<value value="30" name="A8XX_HLSQ_INST_DATA_RAM"/>
30
+
<value value="31" name="A8XX_SP_INST_DATA_3"/>
31
+
<value value="32" name="A8XX_SP_NCTX_REG"/>
32
+
<value value="33" name="A8XX_SP_CTX0_3D_CVS_REG"/>
33
+
<value value="34" name="A8XX_SP_CTX0_3D_CPS_REG"/>
34
+
<value value="35" name="A8XX_SP_CTX1_3D_CVS_REG"/>
35
+
<value value="36" name="A8XX_SP_CTX1_3D_CPS_REG"/>
36
+
<value value="37" name="A8XX_SP_CTX2_3D_CPS_REG"/>
37
+
<value value="38" name="A8XX_SP_CTX3_3D_CPS_REG"/>
38
+
<value value="39" name="A8XX_SP_INST_DATA"/>
39
+
<value value="40" name="A8XX_SP_INST_DATA_1"/>
40
+
<value value="41" name="A8XX_SP_LB_0_DATA"/>
41
+
<value value="42" name="A8XX_SP_LB_1_DATA"/>
42
+
<value value="43" name="A8XX_SP_LB_2_DATA"/>
43
+
<value value="44" name="A8XX_SP_LB_3_DATA"/>
44
+
<value value="45" name="A8XX_SP_LB_4_DATA"/>
45
+
<value value="46" name="A8XX_SP_LB_5_DATA"/>
46
+
<value value="47" name="A8XX_SP_LB_6_DATA"/>
47
+
<value value="48" name="A8XX_SP_LB_7_DATA"/>
48
+
<value value="49" name="A8XX_SP_CB_RAM"/>
49
+
<value value="50" name="A8XX_SP_LB_13_DATA"/>
50
+
<value value="51" name="A8XX_SP_LB_14_DATA"/>
51
+
<value value="52" name="A8XX_SP_INST_TAG"/>
52
+
<value value="53" name="A8XX_SP_INST_DATA_2"/>
53
+
<value value="54" name="A8XX_SP_TMO_TAG"/>
54
+
<value value="55" name="A8XX_SP_SMO_TAG"/>
55
+
<value value="56" name="A8XX_SP_STATE_DATA"/>
56
+
<value value="57" name="A8XX_SP_HWAVE_RAM"/>
57
+
<value value="58" name="A8XX_SP_L0_INST_BUF"/>
58
+
<value value="59" name="A8XX_SP_LB_8_DATA"/>
59
+
<value value="60" name="A8XX_SP_LB_9_DATA"/>
60
+
<value value="61" name="A8XX_SP_LB_10_DATA"/>
61
+
<value value="62" name="A8XX_SP_LB_11_DATA"/>
62
+
<value value="63" name="A8XX_SP_LB_12_DATA"/>
63
+
<value value="64" name="A8XX_HLSQ_DATAPATH_DSTR_META"/>
64
+
<value value="65" name="A8XX_HLSQ_DESC_REMAP_META"/>
65
+
<value value="66" name="A8XX_HLSQ_SLICE_TOP_META"/>
66
+
<value value="67" name="A8XX_HLSQ_L2STC_TAG_RAM"/>
67
+
<value value="68" name="A8XX_HLSQ_L2STC_INFO_CMD"/>
68
+
<value value="69" name="A8XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
69
+
<value value="70" name="A8XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
70
+
<value value="71" name="A8XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
71
+
<value value="72" name="A8XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
72
+
<value value="73" name="A8XX_HLSQ_CHUNK_CVS_RAM"/>
73
+
<value value="74" name="A8XX_HLSQ_CHUNK_CPS_RAM"/>
74
+
<value value="75" name="A8XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
75
+
<value value="76" name="A8XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
76
+
<value value="77" name="A8XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
77
+
<value value="78" name="A8XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
78
+
<value value="79" name="A8XX_HLSQ_CVS_MISC_RAM"/>
79
+
<value value="80" name="A8XX_HLSQ_CPS_MISC_RAM"/>
80
+
<value value="81" name="A8XX_HLSQ_CPS_MISC_RAM_1"/>
81
+
<value value="82" name="A8XX_HLSQ_INST_RAM"/>
82
+
<value value="83" name="A8XX_HLSQ_GFX_CVS_CONST_RAM"/>
83
+
<value value="84" name="A8XX_HLSQ_GFX_CPS_CONST_RAM"/>
84
+
<value value="85" name="A8XX_HLSQ_CVS_MISC_RAM_TAG"/>
85
+
<value value="86" name="A8XX_HLSQ_CPS_MISC_RAM_TAG"/>
86
+
<value value="87" name="A8XX_HLSQ_INST_RAM_TAG"/>
87
+
<value value="88" name="A8XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
88
+
<value value="89" name="A8XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
89
+
<value value="90" name="A8XX_HLSQ_GFX_LOCAL_MISC_RAM"/>
90
+
<value value="91" name="A8XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>
91
+
<value value="92" name="A8XX_HLSQ_INST_RAM_1"/>
92
+
<value value="93" name="A8XX_HLSQ_STPROC_META"/>
93
+
<value value="94" name="A8XX_HLSQ_SLICE_BACKEND_META"/>
94
+
<value value="95" name="A8XX_HLSQ_INST_RAM_2"/>
95
+
<value value="96" name="A8XX_HLSQ_DATAPATH_META"/>
96
+
<value value="97" name="A8XX_HLSQ_FRONTEND_META"/>
97
+
<value value="98" name="A8XX_HLSQ_INDIRECT_META"/>
98
+
<value value="99" name="A8XX_HLSQ_BACKEND_META"/>
99
+
</enum>
100
+
101
+
<enum name="a8xx_state_location">
102
+
<value value="0" name="A8XX_HLSQ_STATE"/>
103
+
<value value="1" name="A8XX_HLSQ_DP"/>
104
+
<value value="2" name="A8XX_SP_TOP"/>
105
+
<value value="3" name="A8XX_USPTP"/>
106
+
<value value="4" name="A8XX_HLSQ_DP_STR"/>
107
+
</enum>
108
+
109
+
<enum name="a8xx_cluster">
110
+
<value value="0" name="A8XX_CLUSTER_NONE"/>
111
+
<value value="1" name="A8XX_CLUSTER_FE_US"/>
112
+
<value value="2" name="A8XX_CLUSTER_FE_S"/>
113
+
<value value="3" name="A8XX_CLUSTER_SP_VS"/>
114
+
<value value="4" name="A8XX_CLUSTER_VPC_VS"/>
115
+
<value value="5" name="A8XX_CLUSTER_VPC_US"/>
116
+
<value value="6" name="A8XX_CLUSTER_GRAS"/>
117
+
<value value="7" name="A8XX_CLUSTER_SP_PS"/>
118
+
<value value="8" name="A8XX_CLUSTER_VPC_PS"/>
119
+
<value value="9" name="A8XX_CLUSTER_PS"/>
120
+
</enum>
121
+
122
+
<enum name="a8xx_debugbus_id">
123
+
<value value="1" name="A8XX_DEBUGBUS_GBIF_CX_GC_US_I_0"/>
124
+
<value value="2" name="A8XX_DEBUGBUS_GMU_CX_GC_US_I_0"/>
125
+
<value value="3" name="A8XX_DEBUGBUS_CX_GC_US_I_0"/>
126
+
<value value="8" name="A8XX_DEBUGBUS_GBIF_GX_GC_US_I_0"/>
127
+
<value value="9" name="A8XX_DEBUGBUS_GMU_GX_GC_US_I_0"/>
128
+
<value value="10" name="A8XX_DEBUGBUS_DBGC_GC_US_I_0"/>
129
+
<value value="11" name="A8XX_DEBUGBUS_RBBM_GC_US_I_0"/>
130
+
<value value="12" name="A8XX_DEBUGBUS_LARC_GC_US_I_0"/>
131
+
<value value="13" name="A8XX_DEBUGBUS_COM_GC_US_I_0"/>
132
+
<value value="14" name="A8XX_DEBUGBUS_HLSQ_GC_US_I_0"/>
133
+
<value value="15" name="A8XX_DEBUGBUS_CGC_GC_US_I_0"/>
134
+
<value value="20" name="A8XX_DEBUGBUS_VSC_GC_US_I_0_0"/>
135
+
<value value="21" name="A8XX_DEBUGBUS_VSC_GC_US_I_0_1"/>
136
+
<value value="24" name="A8XX_DEBUGBUS_UFC_GC_US_I_0"/>
137
+
<value value="25" name="A8XX_DEBUGBUS_UFC_GC_US_I_1"/>
138
+
<value value="40" name="A8XX_DEBUGBUS_CP_GC_US_I_0_0"/>
139
+
<value value="41" name="A8XX_DEBUGBUS_CP_GC_US_I_0_1"/>
140
+
<value value="42" name="A8XX_DEBUGBUS_CP_GC_US_I_0_2"/>
141
+
<value value="56" name="A8XX_DEBUGBUS_PC_BR_US_I_0"/>
142
+
<value value="57" name="A8XX_DEBUGBUS_PC_BV_US_I_0"/>
143
+
<value value="58" name="A8XX_DEBUGBUS_GPC_BR_US_I_0"/>
144
+
<value value="59" name="A8XX_DEBUGBUS_GPC_BV_US_I_0"/>
145
+
<value value="60" name="A8XX_DEBUGBUS_VPC_BR_US_I_0"/>
146
+
<value value="61" name="A8XX_DEBUGBUS_VPC_BV_US_I_0"/>
147
+
<value value="80" name="A8XX_DEBUGBUS_UCHE_WRAPPER_GC_US_I_0"/>
148
+
<value value="81" name="A8XX_DEBUGBUS_UCHE_GC_US_I_0"/>
149
+
<value value="82" name="A8XX_DEBUGBUS_UCHE_GC_US_I_1"/>
150
+
<value value="83" name="A8XX_DEBUGBUS_UCHE_GC_US_I_0_1"/>
151
+
<value value="84" name="A8XX_DEBUGBUS_UCHE_GC_US_I_1_1"/>
152
+
<value value="128" name="A8XX_DEBUGBUS_CP_GC_S_0_I_0"/>
153
+
<value value="129" name="A8XX_DEBUGBUS_PC_BR_S_0_I_0"/>
154
+
<value value="130" name="A8XX_DEBUGBUS_PC_BV_S_0_I_0"/>
155
+
<value value="131" name="A8XX_DEBUGBUS_TESS_GC_S_0_I_0"/>
156
+
<value value="132" name="A8XX_DEBUGBUS_TSEFE_GC_S_0_I_0"/>
157
+
<value value="133" name="A8XX_DEBUGBUS_TSEBE_GC_S_0_I_0"/>
158
+
<value value="134" name="A8XX_DEBUGBUS_RAS_GC_S_0_I_0"/>
159
+
<value value="135" name="A8XX_DEBUGBUS_LRZ_BR_S_0_I_0"/>
160
+
<value value="136" name="A8XX_DEBUGBUS_LRZ_BV_S_0_I_0"/>
161
+
<value value="137" name="A8XX_DEBUGBUS_VFDP_GC_S_0_I_0"/>
162
+
<value value="138" name="A8XX_DEBUGBUS_GPC_BR_S_0_I_0"/>
163
+
<value value="139" name="A8XX_DEBUGBUS_GPC_BV_S_0_I_0"/>
164
+
<value value="140" name="A8XX_DEBUGBUS_VPCFE_BR_S_0_I_0"/>
165
+
<value value="141" name="A8XX_DEBUGBUS_VPCFE_BV_S_0_I_0"/>
166
+
<value value="142" name="A8XX_DEBUGBUS_VPCBE_BR_S_0_I_0"/>
167
+
<value value="143" name="A8XX_DEBUGBUS_VPCBE_BV_S_0_I_0"/>
168
+
<value value="144" name="A8XX_DEBUGBUS_CCHE_GC_S_0_I_0"/>
169
+
<value value="145" name="A8XX_DEBUGBUS_DBGC_GC_S_0_I_0"/>
170
+
<value value="146" name="A8XX_DEBUGBUS_LARC_GC_S_0_I_0"/>
171
+
<value value="147" name="A8XX_DEBUGBUS_RBBM_GC_S_0_I_0"/>
172
+
<value value="148" name="A8XX_DEBUGBUS_CCRE_GC_S_0_I_0"/>
173
+
<value value="149" name="A8XX_DEBUGBUS_CGC_GC_S_0_I_0"/>
174
+
<value value="150" name="A8XX_DEBUGBUS_GMU_GC_S_0_I_0"/>
175
+
<value value="151" name="A8XX_DEBUGBUS_SLICE_GC_S_0_I_0"/>
176
+
<value value="152" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_0_I_0"/>
177
+
<value value="160" name="A8XX_DEBUGBUS_USP_GC_S_0_I_0"/>
178
+
<value value="161" name="A8XX_DEBUGBUS_USP_GC_S_0_I_1"/>
179
+
<value value="166" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_0"/>
180
+
<value value="167" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_1"/>
181
+
<value value="168" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_2"/>
182
+
<value value="169" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_3"/>
183
+
<value value="178" name="A8XX_DEBUGBUS_TP_GC_S_0_I_0"/>
184
+
<value value="179" name="A8XX_DEBUGBUS_TP_GC_S_0_I_1"/>
185
+
<value value="180" name="A8XX_DEBUGBUS_TP_GC_S_0_I_2"/>
186
+
<value value="181" name="A8XX_DEBUGBUS_TP_GC_S_0_I_3"/>
187
+
<value value="190" name="A8XX_DEBUGBUS_RB_GC_S_0_I_0"/>
188
+
<value value="191" name="A8XX_DEBUGBUS_RB_GC_S_0_I_1"/>
189
+
<value value="196" name="A8XX_DEBUGBUS_CCU_GC_S_0_I_0"/>
190
+
<value value="197" name="A8XX_DEBUGBUS_CCU_GC_S_0_I_1"/>
191
+
<value value="202" name="A8XX_DEBUGBUS_HLSQ_GC_S_0_I_0"/>
192
+
<value value="203" name="A8XX_DEBUGBUS_HLSQ_GC_S_0_I_1"/>
193
+
<value value="208" name="A8XX_DEBUGBUS_VFD_GC_S_0_I_0"/>
194
+
<value value="209" name="A8XX_DEBUGBUS_VFD_GC_S_0_I_1"/>
195
+
<value value="256" name="A8XX_DEBUGBUS_CP_GC_S_1_I_0"/>
196
+
<value value="257" name="A8XX_DEBUGBUS_PC_BR_S_1_I_0"/>
197
+
<value value="258" name="A8XX_DEBUGBUS_PC_BV_S_1_I_0"/>
198
+
<value value="259" name="A8XX_DEBUGBUS_TESS_GC_S_1_I_0"/>
199
+
<value value="260" name="A8XX_DEBUGBUS_TSEFE_GC_S_1_I_0"/>
200
+
<value value="261" name="A8XX_DEBUGBUS_TSEBE_GC_S_1_I_0"/>
201
+
<value value="262" name="A8XX_DEBUGBUS_RAS_GC_S_1_I_0"/>
202
+
<value value="263" name="A8XX_DEBUGBUS_LRZ_BR_S_1_I_0"/>
203
+
<value value="264" name="A8XX_DEBUGBUS_LRZ_BV_S_1_I_0"/>
204
+
<value value="265" name="A8XX_DEBUGBUS_VFDP_GC_S_1_I_0"/>
205
+
<value value="266" name="A8XX_DEBUGBUS_GPC_BR_S_1_I_0"/>
206
+
<value value="267" name="A8XX_DEBUGBUS_GPC_BV_S_1_I_0"/>
207
+
<value value="268" name="A8XX_DEBUGBUS_VPCFE_BR_S_1_I_0"/>
208
+
<value value="269" name="A8XX_DEBUGBUS_VPCFE_BV_S_1_I_0"/>
209
+
<value value="270" name="A8XX_DEBUGBUS_VPCBE_BR_S_1_I_0"/>
210
+
<value value="271" name="A8XX_DEBUGBUS_VPCBE_BV_S_1_I_0"/>
211
+
<value value="272" name="A8XX_DEBUGBUS_CCHE_GC_S_1_I_0"/>
212
+
<value value="273" name="A8XX_DEBUGBUS_DBGC_GC_S_1_I_0"/>
213
+
<value value="274" name="A8XX_DEBUGBUS_LARC_GC_S_1_I_0"/>
214
+
<value value="275" name="A8XX_DEBUGBUS_RBBM_GC_S_1_I_0"/>
215
+
<value value="276" name="A8XX_DEBUGBUS_CCRE_GC_S_1_I_0"/>
216
+
<value value="277" name="A8XX_DEBUGBUS_CGC_GC_S_1_I_0"/>
217
+
<value value="278" name="A8XX_DEBUGBUS_GMU_GC_S_1_I_0"/>
218
+
<value value="279" name="A8XX_DEBUGBUS_SLICE_GC_S_1_I_0"/>
219
+
<value value="280" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_1_I_0"/>
220
+
<value value="288" name="A8XX_DEBUGBUS_USP_GC_S_1_I_0"/>
221
+
<value value="289" name="A8XX_DEBUGBUS_USP_GC_S_1_I_1"/>
222
+
<value value="294" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_0"/>
223
+
<value value="295" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_1"/>
224
+
<value value="296" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_2"/>
225
+
<value value="297" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_3"/>
226
+
<value value="306" name="A8XX_DEBUGBUS_TP_GC_S_1_I_0"/>
227
+
<value value="307" name="A8XX_DEBUGBUS_TP_GC_S_1_I_1"/>
228
+
<value value="308" name="A8XX_DEBUGBUS_TP_GC_S_1_I_2"/>
229
+
<value value="309" name="A8XX_DEBUGBUS_TP_GC_S_1_I_3"/>
230
+
<value value="318" name="A8XX_DEBUGBUS_RB_GC_S_1_I_0"/>
231
+
<value value="319" name="A8XX_DEBUGBUS_RB_GC_S_1_I_1"/>
232
+
<value value="324" name="A8XX_DEBUGBUS_CCU_GC_S_1_I_0"/>
233
+
<value value="325" name="A8XX_DEBUGBUS_CCU_GC_S_1_I_1"/>
234
+
<value value="330" name="A8XX_DEBUGBUS_HLSQ_GC_S_1_I_0"/>
235
+
<value value="331" name="A8XX_DEBUGBUS_HLSQ_GC_S_1_I_1"/>
236
+
<value value="336" name="A8XX_DEBUGBUS_VFD_GC_S_1_I_0"/>
237
+
<value value="337" name="A8XX_DEBUGBUS_VFD_GC_S_1_I_1"/>
238
+
<value value="384" name="A8XX_DEBUGBUS_CP_GC_S_2_I_0"/>
239
+
<value value="385" name="A8XX_DEBUGBUS_PC_BR_S_2_I_0"/>
240
+
<value value="386" name="A8XX_DEBUGBUS_PC_BV_S_2_I_0"/>
241
+
<value value="387" name="A8XX_DEBUGBUS_TESS_GC_S_2_I_0"/>
242
+
<value value="388" name="A8XX_DEBUGBUS_TSEFE_GC_S_2_I_0"/>
243
+
<value value="389" name="A8XX_DEBUGBUS_TSEBE_GC_S_2_I_0"/>
244
+
<value value="390" name="A8XX_DEBUGBUS_RAS_GC_S_2_I_0"/>
245
+
<value value="391" name="A8XX_DEBUGBUS_LRZ_BR_S_2_I_0"/>
246
+
<value value="392" name="A8XX_DEBUGBUS_LRZ_BV_S_2_I_0"/>
247
+
<value value="393" name="A8XX_DEBUGBUS_VFDP_GC_S_2_I_0"/>
248
+
<value value="394" name="A8XX_DEBUGBUS_GPC_BR_S_2_I_0"/>
249
+
<value value="395" name="A8XX_DEBUGBUS_GPC_BV_S_2_I_0"/>
250
+
<value value="396" name="A8XX_DEBUGBUS_VPCFE_BR_S_2_I_0"/>
251
+
<value value="397" name="A8XX_DEBUGBUS_VPCFE_BV_S_2_I_0"/>
252
+
<value value="398" name="A8XX_DEBUGBUS_VPCBE_BR_S_2_I_0"/>
253
+
<value value="399" name="A8XX_DEBUGBUS_VPCBE_BV_S_2_I_0"/>
254
+
<value value="400" name="A8XX_DEBUGBUS_CCHE_GC_S_2_I_0"/>
255
+
<value value="401" name="A8XX_DEBUGBUS_DBGC_GC_S_2_I_0"/>
256
+
<value value="402" name="A8XX_DEBUGBUS_LARC_GC_S_2_I_0"/>
257
+
<value value="403" name="A8XX_DEBUGBUS_RBBM_GC_S_2_I_0"/>
258
+
<value value="404" name="A8XX_DEBUGBUS_CCRE_GC_S_2_I_0"/>
259
+
<value value="405" name="A8XX_DEBUGBUS_CGC_GC_S_2_I_0"/>
260
+
<value value="406" name="A8XX_DEBUGBUS_GMU_GC_S_2_I_0"/>
261
+
<value value="407" name="A8XX_DEBUGBUS_SLICE_GC_S_2_I_0"/>
262
+
<value value="408" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_2_I_0"/>
263
+
<value value="416" name="A8XX_DEBUGBUS_USP_GC_S_2_I_0"/>
264
+
<value value="417" name="A8XX_DEBUGBUS_USP_GC_S_2_I_1"/>
265
+
<value value="422" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_0"/>
266
+
<value value="423" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_1"/>
267
+
<value value="424" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_2"/>
268
+
<value value="425" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_3"/>
269
+
<value value="434" name="A8XX_DEBUGBUS_TP_GC_S_2_I_0"/>
270
+
<value value="435" name="A8XX_DEBUGBUS_TP_GC_S_2_I_1"/>
271
+
<value value="436" name="A8XX_DEBUGBUS_TP_GC_S_2_I_2"/>
272
+
<value value="437" name="A8XX_DEBUGBUS_TP_GC_S_2_I_3"/>
273
+
<value value="446" name="A8XX_DEBUGBUS_RB_GC_S_2_I_0"/>
274
+
<value value="447" name="A8XX_DEBUGBUS_RB_GC_S_2_I_1"/>
275
+
<value value="452" name="A8XX_DEBUGBUS_CCU_GC_S_2_I_0"/>
276
+
<value value="453" name="A8XX_DEBUGBUS_CCU_GC_S_2_I_1"/>
277
+
<value value="458" name="A8XX_DEBUGBUS_HLSQ_GC_S_2_I_0"/>
278
+
<value value="459" name="A8XX_DEBUGBUS_HLSQ_GC_S_2_I_1"/>
279
+
<value value="464" name="A8XX_DEBUGBUS_VFD_GC_S_2_I_0"/>
280
+
<value value="465" name="A8XX_DEBUGBUS_VFD_GC_S_2_I_1"/>
281
+
</enum>
282
+
283
+
<enum name="a8xx_usptp_id">
284
+
<value value="0" name="A8XX_uSPTP0"/>
285
+
<value value="1" name="A8XX_uSPTP1"/>
286
+
<value value="15" name="A8XX_SPTOP"/>
287
+
</enum>
288
+
289
+
<enum name="a8xx_tex_swiz">
290
+
<value name="A8XX_SWIZ_IDENTITY" value="0"/>
291
+
<value name="A8XX_SWIZ_ZERO" value="1"/>
292
+
<value name="A8XX_SWIZ_ONE" value="2"/>
293
+
<value name="A8XX_SWIZ_X" value="3"/>
294
+
<value name="A8XX_SWIZ_Y" value="4"/>
295
+
<value name="A8XX_SWIZ_Z" value="5"/>
296
+
<value name="A8XX_SWIZ_W" value="6"/>
297
+
</enum>
298
+
299
+
</database>
+12
drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
+12
drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
···
11
11
<value name="A5XX" value="5"/>
12
12
<value name="A6XX" value="6"/>
13
13
<value name="A7XX" value="7"/>
14
+
<value name="A8XX" value="8"/>
14
15
</enum>
15
16
16
17
<enum name="adreno_pa_su_sc_draw">
···
396
395
<value value="0x6" name="TEX_PREFETCH_UNK6"/>
397
396
<doc> Results in color being zero </doc>
398
397
<value value="0x7" name="TEX_PREFETCH_UNK7"/>
398
+
</enum>
399
+
400
+
<enum name="adreno_pipe">
401
+
<value value="0" name="PIPE_NONE"/>
402
+
<value value="1" name="PIPE_BR"/>
403
+
<value value="2" name="PIPE_BV"/>
404
+
<value value="3" name="PIPE_LPAC"/>
405
+
<value value="4" name="PIPE_AQE0"/>
406
+
<value value="5" name="PIPE_AQE1"/>
407
+
<value value="6" name="PIPE_DDE_BR"/>
408
+
<value value="7" name="PIPE_DDE_BV"/>
399
409
</enum>
400
410
401
411
</database>
+242
-109
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+242
-109
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
···
6
6
<import file="adreno/adreno_common.xml"/>
7
7
8
8
<enum name="vgt_event_type" varset="chip">
9
-
<value name="VS_DEALLOC" value="0"/>
10
-
<value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
11
-
<value name="VS_DONE_TS" value="2"/>
12
-
<value name="PS_DONE_TS" value="3"/>
9
+
<value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>
10
+
<value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>
11
+
<value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>
12
+
<value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>
13
13
<doc>
14
14
Flushes dirty data from UCHE, and also writes a GPU timestamp to
15
15
the address if one is provided.
16
16
</doc>
17
-
<value name="CACHE_FLUSH_TS" value="4"/>
18
-
<value name="CONTEXT_DONE" value="5"/>
19
-
<value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
20
-
<value name="VIZQUERY_START" value="7" variants="A2XX"/>
21
-
<value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
22
-
<value name="VIZQUERY_END" value="8" variants="A2XX"/>
23
-
<value name="SC_WAIT_WC" value="9" variants="A2XX"/>
24
-
<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/>
25
-
<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/>
26
-
<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/>
17
+
<value name="CACHE_FLUSH_TS" value="0x04"/>
18
+
<value name="CONTEXT_DONE" value="0x05"/>
19
+
<value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/>
20
+
<value name="VIZQUERY_START" value="0x07" variants="A2XX"/>
21
+
<value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/>
22
+
<value name="VIZQUERY_END" value="0x08" variants="A2XX"/>
23
+
<value name="SC_WAIT_WC" value="0x09" variants="A2XX"/>
24
+
<value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>
25
+
<value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/>
26
+
<value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/>
27
27
<!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
28
-
<value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
29
-
<value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
30
-
<value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
31
-
<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
32
-
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
28
+
<value name="RST_PIX_CNT" value="0x0d" variants="A2XX-A4XX"/>
29
+
<value name="RST_VTX_CNT" value="0x0e" variants="A2XX-A4XX"/>
30
+
<value name="TILE_FLUSH" value="0x0f" variants="A2XX-A4XX"/>
31
+
<value name="STAT_EVENT" value="0x10" variants="A2XX-A4XX"/>
32
+
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="0x14" variants="A2XX-A4XX"/>
33
33
<doc>
34
34
If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
35
35
sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
36
36
memory, skipping UCHE.
37
37
</doc>
38
-
<value name="ZPASS_DONE" value="21"/>
39
-
<value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
38
+
<value name="ZPASS_DONE" value="0x15"/>
39
+
<value name="CACHE_FLUSH_AND_INV_EVENT" value="0x16" variants="A2XX"/>
40
40
41
41
<doc>
42
42
Writes the GPU timestamp to the address that follows, once RB
43
43
access and flushes are complete.
44
44
</doc>
45
-
<value name="RB_DONE_TS" value="22" variants="A3XX-"/>
45
+
<value name="RB_DONE_TS" value="0x16" variants="A3XX-"/>
46
46
47
-
<value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
48
-
<value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
49
-
<value name="VS_FETCH_DONE" value="27"/>
50
-
<value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
47
+
<value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/>
48
+
<value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/>
49
+
<value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/>
50
+
<value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/>
51
51
52
52
<!-- a5xx events -->
53
-
<value name="WT_DONE_TS" value="8" variants="A5XX-"/>
54
-
<value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
55
-
<value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
56
-
<value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
57
-
<value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
58
-
<value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
59
-
<value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
60
-
<value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
61
-
<value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
53
+
<value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>
54
+
<value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/>
55
+
<value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/>
56
+
<value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/>
57
+
<value name="STOP_COMPUTE_CTRS" value="0x10" variants="A5XX-"/>
58
+
<value name="FLUSH_SO_0" value="0x11" variants="A5XX-"/>
59
+
<value name="FLUSH_SO_1" value="0x12" variants="A5XX-"/>
60
+
<value name="FLUSH_SO_2" value="0x13" variants="A5XX-"/>
61
+
<value name="FLUSH_SO_3" value="0x14" variants="A5XX-"/>
62
62
63
63
<doc>
64
64
Invalidates depth attachment data from the CCU. We assume this
65
65
happens in the last stage.
66
66
</doc>
67
-
<value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
67
+
<value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/>
68
68
69
69
<doc>
70
70
Invalidates color attachment data from the CCU. We assume this
71
71
happens in the last stage.
72
72
</doc>
73
-
<value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
73
+
<value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/>
74
74
75
75
<doc>
76
76
Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
77
77
along with its registers, would be better named RESOLVE).
78
78
</doc>
79
-
<value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
79
+
<value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/>
80
80
81
81
<doc>
82
82
Flushes depth attachment data from the CCU. We assume this
83
83
happens in the last stage.
84
84
</doc>
85
-
<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
85
+
<value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/>
86
86
87
87
<doc>
88
88
Flushes color attachment data from the CCU. We assume this
89
89
happens in the last stage.
90
90
</doc>
91
-
<value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
91
+
<value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/>
92
92
93
93
<doc>
94
-
2D blit to resolve GMEM to system memory (skipping CCU) at the
95
-
end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
96
-
more general blitting.
94
+
Triggers a resolve (GMEM to sysmem) or unresolve (sysmem to
95
+
GMEM) or clear blit, depending on CCU programming.
97
96
</doc>
98
-
<value name="BLIT" value="30" variants="A5XX-"/>
97
+
<value name="CCU_RESOLVE" value="0x1e" variants="A5XX-"/>
99
98
100
99
<doc>
101
100
Flip between the primary and secondary LRZ buffers. This is used
102
101
for concurrent binning, so that BV can write to one buffer while
103
102
BR reads from the other.
104
103
</doc>
105
-
<value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/>
104
+
<value name="LRZ_FLIP_BUFFER" value="0x24" variants="A7XX-"/>
106
105
107
106
<doc>
108
107
Clears based on GRAS_LRZ_CNTL configuration, could clear
···
114
115
CUR_DIR_UNSET = 0x3
115
116
Clear of direction means setting the direction to CUR_DIR_UNSET.
116
117
</doc>
117
-
<value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
118
+
<value name="LRZ_CLEAR" value="0x25" variants="A5XX-"/>
118
119
119
-
<value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
120
-
<value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
121
-
<value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
122
-
<value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX"/>
123
-
<value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/>
124
-
<value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
125
-
<value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
126
-
<value name="VSC_BINNING_START" value="44" variants="A5XX-"/>
127
-
<value name="VSC_BINNING_END" value="45" variants="A5XX-"/>
120
+
<value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/>
121
+
<value name="LRZ_CACHE_FLUSH" value="0x26" variants="A7XX-"/>
122
+
<value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-A6XX"/>
123
+
<value name="BLIT_OP_COPY_2D" value="0x28" variants="A5XX-A6XX"/>
124
+
<value name="LRZ_CACHE_INVALIDATE" value="0x28" variants="A7XX-"/>
125
+
<value name="LRZ_Q_CACHE_INVALIDATE" value="0x29" variants="A7XX-"/>
126
+
<value name="BLIT_OP_SCALE_2D" value="0x2a" variants="A5XX-"/>
127
+
<value name="CONTEXT_DONE_2D" value="0x2b" variants="A5XX-"/>
128
+
<value name="VSC_BINNING_START" value="0x2c" variants="A5XX-"/>
129
+
<value name="VSC_BINNING_END" value="0x2d" variants="A5XX-"/>
128
130
129
131
<!-- a6xx events -->
130
132
<doc>
131
133
Invalidates UCHE.
132
134
</doc>
133
-
<value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
135
+
<value name="CACHE_INVALIDATE" value="0x31" variants="A6XX"/>
134
136
135
-
<value name="LABEL" value="63" variants="A6XX-"/>
137
+
<value name="DEBUG_LABEL" value="0x3f" variants="A6XX-"/>
136
138
137
139
<!-- note, some of these are the same as a6xx, just named differently -->
138
140
139
141
<doc> Doesn't seem to do anything </doc>
140
-
<value name="DUMMY_EVENT" value="1" variants="A7XX"/>
141
-
<value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
142
-
<value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
143
-
<value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
144
-
<value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
145
-
<value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
146
-
<value name="CCU_RESOLVE" value="30" variants="A7XX"/>
147
-
<value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
148
-
<value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
149
-
<value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
150
-
<value name="CACHE_RESET" value="48" variants="A7XX"/>
151
-
<value name="CACHE_CLEAN" value="49" variants="A7XX"/>
142
+
<value name="DUMMY_EVENT" value="0x01" variants="A7XX-"/>
143
+
<value name="CCU_INVALIDATE_DEPTH" value="0x18" variants="A7XX-"/>
144
+
<value name="CCU_INVALIDATE_COLOR" value="0x19" variants="A7XX-"/>
145
+
<value name="CCU_RESOLVE_CLEAN" value="0x1a" variants="A7XX-"/>
146
+
<value name="CCU_FLUSH_DEPTH" value="0x1c" variants="A7XX-"/>
147
+
<value name="CCU_FLUSH_COLOR" value="0x1d" variants="A7XX-"/>
148
+
<value name="CCU_END_RESOLVE_GROUP" value="0x1f" variants="A7XX-"/>
149
+
<value name="CCU_CLEAN_DEPTH" value="0x20" variants="A7XX-"/>
150
+
<value name="CCU_CLEAN_COLOR" value="0x21" variants="A7XX-"/>
151
+
<value name="CACHE_RESET" value="0x30" variants="A7XX-"/>
152
+
<value name="CACHE_CLEAN" value="0x31" variants="A7XX-"/>
152
153
<!-- TODO: deal with name conflicts with other gens -->
153
-
<value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
154
-
<value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
154
+
<value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/>
155
+
<value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/>
156
+
<value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/>
157
+
<value name="CCH_FAST_CLEAR_CLEAN" value="0x1b" variants="A8XX-"/>
155
158
</enum>
156
159
157
160
<enum name="pc_di_primtype">
···
311
310
<value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
312
311
<value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
313
312
<doc>generate a VS|PS_done event</doc>
314
-
<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
313
+
<value name="CP_EVENT_WRITE_SHD" value="0x58" variants="A2XX"/>
315
314
<doc>generate a cache flush done event</doc>
316
-
<value name="CP_EVENT_WRITE_CFL" value="0x59"/>
315
+
<value name="CP_EVENT_WRITE_CFL" value="0x59" variants="A2XX"/>
317
316
<doc>generate a z_pass done event</doc>
318
-
<value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
317
+
<value name="CP_EVENT_WRITE_ZPD" value="0x5b" variants="A2XX"/>
319
318
<doc>
320
319
not sure the real name, but this seems to be what is used for
321
320
opencl, instead of CP_DRAW_INDX..
···
336
335
<doc>load constant into chip and to memory</doc>
337
336
<value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
338
337
<doc>load sequencer instruction memory (pointer-based)</doc>
339
-
<value name="CP_IM_LOAD" value="0x27"/>
338
+
<value name="CP_IM_LOAD" value="0x27" variants="A2XX"/>
340
339
<doc>load sequencer instruction memory (code embedded in packet)</doc>
341
-
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
340
+
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b" variants="A2XX"/>
342
341
<doc>load constants from a location in memory</doc>
343
342
<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
344
343
<doc>selective invalidation of state pointers</doc>
···
663
662
<value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/>
664
663
665
664
<value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/>
665
+
666
+
<value name="CP_SKIP_IB_MODE" value="0x27" variants="A7XX-"/>
667
+
668
+
<value name="CP_MEMORY_MAP_UPDATE" value="0x58" variants="A8XX-"/>
669
+
670
+
<value name="CP_BARRIER" value="0x59" variants="A8XX-"/>
666
671
</enum>
667
672
668
673
···
1807
1800
<value value="6" name="RM6_BIN_RESOLVE"/>
1808
1801
<value value="7" name="RM6_BIN_RENDER_END"/>
1809
1802
<value value="8" name="RM6_COMPUTE"/>
1810
-
<value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1803
+
<value value="12" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1811
1804
1812
1805
<!--
1813
1806
These values come from a6xx_set_marker() in the
1814
1807
downstream kernel, and they can only be set by the kernel
1815
1808
-->
1816
-
<value value="0xd" name="RM6_IB1LIST_START"/>
1817
-
<value value="0xe" name="RM6_IB1LIST_END"/>
1809
+
<value value="13" name="RM6_IB1LIST_START"/>
1810
+
<value value="14" name="RM6_IB1LIST_END"/>
1811
+
<value value="15" name="RM7_BIN_VISIBILITY_END"/>
1812
+
1813
+
<!-- new in a8xx: -->
1814
+
<value value="32" name="RM8_DEPTH_PASS_START"/>
1815
+
<value value="33" name="RM8_DEPTH_PASS_END"/>
1816
+
<value value="34" name="RM8_SET_RENDER_TARGET"/>
1817
+
<value value="35" name="RM8_PGMEM_ON"/>
1818
+
<value value="36" name="RM8_PGMEM_OFF"/>
1818
1819
</enum>
1819
-
<reg32 offset="0" name="0">
1820
-
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
1821
-
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
1820
+
<stripe varset="chip" variants="A6XX-A7XX">
1821
+
<reg32 offset="0" name="0">
1822
+
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
1823
+
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
1822
1824
1823
-
<bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
1824
-
<!-- used by preemption to determine if GMEM needs to be saved or not -->
1825
-
<bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
1826
1825
1827
-
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
1826
+
<bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
1827
+
<!-- used by preemption to determine if GMEM needs to be saved or not -->
1828
+
<bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
1828
1829
1829
-
<!--
1830
-
CP_SET_MARKER is used with these bits to create a
1831
-
critical section around a workaround for ray tracing.
1832
-
The workaround happens after BVH building, and appears
1833
-
to invalidate the RTU's BVH node cache. It makes sure
1834
-
that only one of BR/BV/LPAC is executing the
1835
-
workaround at a time, and no draws using RT on BV/LPAC
1836
-
are executing while the workaround is executed on BR (or
1837
-
vice versa, that no draws on BV/BR using RT are executed
1838
-
while the workaround executes on LPAC), by
1839
-
hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS.
1840
-
The blob usage is:
1841
1830
1842
-
CP_SET_MARKER(RT_WA_START)
1843
-
... workaround here ...
1844
-
CP_SET_MARKER(RT_WA_END)
1845
-
...
1846
-
CP_SET_MARKER(SHADER_USES_RT)
1847
-
CP_DRAW_INDX(...) or CP_EXEC_CS(...)
1848
-
-->
1849
-
<bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/>
1850
-
<bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/>
1851
-
<bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/>
1852
-
</reg32>
1831
+
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
1832
+
1833
+
1834
+
<!--
1835
+
CP_SET_MARKER is used with these bits to create a
1836
+
critical section around a workaround for ray tracing.
1837
+
The workaround happens after BVH building, and appears
1838
+
to invalidate the RTU's BVH node cache. It makes sure
1839
+
that only one of BR/BV/LPAC is executing the
1840
+
workaround at a time, and no draws using RT on BV/LPAC
1841
+
are executing while the workaround is executed on BR (or
1842
+
vice versa, that no draws on BV/BR using RT are executed
1843
+
while the workaround executes on LPAC), by
1844
+
hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS.
1845
+
The blob usage is:
1846
+
1847
+
1848
+
CP_SET_MARKER(RT_WA_START)
1849
+
... workaround here ...
1850
+
CP_SET_MARKER(RT_WA_END)
1851
+
...
1852
+
CP_SET_MARKER(SHADER_USES_RT)
1853
+
CP_DRAW_INDX(...) or CP_EXEC_CS(...)
1854
+
-->
1855
+
<bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/>
1856
+
<bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/>
1857
+
<bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/>
1858
+
</reg32>
1859
+
</stripe>
1860
+
<stripe varset="chip" variants="A8XX-">
1861
+
<reg32 offset="0" name="0">
1862
+
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
1863
+
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
1864
+
<bitfield name="MODE" low="0" high="6" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
1865
+
<bitfield name="USES_GMEM" pos="7" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
1866
+
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
1867
+
<!-- idk if the RT w/a fields apply to a8xx as well -->
1868
+
</reg32>
1869
+
</stripe>
1853
1870
</domain>
1854
1871
1855
1872
<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
···
2097
2066
payload *and* skipsaverestore is set. This is
2098
2067
expected to restore static register values not
2099
2068
saved when skipsaverestore is set.
2069
+
2070
+
On BV, a skipsaverestore preemption is triggered
2071
+
and this preamble type is executed whenever a
2072
+
CP_THREAD_CONTROL that synchronizes threads
2073
+
happens. This can be explicitly via
2074
+
SYNC_THREADS, or implicitly when the value of
2075
+
CONCURRENT_BIN_DISABLE changes from the previous
2076
+
thread control.
2100
2077
</doc>
2101
2078
</value>
2102
2079
<value name="POSTAMBLE_AMBLE_TYPE" value="2">
···
2345
2306
<reg32 offset="2" name="2">
2346
2307
<bitfield name="IB_SIZE" low="0" high="19"/>
2347
2308
</reg32>
2309
+
</domain>
2310
+
2311
+
<domain name="CP_RESOURCE_LIST" width="32">
2312
+
<doc>
2313
+
A7xx introduces the "resource table" which is managed by
2314
+
CP_RESOURCE_LIST. It is used to synchronize BR and BV access
2315
+
to resources such as LRZ buffers.
2316
+
2317
+
The resource table consists of resources that are in-use by BR.
2318
+
Each "resource" has a base address, which is
2319
+
usually a pointer but is treated by the HW as an opaque handle,
2320
+
a read/write bit, and a timestamp when it was last used.
2321
+
Resources are removed from the table upon event completion when
2322
+
a special CP_EVENT_WRITE::CLEAR_RENDER_RESOURCE bit is set, which
2323
+
will remove all resources with a timestamp up to the current
2324
+
timestamp.
2325
+
2326
+
CP_RESOURCE_LIST first specifies a list of BV resources. For
2327
+
each BV resource, the HW will check if there is a corresponding
2328
+
BR resource in the table, and if at least one of the BV and BR
2329
+
resources is marked WRITE then it will stall until the BR
2330
+
resource is removed.
2331
+
2332
+
It then specifies a list of BR resources. These will be added to
2333
+
the resource table, unless there is an overflow in which case
2334
+
the designated overflow register will have bit 0 set. Overflow
2335
+
should cause the next binning pass to stall until BR is done,
2336
+
effectively disabling concurrent binning.
2337
+
2338
+
CP_RESOURCE_LIST must be executed by BV. BR resources are added
2339
+
by BV and removed by BR.
2340
+
2341
+
There is a separate table for "LRZ resources." These behave a
2342
+
bit differently: specifying an LRZ resource via BV_RES_LRZ
2343
+
stalls on any matching resource existing and then adds it to the
2344
+
table, making it both a BV and BR resource in one. There is a
2345
+
separate CLEAR_LRZ_RESOURCE bit for removing resources from the
2346
+
LRZ table, and it only removes one resource given by a base
2347
+
address passed to CP_EVENT_WRITE. Therefore timestamps are
2348
+
unnecessary.
2349
+
</doc>
2350
+
<reg32 offset="0" name="BV_COUNT" type="uint"/>
2351
+
<doc>
2352
+
What follows is a list of CP_BV_RESOURCE and then CP_RESOURCE_LIST_BR.
2353
+
</doc>
2354
+
</domain>
2355
+
2356
+
<domain name="CP_BV_RESOURCE" width="32">
2357
+
<doc>
2358
+
BV resources don't go in the table. Instead CP waits until any
2359
+
corresponding BR resources with the same base pointer are
2360
+
finished before the packet completes.
2361
+
</doc>
2362
+
<enum name="cp_bv_resource_encoding">
2363
+
<value value="0" name="BV_RES_DIRECT"/>
2364
+
<doc>
2365
+
INDIRECT resources are encoded as a 32b offset + 3b
2366
+
bindless base selector. The offset is added to the given
2367
+
BINDLESS_BASE pseudoregister and then the 64b value
2368
+
fetched there is used as the pointer.
2369
+
</doc>
2370
+
<value value="1" name="BV_RES_INDIRECT_READ"/>
2371
+
<value value="2" name="BV_RES_LRZ"/>
2372
+
<value value="3" name="BV_RES_INDIRECT_WRITE"/>
2373
+
</enum>
2374
+
<reg64 offset="0" name="0">
2375
+
<bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/>
2376
+
<bitfield name="WRITE" pos="0" type="boolean"/>
2377
+
<bitfield name="ENCODING" low="62" high="63" type="cp_bv_resource_encoding"/>
2378
+
</reg64>
2379
+
</domain>
2380
+
2381
+
<domain name="CP_RESOURCE_LIST_BR" width="32">
2382
+
<reg32 offset="0" name="0">
2383
+
<bitfield name="BR_COUNT" low="0" high="23" type="uint"/>
2384
+
<bitfield name="OVERFLOW_ONCHIP_ADDR" low="24" high="26"/>
2385
+
<bitfield name="OVERFLOW" pos="31" type="boolean"/>
2386
+
</reg32>
2387
+
<doc>
2388
+
What follows is a list of CP_BR_RESOURCE.
2389
+
</doc>
2390
+
</domain>
2391
+
2392
+
<domain name="CP_BR_RESOURCE" width="32">
2393
+
<enum name="cp_br_resource_encoding">
2394
+
<value value="0" name="BR_RES_DIRECT"/>
2395
+
<value value="2" name="BR_RES_INDIRECT_READ"/>
2396
+
<value value="3" name="BR_RES_INDIRECT_WRITE"/> <!-- set WRITE bit -->
2397
+
</enum>
2398
+
<reg64 offset="0" name="0">
2399
+
<bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/>
2400
+
<bitfield name="WRITE" pos="0" type="boolean"/>
2401
+
<bitfield name="ENCODING" low="62" high="63" type="cp_br_resource_encoding"/>
2402
+
</reg64>
2348
2403
</domain>
2349
2404
2350
2405
</database>
+12
-7
drivers/gpu/drm/msm/registers/gen_header.py
+12
-7
drivers/gpu/drm/msm/registers/gen_header.py
···
189
189
print(" return (struct fd_reg_pair) {")
190
190
print(" .reg = (uint32_t)%s," % reg.reg_offset())
191
191
print(" .value =")
192
+
cast = "(uint64_t)" if reg.bit_size == 64 else ""
192
193
for f in self.fields:
193
194
if f.type in [ "address", "waddress" ]:
194
195
continue
195
196
else:
196
197
type, val = f.ctype("fields.%s" % field_name(reg, f))
197
-
print(" (%-40s << %2d) |" % (val, f.low))
198
+
print(" (%s%-40s << %2d) |" % (cast, val, f.low))
198
199
value_name = "dword"
199
200
if reg.bit_size == 64:
200
201
value_name = "qword"
···
265
264
(prefix, prefix, prefix, skip))
266
265
267
266
268
-
def dump(self, is_deprecated, prefix=None):
267
+
def dump(self, is_deprecated, prefix=None, reg=None):
269
268
if prefix is None:
270
269
prefix = self.name
271
-
if self.reg and self.reg.bit_size == 64:
270
+
reg64 = reg and self.reg and self.reg.bit_size == 64
271
+
if reg64:
272
272
print("static inline uint32_t %s_LO(uint32_t val)\n{" % prefix)
273
273
print("\treturn val;\n}")
274
274
print("static inline uint32_t %s_HI(uint32_t val)\n{" % prefix)
···
285
283
elif f.type == "boolean" or (f.type is None and f.low == f.high):
286
284
tab_to("#define %s" % name, "0x%08x" % (1 << f.low))
287
285
else:
288
-
tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high))
286
+
typespec = "ull" if reg64 else "u"
287
+
tab_to("#define %s__MASK" % name, "0x%08x%s" % (mask(f.low, f.high), typespec))
289
288
tab_to("#define %s__SHIFT" % name, "%d" % f.low)
290
289
type, val = f.ctype("val")
290
+
ret_type = "uint64_t" if reg64 else "uint32_t"
291
+
cast = "(uint64_t)" if reg64 else ""
291
292
292
-
print("static inline uint32_t %s(%s val)\n{" % (name, type))
293
+
print("static inline %s %s(%s val)\n{" % (ret_type, name, type))
293
294
if f.shr > 0:
294
295
print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1))
295
-
print("\treturn ((%s) << %s__SHIFT) & %s__MASK;\n}" % (val, name, name))
296
+
print("\treturn (%s(%s) << %s__SHIFT) & %s__MASK;\n}" % (cast, val, name, name))
296
297
print()
297
298
298
299
class Array(object):
···
442
437
print("static inline%s uint32_t REG_%s(%s) { return 0x%08x + %s; }" % (depcrstr, self.full_name, proto, offset, strides))
443
438
444
439
if self.bitset.inline:
445
-
self.bitset.dump(is_deprecated, self.full_name)
440
+
self.bitset.dump(is_deprecated, self.full_name, self)
446
441
print("")
447
442
448
443
def dump_pack_struct(self, is_deprecated):