tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/msm/a8xx: Implement IFPC support for A840

Implement pwrup reglist support and add the necessary register
configurations to enable IFPC support on A840

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714679/
Message-ID: <20260327-a8xx-gpu-batch2-v2-14-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark ee37487f dd108bb9

+281 -3
+184 -1
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
··· 1891 1891 { }, 1892 1892 }; 1893 1893 1894 + static const uint32_t a840_pwrup_reglist_regs[] = { 1895 + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 1896 + REG_A7XX_SP_READ_SEL, 1897 + REG_A6XX_UCHE_MODE_CNTL, 1898 + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 1899 + REG_A8XX_UCHE_GBIF_GX_CONFIG, 1900 + REG_A8XX_UCHE_CCHE_MODE_CNTL, 1901 + REG_A8XX_UCHE_CCHE_CACHE_WAYS, 1902 + REG_A8XX_UCHE_CACHE_WAYS, 1903 + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, 1904 + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, 1905 + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN, 1906 + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1, 1907 + REG_A8XX_UCHE_CCHE_TRAP_BASE, 1908 + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, 1909 + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, 1910 + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, 1911 + REG_A8XX_UCHE_HW_DBG_CNTL, 1912 + REG_A8XX_UCHE_WRITE_THRU_BASE, 1913 + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, 1914 + REG_A8XX_UCHE_TRAP_BASE, 1915 + REG_A8XX_UCHE_TRAP_BASE + 1, 1916 + REG_A8XX_UCHE_CLIENT_PF, 1917 + REG_A8XX_RB_CMP_NC_MODE_CNTL, 1918 + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, 1919 + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, 1920 + REG_A6XX_TPL1_NC_MODE_CNTL, 1921 + REG_A6XX_TPL1_DBG_ECO_CNTL, 1922 + REG_A6XX_TPL1_DBG_ECO_CNTL1, 1923 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 1924 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1925 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1926 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1927 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1928 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), 1929 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), 1930 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), 1931 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), 1932 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), 1933 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), 1934 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), 1935 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), 1936 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), 1937 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), 1938 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), 1939 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), 1940 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), 1941 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), 1942 + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), 1943 + }; 1944 + DECLARE_ADRENO_REGLIST_LIST(a840_pwrup_reglist); 1945 + 1946 + static const u32 a840_ifpc_reglist_regs[] = { 1947 + REG_A8XX_RBBM_NC_MODE_CNTL, 1948 + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 1949 + REG_A6XX_SP_NC_MODE_CNTL, 1950 + REG_A6XX_SP_CHICKEN_BITS, 1951 + REG_A8XX_SP_SS_CHICKEN_BITS_0, 1952 + REG_A7XX_SP_CHICKEN_BITS_1, 1953 + REG_A7XX_SP_CHICKEN_BITS_2, 1954 + REG_A7XX_SP_CHICKEN_BITS_3, 1955 + REG_A8XX_SP_CHICKEN_BITS_4, 1956 + REG_A6XX_SP_PERFCTR_SHADER_MASK, 1957 + REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, 1958 + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, 1959 + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 1960 + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 1961 + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, 1962 + REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, 1963 + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN, 1964 + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1, 1965 + REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, 1966 + REG_A8XX_RBBM_PERFCTR_CNTL, 1967 + REG_A8XX_CP_PROTECT_GLOBAL(0), 1968 + REG_A8XX_CP_PROTECT_GLOBAL(1), 1969 + REG_A8XX_CP_PROTECT_GLOBAL(2), 1970 + REG_A8XX_CP_PROTECT_GLOBAL(3), 1971 + REG_A8XX_CP_PROTECT_GLOBAL(4), 1972 + REG_A8XX_CP_PROTECT_GLOBAL(5), 1973 + REG_A8XX_CP_PROTECT_GLOBAL(6), 1974 + REG_A8XX_CP_PROTECT_GLOBAL(7), 1975 + REG_A8XX_CP_PROTECT_GLOBAL(8), 1976 + REG_A8XX_CP_PROTECT_GLOBAL(9), 1977 + REG_A8XX_CP_PROTECT_GLOBAL(10), 1978 + REG_A8XX_CP_PROTECT_GLOBAL(11), 1979 + REG_A8XX_CP_PROTECT_GLOBAL(12), 1980 + REG_A8XX_CP_PROTECT_GLOBAL(13), 1981 + REG_A8XX_CP_PROTECT_GLOBAL(14), 1982 + REG_A8XX_CP_PROTECT_GLOBAL(15), 1983 + REG_A8XX_CP_PROTECT_GLOBAL(16), 1984 + REG_A8XX_CP_PROTECT_GLOBAL(17), 1985 + REG_A8XX_CP_PROTECT_GLOBAL(18), 1986 + REG_A8XX_CP_PROTECT_GLOBAL(19), 1987 + REG_A8XX_CP_PROTECT_GLOBAL(20), 1988 + REG_A8XX_CP_PROTECT_GLOBAL(21), 1989 + REG_A8XX_CP_PROTECT_GLOBAL(22), 1990 + REG_A8XX_CP_PROTECT_GLOBAL(23), 1991 + REG_A8XX_CP_PROTECT_GLOBAL(24), 1992 + REG_A8XX_CP_PROTECT_GLOBAL(25), 1993 + REG_A8XX_CP_PROTECT_GLOBAL(26), 1994 + REG_A8XX_CP_PROTECT_GLOBAL(27), 1995 + REG_A8XX_CP_PROTECT_GLOBAL(28), 1996 + REG_A8XX_CP_PROTECT_GLOBAL(29), 1997 + REG_A8XX_CP_PROTECT_GLOBAL(30), 1998 + REG_A8XX_CP_PROTECT_GLOBAL(31), 1999 + REG_A8XX_CP_PROTECT_GLOBAL(32), 2000 + REG_A8XX_CP_PROTECT_GLOBAL(33), 2001 + REG_A8XX_CP_PROTECT_GLOBAL(34), 2002 + REG_A8XX_CP_PROTECT_GLOBAL(35), 2003 + REG_A8XX_CP_PROTECT_GLOBAL(36), 2004 + REG_A8XX_CP_PROTECT_GLOBAL(37), 2005 + REG_A8XX_CP_PROTECT_GLOBAL(38), 2006 + REG_A8XX_CP_PROTECT_GLOBAL(39), 2007 + REG_A8XX_CP_PROTECT_GLOBAL(40), 2008 + REG_A8XX_CP_PROTECT_GLOBAL(41), 2009 + REG_A8XX_CP_PROTECT_GLOBAL(42), 2010 + REG_A8XX_CP_PROTECT_GLOBAL(43), 2011 + REG_A8XX_CP_PROTECT_GLOBAL(44), 2012 + REG_A8XX_CP_PROTECT_GLOBAL(45), 2013 + REG_A8XX_CP_PROTECT_GLOBAL(46), 2014 + REG_A8XX_CP_PROTECT_GLOBAL(47), 2015 + REG_A8XX_CP_PROTECT_GLOBAL(48), 2016 + REG_A8XX_CP_PROTECT_GLOBAL(49), 2017 + REG_A8XX_CP_PROTECT_GLOBAL(50), 2018 + REG_A8XX_CP_PROTECT_GLOBAL(51), 2019 + REG_A8XX_CP_PROTECT_GLOBAL(52), 2020 + REG_A8XX_CP_PROTECT_GLOBAL(53), 2021 + REG_A8XX_CP_PROTECT_GLOBAL(54), 2022 + REG_A8XX_CP_PROTECT_GLOBAL(55), 2023 + REG_A8XX_CP_PROTECT_GLOBAL(56), 2024 + REG_A8XX_CP_PROTECT_GLOBAL(57), 2025 + REG_A8XX_CP_PROTECT_GLOBAL(58), 2026 + REG_A8XX_CP_PROTECT_GLOBAL(59), 2027 + REG_A8XX_CP_PROTECT_GLOBAL(60), 2028 + REG_A8XX_CP_PROTECT_GLOBAL(61), 2029 + REG_A8XX_CP_PROTECT_GLOBAL(62), 2030 + REG_A8XX_CP_PROTECT_GLOBAL(63), 2031 + }; 2032 + DECLARE_ADRENO_REGLIST_LIST(a840_ifpc_reglist); 2033 + 2034 + static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = { 2035 + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2036 + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2037 + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2038 + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2039 + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2040 + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2041 + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2042 + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2043 + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2044 + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2045 + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, 2046 + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, 2047 + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, 2048 + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, 2049 + { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2050 + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, 2051 + { REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2052 + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, 2053 + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2054 + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2055 + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2056 + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2057 + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2058 + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 2059 + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | 2060 + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | 2061 + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, 2062 + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | 2063 + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | 2064 + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, 2065 + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)}, 2066 + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, 2067 + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, 2068 + { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, 2069 + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, 2070 + }; 2071 + DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist); 2072 + 1894 2073 static const struct adreno_info a8xx_gpus[] = { 1895 2074 { 1896 2075 .chip_ids = ADRENO_CHIP_IDS(0x44070001), ··· 2119 1940 .gmem = 18 * SZ_1M, 2120 1941 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 2121 1942 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 2122 - ADRENO_QUIRK_HAS_HW_APRIV, 1943 + ADRENO_QUIRK_HAS_HW_APRIV | 1944 + ADRENO_QUIRK_IFPC, 2123 1945 .funcs = &a8xx_gpu_funcs, 2124 1946 .a6xx = &(const struct a6xx_info) { 2125 1947 .protect = &a840_protect, 2126 1948 .nonctxt_reglist = a840_nonctxt_regs, 1949 + .pwrup_reglist = &a840_pwrup_reglist, 1950 + .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist, 1951 + .ifpc_reglist = &a840_ifpc_reglist, 2127 1952 .gbif_cx = a840_gbif, 2128 1953 .max_slices = 3, 2129 1954 .gmu_chipid = 0x8020100,
+97 -2
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
··· 183 183 /* Update HW if this is the current ring and we are not in preempt*/ 184 184 if (!a6xx_in_preempt(a6xx_gpu)) { 185 185 if (a6xx_gpu->cur_ring == ring) 186 - gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 186 + a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false); 187 187 else 188 188 ring->restore_wptr = true; 189 189 } else { ··· 396 396 a8xx_aperture_clear(gpu); 397 397 } 398 398 399 + static void a8xx_patch_pwrup_reglist(struct msm_gpu *gpu) 400 + { 401 + const struct adreno_reglist_pipe_list *dyn_pwrup_reglist; 402 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 403 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 404 + const struct adreno_reglist_list *reglist; 405 + void *ptr = a6xx_gpu->pwrup_reglist_ptr; 406 + struct cpu_gpu_lock *lock = ptr; 407 + u32 *dest = (u32 *)&lock->regs[0]; 408 + u32 dyn_pwrup_reglist_count = 0; 409 + int i; 410 + 411 + lock->gpu_req = lock->cpu_req = lock->turn = 0; 412 + 413 + reglist = adreno_gpu->info->a6xx->ifpc_reglist; 414 + if (reglist) { 415 + lock->ifpc_list_len = reglist->count; 416 + 417 + /* 418 + * For each entry in each of the lists, write the offset and the current 419 + * register value into the GPU buffer 420 + */ 421 + for (i = 0; i < reglist->count; i++) { 422 + *dest++ = reglist->regs[i]; 423 + *dest++ = gpu_read(gpu, reglist->regs[i]); 424 + } 425 + } 426 + 427 + reglist = adreno_gpu->info->a6xx->pwrup_reglist; 428 + if (reglist) { 429 + lock->preemption_list_len = reglist->count; 430 + 431 + for (i = 0; i < reglist->count; i++) { 432 + *dest++ = reglist->regs[i]; 433 + *dest++ = gpu_read(gpu, reglist->regs[i]); 434 + } 435 + } 436 + 437 + /* 438 + * The overall register list is composed of 439 + * 1. Static IFPC-only registers 440 + * 2. Static IFPC + preemption registers 441 + * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) 442 + * 443 + * The first two lists are static. Size of these lists are stored as 444 + * number of pairs in ifpc_list_len and preemption_list_len 445 + * respectively. With concurrent binning, Some of the perfcounter 446 + * registers being virtualized, CP needs to know the pipe id to program 447 + * the aperture inorder to restore the same. Thus, third list is a 448 + * dynamic list with triplets as 449 + * (<aperture, shifted 12 bits> <address> <data>), and the length is 450 + * stored as number for triplets in dynamic_list_len. 451 + */ 452 + dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; 453 + if (!dyn_pwrup_reglist) 454 + goto done; 455 + 456 + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) { 457 + for (i = 0; i < dyn_pwrup_reglist->count; i++) { 458 + if (!(dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id))) 459 + continue; 460 + *dest++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe_id); 461 + *dest++ = dyn_pwrup_reglist->regs[i].offset; 462 + *dest++ = a8xx_read_pipe_slice(gpu, 463 + pipe_id, 464 + a8xx_get_first_slice(a6xx_gpu), 465 + dyn_pwrup_reglist->regs[i].offset); 466 + dyn_pwrup_reglist_count++; 467 + } 468 + } 469 + 470 + lock->dynamic_list_len = dyn_pwrup_reglist_count; 471 + 472 + done: 473 + a8xx_aperture_clear(gpu); 474 + } 475 + 399 476 static int a8xx_cp_init(struct msm_gpu *gpu) 400 477 { 478 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 479 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 401 480 struct msm_ringbuffer *ring = gpu->rb[0]; 402 481 u32 mask; 403 482 ··· 484 405 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 485 406 OUT_RING(ring, BIT(27)); 486 407 487 - OUT_PKT7(ring, CP_ME_INIT, 4); 408 + OUT_PKT7(ring, CP_ME_INIT, 7); 488 409 489 410 /* Use multiple HW contexts */ 490 411 mask = BIT(0); ··· 498 419 /* Disable save/restore of performance counters across preemption */ 499 420 mask |= BIT(6); 500 421 422 + /* Enable the register init list with the spinlock */ 423 + mask |= BIT(8); 424 + 501 425 OUT_RING(ring, mask); 502 426 503 427 /* Enable multiple hardware contexts */ ··· 511 429 512 430 /* Operation mode mask */ 513 431 OUT_RING(ring, 0x00000002); 432 + 433 + /* Lo address */ 434 + OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); 435 + /* Hi address */ 436 + OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); 437 + 438 + /* Enable dyn pwrup list with triplets (offset, value, pipe) */ 439 + OUT_RING(ring, BIT(31)); 514 440 515 441 a6xx_flush(gpu, ring); 516 442 return a8xx_idle(gpu, ring) ? 0 : -EINVAL; ··· 801 711 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); 802 712 WARN_ON(!gmem_protect); 803 713 a8xx_aperture_clear(gpu); 714 + 715 + if (!a6xx_gpu->pwrup_reglist_emitted) { 716 + a8xx_patch_pwrup_reglist(gpu); 717 + a6xx_gpu->pwrup_reglist_emitted = true; 718 + } 804 719 805 720 /* Enable hardware clockgating */ 806 721 a8xx_set_hwcg(gpu, true);