tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"This round of fixes has two larger changes that came in last week:

- a couple of patches all intended to finally turn on USB support on
various Amlogic SoC based boards. The respective driver were not
finalized until very late before the merge window and the DT
portion is the last bit now.

- a defconfig update for gemini that had repeatedly missed the cut
but that is required to actually boot any real machines with the
default build.

The rest are the usual small changes:

- a fix for a nasty build regression on the OMAP memory drivers

- a fix for a boot problem on Intel/Altera SocFPGA

- a MAINTAINER file update

- a couple of fixes for issues found by automated testing (kernelci,
coverity, sparse, ...)

- a few incorrect DT entries are updated to match the hardware"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: defconfig: Update Gemini defconfig
ARM: s3c24xx: jive: Fix some GPIO names
HISI LPC: Add Kconfig MFD_CORE dependency
ARM: dts: Fix NAS4220B pin config
MAINTAINERS: Remove myself as maintainer
arm64: dts: correct SATA addresses for Stingray
ARM64: dts: meson-gxm-khadas-vim2: enable the USB controller
ARM64: dts: meson-gxl-nexbox-a95x: enable the USB controller
ARM64: dts: meson-gxl-s905x-libretech-cc: enable the USB controller
ARM64: dts: meson-gx-p23x-q20x: enable the USB controller
ARM64: dts: meson-gxl-s905x-p212: enable the USB controller
ARM64: dts: meson-gxm: add GXM specific USB host configuration
ARM64: dts: meson-gxl: add USB host support
ARM: OMAP2+: Fix build when using split object directories
soc: bcm2835: Make !RASPBERRYPI_FIRMWARE dummies return failure
soc: bcm: raspberrypi-power: Fix use of __packed
ARM: dts: Fix cm2 and prm sizes for omap4
ARM: socfpga_defconfig: Remove QSPI Sector 4K size force
firmware: arm_scmi: remove redundant null check on array
arm64: dts: juno: drop unnecessary address-cells and size-cells properties

Linus Torvalds ee7141c9 245131e2

+277 -148
-2
MAINTAINERS
··· 1208 1208 ARM/ARTPEC MACHINE SUPPORT 1209 1209 M: Jesper Nilsson <jesper.nilsson@axis.com> 1210 1210 M: Lars Persson <lars.persson@axis.com> 1211 - M: Niklas Cassel <niklas.cassel@axis.com> 1212 1211 S: Maintained 1213 1212 L: linux-arm-kernel@axis.com 1214 1213 F: arch/arm/mach-artpec ··· 10908 10909 F: drivers/pci/dwc/ 10909 10910 10910 10911 PCIE DRIVER FOR AXIS ARTPEC 10911 - M: Niklas Cassel <niklas.cassel@axis.com> 10912 10912 M: Jesper Nilsson <jesper.nilsson@axis.com> 10913 10913 L: linux-arm-kernel@axis.com 10914 10914 L: linux-pci@vger.kernel.org
+14 -14
arch/arm/boot/dts/gemini-nas4220b.dts
··· 134 134 function = "gmii"; 135 135 groups = "gmii_gmac0_grp"; 136 136 }; 137 - /* Settings come from OpenWRT */ 137 + /* Settings come from OpenWRT, pins on SL3516 */ 138 138 conf0 { 139 - pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; 139 + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; 140 140 skew-delay = <0>; 141 141 }; 142 142 conf1 { 143 - pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC"; 143 + pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; 144 144 skew-delay = <15>; 145 145 }; 146 146 conf2 { 147 - pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; 147 + pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; 148 148 skew-delay = <7>; 149 149 }; 150 150 conf3 { 151 - pins = "V7 GMAC0 TXC"; 151 + pins = "U8 GMAC0 TXC"; 152 152 skew-delay = <11>; 153 153 }; 154 154 conf4 { 155 - pins = "P10 GMAC1 TXC"; 155 + pins = "V11 GMAC1 TXC"; 156 156 skew-delay = <10>; 157 157 }; 158 158 conf5 { 159 159 /* The data lines all have default skew */ 160 - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", 161 - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", 162 - "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", 163 - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3", 164 - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", 165 - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", 166 - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", 167 - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; 160 + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", 161 + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", 162 + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", 163 + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", 164 + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", 165 + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", 166 + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", 167 + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; 168 168 skew-delay = <7>; 169 169 }; 170 170 /* Set up drive strength on GMAC0 to 16 mA */
+4 -4
arch/arm/boot/dts/omap4.dtsi
··· 163 163 164 164 cm2: cm2@8000 { 165 165 compatible = "ti,omap4-cm2", "simple-bus"; 166 - reg = <0x8000 0x3000>; 166 + reg = <0x8000 0x2000>; 167 167 #address-cells = <1>; 168 168 #size-cells = <1>; 169 - ranges = <0 0x8000 0x3000>; 169 + ranges = <0 0x8000 0x2000>; 170 170 171 171 cm2_clocks: clocks { 172 172 #address-cells = <1>; ··· 250 250 251 251 prm: prm@6000 { 252 252 compatible = "ti,omap4-prm"; 253 - reg = <0x6000 0x3000>; 253 + reg = <0x6000 0x2000>; 254 254 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 255 255 #address-cells = <1>; 256 256 #size-cells = <1>; 257 - ranges = <0 0x6000 0x3000>; 257 + ranges = <0 0x6000 0x2000>; 258 258 259 259 prm_clocks: clocks { 260 260 #address-cells = <1>;
+25 -2
arch/arm/configs/gemini_defconfig
··· 1 1 # CONFIG_LOCALVERSION_AUTO is not set 2 2 CONFIG_SYSVIPC=y 3 3 CONFIG_NO_HZ_IDLE=y 4 + CONFIG_HIGH_RES_TIMERS=y 4 5 CONFIG_BSD_PROCESS_ACCT=y 5 6 CONFIG_USER_NS=y 6 7 CONFIG_RELAY=y ··· 13 12 CONFIG_PCI=y 14 13 CONFIG_PREEMPT=y 15 14 CONFIG_AEABI=y 15 + CONFIG_HIGHMEM=y 16 + CONFIG_CMA=y 16 17 CONFIG_CMDLINE="console=ttyS0,115200n8" 17 18 CONFIG_KEXEC=y 18 19 CONFIG_BINFMT_MISC=y 19 20 CONFIG_PM=y 21 + CONFIG_NET=y 22 + CONFIG_UNIX=y 23 + CONFIG_INET=y 20 24 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 21 25 CONFIG_DEVTMPFS=y 22 26 CONFIG_MTD=y 23 27 CONFIG_MTD_BLOCK=y 24 28 CONFIG_MTD_CFI=y 29 + CONFIG_MTD_JEDECPROBE=y 25 30 CONFIG_MTD_CFI_INTELEXT=y 26 31 CONFIG_MTD_CFI_AMDSTD=y 27 32 CONFIG_MTD_CFI_STAA=y ··· 40 33 # CONFIG_SCSI_LOWLEVEL is not set 41 34 CONFIG_ATA=y 42 35 CONFIG_PATA_FTIDE010=y 36 + CONFIG_NETDEVICES=y 37 + CONFIG_GEMINI_ETHERNET=y 38 + CONFIG_MDIO_BITBANG=y 39 + CONFIG_MDIO_GPIO=y 40 + CONFIG_REALTEK_PHY=y 43 41 CONFIG_INPUT_EVDEV=y 44 42 CONFIG_KEYBOARD_GPIO=y 45 43 # CONFIG_INPUT_MOUSE is not set ··· 55 43 CONFIG_SERIAL_8250_RUNTIME_UARTS=1 56 44 CONFIG_SERIAL_OF_PLATFORM=y 57 45 # CONFIG_HW_RANDOM is not set 58 - # CONFIG_HWMON is not set 46 + CONFIG_I2C_GPIO=y 47 + CONFIG_SPI=y 48 + CONFIG_SPI_GPIO=y 49 + CONFIG_SENSORS_GPIO_FAN=y 50 + CONFIG_SENSORS_LM75=y 51 + CONFIG_THERMAL=y 59 52 CONFIG_WATCHDOG=y 60 - CONFIG_GEMINI_WATCHDOG=y 53 + CONFIG_REGULATOR=y 54 + CONFIG_REGULATOR_FIXED_VOLTAGE=y 55 + CONFIG_DRM=y 56 + CONFIG_DRM_PANEL_ILITEK_IL9322=y 57 + CONFIG_DRM_TVE200=y 58 + CONFIG_LOGO=y 61 59 CONFIG_USB=y 62 60 CONFIG_USB_MON=y 63 61 CONFIG_USB_FOTG210_HCD=y ··· 76 54 CONFIG_LEDS_CLASS=y 77 55 CONFIG_LEDS_GPIO=y 78 56 CONFIG_LEDS_TRIGGERS=y 57 + CONFIG_LEDS_TRIGGER_DISK=y 79 58 CONFIG_LEDS_TRIGGER_HEARTBEAT=y 80 59 CONFIG_RTC_CLASS=y 81 60 CONFIG_DMADEVICES=y
+1
arch/arm/configs/socfpga_defconfig
··· 57 57 CONFIG_MTD_NAND=y 58 58 CONFIG_MTD_NAND_DENALI_DT=y 59 59 CONFIG_MTD_SPI_NOR=y 60 + # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set 60 61 CONFIG_SPI_CADENCE_QUADSPI=y 61 62 CONFIG_OF_OVERLAY=y 62 63 CONFIG_OF_CONFIGFS=y
+1 -5
arch/arm/mach-omap2/Makefile
··· 243 243 include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE 244 244 $(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__) 245 245 246 - # For rule to generate ti-emif-asm-offsets.h dependency 247 - include drivers/memory/Makefile.asm-offsets 248 - 249 - arch/arm/mach-omap2/sleep33xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h 250 - arch/arm/mach-omap2/sleep43xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h 246 + $(obj)/sleep33xx.o $(obj)/sleep43xx.o: include/generated/ti-pm-asm-offsets.h
+3
arch/arm/mach-omap2/pm-asm-offsets.c
··· 7 7 8 8 #include <linux/kbuild.h> 9 9 #include <linux/platform_data/pm33xx.h> 10 + #include <linux/ti-emif-sram.h> 10 11 11 12 int main(void) 12 13 { 14 + ti_emif_asm_offsets(); 15 + 13 16 DEFINE(AMX3_PM_WFI_FLAGS_OFFSET, 14 17 offsetof(struct am33xx_pm_sram_data, wfi_flags)); 15 18 DEFINE(AMX3_PM_L2_AUX_CTRL_VAL_OFFSET,
-1
arch/arm/mach-omap2/sleep33xx.S
··· 6 6 * Dave Gerlach, Vaibhav Bedia 7 7 */ 8 8 9 - #include <generated/ti-emif-asm-offsets.h> 10 9 #include <generated/ti-pm-asm-offsets.h> 11 10 #include <linux/linkage.h> 12 11 #include <linux/ti-emif-sram.h>
-1
arch/arm/mach-omap2/sleep43xx.S
··· 6 6 * Dave Gerlach, Vaibhav Bedia 7 7 */ 8 8 9 - #include <generated/ti-emif-asm-offsets.h> 10 9 #include <generated/ti-pm-asm-offsets.h> 11 10 #include <linux/linkage.h> 12 11 #include <linux/ti-emif-sram.h>
+2 -2
arch/arm/mach-s3c24xx/mach-jive.c
··· 427 427 .dev_id = "spi_gpio", 428 428 .table = { 429 429 GPIO_LOOKUP("GPIOB", 4, 430 - "gpio-sck", GPIO_ACTIVE_HIGH), 430 + "sck", GPIO_ACTIVE_HIGH), 431 431 GPIO_LOOKUP("GPIOB", 9, 432 - "gpio-mosi", GPIO_ACTIVE_HIGH), 432 + "mosi", GPIO_ACTIVE_HIGH), 433 433 GPIO_LOOKUP("GPIOH", 10, 434 434 "cs", GPIO_ACTIVE_HIGH), 435 435 { },
+4
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
··· 212 212 pinctrl-0 = <&uart_ao_a_pins>; 213 213 pinctrl-names = "default"; 214 214 }; 215 + 216 + &usb0 { 217 + status = "okay"; 218 + };
+12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
··· 271 271 pinctrl-0 = <&uart_ao_a_pins>; 272 272 pinctrl-names = "default"; 273 273 }; 274 + 275 + &usb0 { 276 + status = "okay"; 277 + }; 278 + 279 + &usb2_phy0 { 280 + /* 281 + * even though the schematics don't show it: 282 + * HDMI_5V is also used as supply for the USB VBUS. 283 + */ 284 + phy-supply = <&hdmi_5v>; 285 + };
+4
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
··· 215 215 pinctrl-0 = <&uart_ao_a_pins>; 216 216 pinctrl-names = "default"; 217 217 }; 218 + 219 + &usb0 { 220 + status = "okay"; 221 + };
+4
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
··· 185 185 pinctrl-0 = <&uart_ao_a_pins>; 186 186 pinctrl-names = "default"; 187 187 }; 188 + 189 + &usb0 { 190 + status = "okay"; 191 + };
+61
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
··· 20 20 no-map; 21 21 }; 22 22 }; 23 + 24 + soc { 25 + usb0: usb@c9000000 { 26 + status = "disabled"; 27 + compatible = "amlogic,meson-gxl-dwc3"; 28 + #address-cells = <2>; 29 + #size-cells = <2>; 30 + ranges; 31 + 32 + clocks = <&clkc CLKID_USB>; 33 + clock-names = "usb_general"; 34 + resets = <&reset RESET_USB_OTG>; 35 + reset-names = "usb_otg"; 36 + 37 + dwc3: dwc3@c9000000 { 38 + compatible = "snps,dwc3"; 39 + reg = <0x0 0xc9000000 0x0 0x100000>; 40 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 41 + dr_mode = "host"; 42 + maximum-speed = "high-speed"; 43 + snps,dis_u2_susphy_quirk; 44 + phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>; 45 + }; 46 + }; 47 + }; 48 + }; 49 + 50 + &apb { 51 + usb2_phy0: phy@78000 { 52 + compatible = "amlogic,meson-gxl-usb2-phy"; 53 + #phy-cells = <0>; 54 + reg = <0x0 0x78000 0x0 0x20>; 55 + clocks = <&clkc CLKID_USB>; 56 + clock-names = "phy"; 57 + resets = <&reset RESET_USB_OTG>; 58 + reset-names = "phy"; 59 + status = "okay"; 60 + }; 61 + 62 + usb2_phy1: phy@78020 { 63 + compatible = "amlogic,meson-gxl-usb2-phy"; 64 + #phy-cells = <0>; 65 + reg = <0x0 0x78020 0x0 0x20>; 66 + clocks = <&clkc CLKID_USB>; 67 + clock-names = "phy"; 68 + resets = <&reset RESET_USB_OTG>; 69 + reset-names = "phy"; 70 + status = "okay"; 71 + }; 72 + 73 + usb3_phy: phy@78080 { 74 + compatible = "amlogic,meson-gxl-usb3-phy"; 75 + #phy-cells = <0>; 76 + reg = <0x0 0x78080 0x0 0x20>; 77 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 78 + clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>; 79 + clock-names = "phy", "peripheral"; 80 + resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; 81 + reset-names = "phy", "peripheral"; 82 + status = "okay"; 83 + }; 23 84 }; 24 85 25 86 &ethmac {
+4
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
··· 406 406 status = "okay"; 407 407 vref-supply = <&vddio_ao18>; 408 408 }; 409 + 410 + &usb0 { 411 + status = "okay"; 412 + };
+17
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
··· 80 80 }; 81 81 }; 82 82 83 + &apb { 84 + usb2_phy2: phy@78040 { 85 + compatible = "amlogic,meson-gxl-usb2-phy"; 86 + #phy-cells = <0>; 87 + reg = <0x0 0x78040 0x0 0x20>; 88 + clocks = <&clkc CLKID_USB>; 89 + clock-names = "phy"; 90 + resets = <&reset RESET_USB_OTG>; 91 + reset-names = "phy"; 92 + status = "okay"; 93 + }; 94 + }; 95 + 83 96 &clkc_AO { 84 97 compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; 85 98 }; ··· 112 99 113 100 &hdmi_tx { 114 101 compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; 102 + }; 103 + 104 + &dwc3 { 105 + phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; 115 106 };
-2
arch/arm64/boot/dts/arm/juno-motherboard.dtsi
··· 56 56 57 57 gpio_keys { 58 58 compatible = "gpio-keys"; 59 - #address-cells = <1>; 60 - #size-cells = <0>; 61 59 62 60 power-button { 63 61 debounce_interval = <50>;
+40 -40
arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
··· 36 36 #size-cells = <1>; 37 37 ranges = <0x0 0x0 0x67d00000 0x00800000>; 38 38 39 - sata0: ahci@210000 { 39 + sata0: ahci@0 { 40 40 compatible = "brcm,iproc-ahci", "generic-ahci"; 41 - reg = <0x00210000 0x1000>; 41 + reg = <0x00000000 0x1000>; 42 42 reg-names = "ahci"; 43 - interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 43 + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 44 44 #address-cells = <1>; 45 45 #size-cells = <0>; 46 46 status = "disabled"; ··· 52 52 }; 53 53 }; 54 54 55 - sata_phy0: sata_phy@212100 { 55 + sata_phy0: sata_phy@2100 { 56 56 compatible = "brcm,iproc-sr-sata-phy"; 57 - reg = <0x00212100 0x1000>; 57 + reg = <0x00002100 0x1000>; 58 58 reg-names = "phy"; 59 59 #address-cells = <1>; 60 60 #size-cells = <0>; ··· 66 66 }; 67 67 }; 68 68 69 - sata1: ahci@310000 { 69 + sata1: ahci@10000 { 70 70 compatible = "brcm,iproc-ahci", "generic-ahci"; 71 - reg = <0x00310000 0x1000>; 71 + reg = <0x00010000 0x1000>; 72 72 reg-names = "ahci"; 73 - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 73 + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 74 74 #address-cells = <1>; 75 75 #size-cells = <0>; 76 76 status = "disabled"; ··· 82 82 }; 83 83 }; 84 84 85 - sata_phy1: sata_phy@312100 { 85 + sata_phy1: sata_phy@12100 { 86 86 compatible = "brcm,iproc-sr-sata-phy"; 87 - reg = <0x00312100 0x1000>; 87 + reg = <0x00012100 0x1000>; 88 88 reg-names = "phy"; 89 89 #address-cells = <1>; 90 90 #size-cells = <0>; ··· 96 96 }; 97 97 }; 98 98 99 - sata2: ahci@120000 { 99 + sata2: ahci@20000 { 100 100 compatible = "brcm,iproc-ahci", "generic-ahci"; 101 - reg = <0x00120000 0x1000>; 101 + reg = <0x00020000 0x1000>; 102 102 reg-names = "ahci"; 103 - interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 103 + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 104 104 #address-cells = <1>; 105 105 #size-cells = <0>; 106 106 status = "disabled"; ··· 112 112 }; 113 113 }; 114 114 115 - sata_phy2: sata_phy@122100 { 115 + sata_phy2: sata_phy@22100 { 116 116 compatible = "brcm,iproc-sr-sata-phy"; 117 - reg = <0x00122100 0x1000>; 117 + reg = <0x00022100 0x1000>; 118 118 reg-names = "phy"; 119 119 #address-cells = <1>; 120 120 #size-cells = <0>; ··· 126 126 }; 127 127 }; 128 128 129 - sata3: ahci@130000 { 129 + sata3: ahci@30000 { 130 130 compatible = "brcm,iproc-ahci", "generic-ahci"; 131 - reg = <0x00130000 0x1000>; 131 + reg = <0x00030000 0x1000>; 132 132 reg-names = "ahci"; 133 - interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 133 + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 134 134 #address-cells = <1>; 135 135 #size-cells = <0>; 136 136 status = "disabled"; ··· 142 142 }; 143 143 }; 144 144 145 - sata_phy3: sata_phy@132100 { 145 + sata_phy3: sata_phy@32100 { 146 146 compatible = "brcm,iproc-sr-sata-phy"; 147 - reg = <0x00132100 0x1000>; 147 + reg = <0x00032100 0x1000>; 148 148 reg-names = "phy"; 149 149 #address-cells = <1>; 150 150 #size-cells = <0>; ··· 156 156 }; 157 157 }; 158 158 159 - sata4: ahci@330000 { 159 + sata4: ahci@100000 { 160 160 compatible = "brcm,iproc-ahci", "generic-ahci"; 161 - reg = <0x00330000 0x1000>; 161 + reg = <0x00100000 0x1000>; 162 162 reg-names = "ahci"; 163 - interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 163 + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 164 164 #address-cells = <1>; 165 165 #size-cells = <0>; 166 166 status = "disabled"; ··· 172 172 }; 173 173 }; 174 174 175 - sata_phy4: sata_phy@332100 { 175 + sata_phy4: sata_phy@102100 { 176 176 compatible = "brcm,iproc-sr-sata-phy"; 177 - reg = <0x00332100 0x1000>; 177 + reg = <0x00102100 0x1000>; 178 178 reg-names = "phy"; 179 179 #address-cells = <1>; 180 180 #size-cells = <0>; ··· 186 186 }; 187 187 }; 188 188 189 - sata5: ahci@400000 { 189 + sata5: ahci@110000 { 190 190 compatible = "brcm,iproc-ahci", "generic-ahci"; 191 - reg = <0x00400000 0x1000>; 191 + reg = <0x00110000 0x1000>; 192 192 reg-names = "ahci"; 193 - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 193 + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 194 194 #address-cells = <1>; 195 195 #size-cells = <0>; 196 196 status = "disabled"; ··· 202 202 }; 203 203 }; 204 204 205 - sata_phy5: sata_phy@402100 { 205 + sata_phy5: sata_phy@112100 { 206 206 compatible = "brcm,iproc-sr-sata-phy"; 207 - reg = <0x00402100 0x1000>; 207 + reg = <0x00112100 0x1000>; 208 208 reg-names = "phy"; 209 209 #address-cells = <1>; 210 210 #size-cells = <0>; ··· 216 216 }; 217 217 }; 218 218 219 - sata6: ahci@410000 { 219 + sata6: ahci@120000 { 220 220 compatible = "brcm,iproc-ahci", "generic-ahci"; 221 - reg = <0x00410000 0x1000>; 221 + reg = <0x00120000 0x1000>; 222 222 reg-names = "ahci"; 223 - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 223 + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 224 224 #address-cells = <1>; 225 225 #size-cells = <0>; 226 226 status = "disabled"; ··· 232 232 }; 233 233 }; 234 234 235 - sata_phy6: sata_phy@412100 { 235 + sata_phy6: sata_phy@122100 { 236 236 compatible = "brcm,iproc-sr-sata-phy"; 237 - reg = <0x00412100 0x1000>; 237 + reg = <0x00122100 0x1000>; 238 238 reg-names = "phy"; 239 239 #address-cells = <1>; 240 240 #size-cells = <0>; ··· 246 246 }; 247 247 }; 248 248 249 - sata7: ahci@420000 { 249 + sata7: ahci@130000 { 250 250 compatible = "brcm,iproc-ahci", "generic-ahci"; 251 - reg = <0x00420000 0x1000>; 251 + reg = <0x00130000 0x1000>; 252 252 reg-names = "ahci"; 253 - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 253 + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 254 254 #address-cells = <1>; 255 255 #size-cells = <0>; 256 256 status = "disabled"; ··· 262 262 }; 263 263 }; 264 264 265 - sata_phy7: sata_phy@422100 { 265 + sata_phy7: sata_phy@132100 { 266 266 compatible = "brcm,iproc-sr-sata-phy"; 267 - reg = <0x00422100 0x1000>; 267 + reg = <0x00132100 0x1000>; 268 268 reg-names = "phy"; 269 269 #address-cells = <1>; 270 270 #size-cells = <0>;
+1
drivers/bus/Kconfig
··· 33 33 bool "Support for ISA I/O space on HiSilicon Hip06/7" 34 34 depends on ARM64 && (ARCH_HISI || COMPILE_TEST) 35 35 select INDIRECT_PIO 36 + select MFD_CORE if ACPI 36 37 help 37 38 Driver to enable I/O access to devices attached to the Low Pin 38 39 Count bus on the HiSilicon Hip06/7 SoC.
+1 -1
drivers/firmware/arm_scmi/clock.c
··· 284 284 struct clock_info *ci = handle->clk_priv; 285 285 struct scmi_clock_info *clk = ci->clk + clk_id; 286 286 287 - if (!clk->name || !clk->name[0]) 287 + if (!clk->name[0]) 288 288 return NULL; 289 289 290 290 return clk;
+1 -71
drivers/memory/emif-asm-offsets.c
··· 16 16 17 17 int main(void) 18 18 { 19 - DEFINE(EMIF_SDCFG_VAL_OFFSET, 20 - offsetof(struct emif_regs_amx3, emif_sdcfg_val)); 21 - DEFINE(EMIF_TIMING1_VAL_OFFSET, 22 - offsetof(struct emif_regs_amx3, emif_timing1_val)); 23 - DEFINE(EMIF_TIMING2_VAL_OFFSET, 24 - offsetof(struct emif_regs_amx3, emif_timing2_val)); 25 - DEFINE(EMIF_TIMING3_VAL_OFFSET, 26 - offsetof(struct emif_regs_amx3, emif_timing3_val)); 27 - DEFINE(EMIF_REF_CTRL_VAL_OFFSET, 28 - offsetof(struct emif_regs_amx3, emif_ref_ctrl_val)); 29 - DEFINE(EMIF_ZQCFG_VAL_OFFSET, 30 - offsetof(struct emif_regs_amx3, emif_zqcfg_val)); 31 - DEFINE(EMIF_PMCR_VAL_OFFSET, 32 - offsetof(struct emif_regs_amx3, emif_pmcr_val)); 33 - DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET, 34 - offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val)); 35 - DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET, 36 - offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl)); 37 - DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET, 38 - offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh)); 39 - DEFINE(EMIF_COS_CONFIG_OFFSET, 40 - offsetof(struct emif_regs_amx3, emif_cos_config)); 41 - DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET, 42 - offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping)); 43 - DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET, 44 - offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map)); 45 - DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET, 46 - offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map)); 47 - DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET, 48 - offsetof(struct emif_regs_amx3, emif_ocp_config_val)); 49 - DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET, 50 - offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim)); 51 - DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET, 52 - offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw)); 53 - DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET, 54 - offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val)); 55 - DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET, 56 - offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw)); 57 - DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET, 58 - offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1)); 59 - DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET, 60 - offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals)); 61 - DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3)); 62 - 63 - BLANK(); 64 - 65 - DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET, 66 - offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt)); 67 - DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET, 68 - offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys)); 69 - DEFINE(EMIF_PM_CONFIG_OFFSET, 70 - offsetof(struct ti_emif_pm_data, ti_emif_sram_config)); 71 - DEFINE(EMIF_PM_REGS_VIRT_OFFSET, 72 - offsetof(struct ti_emif_pm_data, regs_virt)); 73 - DEFINE(EMIF_PM_REGS_PHYS_OFFSET, 74 - offsetof(struct ti_emif_pm_data, regs_phys)); 75 - DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data)); 76 - 77 - BLANK(); 78 - 79 - DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET, 80 - offsetof(struct ti_emif_pm_functions, save_context)); 81 - DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET, 82 - offsetof(struct ti_emif_pm_functions, restore_context)); 83 - DEFINE(EMIF_PM_ENTER_SR_OFFSET, 84 - offsetof(struct ti_emif_pm_functions, enter_sr)); 85 - DEFINE(EMIF_PM_EXIT_SR_OFFSET, 86 - offsetof(struct ti_emif_pm_functions, exit_sr)); 87 - DEFINE(EMIF_PM_ABORT_SR_OFFSET, 88 - offsetof(struct ti_emif_pm_functions, abort_sr)); 89 - DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions)); 19 + ti_emif_asm_offsets(); 90 20 91 21 return 0; 92 22 }
+1 -1
drivers/soc/bcm/raspberrypi-power.c
··· 45 45 struct rpi_power_domain_packet { 46 46 u32 domain; 47 47 u32 on; 48 - } __packet; 48 + }; 49 49 50 50 /* 51 51 * Asks the firmware to enable or disable power on a specific power
+75
include/linux/ti-emif-sram.h
··· 60 60 u32 abort_sr; 61 61 } __packed __aligned(8); 62 62 63 + static inline void ti_emif_asm_offsets(void) 64 + { 65 + DEFINE(EMIF_SDCFG_VAL_OFFSET, 66 + offsetof(struct emif_regs_amx3, emif_sdcfg_val)); 67 + DEFINE(EMIF_TIMING1_VAL_OFFSET, 68 + offsetof(struct emif_regs_amx3, emif_timing1_val)); 69 + DEFINE(EMIF_TIMING2_VAL_OFFSET, 70 + offsetof(struct emif_regs_amx3, emif_timing2_val)); 71 + DEFINE(EMIF_TIMING3_VAL_OFFSET, 72 + offsetof(struct emif_regs_amx3, emif_timing3_val)); 73 + DEFINE(EMIF_REF_CTRL_VAL_OFFSET, 74 + offsetof(struct emif_regs_amx3, emif_ref_ctrl_val)); 75 + DEFINE(EMIF_ZQCFG_VAL_OFFSET, 76 + offsetof(struct emif_regs_amx3, emif_zqcfg_val)); 77 + DEFINE(EMIF_PMCR_VAL_OFFSET, 78 + offsetof(struct emif_regs_amx3, emif_pmcr_val)); 79 + DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET, 80 + offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val)); 81 + DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET, 82 + offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl)); 83 + DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET, 84 + offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh)); 85 + DEFINE(EMIF_COS_CONFIG_OFFSET, 86 + offsetof(struct emif_regs_amx3, emif_cos_config)); 87 + DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET, 88 + offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping)); 89 + DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET, 90 + offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map)); 91 + DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET, 92 + offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map)); 93 + DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET, 94 + offsetof(struct emif_regs_amx3, emif_ocp_config_val)); 95 + DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET, 96 + offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim)); 97 + DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET, 98 + offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw)); 99 + DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET, 100 + offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val)); 101 + DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET, 102 + offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw)); 103 + DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET, 104 + offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1)); 105 + DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET, 106 + offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals)); 107 + DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3)); 108 + 109 + BLANK(); 110 + 111 + DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET, 112 + offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt)); 113 + DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET, 114 + offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys)); 115 + DEFINE(EMIF_PM_CONFIG_OFFSET, 116 + offsetof(struct ti_emif_pm_data, ti_emif_sram_config)); 117 + DEFINE(EMIF_PM_REGS_VIRT_OFFSET, 118 + offsetof(struct ti_emif_pm_data, regs_virt)); 119 + DEFINE(EMIF_PM_REGS_PHYS_OFFSET, 120 + offsetof(struct ti_emif_pm_data, regs_phys)); 121 + DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data)); 122 + 123 + BLANK(); 124 + 125 + DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET, 126 + offsetof(struct ti_emif_pm_functions, save_context)); 127 + DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET, 128 + offsetof(struct ti_emif_pm_functions, restore_context)); 129 + DEFINE(EMIF_PM_ENTER_SR_OFFSET, 130 + offsetof(struct ti_emif_pm_functions, enter_sr)); 131 + DEFINE(EMIF_PM_EXIT_SR_OFFSET, 132 + offsetof(struct ti_emif_pm_functions, exit_sr)); 133 + DEFINE(EMIF_PM_ABORT_SR_OFFSET, 134 + offsetof(struct ti_emif_pm_functions, abort_sr)); 135 + DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions)); 136 + } 137 + 63 138 struct gen_pool; 64 139 65 140 int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
+2 -2
include/soc/bcm2835/raspberrypi-firmware.h
··· 143 143 static inline int rpi_firmware_property(struct rpi_firmware *fw, u32 tag, 144 144 void *data, size_t len) 145 145 { 146 - return 0; 146 + return -ENOSYS; 147 147 } 148 148 149 149 static inline int rpi_firmware_property_list(struct rpi_firmware *fw, 150 150 void *data, size_t tag_size) 151 151 { 152 - return 0; 152 + return -ENOSYS; 153 153 } 154 154 155 155 static inline struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)