Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'convert-the-micrel-bindings-to-dt-schema'
Stefan Eichenberger says:
====================
Convert the Micrel bindings to DT schema
Convert the device tree bindings for the Micrel PHYs and switches to DT
schema.
====================
Link: https://patch.msgid.link/20260116130948.79558-1-eichest@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+384
-285
+253
Documentation/devicetree/bindings/net/micrel,gigabit.yaml
+253
Documentation/devicetree/bindings/net/micrel,gigabit.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/micrel,gigabit.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Micrel series Gigabit Ethernet PHYs
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Stefan Eichenberger <eichest@gmail.com>
12
+
13
+
description:
14
+
Some boards require special skew tuning values, particularly when it comes
15
+
to clock delays. These values can be specified in the device tree using
16
+
the properties listed here.
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- ethernet-phy-id0022.1610 # KSZ9021
22
+
- ethernet-phy-id0022.1611 # KSZ9021RLRN
23
+
- ethernet-phy-id0022.1620 # KSZ9031
24
+
- ethernet-phy-id0022.1631 # KSZ9477
25
+
- ethernet-phy-id0022.1640 # KSZ9131
26
+
- ethernet-phy-id0022.1650 # LAN8841
27
+
- ethernet-phy-id0022.1660 # LAN8814
28
+
- ethernet-phy-id0022.1670 # LAN8804
29
+
30
+
micrel,force-master:
31
+
type: boolean
32
+
description: |
33
+
Force phy to master mode. Only set this option if the phy reference
34
+
clock provided at CLK125_NDO pin is used as MAC reference clock
35
+
because the clock jitter in slave mode is too high (errata#2).
36
+
Attention: The link partner must be configurable as slave otherwise
37
+
no link will be established.
38
+
39
+
coma-mode-gpios:
40
+
maxItems: 1
41
+
description: |
42
+
If present the given gpio will be deasserted when the PHY is probed.
43
+
44
+
Some PHYs have a COMA mode input pin which puts the PHY into
45
+
isolate and power-down mode. On some boards this input is connected
46
+
to a GPIO of the SoC.
47
+
48
+
micrel,led-mode:
49
+
$ref: /schemas/types.yaml#/definitions/uint32
50
+
description: |
51
+
LED mode value to set for PHYs with configurable LEDs.
52
+
53
+
Configure the LED mode with single value. The list of PHYs and the
54
+
bits that are currently supported:
55
+
56
+
LAN8814: register EP5.0, bit 6
57
+
58
+
See the respective PHY datasheet for the mode values.
59
+
minimum: 0
60
+
maximum: 1
61
+
62
+
patternProperties:
63
+
'^([rt]xc)-skew-psec$':
64
+
$ref: /schemas/types.yaml#/definitions/int32
65
+
description:
66
+
Skew control of the pad in picoseconds.
67
+
minimum: -700
68
+
maximum: 2400
69
+
multipleOf: 100
70
+
default: 0
71
+
72
+
'^([rt]xd[0-3]|rxdv|txen)-skew-psec$':
73
+
$ref: /schemas/types.yaml#/definitions/int32
74
+
description: |
75
+
Skew control of the pad in picoseconds.
76
+
minimum: -700
77
+
maximum: 800
78
+
multipleOf: 100
79
+
default: 0
80
+
81
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allOf:
82
+
- $ref: ethernet-phy.yaml#
83
+
- if:
84
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properties:
85
+
compatible:
86
+
contains:
87
+
enum:
88
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- ethernet-phy-id0022.1610
89
+
- ethernet-phy-id0022.1611
90
+
then:
91
+
patternProperties:
92
+
'^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-ps$':
93
+
description: |
94
+
Skew control of the pad in picoseconds.
95
+
The actual increment on the chip is 120ps ranging from -840ps to
96
+
960ps, this mismatch comes from a documentation error before
97
+
datasheet revision 1.2 (Feb 2014).
98
+
99
+
The device tree value to delay mapping looks as follows:
100
+
Device Tree Value Delay
101
+
--------------------------
102
+
0 -840ps
103
+
200 -720ps
104
+
400 -600ps
105
+
600 -480ps
106
+
800 -360ps
107
+
1000 -240ps
108
+
1200 -120ps
109
+
1400 0ps
110
+
1600 120ps
111
+
1800 240ps
112
+
2000 360ps
113
+
2200 480ps
114
+
2400 600ps
115
+
2600 720ps
116
+
2800 840ps
117
+
3000 960ps
118
+
minimum: 0
119
+
maximum: 3000
120
+
multipleOf: 200
121
+
default: 1400
122
+
- if:
123
+
properties:
124
+
compatible:
125
+
contains:
126
+
const: ethernet-phy-id0022.1620
127
+
then:
128
+
patternProperties:
129
+
'^([rt]xc)-skew-ps$':
130
+
description: |
131
+
Skew control of the pad in picoseconds.
132
+
133
+
The device tree value to delay mapping is as follows:
134
+
Device Tree Value Delay
135
+
--------------------------
136
+
0 -900ps
137
+
60 -840ps
138
+
120 -780ps
139
+
180 -720ps
140
+
240 -660ps
141
+
300 -600ps
142
+
360 -540ps
143
+
420 -480ps
144
+
480 -420ps
145
+
540 -360ps
146
+
600 -300ps
147
+
660 -240ps
148
+
720 -180ps
149
+
780 -120ps
150
+
840 -60ps
151
+
900 0ps
152
+
960 60ps
153
+
1020 120ps
154
+
1080 180ps
155
+
1140 240ps
156
+
1200 300ps
157
+
1260 360ps
158
+
1320 420ps
159
+
1380 480ps
160
+
1440 540ps
161
+
1500 600ps
162
+
1560 660ps
163
+
1620 720ps
164
+
1680 780ps
165
+
1740 840ps
166
+
1800 900ps
167
+
1860 960ps
168
+
minimum: 0
169
+
maximum: 1860
170
+
multipleOf: 60
171
+
default: 900
172
+
'^([rt]xd[0-3]|rxdv|txen)-skew-ps$':
173
+
description: |
174
+
Skew control of the pad in picoseconds.
175
+
176
+
The device tree value to delay mapping is as follows:
177
+
Device Tree Value Delay
178
+
--------------------------
179
+
0 -420ps
180
+
60 -360ps
181
+
120 -300ps
182
+
180 -240ps
183
+
240 -180ps
184
+
300 -120ps
185
+
360 -60ps
186
+
420 0ps
187
+
480 60ps
188
+
540 120ps
189
+
600 180ps
190
+
660 240ps
191
+
720 300ps
192
+
780 360ps
193
+
840 420ps
194
+
900 480ps
195
+
minimum: 0
196
+
maximum: 900
197
+
multipleOf: 60
198
+
default: 420
199
+
- if:
200
+
not:
201
+
properties:
202
+
compatible:
203
+
contains:
204
+
enum:
205
+
- ethernet-phy-id0022.1640
206
+
- ethernet-phy-id0022.1650
207
+
then:
208
+
patternProperties:
209
+
'^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-psec$': false
210
+
- if:
211
+
not:
212
+
properties:
213
+
compatible:
214
+
contains:
215
+
const: ethernet-phy-id0022.1620
216
+
then:
217
+
properties:
218
+
micrel,force-master: false
219
+
- if:
220
+
not:
221
+
properties:
222
+
compatible:
223
+
contains:
224
+
const: ethernet-phy-id0022.1660
225
+
then:
226
+
properties:
227
+
coma-mode-gpios: false
228
+
micrel,led-mode: false
229
+
230
+
unevaluatedProperties: false
231
+
232
+
examples:
233
+
- |
234
+
mdio {
235
+
#address-cells = <1>;
236
+
#size-cells = <0>;
237
+
238
+
ethernet-phy@7 {
239
+
compatible = "ethernet-phy-id0022.1610";
240
+
reg = <7>;
241
+
rxc-skew-ps = <3000>;
242
+
rxdv-skew-ps = <0>;
243
+
txc-skew-ps = <3000>;
244
+
txen-skew-ps = <0>;
245
+
};
246
+
247
+
ethernet-phy@9 {
248
+
compatible = "ethernet-phy-id0022.1640";
249
+
reg = <9>;
250
+
rxc-skew-psec = <(-100)>;
251
+
txc-skew-psec = <(-100)>;
252
+
};
253
+
};
-228
Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
-228
Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
···
1
-
Micrel KSZ9021/KSZ9031/KSZ9131 Gigabit Ethernet PHY
2
-
3
-
Some boards require special tuning values, particularly when it comes
4
-
to clock delays. You can specify clock delay values in the PHY OF
5
-
device node. Deprecated, but still supported, these properties can
6
-
also be added to an Ethernet OF device node.
7
-
8
-
Note that these settings are applied after any phy-specific fixup from
9
-
phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c),
10
-
and therefore may overwrite them.
11
-
12
-
KSZ9021:
13
-
14
-
All skew control options are specified in picoseconds. The minimum
15
-
value is 0, the maximum value is 3000, and it can be specified in 200ps
16
-
steps, *but* these values are in no way what you get because this chip's
17
-
skew values actually increase in 120ps steps, starting from -840ps. The
18
-
incorrect values came from an error in the original KSZ9021 datasheet
19
-
before it was corrected in revision 1.2 (Feb 2014), but it is too late to
20
-
change the driver now because of the many existing device trees that have
21
-
been created using values that go up in increments of 200.
22
-
23
-
The following table shows the actual skew delay you will get for each of the
24
-
possible devicetree values, and the number that will be programmed into the
25
-
corresponding pad skew register:
26
-
27
-
Device Tree Value Delay Pad Skew Register Value
28
-
-----------------------------------------------------
29
-
0 -840ps 0000
30
-
200 -720ps 0001
31
-
400 -600ps 0010
32
-
600 -480ps 0011
33
-
800 -360ps 0100
34
-
1000 -240ps 0101
35
-
1200 -120ps 0110
36
-
1400 0ps 0111
37
-
1600 120ps 1000
38
-
1800 240ps 1001
39
-
2000 360ps 1010
40
-
2200 480ps 1011
41
-
2400 600ps 1100
42
-
2600 720ps 1101
43
-
2800 840ps 1110
44
-
3000 960ps 1111
45
-
46
-
Optional properties:
47
-
48
-
- rxc-skew-ps : Skew control of RXC pad
49
-
- rxdv-skew-ps : Skew control of RX CTL pad
50
-
- txc-skew-ps : Skew control of TXC pad
51
-
- txen-skew-ps : Skew control of TX CTL pad
52
-
- rxd0-skew-ps : Skew control of RX data 0 pad
53
-
- rxd1-skew-ps : Skew control of RX data 1 pad
54
-
- rxd2-skew-ps : Skew control of RX data 2 pad
55
-
- rxd3-skew-ps : Skew control of RX data 3 pad
56
-
- txd0-skew-ps : Skew control of TX data 0 pad
57
-
- txd1-skew-ps : Skew control of TX data 1 pad
58
-
- txd2-skew-ps : Skew control of TX data 2 pad
59
-
- txd3-skew-ps : Skew control of TX data 3 pad
60
-
61
-
KSZ9031:
62
-
63
-
All skew control options are specified in picoseconds. The minimum
64
-
value is 0, and the maximum is property-dependent. The increment
65
-
step is 60ps. The default value is the neutral setting, so setting
66
-
rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.
67
-
68
-
The KSZ9031 hardware supports a range of skew values from negative to
69
-
positive, where the specific range is property dependent. All values
70
-
specified in the devicetree are offset by the minimum value so they
71
-
can be represented as positive integers in the devicetree since it's
72
-
difficult to represent a negative number in the devictree.
73
-
74
-
The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
75
-
76
-
Pad Skew Value Delay (ps) Devicetree Value
77
-
------------------------------------------------------
78
-
0_0000 -900ps 0
79
-
0_0001 -840ps 60
80
-
0_0010 -780ps 120
81
-
0_0011 -720ps 180
82
-
0_0100 -660ps 240
83
-
0_0101 -600ps 300
84
-
0_0110 -540ps 360
85
-
0_0111 -480ps 420
86
-
0_1000 -420ps 480
87
-
0_1001 -360ps 540
88
-
0_1010 -300ps 600
89
-
0_1011 -240ps 660
90
-
0_1100 -180ps 720
91
-
0_1101 -120ps 780
92
-
0_1110 -60ps 840
93
-
0_1111 0ps 900
94
-
1_0000 60ps 960
95
-
1_0001 120ps 1020
96
-
1_0010 180ps 1080
97
-
1_0011 240ps 1140
98
-
1_0100 300ps 1200
99
-
1_0101 360ps 1260
100
-
1_0110 420ps 1320
101
-
1_0111 480ps 1380
102
-
1_1000 540ps 1440
103
-
1_1001 600ps 1500
104
-
1_1010 660ps 1560
105
-
1_1011 720ps 1620
106
-
1_1100 780ps 1680
107
-
1_1101 840ps 1740
108
-
1_1110 900ps 1800
109
-
1_1111 960ps 1860
110
-
111
-
The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
112
-
data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
113
-
114
-
Pad Skew Value Delay (ps) Devicetree Value
115
-
------------------------------------------------------
116
-
0000 -420ps 0
117
-
0001 -360ps 60
118
-
0010 -300ps 120
119
-
0011 -240ps 180
120
-
0100 -180ps 240
121
-
0101 -120ps 300
122
-
0110 -60ps 360
123
-
0111 0ps 420
124
-
1000 60ps 480
125
-
1001 120ps 540
126
-
1010 180ps 600
127
-
1011 240ps 660
128
-
1100 300ps 720
129
-
1101 360ps 780
130
-
1110 420ps 840
131
-
1111 480ps 900
132
-
133
-
Optional properties:
134
-
135
-
Maximum value of 1860, default value 900:
136
-
137
-
- rxc-skew-ps : Skew control of RX clock pad
138
-
- txc-skew-ps : Skew control of TX clock pad
139
-
140
-
Maximum value of 900, default value 420:
141
-
142
-
- rxdv-skew-ps : Skew control of RX CTL pad
143
-
- txen-skew-ps : Skew control of TX CTL pad
144
-
- rxd0-skew-ps : Skew control of RX data 0 pad
145
-
- rxd1-skew-ps : Skew control of RX data 1 pad
146
-
- rxd2-skew-ps : Skew control of RX data 2 pad
147
-
- rxd3-skew-ps : Skew control of RX data 3 pad
148
-
- txd0-skew-ps : Skew control of TX data 0 pad
149
-
- txd1-skew-ps : Skew control of TX data 1 pad
150
-
- txd2-skew-ps : Skew control of TX data 2 pad
151
-
- txd3-skew-ps : Skew control of TX data 3 pad
152
-
153
-
- micrel,force-master:
154
-
Boolean, force phy to master mode. Only set this option if the phy
155
-
reference clock provided at CLK125_NDO pin is used as MAC reference
156
-
clock because the clock jitter in slave mode is too high (errata#2).
157
-
Attention: The link partner must be configurable as slave otherwise
158
-
no link will be established.
159
-
160
-
KSZ9131:
161
-
LAN8841:
162
-
163
-
All skew control options are specified in picoseconds. The increment
164
-
step is 100ps. Unlike KSZ9031, the values represent picoseccond delays.
165
-
A negative value can be assigned as rxc-skew-psec = <(-100)>;.
166
-
167
-
Optional properties:
168
-
169
-
Range of the value -700 to 2400, default value 0:
170
-
171
-
- rxc-skew-psec : Skew control of RX clock pad
172
-
- txc-skew-psec : Skew control of TX clock pad
173
-
174
-
Range of the value -700 to 800, default value 0:
175
-
176
-
- rxdv-skew-psec : Skew control of RX CTL pad
177
-
- txen-skew-psec : Skew control of TX CTL pad
178
-
- rxd0-skew-psec : Skew control of RX data 0 pad
179
-
- rxd1-skew-psec : Skew control of RX data 1 pad
180
-
- rxd2-skew-psec : Skew control of RX data 2 pad
181
-
- rxd3-skew-psec : Skew control of RX data 3 pad
182
-
- txd0-skew-psec : Skew control of TX data 0 pad
183
-
- txd1-skew-psec : Skew control of TX data 1 pad
184
-
- txd2-skew-psec : Skew control of TX data 2 pad
185
-
- txd3-skew-psec : Skew control of TX data 3 pad
186
-
187
-
Examples:
188
-
189
-
/* Attach to an Ethernet device with autodetected PHY */
190
-
&enet {
191
-
rxc-skew-ps = <1800>;
192
-
rxdv-skew-ps = <0>;
193
-
txc-skew-ps = <1800>;
194
-
txen-skew-ps = <0>;
195
-
status = "okay";
196
-
};
197
-
198
-
/* Attach to an explicitly-specified PHY */
199
-
mdio {
200
-
phy0: ethernet-phy@0 {
201
-
rxc-skew-ps = <1800>;
202
-
rxdv-skew-ps = <0>;
203
-
txc-skew-ps = <1800>;
204
-
txen-skew-ps = <0>;
205
-
reg = <0>;
206
-
};
207
-
};
208
-
ethernet@70000 {
209
-
phy = <&phy0>;
210
-
phy-mode = "rgmii-id";
211
-
};
212
-
213
-
References
214
-
215
-
Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
216
-
http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
217
-
218
-
Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
219
-
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
220
-
221
-
Notes:
222
-
223
-
Note that a previous version of the Micrel ksz9021rl/rn Data Sheet
224
-
was missing extended register 106 (transmit data pad skews), and
225
-
incorrectly specified the ps per step as 200ps/step instead of
226
-
120ps/step. The latest update to this document reflects the latest
227
-
revision of the Micrel specification even though usage in the kernel
228
-
still reflects that incorrect document.
-57
Documentation/devicetree/bindings/net/micrel.txt
-57
Documentation/devicetree/bindings/net/micrel.txt
···
1
-
Micrel PHY properties.
2
-
3
-
These properties cover the base properties Micrel PHYs.
4
-
5
-
Optional properties:
6
-
7
-
- micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
8
-
9
-
Configure the LED mode with single value. The list of PHYs and the
10
-
bits that are currently supported:
11
-
12
-
KSZ8001: register 0x1e, bits 15..14
13
-
KSZ8041: register 0x1e, bits 15..14
14
-
KSZ8021: register 0x1f, bits 5..4
15
-
KSZ8031: register 0x1f, bits 5..4
16
-
KSZ8051: register 0x1f, bits 5..4
17
-
KSZ8081: register 0x1f, bits 5..4
18
-
KSZ8091: register 0x1f, bits 5..4
19
-
LAN8814: register EP5.0, bit 6
20
-
21
-
See the respective PHY datasheet for the mode values.
22
-
23
-
- micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24
-
bit selects 25 MHz mode
25
-
26
-
Setting the RMII Reference Clock Select bit enables 25 MHz rather
27
-
than 50 MHz clock mode.
28
-
29
-
Note that this option is only needed for certain PHY revisions with a
30
-
non-standard, inverted function of this configuration bit.
31
-
Specifically, a clock reference ("rmii-ref" below) is always needed to
32
-
actually select a mode.
33
-
34
-
- clocks, clock-names: contains clocks according to the common clock bindings.
35
-
36
-
supported clocks:
37
-
- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
38
-
input clock. Used to determine the XI input clock.
39
-
40
-
- micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
41
-
42
-
Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
43
-
by the FXEN boot strapping pin. It can't be determined from the PHY
44
-
registers whether the PHY is in fiber mode, so this boolean device tree
45
-
property can be used to describe it.
46
-
47
-
In fiber mode, auto-negotiation is disabled and the PHY can only work in
48
-
100base-fx (full and half duplex) modes.
49
-
50
-
- coma-mode-gpios: If present the given gpio will be deasserted when the
51
-
PHY is probed.
52
-
53
-
Some PHYs have a COMA mode input pin which puts the PHY into
54
-
isolate and power-down mode. On some boards this input is connected
55
-
to a GPIO of the SoC.
56
-
57
-
Supported on the LAN8814.
+131
Documentation/devicetree/bindings/net/micrel.yaml
+131
Documentation/devicetree/bindings/net/micrel.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/micrel.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Micrel KSZ series PHYs and switches
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Stefan Eichenberger <eichest@gmail.com>
12
+
13
+
description:
14
+
The Micrel KSZ series contains different network phys and switches.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- ethernet-phy-id000e.7237 # KSZ8873MLL
20
+
- ethernet-phy-id0022.1430 # KSZ886X
21
+
- ethernet-phy-id0022.1435 # KSZ8863
22
+
- ethernet-phy-id0022.1510 # KSZ8041
23
+
- ethernet-phy-id0022.1537 # KSZ8041RNLI
24
+
- ethernet-phy-id0022.1550 # KSZ8051
25
+
- ethernet-phy-id0022.1555 # KSZ8021
26
+
- ethernet-phy-id0022.1556 # KSZ8031
27
+
- ethernet-phy-id0022.1560 # KSZ8081, KSZ8091
28
+
- ethernet-phy-id0022.1570 # KSZ8061
29
+
- ethernet-phy-id0022.161a # KSZ8001
30
+
- ethernet-phy-id0022.1720 # KS8737
31
+
32
+
micrel,fiber-mode:
33
+
type: boolean
34
+
description: |
35
+
If present the PHY is configured to operate in fiber mode.
36
+
37
+
The KSZ8041FTL variant supports fiber mode, enabled by the FXEN
38
+
boot strapping pin. It can't be determined from the PHY registers
39
+
whether the PHY is in fiber mode, so this boolean device tree
40
+
property can be used to describe it.
41
+
42
+
In fiber mode, auto-negotiation is disabled and the PHY can only
43
+
work in 100base-fx (full and half duplex) modes.
44
+
45
+
micrel,led-mode:
46
+
$ref: /schemas/types.yaml#/definitions/uint32
47
+
description: |
48
+
LED mode value to set for PHYs with configurable LEDs.
49
+
50
+
Configure the LED mode with single value. The list of PHYs and the
51
+
bits that are currently supported:
52
+
53
+
KSZ8001: register 0x1e, bits 15..14
54
+
KSZ8041: register 0x1e, bits 15..14
55
+
KSZ8021: register 0x1f, bits 5..4
56
+
KSZ8031: register 0x1f, bits 5..4
57
+
KSZ8051: register 0x1f, bits 5..4
58
+
KSZ8081: register 0x1f, bits 5..4
59
+
KSZ8091: register 0x1f, bits 5..4
60
+
61
+
See the respective PHY datasheet for the mode values.
62
+
minimum: 0
63
+
maximum: 3
64
+
65
+
allOf:
66
+
- $ref: ethernet-phy.yaml#
67
+
- if:
68
+
not:
69
+
properties:
70
+
compatible:
71
+
contains:
72
+
const: ethernet-phy-id0022.1510
73
+
then:
74
+
properties:
75
+
micrel,fiber-mode: false
76
+
- if:
77
+
not:
78
+
properties:
79
+
compatible:
80
+
contains:
81
+
enum:
82
+
- ethernet-phy-id0022.1510
83
+
- ethernet-phy-id0022.1555
84
+
- ethernet-phy-id0022.1556
85
+
- ethernet-phy-id0022.1550
86
+
- ethernet-phy-id0022.1560
87
+
- ethernet-phy-id0022.161a
88
+
then:
89
+
properties:
90
+
micrel,led-mode: false
91
+
- if:
92
+
properties:
93
+
compatible:
94
+
contains:
95
+
enum:
96
+
- ethernet-phy-id0022.1555
97
+
- ethernet-phy-id0022.1556
98
+
- ethernet-phy-id0022.1560
99
+
then:
100
+
properties:
101
+
clock-names:
102
+
const: rmii-ref
103
+
description:
104
+
The RMII reference input clock. Used to determine the XI input
105
+
clock.
106
+
micrel,rmii-reference-clock-select-25-mhz:
107
+
type: boolean
108
+
description: |
109
+
RMII Reference Clock Select bit selects 25 MHz mode
110
+
111
+
Setting the RMII Reference Clock Select bit enables 25 MHz rather
112
+
than 50 MHz clock mode.
113
+
114
+
dependentRequired:
115
+
micrel,rmii-reference-clock-select-25-mhz: [ clock-names ]
116
+
117
+
unevaluatedProperties: false
118
+
119
+
examples:
120
+
- |
121
+
mdio {
122
+
#address-cells = <1>;
123
+
#size-cells = <0>;
124
+
125
+
ethernet-phy@5 {
126
+
compatible = "ethernet-phy-id0022.1510";
127
+
reg = <5>;
128
+
micrel,led-mode = <2>;
129
+
micrel,fiber-mode;
130
+
};
131
+
};