Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fbdev-for-7.0-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev
Pull more fbdev updates from Helge Deller:
"Code cleanups for the au1100fb fbdev driver (Uwe Kleine-König)"
* tag 'fbdev-for-7.0-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev:
fbdev: au1100fb: Replace license boilerplate by SPDX header
fbdev: au1100fb: Fold au1100fb.h into its only user
fbdev: au1100fb: Replace custom printk wrappers by pr_*
fbdev: au1100fb: Make driver compilable on non-mips platforms
fbdev: au1100fb: Use proper conversion specifiers in printk formats
fbdev: au1100fb: Mark several local functions as static
fbdev: au1100fb: Don't store device specific data in global variables
+406
-463
+2
-1
drivers/video/fbdev/Kconfig
+2
-1
drivers/video/fbdev/Kconfig
···
1345
1345
1346
1346
config FB_AU1100
1347
1347
bool "Au1100 LCD Driver"
1348
-
depends on (FB = y) && MIPS_ALCHEMY
1348
+
depends on FB = y
1349
+
depends on MIPS_ALCHEMY || COMPILE_TEST
1349
1350
select FB_IOMEM_HELPERS
1350
1351
help
1351
1352
This is the framebuffer driver for the AMD Au1100 SOC. It can drive
+404
-83
drivers/video/fbdev/au1100fb.c
+404
-83
drivers/video/fbdev/au1100fb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
1
2
/*
2
3
* BRIEF MODULE DESCRIPTION
3
4
* Au1100 LCD Driver.
···
21
20
* Based on:
22
21
* linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
23
22
* Created 28 Dec 1997 by Geert Uytterhoeven
24
-
*
25
-
* This program is free software; you can redistribute it and/or modify it
26
-
* under the terms of the GNU General Public License as published by the
27
-
* Free Software Foundation; either version 2 of the License, or (at your
28
-
* option) any later version.
29
-
*
30
-
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31
-
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32
-
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
33
-
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34
-
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
35
-
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
36
-
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
37
-
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
39
-
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
-
*
41
-
* You should have received a copy of the GNU General Public License along
42
-
* with this program; if not, write to the Free Software Foundation, Inc.,
43
-
* 675 Mass Ave, Cambridge, MA 02139, USA.
44
23
*/
24
+
25
+
#define pr_fmt(fmt) "au1100fb:" fmt "\n"
26
+
45
27
#include <linux/clk.h>
28
+
#include <linux/delay.h>
29
+
#include <linux/io.h>
46
30
#include <linux/module.h>
47
31
#include <linux/kernel.h>
48
32
#include <linux/errno.h>
···
41
55
#include <linux/platform_device.h>
42
56
#include <linux/slab.h>
43
57
44
-
#include <asm/mach-au1x00/au1000.h>
58
+
#if defined(__BIG_ENDIAN)
59
+
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
60
+
#else
61
+
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
62
+
#endif
63
+
#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
45
64
46
-
#define DEBUG 0
65
+
/********************************************************************/
47
66
48
-
#include "au1100fb.h"
67
+
/* LCD controller restrictions */
68
+
#define AU1100_LCD_MAX_XRES 800
69
+
#define AU1100_LCD_MAX_YRES 600
70
+
#define AU1100_LCD_MAX_BPP 16
71
+
#define AU1100_LCD_MAX_CLK 48000000
72
+
#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
73
+
74
+
/* Default number of visible screen buffer to allocate */
75
+
#define AU1100FB_NBR_VIDEO_BUFFERS 4
76
+
77
+
/********************************************************************/
78
+
79
+
struct au1100fb_panel
80
+
{
81
+
const char name[25]; /* Full name <vendor>_<model> */
82
+
83
+
u32 control_base; /* Mode-independent control values */
84
+
u32 clkcontrol_base; /* Panel pixclock preferences */
85
+
86
+
u32 horztiming;
87
+
u32 verttiming;
88
+
89
+
u32 xres; /* Maximum horizontal resolution */
90
+
u32 yres; /* Maximum vertical resolution */
91
+
u32 bpp; /* Maximum depth supported */
92
+
};
93
+
94
+
struct au1100fb_regs
95
+
{
96
+
u32 lcd_control;
97
+
u32 lcd_intstatus;
98
+
u32 lcd_intenable;
99
+
u32 lcd_horztiming;
100
+
u32 lcd_verttiming;
101
+
u32 lcd_clkcontrol;
102
+
u32 lcd_dmaaddr0;
103
+
u32 lcd_dmaaddr1;
104
+
u32 lcd_words;
105
+
u32 lcd_pwmdiv;
106
+
u32 lcd_pwmhi;
107
+
u32 reserved[(0x0400-0x002C)/4];
108
+
u32 lcd_palettebase[256];
109
+
};
110
+
111
+
struct au1100fb_device {
112
+
113
+
struct fb_info info; /* FB driver info record */
114
+
115
+
struct au1100fb_panel *panel; /* Panel connected to this device */
116
+
117
+
struct au1100fb_regs* regs; /* Registers memory map */
118
+
size_t regs_len;
119
+
unsigned int regs_phys;
120
+
121
+
#ifdef CONFIG_PM
122
+
/* stores the register values during suspend */
123
+
struct au1100fb_regs pm_regs;
124
+
#endif
125
+
126
+
unsigned char* fb_mem; /* FrameBuffer memory map */
127
+
size_t fb_len;
128
+
dma_addr_t fb_phys;
129
+
int panel_idx;
130
+
struct clk *lcdclk;
131
+
struct device *dev;
132
+
};
133
+
134
+
/********************************************************************/
135
+
136
+
#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
137
+
#define LCD_CONTROL_SBB_BIT 21
138
+
#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
139
+
#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
140
+
#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
141
+
#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
142
+
#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
143
+
#define LCD_CONTROL_SBPPF_BIT 18
144
+
#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
145
+
#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
146
+
#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
147
+
#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
148
+
#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
149
+
#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
150
+
#define LCD_CONTROL_WP (1<<17)
151
+
#define LCD_CONTROL_WD (1<<16)
152
+
#define LCD_CONTROL_C (1<<15)
153
+
#define LCD_CONTROL_SM_BIT 13
154
+
#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
155
+
#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
156
+
#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
157
+
#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
158
+
#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
159
+
#define LCD_CONTROL_DB (1<<12)
160
+
#define LCD_CONTROL_CCO (1<<11)
161
+
#define LCD_CONTROL_DP (1<<10)
162
+
#define LCD_CONTROL_PO_BIT 8
163
+
#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
164
+
#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
165
+
#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
166
+
#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
167
+
#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
168
+
#define LCD_CONTROL_MPI (1<<7)
169
+
#define LCD_CONTROL_PT (1<<6)
170
+
#define LCD_CONTROL_PC (1<<5)
171
+
#define LCD_CONTROL_BPP_BIT 1
172
+
#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
173
+
#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
174
+
#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
175
+
#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
176
+
#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
177
+
#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
178
+
#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
179
+
#define LCD_CONTROL_GO (1<<0)
180
+
181
+
#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
182
+
#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
183
+
#define LCD_INT_SD (1<<7)
184
+
#define LCD_INT_OF (1<<6)
185
+
#define LCD_INT_UF (1<<5)
186
+
#define LCD_INT_SA (1<<3)
187
+
#define LCD_INT_SS (1<<2)
188
+
#define LCD_INT_S1 (1<<1)
189
+
#define LCD_INT_S0 (1<<0)
190
+
191
+
#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
192
+
#define LCD_HORZTIMING_HN2_BIT 24
193
+
#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
194
+
#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
195
+
#define LCD_HORZTIMING_HN1_BIT 16
196
+
#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
197
+
#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
198
+
#define LCD_HORZTIMING_HPW_BIT 10
199
+
#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
200
+
#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
201
+
#define LCD_HORZTIMING_PPL_BIT 0
202
+
#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
203
+
#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
204
+
205
+
#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
206
+
#define LCD_VERTTIMING_VN2_BIT 24
207
+
#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
208
+
#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
209
+
#define LCD_VERTTIMING_VN1_BIT 16
210
+
#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
211
+
#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
212
+
#define LCD_VERTTIMING_VPW_BIT 10
213
+
#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
214
+
#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
215
+
#define LCD_VERTTIMING_LPP_BIT 0
216
+
#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
217
+
#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
218
+
219
+
#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
220
+
#define LCD_CLKCONTROL_IB (1<<18)
221
+
#define LCD_CLKCONTROL_IC (1<<17)
222
+
#define LCD_CLKCONTROL_IH (1<<16)
223
+
#define LCD_CLKCONTROL_IV (1<<15)
224
+
#define LCD_CLKCONTROL_BF_BIT 10
225
+
#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
226
+
#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
227
+
#define LCD_CLKCONTROL_PCD_BIT 0
228
+
#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
229
+
#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
230
+
231
+
#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
232
+
#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
233
+
#define LCD_DMA_SA_BIT 5
234
+
#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
235
+
#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
236
+
237
+
#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
238
+
#define LCD_WRD_WRDS_BIT 0
239
+
#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
240
+
#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
241
+
242
+
#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
243
+
#define LCD_PWMDIV_EN (1<<12)
244
+
#define LCD_PWMDIV_PWMDIV_BIT 0
245
+
#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
246
+
#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
247
+
248
+
#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
249
+
#define LCD_PWMHI_PWMHI1_BIT 12
250
+
#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
251
+
#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
252
+
#define LCD_PWMHI_PWMHI0_BIT 0
253
+
#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
254
+
#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
255
+
256
+
#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
257
+
#define LCD_PALLETTE_MONO_MI_BIT 0
258
+
#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
259
+
#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
260
+
261
+
#define LCD_PALLETTE_COLOR_RI_BIT 8
262
+
#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
263
+
#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
264
+
#define LCD_PALLETTE_COLOR_GI_BIT 4
265
+
#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
266
+
#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
267
+
#define LCD_PALLETTE_COLOR_BI_BIT 0
268
+
#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
269
+
#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
270
+
271
+
#define LCD_PALLETTE_TFT_DC_BIT 0
272
+
#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
273
+
#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
274
+
275
+
/********************************************************************/
276
+
277
+
/* List of panels known to work with the AU1100 LCD controller.
278
+
* To add a new panel, enter the same specifications as the
279
+
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
280
+
* with the controller restrictions. Restrictions are:
281
+
*
282
+
* STN color panels: max_bpp <= 12
283
+
* STN mono panels: max_bpp <= 4
284
+
* TFT panels: max_bpp <= 16
285
+
* max_xres <= 800
286
+
* max_yres <= 600
287
+
*/
288
+
static struct au1100fb_panel known_lcd_panels[] =
289
+
{
290
+
/* 800x600x16bpp CRT */
291
+
[0] = {
292
+
.name = "CRT_800x600_16",
293
+
.xres = 800,
294
+
.yres = 600,
295
+
.bpp = 16,
296
+
.control_base = 0x0004886A |
297
+
LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
298
+
LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
299
+
.clkcontrol_base = 0x00020000,
300
+
.horztiming = 0x005aff1f,
301
+
.verttiming = 0x16000e57,
302
+
},
303
+
/* just the standard LCD */
304
+
[1] = {
305
+
.name = "WWPC LCD",
306
+
.xres = 240,
307
+
.yres = 320,
308
+
.bpp = 16,
309
+
.control_base = 0x0006806A,
310
+
.horztiming = 0x0A1010EF,
311
+
.verttiming = 0x0301013F,
312
+
.clkcontrol_base = 0x00018001,
313
+
},
314
+
/* Sharp 320x240 TFT panel */
315
+
[2] = {
316
+
.name = "Sharp_LQ038Q5DR01",
317
+
.xres = 320,
318
+
.yres = 240,
319
+
.bpp = 16,
320
+
.control_base =
321
+
( LCD_CONTROL_SBPPF_565
322
+
| LCD_CONTROL_C
323
+
| LCD_CONTROL_SM_0
324
+
| LCD_CONTROL_DEFAULT_PO
325
+
| LCD_CONTROL_PT
326
+
| LCD_CONTROL_PC
327
+
| LCD_CONTROL_BPP_16 ),
328
+
.horztiming =
329
+
( LCD_HORZTIMING_HN2_N(8)
330
+
| LCD_HORZTIMING_HN1_N(60)
331
+
| LCD_HORZTIMING_HPW_N(12)
332
+
| LCD_HORZTIMING_PPL_N(320) ),
333
+
.verttiming =
334
+
( LCD_VERTTIMING_VN2_N(5)
335
+
| LCD_VERTTIMING_VN1_N(17)
336
+
| LCD_VERTTIMING_VPW_N(1)
337
+
| LCD_VERTTIMING_LPP_N(240) ),
338
+
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
339
+
},
340
+
341
+
/* Hitachi SP14Q005 and possibly others */
342
+
[3] = {
343
+
.name = "Hitachi_SP14Qxxx",
344
+
.xres = 320,
345
+
.yres = 240,
346
+
.bpp = 4,
347
+
.control_base =
348
+
( LCD_CONTROL_C
349
+
| LCD_CONTROL_BPP_4 ),
350
+
.horztiming =
351
+
( LCD_HORZTIMING_HN2_N(1)
352
+
| LCD_HORZTIMING_HN1_N(1)
353
+
| LCD_HORZTIMING_HPW_N(1)
354
+
| LCD_HORZTIMING_PPL_N(320) ),
355
+
.verttiming =
356
+
( LCD_VERTTIMING_VN2_N(1)
357
+
| LCD_VERTTIMING_VN1_N(1)
358
+
| LCD_VERTTIMING_VPW_N(1)
359
+
| LCD_VERTTIMING_LPP_N(240) ),
360
+
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
361
+
},
362
+
363
+
/* Generic 640x480 TFT panel */
364
+
[4] = {
365
+
.name = "TFT_640x480_16",
366
+
.xres = 640,
367
+
.yres = 480,
368
+
.bpp = 16,
369
+
.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
370
+
.horztiming = 0x3434d67f,
371
+
.verttiming = 0x0e0e39df,
372
+
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
373
+
},
374
+
375
+
/* Pb1100 LCDB 640x480 PrimeView TFT panel */
376
+
[5] = {
377
+
.name = "PrimeView_640x480_16",
378
+
.xres = 640,
379
+
.yres = 480,
380
+
.bpp = 16,
381
+
.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
382
+
.horztiming = 0x0e4bfe7f,
383
+
.verttiming = 0x210805df,
384
+
.clkcontrol_base = 0x00038001,
385
+
},
386
+
};
387
+
388
+
/********************************************************************/
389
+
390
+
/* Inline helpers */
391
+
392
+
#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
393
+
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
394
+
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
395
+
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
396
+
397
+
#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_MIPS)
398
+
/* This is only defined to be able to compile this driver on non-mips platforms */
399
+
#define KSEG1ADDR(x) (x)
400
+
#endif
49
401
50
402
#define DRIVER_NAME "au1100fb"
51
403
#define DRIVER_DESC "LCD controller driver for AU1100 processors"
···
408
84
{ { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
409
85
};
410
86
411
-
static struct fb_fix_screeninfo au1100fb_fix = {
412
-
.id = "AU1100 FB",
413
-
.xpanstep = 1,
414
-
.ypanstep = 1,
415
-
.type = FB_TYPE_PACKED_PIXELS,
416
-
.accel = FB_ACCEL_NONE,
417
-
};
418
-
419
-
static struct fb_var_screeninfo au1100fb_var = {
420
-
.activate = FB_ACTIVATE_NOW,
421
-
.height = -1,
422
-
.width = -1,
423
-
.vmode = FB_VMODE_NONINTERLACED,
424
-
};
425
-
426
87
/* fb_blank
427
88
* Blank the screen. Depending on the mode, the screen will be
428
89
* activated with the backlight color, or desactivated
···
416
107
{
417
108
struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
418
109
419
-
print_dbg("fb_blank %d %p", blank_mode, fbi);
110
+
pr_devel("fb_blank %d %p", blank_mode, fbi);
420
111
421
112
switch (blank_mode) {
422
113
···
444
135
* Set hardware with var settings. This will enable the controller with a specific
445
136
* mode, normally validated with the fb_check_var method
446
137
*/
447
-
int au1100fb_setmode(struct au1100fb_device *fbdev)
138
+
static int au1100fb_setmode(struct au1100fb_device *fbdev)
448
139
{
449
140
struct fb_info *info;
450
141
u32 words;
···
543
234
/* fb_setcolreg
544
235
* Set color in LCD palette.
545
236
*/
546
-
int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
237
+
static int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
238
+
unsigned transp, struct fb_info *fbi)
547
239
{
548
240
struct au1100fb_device *fbdev;
549
241
u32 *palette;
···
603
293
/* fb_pan_display
604
294
* Pan display in x and/or y as specified
605
295
*/
606
-
int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
296
+
static int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
607
297
{
608
298
struct au1100fb_device *fbdev;
609
299
int dy;
610
300
611
301
fbdev = to_au1100fb_device(fbi);
612
302
613
-
print_dbg("fb_pan_display %p %p", var, fbi);
303
+
pr_devel("fb_pan_display %p %p", var, fbi);
614
304
615
305
if (!var || !fbdev) {
616
306
return -EINVAL;
···
621
311
return -EINVAL;
622
312
}
623
313
624
-
print_dbg("fb_pan_display 2 %p %p", var, fbi);
314
+
pr_devel("fb_pan_display 2 %p %p", var, fbi);
625
315
dy = var->yoffset - fbi->var.yoffset;
626
316
if (dy) {
627
317
628
318
u32 dmaaddr;
629
319
630
-
print_dbg("Panning screen of %d lines", dy);
320
+
pr_devel("Panning screen of %d lines", dy);
631
321
632
322
dmaaddr = fbdev->regs->lcd_dmaaddr0;
633
323
dmaaddr += (fbi->fix.line_length * dy);
···
641
331
fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
642
332
}
643
333
}
644
-
print_dbg("fb_pan_display 3 %p %p", var, fbi);
334
+
pr_devel("fb_pan_display 3 %p %p", var, fbi);
645
335
646
336
return 0;
647
337
}
···
650
340
* Map video memory in user space. We don't use the generic fb_mmap method mainly
651
341
* to allow the use of the TLB streaming flag (CCA=6)
652
342
*/
653
-
int au1100fb_fb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
343
+
static int au1100fb_fb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
654
344
{
655
345
struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
656
346
657
347
vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
658
348
349
+
#ifndef CONFIG_S390
350
+
/* On s390 pgprot_val() is a function and thus not a lvalue */
659
351
pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
352
+
#endif
660
353
661
354
return dma_mmap_coherent(fbdev->dev, vma, fbdev->fb_mem, fbdev->fb_phys,
662
355
fbdev->fb_len);
···
684
371
int num_panels = ARRAY_SIZE(known_lcd_panels);
685
372
686
373
if (num_panels <= 0) {
687
-
print_err("No LCD panels supported by driver!");
374
+
pr_err("No LCD panels supported by driver!");
688
375
return -ENODEV;
689
376
}
690
377
···
707
394
}
708
395
}
709
396
if (i >= num_panels) {
710
-
print_warn("Panel '%s' not supported!", this_opt);
397
+
pr_warn("Panel '%s' not supported!", this_opt);
711
398
return -ENODEV;
712
399
}
713
400
}
714
401
/* Unsupported option */
715
402
else
716
-
print_warn("Unsupported option \"%s\"", this_opt);
403
+
pr_warn("Unsupported option \"%s\"", this_opt);
717
404
}
718
405
719
-
print_info("Panel=%s", fbdev->panel->name);
406
+
pr_info("Panel=%s", fbdev->panel->name);
720
407
721
408
return 0;
722
409
}
···
741
428
/* Allocate region for our registers and map them */
742
429
regs_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
743
430
if (!regs_res) {
744
-
print_err("fail to retrieve registers resource");
431
+
pr_err("fail to retrieve registers resource");
745
432
return -EFAULT;
746
433
}
747
434
748
-
au1100fb_fix.mmio_start = regs_res->start;
749
-
au1100fb_fix.mmio_len = resource_size(regs_res);
435
+
fbdev->info.fix = (struct fb_fix_screeninfo) {
436
+
.mmio_start = regs_res->start,
437
+
.mmio_len = resource_size(regs_res),
438
+
.id = "AU1100 FB",
439
+
.xpanstep = 1,
440
+
.ypanstep = 1,
441
+
.type = FB_TYPE_PACKED_PIXELS,
442
+
.accel = FB_ACCEL_NONE,
443
+
};
750
444
751
445
if (!devm_request_mem_region(&dev->dev,
752
-
au1100fb_fix.mmio_start,
753
-
au1100fb_fix.mmio_len,
446
+
fbdev->info.fix.mmio_start,
447
+
fbdev->info.fix.mmio_len,
754
448
DRIVER_NAME)) {
755
-
print_err("fail to lock memory region at 0x%08lx",
756
-
au1100fb_fix.mmio_start);
449
+
pr_err("fail to lock memory region at 0x%08lx",
450
+
fbdev->info.fix.mmio_start);
757
451
return -EBUSY;
758
452
}
759
453
760
-
fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start);
454
+
fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(fbdev->info.fix.mmio_start);
761
455
762
-
print_dbg("Register memory map at %p", fbdev->regs);
763
-
print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
456
+
pr_devel("Register memory map at %p", fbdev->regs);
457
+
pr_devel("phys=0x%08x, size=%zu", fbdev->regs_phys, fbdev->regs_len);
764
458
765
459
c = clk_get(NULL, "lcd_intclk");
766
460
if (!IS_ERR(c)) {
···
784
464
PAGE_ALIGN(fbdev->fb_len),
785
465
&fbdev->fb_phys, GFP_KERNEL);
786
466
if (!fbdev->fb_mem) {
787
-
print_err("fail to allocate framebuffer (size: %dK))",
467
+
pr_err("fail to allocate framebuffer (size: %zuK))",
788
468
fbdev->fb_len / 1024);
789
469
return -ENOMEM;
790
470
}
791
471
792
-
au1100fb_fix.smem_start = fbdev->fb_phys;
793
-
au1100fb_fix.smem_len = fbdev->fb_len;
472
+
fbdev->info.fix.smem_start = fbdev->fb_phys;
473
+
fbdev->info.fix.smem_len = fbdev->fb_len;
794
474
795
-
print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
796
-
print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
475
+
pr_devel("Framebuffer memory map at %p", fbdev->fb_mem);
476
+
pr_devel("phys=0x%pad, size=%zuK", &fbdev->fb_phys, fbdev->fb_len / 1024);
797
477
798
478
/* load the panel info into the var struct */
799
-
au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
800
-
au1100fb_var.xres = fbdev->panel->xres;
801
-
au1100fb_var.xres_virtual = au1100fb_var.xres;
802
-
au1100fb_var.yres = fbdev->panel->yres;
803
-
au1100fb_var.yres_virtual = au1100fb_var.yres;
479
+
fbdev->info.var = (struct fb_var_screeninfo) {
480
+
.activate = FB_ACTIVATE_NOW,
481
+
.height = -1,
482
+
.width = -1,
483
+
.vmode = FB_VMODE_NONINTERLACED,
484
+
.bits_per_pixel = fbdev->panel->bpp,
485
+
.xres = fbdev->panel->xres,
486
+
.xres_virtual = fbdev->panel->xres,
487
+
.yres = fbdev->panel->yres,
488
+
.yres_virtual = fbdev->panel->yres,
489
+
};
804
490
805
491
fbdev->info.screen_base = fbdev->fb_mem;
806
492
fbdev->info.fbops = &au1100fb_ops;
807
-
fbdev->info.fix = au1100fb_fix;
808
493
809
494
fbdev->info.pseudo_palette =
810
495
devm_kcalloc(&dev->dev, 16, sizeof(u32), GFP_KERNEL);
···
817
492
return -ENOMEM;
818
493
819
494
if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
820
-
print_err("Fail to allocate colormap (%d entries)",
495
+
pr_err("Fail to allocate colormap (%d entries)",
821
496
AU1100_LCD_NBR_PALETTE_ENTRIES);
822
497
return -EFAULT;
823
498
}
824
-
825
-
fbdev->info.var = au1100fb_var;
826
499
827
500
/* Set h/w registers */
828
501
au1100fb_setmode(fbdev);
829
502
830
503
/* Register new framebuffer */
831
504
if (register_framebuffer(&fbdev->info) < 0) {
832
-
print_err("cannot register new framebuffer");
505
+
pr_err("cannot register new framebuffer");
833
506
goto failed;
834
507
}
835
508
···
845
522
return -ENODEV;
846
523
}
847
524
848
-
void au1100fb_drv_remove(struct platform_device *dev)
525
+
static void au1100fb_drv_remove(struct platform_device *dev)
849
526
{
850
527
struct au1100fb_device *fbdev = NULL;
851
528
···
868
545
}
869
546
870
547
#ifdef CONFIG_PM
871
-
static struct au1100fb_regs fbregs;
872
-
873
-
int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
548
+
static int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
874
549
{
875
550
struct au1100fb_device *fbdev = platform_get_drvdata(dev);
876
551
···
880
559
881
560
clk_disable(fbdev->lcdclk);
882
561
883
-
memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs));
562
+
memcpy(&fbdev->pm_regs, fbdev->regs, sizeof(struct au1100fb_regs));
884
563
885
564
return 0;
886
565
}
887
566
888
-
int au1100fb_drv_resume(struct platform_device *dev)
567
+
static int au1100fb_drv_resume(struct platform_device *dev)
889
568
{
890
569
struct au1100fb_device *fbdev = platform_get_drvdata(dev);
891
570
int ret;
···
893
572
if (!fbdev)
894
573
return 0;
895
574
896
-
memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs));
575
+
memcpy(fbdev->regs, &fbdev->pm_regs, sizeof(struct au1100fb_regs));
897
576
898
577
ret = clk_enable(fbdev->lcdclk);
899
578
if (ret)
-379
drivers/video/fbdev/au1100fb.h
-379
drivers/video/fbdev/au1100fb.h
···
1
-
/*
2
-
* BRIEF MODULE DESCRIPTION
3
-
* Hardware definitions for the Au1100 LCD controller
4
-
*
5
-
* Copyright 2002 MontaVista Software
6
-
* Copyright 2002 Alchemy Semiconductor
7
-
* Author: Alchemy Semiconductor, MontaVista Software
8
-
*
9
-
* This program is free software; you can redistribute it and/or modify it
10
-
* under the terms of the GNU General Public License as published by the
11
-
* Free Software Foundation; either version 2 of the License, or (at your
12
-
* option) any later version.
13
-
*
14
-
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15
-
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16
-
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17
-
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18
-
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19
-
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20
-
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21
-
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23
-
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24
-
*
25
-
* You should have received a copy of the GNU General Public License along
26
-
* with this program; if not, write to the Free Software Foundation, Inc.,
27
-
* 675 Mass Ave, Cambridge, MA 02139, USA.
28
-
*/
29
-
30
-
#ifndef _AU1100LCD_H
31
-
#define _AU1100LCD_H
32
-
33
-
#include <asm/mach-au1x00/au1000.h>
34
-
35
-
#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
36
-
#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
37
-
#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
38
-
39
-
#if DEBUG
40
-
#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
41
-
#else
42
-
#define print_dbg(f, arg...) do {} while (0)
43
-
#endif
44
-
45
-
#if defined(__BIG_ENDIAN)
46
-
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
47
-
#else
48
-
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
49
-
#endif
50
-
#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
51
-
52
-
/********************************************************************/
53
-
54
-
/* LCD controller restrictions */
55
-
#define AU1100_LCD_MAX_XRES 800
56
-
#define AU1100_LCD_MAX_YRES 600
57
-
#define AU1100_LCD_MAX_BPP 16
58
-
#define AU1100_LCD_MAX_CLK 48000000
59
-
#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
60
-
61
-
/* Default number of visible screen buffer to allocate */
62
-
#define AU1100FB_NBR_VIDEO_BUFFERS 4
63
-
64
-
/********************************************************************/
65
-
66
-
struct au1100fb_panel
67
-
{
68
-
const char name[25]; /* Full name <vendor>_<model> */
69
-
70
-
u32 control_base; /* Mode-independent control values */
71
-
u32 clkcontrol_base; /* Panel pixclock preferences */
72
-
73
-
u32 horztiming;
74
-
u32 verttiming;
75
-
76
-
u32 xres; /* Maximum horizontal resolution */
77
-
u32 yres; /* Maximum vertical resolution */
78
-
u32 bpp; /* Maximum depth supported */
79
-
};
80
-
81
-
struct au1100fb_regs
82
-
{
83
-
u32 lcd_control;
84
-
u32 lcd_intstatus;
85
-
u32 lcd_intenable;
86
-
u32 lcd_horztiming;
87
-
u32 lcd_verttiming;
88
-
u32 lcd_clkcontrol;
89
-
u32 lcd_dmaaddr0;
90
-
u32 lcd_dmaaddr1;
91
-
u32 lcd_words;
92
-
u32 lcd_pwmdiv;
93
-
u32 lcd_pwmhi;
94
-
u32 reserved[(0x0400-0x002C)/4];
95
-
u32 lcd_palettebase[256];
96
-
};
97
-
98
-
struct au1100fb_device {
99
-
100
-
struct fb_info info; /* FB driver info record */
101
-
102
-
struct au1100fb_panel *panel; /* Panel connected to this device */
103
-
104
-
struct au1100fb_regs* regs; /* Registers memory map */
105
-
size_t regs_len;
106
-
unsigned int regs_phys;
107
-
108
-
unsigned char* fb_mem; /* FrameBuffer memory map */
109
-
size_t fb_len;
110
-
dma_addr_t fb_phys;
111
-
int panel_idx;
112
-
struct clk *lcdclk;
113
-
struct device *dev;
114
-
};
115
-
116
-
/********************************************************************/
117
-
118
-
#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
119
-
#define LCD_CONTROL_SBB_BIT 21
120
-
#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
121
-
#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
122
-
#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
123
-
#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
124
-
#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
125
-
#define LCD_CONTROL_SBPPF_BIT 18
126
-
#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
127
-
#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
128
-
#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
129
-
#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
130
-
#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
131
-
#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
132
-
#define LCD_CONTROL_WP (1<<17)
133
-
#define LCD_CONTROL_WD (1<<16)
134
-
#define LCD_CONTROL_C (1<<15)
135
-
#define LCD_CONTROL_SM_BIT 13
136
-
#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
137
-
#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
138
-
#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
139
-
#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
140
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#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
141
-
#define LCD_CONTROL_DB (1<<12)
142
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#define LCD_CONTROL_CCO (1<<11)
143
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#define LCD_CONTROL_DP (1<<10)
144
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#define LCD_CONTROL_PO_BIT 8
145
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#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
146
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#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
147
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#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
148
-
#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
149
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#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
150
-
#define LCD_CONTROL_MPI (1<<7)
151
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#define LCD_CONTROL_PT (1<<6)
152
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#define LCD_CONTROL_PC (1<<5)
153
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#define LCD_CONTROL_BPP_BIT 1
154
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#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
155
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#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
156
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#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
157
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#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
158
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#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
159
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#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
160
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#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
161
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#define LCD_CONTROL_GO (1<<0)
162
-
163
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#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
164
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#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
165
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#define LCD_INT_SD (1<<7)
166
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#define LCD_INT_OF (1<<6)
167
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#define LCD_INT_UF (1<<5)
168
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#define LCD_INT_SA (1<<3)
169
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#define LCD_INT_SS (1<<2)
170
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#define LCD_INT_S1 (1<<1)
171
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#define LCD_INT_S0 (1<<0)
172
-
173
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#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
174
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#define LCD_HORZTIMING_HN2_BIT 24
175
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#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
176
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#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
177
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#define LCD_HORZTIMING_HN1_BIT 16
178
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#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
179
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#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
180
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#define LCD_HORZTIMING_HPW_BIT 10
181
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#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
182
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#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
183
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#define LCD_HORZTIMING_PPL_BIT 0
184
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#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
185
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#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
186
-
187
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#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
188
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#define LCD_VERTTIMING_VN2_BIT 24
189
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#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
190
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#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
191
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#define LCD_VERTTIMING_VN1_BIT 16
192
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#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
193
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#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
194
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#define LCD_VERTTIMING_VPW_BIT 10
195
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#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
196
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#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
197
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#define LCD_VERTTIMING_LPP_BIT 0
198
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#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
199
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#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
200
-
201
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#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
202
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#define LCD_CLKCONTROL_IB (1<<18)
203
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#define LCD_CLKCONTROL_IC (1<<17)
204
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#define LCD_CLKCONTROL_IH (1<<16)
205
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#define LCD_CLKCONTROL_IV (1<<15)
206
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#define LCD_CLKCONTROL_BF_BIT 10
207
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#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
208
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#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
209
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#define LCD_CLKCONTROL_PCD_BIT 0
210
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#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
211
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#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
212
-
213
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#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
214
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#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
215
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#define LCD_DMA_SA_BIT 5
216
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#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
217
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#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
218
-
219
-
#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
220
-
#define LCD_WRD_WRDS_BIT 0
221
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#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
222
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#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
223
-
224
-
#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
225
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#define LCD_PWMDIV_EN (1<<12)
226
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#define LCD_PWMDIV_PWMDIV_BIT 0
227
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#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
228
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#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
229
-
230
-
#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
231
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#define LCD_PWMHI_PWMHI1_BIT 12
232
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#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
233
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#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
234
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#define LCD_PWMHI_PWMHI0_BIT 0
235
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#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
236
-
#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
237
-
238
-
#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
239
-
#define LCD_PALLETTE_MONO_MI_BIT 0
240
-
#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
241
-
#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
242
-
243
-
#define LCD_PALLETTE_COLOR_RI_BIT 8
244
-
#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
245
-
#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
246
-
#define LCD_PALLETTE_COLOR_GI_BIT 4
247
-
#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
248
-
#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
249
-
#define LCD_PALLETTE_COLOR_BI_BIT 0
250
-
#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
251
-
#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
252
-
253
-
#define LCD_PALLETTE_TFT_DC_BIT 0
254
-
#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
255
-
#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
256
-
257
-
/********************************************************************/
258
-
259
-
/* List of panels known to work with the AU1100 LCD controller.
260
-
* To add a new panel, enter the same specifications as the
261
-
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
262
-
* with the controller restrictions. Restrictions are:
263
-
*
264
-
* STN color panels: max_bpp <= 12
265
-
* STN mono panels: max_bpp <= 4
266
-
* TFT panels: max_bpp <= 16
267
-
* max_xres <= 800
268
-
* max_yres <= 600
269
-
*/
270
-
static struct au1100fb_panel known_lcd_panels[] =
271
-
{
272
-
/* 800x600x16bpp CRT */
273
-
[0] = {
274
-
.name = "CRT_800x600_16",
275
-
.xres = 800,
276
-
.yres = 600,
277
-
.bpp = 16,
278
-
.control_base = 0x0004886A |
279
-
LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
280
-
LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
281
-
.clkcontrol_base = 0x00020000,
282
-
.horztiming = 0x005aff1f,
283
-
.verttiming = 0x16000e57,
284
-
},
285
-
/* just the standard LCD */
286
-
[1] = {
287
-
.name = "WWPC LCD",
288
-
.xres = 240,
289
-
.yres = 320,
290
-
.bpp = 16,
291
-
.control_base = 0x0006806A,
292
-
.horztiming = 0x0A1010EF,
293
-
.verttiming = 0x0301013F,
294
-
.clkcontrol_base = 0x00018001,
295
-
},
296
-
/* Sharp 320x240 TFT panel */
297
-
[2] = {
298
-
.name = "Sharp_LQ038Q5DR01",
299
-
.xres = 320,
300
-
.yres = 240,
301
-
.bpp = 16,
302
-
.control_base =
303
-
( LCD_CONTROL_SBPPF_565
304
-
| LCD_CONTROL_C
305
-
| LCD_CONTROL_SM_0
306
-
| LCD_CONTROL_DEFAULT_PO
307
-
| LCD_CONTROL_PT
308
-
| LCD_CONTROL_PC
309
-
| LCD_CONTROL_BPP_16 ),
310
-
.horztiming =
311
-
( LCD_HORZTIMING_HN2_N(8)
312
-
| LCD_HORZTIMING_HN1_N(60)
313
-
| LCD_HORZTIMING_HPW_N(12)
314
-
| LCD_HORZTIMING_PPL_N(320) ),
315
-
.verttiming =
316
-
( LCD_VERTTIMING_VN2_N(5)
317
-
| LCD_VERTTIMING_VN1_N(17)
318
-
| LCD_VERTTIMING_VPW_N(1)
319
-
| LCD_VERTTIMING_LPP_N(240) ),
320
-
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
321
-
},
322
-
323
-
/* Hitachi SP14Q005 and possibly others */
324
-
[3] = {
325
-
.name = "Hitachi_SP14Qxxx",
326
-
.xres = 320,
327
-
.yres = 240,
328
-
.bpp = 4,
329
-
.control_base =
330
-
( LCD_CONTROL_C
331
-
| LCD_CONTROL_BPP_4 ),
332
-
.horztiming =
333
-
( LCD_HORZTIMING_HN2_N(1)
334
-
| LCD_HORZTIMING_HN1_N(1)
335
-
| LCD_HORZTIMING_HPW_N(1)
336
-
| LCD_HORZTIMING_PPL_N(320) ),
337
-
.verttiming =
338
-
( LCD_VERTTIMING_VN2_N(1)
339
-
| LCD_VERTTIMING_VN1_N(1)
340
-
| LCD_VERTTIMING_VPW_N(1)
341
-
| LCD_VERTTIMING_LPP_N(240) ),
342
-
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
343
-
},
344
-
345
-
/* Generic 640x480 TFT panel */
346
-
[4] = {
347
-
.name = "TFT_640x480_16",
348
-
.xres = 640,
349
-
.yres = 480,
350
-
.bpp = 16,
351
-
.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
352
-
.horztiming = 0x3434d67f,
353
-
.verttiming = 0x0e0e39df,
354
-
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
355
-
},
356
-
357
-
/* Pb1100 LCDB 640x480 PrimeView TFT panel */
358
-
[5] = {
359
-
.name = "PrimeView_640x480_16",
360
-
.xres = 640,
361
-
.yres = 480,
362
-
.bpp = 16,
363
-
.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
364
-
.horztiming = 0x0e4bfe7f,
365
-
.verttiming = 0x210805df,
366
-
.clkcontrol_base = 0x00038001,
367
-
},
368
-
};
369
-
370
-
/********************************************************************/
371
-
372
-
/* Inline helpers */
373
-
374
-
#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
375
-
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
376
-
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
377
-
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
378
-
379
-
#endif /* _AU1100LCD_H */