Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/gmch: split out i915_gmch.[ch] from soc
Most of the soc/intel_gmch.[ch] code is i915 core specific. Split it out
to i915_gmch.[ch].
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/f4f8cc931ef2a5958cebe3ca44d40aedad01626f.1763578288.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+160
-141
+1
drivers/gpu/drm/i915/Makefile
+1
drivers/gpu/drm/i915/Makefile
+5
-6
drivers/gpu/drm/i915/i915_driver.c
+5
-6
drivers/gpu/drm/i915/i915_driver.c
···
88
88
#include "pxp/intel_pxp_debugfs.h"
89
89
#include "pxp/intel_pxp_pm.h"
90
90
91
-
#include "soc/intel_gmch.h"
92
-
93
91
#include "i915_debugfs.h"
94
92
#include "i915_driver.h"
95
93
#include "i915_drm_client.h"
···
95
97
#include "i915_edram.h"
96
98
#include "i915_file_private.h"
97
99
#include "i915_getparam.h"
100
+
#include "i915_gmch.h"
98
101
#include "i915_hwmon.h"
99
102
#include "i915_ioc32.h"
100
103
#include "i915_ioctl.h"
···
322
323
if (i915_inject_probe_failure(dev_priv))
323
324
return -ENODEV;
324
325
325
-
ret = intel_gmch_bridge_setup(dev_priv);
326
+
ret = i915_gmch_bridge_setup(dev_priv);
326
327
if (ret < 0)
327
328
return ret;
328
329
···
339
340
}
340
341
341
342
/* Try to make sure MCHBAR is enabled before poking at it */
342
-
intel_gmch_bar_setup(dev_priv);
343
+
i915_gmch_bar_setup(dev_priv);
343
344
intel_device_info_runtime_init(dev_priv);
344
345
intel_display_device_info_runtime_init(display);
345
346
···
355
356
return 0;
356
357
357
358
err_uncore:
358
-
intel_gmch_bar_teardown(dev_priv);
359
+
i915_gmch_bar_teardown(dev_priv);
359
360
360
361
return ret;
361
362
}
···
366
367
*/
367
368
static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
368
369
{
369
-
intel_gmch_bar_teardown(dev_priv);
370
+
i915_gmch_bar_teardown(dev_priv);
370
371
}
371
372
372
373
/**
+141
drivers/gpu/drm/i915/i915_gmch.c
+141
drivers/gpu/drm/i915/i915_gmch.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/* Copyright © 2025 Intel Corporation */
3
+
4
+
#include <linux/pnp.h>
5
+
6
+
#include <drm/drm_managed.h>
7
+
#include <drm/drm_print.h>
8
+
9
+
#include "i915_drv.h"
10
+
#include "i915_gmch.h"
11
+
#include "intel_pci_config.h"
12
+
13
+
static void i915_gmch_bridge_release(struct drm_device *dev, void *bridge)
14
+
{
15
+
pci_dev_put(bridge);
16
+
}
17
+
18
+
int i915_gmch_bridge_setup(struct drm_i915_private *i915)
19
+
{
20
+
int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
21
+
22
+
i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
23
+
if (!i915->gmch.pdev) {
24
+
drm_err(&i915->drm, "bridge device not found\n");
25
+
return -EIO;
26
+
}
27
+
28
+
return drmm_add_action_or_reset(&i915->drm, i915_gmch_bridge_release,
29
+
i915->gmch.pdev);
30
+
}
31
+
32
+
static int mchbar_reg(struct drm_i915_private *i915)
33
+
{
34
+
return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
35
+
}
36
+
37
+
/* Allocate space for the MCH regs if needed, return nonzero on error */
38
+
static int
39
+
intel_alloc_mchbar_resource(struct drm_i915_private *i915)
40
+
{
41
+
u32 temp_lo, temp_hi = 0;
42
+
u64 mchbar_addr;
43
+
int ret;
44
+
45
+
if (GRAPHICS_VER(i915) >= 4)
46
+
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi);
47
+
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo);
48
+
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
49
+
50
+
/* If ACPI doesn't have it, assume we need to allocate it ourselves */
51
+
if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
52
+
pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
53
+
return 0;
54
+
55
+
/* Get some space for it */
56
+
i915->gmch.mch_res.name = "i915 MCHBAR";
57
+
i915->gmch.mch_res.flags = IORESOURCE_MEM;
58
+
ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
59
+
&i915->gmch.mch_res,
60
+
MCHBAR_SIZE, MCHBAR_SIZE,
61
+
PCIBIOS_MIN_MEM,
62
+
0, pcibios_align_resource,
63
+
i915->gmch.pdev);
64
+
if (ret) {
65
+
drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
66
+
i915->gmch.mch_res.start = 0;
67
+
return ret;
68
+
}
69
+
70
+
if (GRAPHICS_VER(i915) >= 4)
71
+
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4,
72
+
upper_32_bits(i915->gmch.mch_res.start));
73
+
74
+
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
75
+
lower_32_bits(i915->gmch.mch_res.start));
76
+
return 0;
77
+
}
78
+
79
+
/* Setup MCHBAR if possible, return true if we should disable it again */
80
+
void i915_gmch_bar_setup(struct drm_i915_private *i915)
81
+
{
82
+
u32 temp;
83
+
bool enabled;
84
+
85
+
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
86
+
return;
87
+
88
+
i915->gmch.mchbar_need_disable = false;
89
+
90
+
if (IS_I915G(i915) || IS_I915GM(i915)) {
91
+
pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
92
+
enabled = !!(temp & DEVEN_MCHBAR_EN);
93
+
} else {
94
+
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
95
+
enabled = temp & 1;
96
+
}
97
+
98
+
/* If it's already enabled, don't have to do anything */
99
+
if (enabled)
100
+
return;
101
+
102
+
if (intel_alloc_mchbar_resource(i915))
103
+
return;
104
+
105
+
i915->gmch.mchbar_need_disable = true;
106
+
107
+
/* Space is allocated or reserved, so enable it. */
108
+
if (IS_I915G(i915) || IS_I915GM(i915)) {
109
+
pci_write_config_dword(i915->gmch.pdev, DEVEN,
110
+
temp | DEVEN_MCHBAR_EN);
111
+
} else {
112
+
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
113
+
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1);
114
+
}
115
+
}
116
+
117
+
void i915_gmch_bar_teardown(struct drm_i915_private *i915)
118
+
{
119
+
if (i915->gmch.mchbar_need_disable) {
120
+
if (IS_I915G(i915) || IS_I915GM(i915)) {
121
+
u32 deven_val;
122
+
123
+
pci_read_config_dword(i915->gmch.pdev, DEVEN,
124
+
&deven_val);
125
+
deven_val &= ~DEVEN_MCHBAR_EN;
126
+
pci_write_config_dword(i915->gmch.pdev, DEVEN,
127
+
deven_val);
128
+
} else {
129
+
u32 mchbar_val;
130
+
131
+
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915),
132
+
&mchbar_val);
133
+
mchbar_val &= ~1;
134
+
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
135
+
mchbar_val);
136
+
}
137
+
}
138
+
139
+
if (i915->gmch.mch_res.start)
140
+
release_resource(&i915->gmch.mch_res);
141
+
}
+13
drivers/gpu/drm/i915/i915_gmch.h
+13
drivers/gpu/drm/i915/i915_gmch.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright © 2025 Intel Corporation */
3
+
4
+
#ifndef __I915_GMCH_H__
5
+
#define __I915_GMCH_H__
6
+
7
+
struct drm_i915_private;
8
+
9
+
int i915_gmch_bridge_setup(struct drm_i915_private *i915);
10
+
void i915_gmch_bar_setup(struct drm_i915_private *i915);
11
+
void i915_gmch_bar_teardown(struct drm_i915_private *i915);
12
+
13
+
#endif /* __I915_GMCH_H__ */
-132
drivers/gpu/drm/i915/soc/intel_gmch.c
-132
drivers/gpu/drm/i915/soc/intel_gmch.c
···
4
4
*/
5
5
6
6
#include <linux/pci.h>
7
-
#include <linux/pnp.h>
8
7
#include <linux/vgaarb.h>
9
8
10
-
#include <drm/drm_managed.h>
11
9
#include <drm/drm_print.h>
12
10
#include <drm/intel/i915_drm.h>
13
11
···
14
16
#include "i915_drv.h"
15
17
#include "intel_gmch.h"
16
18
#include "intel_pci_config.h"
17
-
18
-
static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
19
-
{
20
-
pci_dev_put(bridge);
21
-
}
22
-
23
-
int intel_gmch_bridge_setup(struct drm_i915_private *i915)
24
-
{
25
-
int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
26
-
27
-
i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
28
-
if (!i915->gmch.pdev) {
29
-
drm_err(&i915->drm, "bridge device not found\n");
30
-
return -EIO;
31
-
}
32
-
33
-
return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
34
-
i915->gmch.pdev);
35
-
}
36
-
37
-
static int mchbar_reg(struct drm_i915_private *i915)
38
-
{
39
-
return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
40
-
}
41
-
42
-
/* Allocate space for the MCH regs if needed, return nonzero on error */
43
-
static int
44
-
intel_alloc_mchbar_resource(struct drm_i915_private *i915)
45
-
{
46
-
u32 temp_lo, temp_hi = 0;
47
-
u64 mchbar_addr;
48
-
int ret;
49
-
50
-
if (GRAPHICS_VER(i915) >= 4)
51
-
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi);
52
-
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo);
53
-
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
54
-
55
-
/* If ACPI doesn't have it, assume we need to allocate it ourselves */
56
-
if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
57
-
pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
58
-
return 0;
59
-
60
-
/* Get some space for it */
61
-
i915->gmch.mch_res.name = "i915 MCHBAR";
62
-
i915->gmch.mch_res.flags = IORESOURCE_MEM;
63
-
ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
64
-
&i915->gmch.mch_res,
65
-
MCHBAR_SIZE, MCHBAR_SIZE,
66
-
PCIBIOS_MIN_MEM,
67
-
0, pcibios_align_resource,
68
-
i915->gmch.pdev);
69
-
if (ret) {
70
-
drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
71
-
i915->gmch.mch_res.start = 0;
72
-
return ret;
73
-
}
74
-
75
-
if (GRAPHICS_VER(i915) >= 4)
76
-
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4,
77
-
upper_32_bits(i915->gmch.mch_res.start));
78
-
79
-
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
80
-
lower_32_bits(i915->gmch.mch_res.start));
81
-
return 0;
82
-
}
83
-
84
-
/* Setup MCHBAR if possible, return true if we should disable it again */
85
-
void intel_gmch_bar_setup(struct drm_i915_private *i915)
86
-
{
87
-
u32 temp;
88
-
bool enabled;
89
-
90
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
91
-
return;
92
-
93
-
i915->gmch.mchbar_need_disable = false;
94
-
95
-
if (IS_I915G(i915) || IS_I915GM(i915)) {
96
-
pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
97
-
enabled = !!(temp & DEVEN_MCHBAR_EN);
98
-
} else {
99
-
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
100
-
enabled = temp & 1;
101
-
}
102
-
103
-
/* If it's already enabled, don't have to do anything */
104
-
if (enabled)
105
-
return;
106
-
107
-
if (intel_alloc_mchbar_resource(i915))
108
-
return;
109
-
110
-
i915->gmch.mchbar_need_disable = true;
111
-
112
-
/* Space is allocated or reserved, so enable it. */
113
-
if (IS_I915G(i915) || IS_I915GM(i915)) {
114
-
pci_write_config_dword(i915->gmch.pdev, DEVEN,
115
-
temp | DEVEN_MCHBAR_EN);
116
-
} else {
117
-
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
118
-
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1);
119
-
}
120
-
}
121
-
122
-
void intel_gmch_bar_teardown(struct drm_i915_private *i915)
123
-
{
124
-
if (i915->gmch.mchbar_need_disable) {
125
-
if (IS_I915G(i915) || IS_I915GM(i915)) {
126
-
u32 deven_val;
127
-
128
-
pci_read_config_dword(i915->gmch.pdev, DEVEN,
129
-
&deven_val);
130
-
deven_val &= ~DEVEN_MCHBAR_EN;
131
-
pci_write_config_dword(i915->gmch.pdev, DEVEN,
132
-
deven_val);
133
-
} else {
134
-
u32 mchbar_val;
135
-
136
-
pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915),
137
-
&mchbar_val);
138
-
mchbar_val &= ~1;
139
-
pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
140
-
mchbar_val);
141
-
}
142
-
}
143
-
144
-
if (i915->gmch.mch_res.start)
145
-
release_resource(&i915->gmch.mch_res);
146
-
}
147
19
148
20
int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
149
21
{
-3
drivers/gpu/drm/i915/soc/intel_gmch.h
-3
drivers/gpu/drm/i915/soc/intel_gmch.h
···
11
11
struct pci_dev;
12
12
struct drm_i915_private;
13
13
14
-
int intel_gmch_bridge_setup(struct drm_i915_private *i915);
15
-
void intel_gmch_bar_setup(struct drm_i915_private *i915);
16
-
void intel_gmch_bar_teardown(struct drm_i915_private *i915);
17
14
int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode);
18
15
unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode);
19
16