Merge branch 'net-mdio-start-separating-c22-and-c45'

+129 -46

drivers/net/dsa/mv88e6xxx/chip.c

··· 3884 3884 return err ? err : val; 3885 3885 } 3886 3886 3887 + static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3888 + int reg) 3889 + { 3890 + struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3891 + struct mv88e6xxx_chip *chip = mdio_bus->chip; 3892 + u16 val; 3893 + int err; 3894 + 3895 + if (!chip->info->ops->phy_read_c45) 3896 + return -EOPNOTSUPP; 3897 + 3898 + mv88e6xxx_reg_lock(chip); 3899 + err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3900 + mv88e6xxx_reg_unlock(chip); 3901 + 3902 + return err ? err : val; 3903 + } 3904 + 3887 3905 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3888 3906 { 3889 3907 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; ··· 3913 3895 3914 3896 mv88e6xxx_reg_lock(chip); 3915 3897 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3898 + mv88e6xxx_reg_unlock(chip); 3899 + 3900 + return err; 3901 + } 3902 + 3903 + static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3904 + int reg, u16 val) 3905 + { 3906 + struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3907 + struct mv88e6xxx_chip *chip = mdio_bus->chip; 3908 + int err; 3909 + 3910 + if (!chip->info->ops->phy_write_c45) 3911 + return -EOPNOTSUPP; 3912 + 3913 + mv88e6xxx_reg_lock(chip); 3914 + err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3916 3915 mv88e6xxx_reg_unlock(chip); 3917 3916 3918 3917 return err; ··· 3973 3938 3974 3939 bus->read = mv88e6xxx_mdio_read; 3975 3940 bus->write = mv88e6xxx_mdio_write; 3941 + bus->read_c45 = mv88e6xxx_mdio_read_c45; 3942 + bus->write_c45 = mv88e6xxx_mdio_write_c45; 3976 3943 bus->parent = chip->dev; 3977 3944 3978 3945 if (!external) { ··· 4186 4149 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4187 4150 .irl_init_all = mv88e6352_g2_irl_init_all, 4188 4151 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4189 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4190 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4152 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4153 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4154 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4155 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4191 4156 .port_set_link = mv88e6xxx_port_set_link, 4192 4157 .port_sync_link = mv88e6185_port_sync_link, 4193 4158 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, ··· 4237 4198 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4238 4199 .irl_init_all = mv88e6352_g2_irl_init_all, 4239 4200 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4240 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4241 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4201 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4202 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4203 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4204 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4242 4205 .port_set_link = mv88e6xxx_port_set_link, 4243 4206 .port_sync_link = mv88e6xxx_port_sync_link, 4244 4207 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, ··· 4320 4279 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4321 4280 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4322 4281 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4323 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4324 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4282 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4283 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4284 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4285 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4325 4286 .port_set_link = mv88e6xxx_port_set_link, 4326 4287 .port_sync_link = mv88e6xxx_port_sync_link, 4327 4288 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 4386 4343 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4387 4344 .irl_init_all = mv88e6352_g2_irl_init_all, 4388 4345 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4389 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4390 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4346 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4347 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4348 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4349 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4391 4350 .port_set_link = mv88e6xxx_port_set_link, 4392 4351 .port_sync_link = mv88e6xxx_port_sync_link, 4393 4352 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, ··· 4471 4426 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4472 4427 .irl_init_all = mv88e6352_g2_irl_init_all, 4473 4428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4474 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4475 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4429 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4430 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4431 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4432 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4476 4433 .port_set_link = mv88e6xxx_port_set_link, 4477 4434 .port_sync_link = mv88e6xxx_port_sync_link, 4478 4435 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 4519 4472 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4520 4473 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4521 4474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4522 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4523 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4475 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4476 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4477 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4478 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4524 4479 .port_set_link = mv88e6xxx_port_set_link, 4525 4480 .port_sync_link = mv88e6xxx_port_sync_link, 4526 4481 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 4576 4527 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4577 4528 .irl_init_all = mv88e6352_g2_irl_init_all, 4578 4529 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4579 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4580 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4530 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4531 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4532 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4533 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4581 4534 .port_set_link = mv88e6xxx_port_set_link, 4582 4535 .port_sync_link = mv88e6xxx_port_sync_link, 4583 4536 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 4624 4573 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4625 4574 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4626 4575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4627 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4628 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4576 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4577 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4578 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4579 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4629 4580 .port_set_link = mv88e6xxx_port_set_link, 4630 4581 .port_sync_link = mv88e6xxx_port_sync_link, 4631 4582 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 4726 4673 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4727 4674 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4728 4675 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4729 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4730 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4676 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4677 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4678 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4679 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4731 4680 .port_set_link = mv88e6xxx_port_set_link, 4732 4681 .port_sync_link = mv88e6xxx_port_sync_link, 4733 4682 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 4791 4736 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4792 4737 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4793 4738 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4794 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4795 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4739 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4740 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4741 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4742 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4796 4743 .port_set_link = mv88e6xxx_port_set_link, 4797 4744 .port_sync_link = mv88e6xxx_port_sync_link, 4798 4745 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 4856 4799 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4857 4800 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4858 4801 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4859 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4860 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4802 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4803 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4804 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4805 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4861 4806 .port_set_link = mv88e6xxx_port_set_link, 4862 4807 .port_sync_link = mv88e6xxx_port_sync_link, 4863 4808 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 4921 4862 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4922 4863 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4923 4864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4924 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4925 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4865 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4866 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4867 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4868 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4926 4869 .port_set_link = mv88e6xxx_port_set_link, 4927 4870 .port_sync_link = mv88e6xxx_port_sync_link, 4928 4871 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 4986 4925 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4987 4926 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4988 4927 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4989 - .phy_read = mv88e6xxx_g2_smi_phy_read, 4990 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4928 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4929 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4930 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4931 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4991 4932 .port_set_link = mv88e6xxx_port_set_link, 4992 4933 .port_sync_link = mv88e6xxx_port_sync_link, 4993 4934 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 5027 4964 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5028 4965 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5029 4966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5030 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5031 - .phy_write = mv88e6xxx_g2_smi_phy_write, 4967 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4968 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4969 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4970 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5032 4971 .port_set_link = mv88e6xxx_port_set_link, 5033 4972 .port_sync_link = mv88e6xxx_port_sync_link, 5034 4973 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 5094 5029 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5095 5030 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5096 5031 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5097 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5098 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5032 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5033 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5034 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5035 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5099 5036 .port_set_link = mv88e6xxx_port_set_link, 5100 5037 .port_sync_link = mv88e6xxx_port_sync_link, 5101 5038 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, ··· 5141 5074 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5142 5075 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5143 5076 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5144 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5145 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5077 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5078 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5079 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5080 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5146 5081 .port_set_link = mv88e6xxx_port_set_link, 5147 5082 .port_sync_link = mv88e6xxx_port_sync_link, 5148 5083 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, ··· 5186 5117 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5187 5118 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5188 5119 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5189 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5190 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5120 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5121 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5122 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5123 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5191 5124 .port_set_link = mv88e6xxx_port_set_link, 5192 5125 .port_sync_link = mv88e6xxx_port_sync_link, 5193 5126 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 5254 5183 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5255 5184 .irl_init_all = mv88e6352_g2_irl_init_all, 5256 5185 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5257 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5258 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5186 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5187 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5188 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5189 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5259 5190 .port_set_link = mv88e6xxx_port_set_link, 5260 5191 .port_sync_link = mv88e6xxx_port_sync_link, 5261 5192 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 5300 5227 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5301 5228 .irl_init_all = mv88e6352_g2_irl_init_all, 5302 5229 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5303 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5304 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5230 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5231 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5232 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5233 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5305 5234 .port_set_link = mv88e6xxx_port_set_link, 5306 5235 .port_sync_link = mv88e6xxx_port_sync_link, 5307 5236 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 5350 5275 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5351 5276 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5352 5277 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5353 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5354 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5278 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5279 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5280 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5281 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5355 5282 .port_set_link = mv88e6xxx_port_set_link, 5356 5283 .port_sync_link = mv88e6xxx_port_sync_link, 5357 5284 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, ··· 5417 5340 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5418 5341 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5419 5342 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5420 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5421 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5343 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5344 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5345 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5346 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5422 5347 .port_set_link = mv88e6xxx_port_set_link, 5423 5348 .port_sync_link = mv88e6xxx_port_sync_link, 5424 5349 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 5486 5407 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5487 5408 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5488 5409 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5489 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5490 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5410 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5411 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5412 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5413 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5491 5414 .port_set_link = mv88e6xxx_port_set_link, 5492 5415 .port_sync_link = mv88e6xxx_port_sync_link, 5493 5416 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, ··· 5554 5473 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5555 5474 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5556 5475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5557 - .phy_read = mv88e6xxx_g2_smi_phy_read, 5558 - .phy_write = mv88e6xxx_g2_smi_phy_write, 5476 + .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5477 + .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5478 + .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5479 + .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5559 5480 .port_set_link = mv88e6xxx_port_set_link, 5560 5481 .port_sync_link = mv88e6xxx_port_sync_link, 5561 5482 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,

+7

drivers/net/dsa/mv88e6xxx/chip.h

··· 454 454 struct mii_bus *bus, 455 455 int addr, int reg, u16 val); 456 456 457 + int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 458 + struct mii_bus *bus, 459 + int addr, int devad, int reg, u16 *val); 460 + int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 461 + struct mii_bus *bus, 462 + int addr, int devad, int reg, u16 val); 463 + 457 464 /* Priority Override Table operations */ 458 465 int (*pot_clear)(struct mv88e6xxx_chip *chip); 459 466

+39 -27

drivers/net/dsa/mv88e6xxx/global2.c

··· 739 739 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 740 740 } 741 741 742 - static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 743 - bool external, int port, int reg, 744 - u16 *data) 742 + static int _mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 743 + bool external, int port, int devad, 744 + int reg, u16 *data) 745 745 { 746 - int dev = (reg >> 16) & 0x1f; 747 - int addr = reg & 0xffff; 748 746 int err; 749 747 750 - err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, 751 - addr); 748 + err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad, 749 + reg); 752 750 if (err) 753 751 return err; 754 752 755 - return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev, 753 + return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, devad, 756 754 data); 757 755 } 758 756 ··· 769 771 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 770 772 } 771 773 772 - static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 773 - bool external, int port, int reg, 774 - u16 data) 774 + static int _mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 775 + bool external, int port, int devad, 776 + int reg, u16 data) 775 777 { 776 - int dev = (reg >> 16) & 0x1f; 777 - int addr = reg & 0xffff; 778 778 int err; 779 779 780 - err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, 781 - addr); 780 + err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad, 781 + reg); 782 782 if (err) 783 783 return err; 784 784 785 - return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev, 785 + return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, devad, 786 786 data); 787 787 } 788 788 789 - int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 790 - int addr, int reg, u16 *val) 789 + int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, 790 + struct mii_bus *bus, 791 + int addr, int reg, u16 *val) 791 792 { 792 793 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 793 794 bool external = mdio_bus->external; 794 - 795 - if (reg & MII_ADDR_C45) 796 - return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg, 797 - val); 798 795 799 796 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg, 800 797 val); 801 798 } 802 799 803 - int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 804 - int addr, int reg, u16 val) 800 + int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 801 + struct mii_bus *bus, int addr, int devad, 802 + int reg, u16 *val) 805 803 { 806 804 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 807 805 bool external = mdio_bus->external; 808 806 809 - if (reg & MII_ADDR_C45) 810 - return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg, 811 - val); 807 + return _mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, devad, reg, 808 + val); 809 + } 810 + 811 + int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, 812 + struct mii_bus *bus, int addr, int reg, 813 + u16 val) 814 + { 815 + struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 816 + bool external = mdio_bus->external; 812 817 813 818 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg, 814 819 val); 820 + } 821 + 822 + int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 823 + struct mii_bus *bus, int addr, int devad, 824 + int reg, u16 val) 825 + { 826 + struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 827 + bool external = mdio_bus->external; 828 + 829 + return _mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, devad, reg, 830 + val); 815 831 } 816 832 817 833 /* Offset 0x1B: Watchdog Control */

+12 -6

drivers/net/dsa/mv88e6xxx/global2.h

··· 314 314 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 315 315 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 316 316 317 - int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 318 - struct mii_bus *bus, 319 - int addr, int reg, u16 *val); 320 - int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 321 - struct mii_bus *bus, 322 - int addr, int reg, u16 val); 317 + int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, 318 + struct mii_bus *bus, 319 + int addr, int reg, u16 *val); 320 + int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, 321 + struct mii_bus *bus, 322 + int addr, int reg, u16 val); 323 + int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 324 + struct mii_bus *bus, 325 + int addr, int devad, int reg, u16 *val); 326 + int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 327 + struct mii_bus *bus, 328 + int addr, int devad, int reg, u16 val); 323 329 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 324 330 325 331 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,

+32

drivers/net/dsa/mv88e6xxx/phy.c

··· 55 55 return chip->info->ops->phy_write(chip, bus, addr, reg, val); 56 56 } 57 57 58 + int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad, 59 + int reg, u16 *val) 60 + { 61 + int addr = phy; /* PHY devices addresses start at 0x0 */ 62 + struct mii_bus *bus; 63 + 64 + bus = mv88e6xxx_default_mdio_bus(chip); 65 + if (!bus) 66 + return -EOPNOTSUPP; 67 + 68 + if (!chip->info->ops->phy_read_c45) 69 + return -EOPNOTSUPP; 70 + 71 + return chip->info->ops->phy_read_c45(chip, bus, addr, devad, reg, val); 72 + } 73 + 74 + int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad, 75 + int reg, u16 val) 76 + { 77 + int addr = phy; /* PHY devices addresses start at 0x0 */ 78 + struct mii_bus *bus; 79 + 80 + bus = mv88e6xxx_default_mdio_bus(chip); 81 + if (!bus) 82 + return -EOPNOTSUPP; 83 + 84 + if (!chip->info->ops->phy_write_c45) 85 + return -EOPNOTSUPP; 86 + 87 + return chip->info->ops->phy_write_c45(chip, bus, addr, devad, reg, val); 88 + } 89 + 58 90 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 59 91 { 60 92 return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page);

+4

drivers/net/dsa/mv88e6xxx/phy.h

··· 28 28 int reg, u16 *val); 29 29 int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 30 30 int reg, u16 val); 31 + int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad, 32 + int reg, u16 *val); 33 + int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad, 34 + int reg, u16 val); 31 35 int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 32 36 u8 page, int reg, u16 *val); 33 37 int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,

+2 -6

drivers/net/dsa/mv88e6xxx/serdes.c

··· 36 36 static int mv88e6390_serdes_read(struct mv88e6xxx_chip *chip, 37 37 int lane, int device, int reg, u16 *val) 38 38 { 39 - int reg_c45 = MII_ADDR_C45 | device << 16 | reg; 40 - 41 - return mv88e6xxx_phy_read(chip, lane, reg_c45, val); 39 + return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); 42 40 } 43 41 44 42 static int mv88e6390_serdes_write(struct mv88e6xxx_chip *chip, 45 43 int lane, int device, int reg, u16 val) 46 44 { 47 - int reg_c45 = MII_ADDR_C45 | device << 16 | reg; 48 - 49 - return mv88e6xxx_phy_write(chip, lane, reg_c45, val); 45 + return mv88e6xxx_phy_write_c45(chip, lane, device, reg, val); 50 46 } 51 47 52 48 static int mv88e6xxx_serdes_pcs_get_state(struct mv88e6xxx_chip *chip,

+109 -56

drivers/net/ethernet/freescale/fec_main.c

··· 1987 1987 return ret; 1988 1988 } 1989 1989 1990 - static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1990 + static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 1991 1991 { 1992 1992 struct fec_enet_private *fep = bus->priv; 1993 1993 struct device *dev = &fep->pdev->dev; 1994 1994 int ret = 0, frame_start, frame_addr, frame_op; 1995 - bool is_c45 = !!(regnum & MII_ADDR_C45); 1996 1995 1997 1996 ret = pm_runtime_resume_and_get(dev); 1998 1997 if (ret < 0) 1999 1998 return ret; 2000 1999 2001 - if (is_c45) { 2002 - frame_start = FEC_MMFR_ST_C45; 2003 - 2004 - /* write address */ 2005 - frame_addr = (regnum >> 16); 2006 - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2007 - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2008 - FEC_MMFR_TA | (regnum & 0xFFFF), 2009 - fep->hwp + FEC_MII_DATA); 2010 - 2011 - /* wait for end of transfer */ 2012 - ret = fec_enet_mdio_wait(fep); 2013 - if (ret) { 2014 - netdev_err(fep->netdev, "MDIO address write timeout\n"); 2015 - goto out; 2016 - } 2017 - 2018 - frame_op = FEC_MMFR_OP_READ_C45; 2019 - 2020 - } else { 2021 - /* C22 read */ 2022 - frame_op = FEC_MMFR_OP_READ; 2023 - frame_start = FEC_MMFR_ST; 2024 - frame_addr = regnum; 2025 - } 2000 + /* C22 read */ 2001 + frame_op = FEC_MMFR_OP_READ; 2002 + frame_start = FEC_MMFR_ST; 2003 + frame_addr = regnum; 2026 2004 2027 2005 /* start a read op */ 2028 2006 writel(frame_start | frame_op | 2029 - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2030 - FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2007 + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2008 + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2031 2009 2032 2010 /* wait for end of transfer */ 2033 2011 ret = fec_enet_mdio_wait(fep); ··· 2023 2045 return ret; 2024 2046 } 2025 2047 2026 - static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 2027 - u16 value) 2048 + static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2049 + int devad, int regnum) 2028 2050 { 2029 2051 struct fec_enet_private *fep = bus->priv; 2030 2052 struct device *dev = &fep->pdev->dev; 2031 - int ret, frame_start, frame_addr; 2032 - bool is_c45 = !!(regnum & MII_ADDR_C45); 2053 + int ret = 0, frame_start, frame_op; 2033 2054 2034 2055 ret = pm_runtime_resume_and_get(dev); 2035 2056 if (ret < 0) 2036 2057 return ret; 2037 2058 2038 - if (is_c45) { 2039 - frame_start = FEC_MMFR_ST_C45; 2059 + frame_start = FEC_MMFR_ST_C45; 2040 2060 2041 - /* write address */ 2042 - frame_addr = (regnum >> 16); 2043 - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2044 - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2045 - FEC_MMFR_TA | (regnum & 0xFFFF), 2046 - fep->hwp + FEC_MII_DATA); 2061 + /* write address */ 2062 + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2063 + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2064 + FEC_MMFR_TA | (regnum & 0xFFFF), 2065 + fep->hwp + FEC_MII_DATA); 2047 2066 2048 - /* wait for end of transfer */ 2049 - ret = fec_enet_mdio_wait(fep); 2050 - if (ret) { 2051 - netdev_err(fep->netdev, "MDIO address write timeout\n"); 2052 - goto out; 2053 - } 2054 - } else { 2055 - /* C22 write */ 2056 - frame_start = FEC_MMFR_ST; 2057 - frame_addr = regnum; 2067 + /* wait for end of transfer */ 2068 + ret = fec_enet_mdio_wait(fep); 2069 + if (ret) { 2070 + netdev_err(fep->netdev, "MDIO address write timeout\n"); 2071 + goto out; 2072 + } 2073 + 2074 + frame_op = FEC_MMFR_OP_READ_C45; 2075 + 2076 + /* start a read op */ 2077 + writel(frame_start | frame_op | 2078 + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2079 + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2080 + 2081 + /* wait for end of transfer */ 2082 + ret = fec_enet_mdio_wait(fep); 2083 + if (ret) { 2084 + netdev_err(fep->netdev, "MDIO read timeout\n"); 2085 + goto out; 2086 + } 2087 + 2088 + ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2089 + 2090 + out: 2091 + pm_runtime_mark_last_busy(dev); 2092 + pm_runtime_put_autosuspend(dev); 2093 + 2094 + return ret; 2095 + } 2096 + 2097 + static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2098 + u16 value) 2099 + { 2100 + struct fec_enet_private *fep = bus->priv; 2101 + struct device *dev = &fep->pdev->dev; 2102 + int ret, frame_start, frame_addr; 2103 + 2104 + ret = pm_runtime_resume_and_get(dev); 2105 + if (ret < 0) 2106 + return ret; 2107 + 2108 + /* C22 write */ 2109 + frame_start = FEC_MMFR_ST; 2110 + frame_addr = regnum; 2111 + 2112 + /* start a write op */ 2113 + writel(frame_start | FEC_MMFR_OP_WRITE | 2114 + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2115 + FEC_MMFR_TA | FEC_MMFR_DATA(value), 2116 + fep->hwp + FEC_MII_DATA); 2117 + 2118 + /* wait for end of transfer */ 2119 + ret = fec_enet_mdio_wait(fep); 2120 + if (ret) 2121 + netdev_err(fep->netdev, "MDIO write timeout\n"); 2122 + 2123 + pm_runtime_mark_last_busy(dev); 2124 + pm_runtime_put_autosuspend(dev); 2125 + 2126 + return ret; 2127 + } 2128 + 2129 + static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2130 + int devad, int regnum, u16 value) 2131 + { 2132 + struct fec_enet_private *fep = bus->priv; 2133 + struct device *dev = &fep->pdev->dev; 2134 + int ret, frame_start; 2135 + 2136 + ret = pm_runtime_resume_and_get(dev); 2137 + if (ret < 0) 2138 + return ret; 2139 + 2140 + frame_start = FEC_MMFR_ST_C45; 2141 + 2142 + /* write address */ 2143 + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2144 + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2145 + FEC_MMFR_TA | (regnum & 0xFFFF), 2146 + fep->hwp + FEC_MII_DATA); 2147 + 2148 + /* wait for end of transfer */ 2149 + ret = fec_enet_mdio_wait(fep); 2150 + if (ret) { 2151 + netdev_err(fep->netdev, "MDIO address write timeout\n"); 2152 + goto out; 2058 2153 } 2059 2154 2060 2155 /* start a write op */ 2061 2156 writel(frame_start | FEC_MMFR_OP_WRITE | 2062 - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2063 - FEC_MMFR_TA | FEC_MMFR_DATA(value), 2064 - fep->hwp + FEC_MII_DATA); 2157 + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2158 + FEC_MMFR_TA | FEC_MMFR_DATA(value), 2159 + fep->hwp + FEC_MII_DATA); 2065 2160 2066 2161 /* wait for end of transfer */ 2067 2162 ret = fec_enet_mdio_wait(fep); ··· 2432 2381 } 2433 2382 2434 2383 fep->mii_bus->name = "fec_enet_mii_bus"; 2435 - fep->mii_bus->read = fec_enet_mdio_read; 2436 - fep->mii_bus->write = fec_enet_mdio_write; 2384 + fep->mii_bus->read = fec_enet_mdio_read_c22; 2385 + fep->mii_bus->write = fec_enet_mdio_write_c22; 2386 + fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2387 + fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2437 2388 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2438 2389 pdev->name, fep->dev_id + 1); 2439 2390 fep->mii_bus->priv = fep;

+109 -41

drivers/net/ethernet/freescale/xgmac_mdio.c

··· 128 128 return 0; 129 129 } 130 130 131 - /* 132 - * Write value to the PHY for this device to the register at regnum,waiting 133 - * until the write is done before it returns. All PHY configuration has to be 134 - * done through the TSEC1 MIIM regs. 135 - */ 136 - static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value) 131 + static int xgmac_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, 132 + u16 value) 137 133 { 138 134 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv; 139 135 struct tgec_mdio_controller __iomem *regs = priv->mdio_base; 140 - uint16_t dev_addr; 136 + bool endian = priv->is_little_endian; 137 + u16 dev_addr = regnum & 0x1f; 141 138 u32 mdio_ctl, mdio_stat; 142 139 int ret; 143 - bool endian = priv->is_little_endian; 144 140 145 141 mdio_stat = xgmac_read32(&regs->mdio_stat, endian); 146 - if (regnum & MII_ADDR_C45) { 147 - /* Clause 45 (ie 10G) */ 148 - dev_addr = (regnum >> 16) & 0x1f; 149 - mdio_stat |= MDIO_STAT_ENC; 150 - } else { 151 - /* Clause 22 (ie 1G) */ 152 - dev_addr = regnum & 0x1f; 153 - mdio_stat &= ~MDIO_STAT_ENC; 154 - } 142 + mdio_stat &= ~MDIO_STAT_ENC; 143 + xgmac_write32(mdio_stat, &regs->mdio_stat, endian); 144 + 145 + ret = xgmac_wait_until_free(&bus->dev, regs, endian); 146 + if (ret) 147 + return ret; 148 + 149 + /* Set the port and dev addr */ 150 + mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); 151 + xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian); 152 + 153 + /* Write the value to the register */ 154 + xgmac_write32(MDIO_DATA(value), &regs->mdio_data, endian); 155 + 156 + ret = xgmac_wait_until_done(&bus->dev, regs, endian); 157 + if (ret) 158 + return ret; 159 + 160 + return 0; 161 + } 162 + 163 + static int xgmac_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, 164 + int regnum, u16 value) 165 + { 166 + struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv; 167 + struct tgec_mdio_controller __iomem *regs = priv->mdio_base; 168 + bool endian = priv->is_little_endian; 169 + u32 mdio_ctl, mdio_stat; 170 + int ret; 171 + 172 + mdio_stat = xgmac_read32(&regs->mdio_stat, endian); 173 + mdio_stat |= MDIO_STAT_ENC; 155 174 156 175 xgmac_write32(mdio_stat, &regs->mdio_stat, endian); 157 176 ··· 183 164 xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian); 184 165 185 166 /* Set the register address */ 186 - if (regnum & MII_ADDR_C45) { 187 - xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian); 167 + xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian); 188 168 189 - ret = xgmac_wait_until_free(&bus->dev, regs, endian); 190 - if (ret) 191 - return ret; 192 - } 169 + ret = xgmac_wait_until_free(&bus->dev, regs, endian); 170 + if (ret) 171 + return ret; 193 172 194 173 /* Write the value to the register */ 195 174 xgmac_write32(MDIO_DATA(value), &regs->mdio_data, endian); ··· 199 182 return 0; 200 183 } 201 184 202 - /* 203 - * Reads from register regnum in the PHY for device dev, returning the value. 185 + /* Reads from register regnum in the PHY for device dev, returning the value. 204 186 * Clears miimcom first. All PHY configuration has to be done through the 205 187 * TSEC1 MIIM regs. 206 188 */ 207 - static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum) 189 + static int xgmac_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) 208 190 { 209 191 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv; 210 192 struct tgec_mdio_controller __iomem *regs = priv->mdio_base; 193 + bool endian = priv->is_little_endian; 194 + u16 dev_addr = regnum & 0x1f; 211 195 unsigned long flags; 212 - uint16_t dev_addr; 213 196 uint32_t mdio_stat; 214 197 uint32_t mdio_ctl; 215 198 int ret; 216 - bool endian = priv->is_little_endian; 217 199 218 200 mdio_stat = xgmac_read32(&regs->mdio_stat, endian); 219 - if (regnum & MII_ADDR_C45) { 220 - dev_addr = (regnum >> 16) & 0x1f; 221 - mdio_stat |= MDIO_STAT_ENC; 201 + mdio_stat &= ~MDIO_STAT_ENC; 202 + xgmac_write32(mdio_stat, &regs->mdio_stat, endian); 203 + 204 + ret = xgmac_wait_until_free(&bus->dev, regs, endian); 205 + if (ret) 206 + return ret; 207 + 208 + /* Set the Port and Device Addrs */ 209 + mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); 210 + xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian); 211 + 212 + if (priv->has_a009885) 213 + /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we 214 + * must read back the data register within 16 MDC cycles. 215 + */ 216 + local_irq_save(flags); 217 + 218 + /* Initiate the read */ 219 + xgmac_write32(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl, endian); 220 + 221 + ret = xgmac_wait_until_done(&bus->dev, regs, endian); 222 + if (ret) 223 + goto irq_restore; 224 + 225 + /* Return all Fs if nothing was there */ 226 + if ((xgmac_read32(&regs->mdio_stat, endian) & MDIO_STAT_RD_ER) && 227 + !priv->has_a011043) { 228 + dev_dbg(&bus->dev, 229 + "Error while reading PHY%d reg at %d.%d\n", 230 + phy_id, dev_addr, regnum); 231 + ret = 0xffff; 222 232 } else { 223 - dev_addr = regnum & 0x1f; 224 - mdio_stat &= ~MDIO_STAT_ENC; 233 + ret = xgmac_read32(&regs->mdio_data, endian) & 0xffff; 234 + dev_dbg(&bus->dev, "read %04x\n", ret); 225 235 } 236 + 237 + irq_restore: 238 + if (priv->has_a009885) 239 + local_irq_restore(flags); 240 + 241 + return ret; 242 + } 243 + 244 + /* Reads from register regnum in the PHY for device dev, returning the value. 245 + * Clears miimcom first. All PHY configuration has to be done through the 246 + * TSEC1 MIIM regs. 247 + */ 248 + static int xgmac_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, 249 + int regnum) 250 + { 251 + struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv; 252 + struct tgec_mdio_controller __iomem *regs = priv->mdio_base; 253 + bool endian = priv->is_little_endian; 254 + u32 mdio_stat, mdio_ctl; 255 + unsigned long flags; 256 + int ret; 257 + 258 + mdio_stat = xgmac_read32(&regs->mdio_stat, endian); 259 + mdio_stat |= MDIO_STAT_ENC; 226 260 227 261 xgmac_write32(mdio_stat, &regs->mdio_stat, endian); 228 262 ··· 286 218 xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian); 287 219 288 220 /* Set the register address */ 289 - if (regnum & MII_ADDR_C45) { 290 - xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian); 221 + xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian); 291 222 292 - ret = xgmac_wait_until_free(&bus->dev, regs, endian); 293 - if (ret) 294 - return ret; 295 - } 223 + ret = xgmac_wait_until_free(&bus->dev, regs, endian); 224 + if (ret) 225 + return ret; 296 226 297 227 if (priv->has_a009885) 298 228 /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we ··· 392 326 return -ENOMEM; 393 327 394 328 bus->name = "Freescale XGMAC MDIO Bus"; 395 - bus->read = xgmac_mdio_read; 396 - bus->write = xgmac_mdio_write; 329 + bus->read = xgmac_mdio_read_c22; 330 + bus->write = xgmac_mdio_write_c22; 331 + bus->read_c45 = xgmac_mdio_read_c45; 332 + bus->write_c45 = xgmac_mdio_write_c45; 397 333 bus->parent = &pdev->dev; 398 334 bus->probe_capabilities = MDIOBUS_C22_C45; 399 335 snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);

+8 -16

drivers/net/ethernet/marvell/mvmdio.c

··· 204 204 .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX, 205 205 }; 206 206 207 - static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id, 208 - int regnum) 207 + static int orion_mdio_xsmi_read_c45(struct mii_bus *bus, int mii_id, 208 + int dev_addr, int regnum) 209 209 { 210 210 struct orion_mdio_dev *dev = bus->priv; 211 - u16 dev_addr = (regnum >> 16) & GENMASK(4, 0); 212 211 int ret; 213 - 214 - if (!(regnum & MII_ADDR_C45)) 215 - return -EOPNOTSUPP; 216 212 217 213 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); 218 214 if (ret < 0) 219 215 return ret; 220 216 221 - writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG); 217 + writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG); 222 218 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) | 223 219 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) | 224 220 MVMDIO_XSMI_READ_OPERATION, ··· 233 237 return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0); 234 238 } 235 239 236 - static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id, 237 - int regnum, u16 value) 240 + static int orion_mdio_xsmi_write_c45(struct mii_bus *bus, int mii_id, 241 + int dev_addr, int regnum, u16 value) 238 242 { 239 243 struct orion_mdio_dev *dev = bus->priv; 240 - u16 dev_addr = (regnum >> 16) & GENMASK(4, 0); 241 244 int ret; 242 - 243 - if (!(regnum & MII_ADDR_C45)) 244 - return -EOPNOTSUPP; 245 245 246 246 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); 247 247 if (ret < 0) 248 248 return ret; 249 249 250 - writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG); 250 + writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG); 251 251 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) | 252 252 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) | 253 253 MVMDIO_XSMI_WRITE_OPERATION | value, ··· 294 302 bus->write = orion_mdio_smi_write; 295 303 break; 296 304 case BUS_TYPE_XSMI: 297 - bus->read = orion_mdio_xsmi_read; 298 - bus->write = orion_mdio_xsmi_write; 305 + bus->read_c45 = orion_mdio_xsmi_read_c45; 306 + bus->write_c45 = orion_mdio_xsmi_write_c45; 299 307 break; 300 308 } 301 309

+31 -6

drivers/net/ethernet/renesas/sh_eth.c

··· 3044 3044 return 0; 3045 3045 } 3046 3046 3047 - static int sh_mdiobb_read(struct mii_bus *bus, int phy, int reg) 3047 + static int sh_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) 3048 3048 { 3049 3049 int res; 3050 3050 3051 3051 pm_runtime_get_sync(bus->parent); 3052 - res = mdiobb_read(bus, phy, reg); 3052 + res = mdiobb_read_c22(bus, phy, reg); 3053 3053 pm_runtime_put(bus->parent); 3054 3054 3055 3055 return res; 3056 3056 } 3057 3057 3058 - static int sh_mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) 3058 + static int sh_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val) 3059 3059 { 3060 3060 int res; 3061 3061 3062 3062 pm_runtime_get_sync(bus->parent); 3063 - res = mdiobb_write(bus, phy, reg, val); 3063 + res = mdiobb_write_c22(bus, phy, reg, val); 3064 + pm_runtime_put(bus->parent); 3065 + 3066 + return res; 3067 + } 3068 + 3069 + static int sh_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg) 3070 + { 3071 + int res; 3072 + 3073 + pm_runtime_get_sync(bus->parent); 3074 + res = mdiobb_read_c45(bus, phy, devad, reg); 3075 + pm_runtime_put(bus->parent); 3076 + 3077 + return res; 3078 + } 3079 + 3080 + static int sh_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, 3081 + int reg, u16 val) 3082 + { 3083 + int res; 3084 + 3085 + pm_runtime_get_sync(bus->parent); 3086 + res = mdiobb_write_c45(bus, phy, devad, reg, val); 3064 3087 pm_runtime_put(bus->parent); 3065 3088 3066 3089 return res; ··· 3114 3091 return -ENOMEM; 3115 3092 3116 3093 /* Wrap accessors with Runtime PM-aware ops */ 3117 - mdp->mii_bus->read = sh_mdiobb_read; 3118 - mdp->mii_bus->write = sh_mdiobb_write; 3094 + mdp->mii_bus->read = sh_mdiobb_read_c22; 3095 + mdp->mii_bus->write = sh_mdiobb_write_c22; 3096 + mdp->mii_bus->read_c45 = sh_mdiobb_read_c45; 3097 + mdp->mii_bus->write_c45 = sh_mdiobb_write_c45; 3119 3098 3120 3099 /* Hook up MII support for ethtool */ 3121 3100 mdp->mii_bus->name = "sh_mii";

+43 -7

drivers/net/ethernet/ti/davinci_mdio.c

··· 225 225 return test_bit(MDIO_PIN, &reg); 226 226 } 227 227 228 - static int davinci_mdiobb_read(struct mii_bus *bus, int phy, int reg) 228 + static int davinci_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) 229 229 { 230 230 int ret; 231 231 ··· 233 233 if (ret < 0) 234 234 return ret; 235 235 236 - ret = mdiobb_read(bus, phy, reg); 236 + ret = mdiobb_read_c22(bus, phy, reg); 237 237 238 238 pm_runtime_mark_last_busy(bus->parent); 239 239 pm_runtime_put_autosuspend(bus->parent); ··· 241 241 return ret; 242 242 } 243 243 244 - static int davinci_mdiobb_write(struct mii_bus *bus, int phy, int reg, 245 - u16 val) 244 + static int davinci_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, 245 + u16 val) 246 246 { 247 247 int ret; 248 248 ··· 250 250 if (ret < 0) 251 251 return ret; 252 252 253 - ret = mdiobb_write(bus, phy, reg, val); 253 + ret = mdiobb_write_c22(bus, phy, reg, val); 254 + 255 + pm_runtime_mark_last_busy(bus->parent); 256 + pm_runtime_put_autosuspend(bus->parent); 257 + 258 + return ret; 259 + } 260 + 261 + static int davinci_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, 262 + int reg) 263 + { 264 + int ret; 265 + 266 + ret = pm_runtime_resume_and_get(bus->parent); 267 + if (ret < 0) 268 + return ret; 269 + 270 + ret = mdiobb_read_c45(bus, phy, devad, reg); 271 + 272 + pm_runtime_mark_last_busy(bus->parent); 273 + pm_runtime_put_autosuspend(bus->parent); 274 + 275 + return ret; 276 + } 277 + 278 + static int davinci_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, 279 + int reg, u16 val) 280 + { 281 + int ret; 282 + 283 + ret = pm_runtime_resume_and_get(bus->parent); 284 + if (ret < 0) 285 + return ret; 286 + 287 + ret = mdiobb_write_c45(bus, phy, devad, reg, val); 254 288 255 289 pm_runtime_mark_last_busy(bus->parent); 256 290 pm_runtime_put_autosuspend(bus->parent); ··· 607 573 data->bus->name = dev_name(dev); 608 574 609 575 if (data->manual_mode) { 610 - data->bus->read = davinci_mdiobb_read; 611 - data->bus->write = davinci_mdiobb_write; 576 + data->bus->read = davinci_mdiobb_read_c22; 577 + data->bus->write = davinci_mdiobb_write_c22; 578 + data->bus->read_c45 = davinci_mdiobb_read_c45; 579 + data->bus->write_c45 = davinci_mdiobb_write_c45; 612 580 data->bus->reset = davinci_mdiobb_reset; 613 581 614 582 dev_info(dev, "Configuring MDIO in manual mode\n");

+52 -25

drivers/net/mdio/mdio-bitbang.c

··· 127 127 128 128 /* In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the 129 129 lower 16 bits of the 21 bit address. This transfer is done identically to a 130 - MDIO_WRITE except for a different code. To enable clause 45 mode or 131 - MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices 132 - can exist on the same bus. Normal devices should ignore the MDIO_ADDR 130 + MDIO_WRITE except for a different code. Theoretically clause 45 and normal 131 + devices can exist on the same bus. Normal devices should ignore the MDIO_ADDR 133 132 phase. */ 134 - static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) 133 + static void mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, int dev_addr, 134 + int reg) 135 135 { 136 - unsigned int dev_addr = (addr >> 16) & 0x1F; 137 - unsigned int reg = addr & 0xFFFF; 138 136 mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr); 139 137 140 138 /* send the turnaround (10) */ ··· 143 145 144 146 ctrl->ops->set_mdio_dir(ctrl, 0); 145 147 mdiobb_get_bit(ctrl); 146 - 147 - return dev_addr; 148 148 } 149 149 150 - int mdiobb_read(struct mii_bus *bus, int phy, int reg) 150 + static int mdiobb_read_common(struct mii_bus *bus, int phy) 151 151 { 152 152 struct mdiobb_ctrl *ctrl = bus->priv; 153 153 int ret, i; 154 - 155 - if (reg & MII_ADDR_C45) { 156 - reg = mdiobb_cmd_addr(ctrl, phy, reg); 157 - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); 158 - } else 159 - mdiobb_cmd(ctrl, ctrl->op_c22_read, phy, reg); 160 154 161 155 ctrl->ops->set_mdio_dir(ctrl, 0); 162 156 ··· 170 180 mdiobb_get_bit(ctrl); 171 181 return ret; 172 182 } 173 - EXPORT_SYMBOL(mdiobb_read); 174 183 175 - int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) 184 + int mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) 176 185 { 177 186 struct mdiobb_ctrl *ctrl = bus->priv; 178 187 179 - if (reg & MII_ADDR_C45) { 180 - reg = mdiobb_cmd_addr(ctrl, phy, reg); 181 - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); 182 - } else 183 - mdiobb_cmd(ctrl, ctrl->op_c22_write, phy, reg); 188 + mdiobb_cmd(ctrl, ctrl->op_c22_read, phy, reg); 189 + 190 + return mdiobb_read_common(bus, phy); 191 + } 192 + EXPORT_SYMBOL(mdiobb_read_c22); 193 + 194 + int mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg) 195 + { 196 + struct mdiobb_ctrl *ctrl = bus->priv; 197 + 198 + mdiobb_cmd_addr(ctrl, phy, devad, reg); 199 + mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); 200 + 201 + return mdiobb_read_common(bus, phy); 202 + } 203 + EXPORT_SYMBOL(mdiobb_read_c45); 204 + 205 + static int mdiobb_write_common(struct mii_bus *bus, u16 val) 206 + { 207 + struct mdiobb_ctrl *ctrl = bus->priv; 184 208 185 209 /* send the turnaround (10) */ 186 210 mdiobb_send_bit(ctrl, 1); ··· 206 202 mdiobb_get_bit(ctrl); 207 203 return 0; 208 204 } 209 - EXPORT_SYMBOL(mdiobb_write); 205 + 206 + int mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val) 207 + { 208 + struct mdiobb_ctrl *ctrl = bus->priv; 209 + 210 + mdiobb_cmd(ctrl, ctrl->op_c22_write, phy, reg); 211 + 212 + return mdiobb_write_common(bus, val); 213 + } 214 + EXPORT_SYMBOL(mdiobb_write_c22); 215 + 216 + int mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, int reg, u16 val) 217 + { 218 + struct mdiobb_ctrl *ctrl = bus->priv; 219 + 220 + mdiobb_cmd_addr(ctrl, phy, devad, reg); 221 + mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); 222 + 223 + return mdiobb_write_common(bus, val); 224 + } 225 + EXPORT_SYMBOL(mdiobb_write_c45); 210 226 211 227 struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl) 212 228 { ··· 238 214 239 215 __module_get(ctrl->ops->owner); 240 216 241 - bus->read = mdiobb_read; 242 - bus->write = mdiobb_write; 217 + bus->read = mdiobb_read_c22; 218 + bus->write = mdiobb_write_c22; 219 + bus->read_c45 = mdiobb_read_c45; 220 + bus->write_c45 = mdiobb_write_c45; 221 + 243 222 bus->priv = ctrl; 244 223 if (!ctrl->override_op_c22) { 245 224 ctrl->op_c22_read = MDIO_READ;

+1 -3

drivers/net/pcs/pcs-xpcs.c

··· 199 199 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 200 200 u16 mask, u16 set) 201 201 { 202 - u32 reg_addr = mdiobus_c45_addr(dev, reg); 203 - 204 - return mdiodev_modify_changed(xpcs->mdiodev, reg_addr, mask, set); 202 + return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 205 203 } 206 204 207 205 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)

+266 -4

drivers/net/phy/mdio_bus.c

··· 526 526 int i, err; 527 527 struct gpio_desc *gpiod; 528 528 529 - if (NULL == bus || NULL == bus->name || 530 - NULL == bus->read || NULL == bus->write) 529 + if (!bus || !bus->name) 530 + return -EINVAL; 531 + 532 + /* An access method always needs both read and write operations */ 533 + if (!!bus->read != !!bus->write || !!bus->read_c45 != !!bus->write_c45) 534 + return -EINVAL; 535 + 536 + /* At least one method is mandatory */ 537 + if (!bus->read && !bus->read_c45) 531 538 return -EINVAL; 532 539 533 540 if (bus->parent && bus->parent->of_node) ··· 766 759 767 760 lockdep_assert_held_once(&bus->mdio_lock); 768 761 769 - retval = bus->read(bus, addr, regnum); 762 + if (bus->read) 763 + retval = bus->read(bus, addr, regnum); 764 + else 765 + retval = -EOPNOTSUPP; 770 766 771 767 trace_mdio_access(bus, 1, addr, regnum, retval, retval); 772 768 mdiobus_stats_acct(&bus->stats[addr], true, retval); ··· 795 785 796 786 lockdep_assert_held_once(&bus->mdio_lock); 797 787 798 - err = bus->write(bus, addr, regnum, val); 788 + if (bus->write) 789 + err = bus->write(bus, addr, regnum, val); 790 + else 791 + err = -EOPNOTSUPP; 799 792 800 793 trace_mdio_access(bus, 0, addr, regnum, val, err); 801 794 mdiobus_stats_acct(&bus->stats[addr], false, err); ··· 838 825 return ret < 0 ? ret : 1; 839 826 } 840 827 EXPORT_SYMBOL_GPL(__mdiobus_modify_changed); 828 + 829 + static u32 mdiobus_c45_addr(int devad, u16 regnum) 830 + { 831 + return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; 832 + } 833 + 834 + /** 835 + * __mdiobus_c45_read - Unlocked version of the mdiobus_c45_read function 836 + * @bus: the mii_bus struct 837 + * @addr: the phy address 838 + * @devad: device address to read 839 + * @regnum: register number to read 840 + * 841 + * Read a MDIO bus register. Caller must hold the mdio bus lock. 842 + * 843 + * NOTE: MUST NOT be called from interrupt context. 844 + */ 845 + int __mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum) 846 + { 847 + int retval; 848 + 849 + lockdep_assert_held_once(&bus->mdio_lock); 850 + 851 + if (bus->read_c45) 852 + retval = bus->read_c45(bus, addr, devad, regnum); 853 + else 854 + retval = bus->read(bus, addr, mdiobus_c45_addr(devad, regnum)); 855 + 856 + trace_mdio_access(bus, 1, addr, regnum, retval, retval); 857 + mdiobus_stats_acct(&bus->stats[addr], true, retval); 858 + 859 + return retval; 860 + } 861 + EXPORT_SYMBOL(__mdiobus_c45_read); 862 + 863 + /** 864 + * __mdiobus_c45_write - Unlocked version of the mdiobus_write function 865 + * @bus: the mii_bus struct 866 + * @addr: the phy address 867 + * @devad: device address to read 868 + * @regnum: register number to write 869 + * @val: value to write to @regnum 870 + * 871 + * Write a MDIO bus register. Caller must hold the mdio bus lock. 872 + * 873 + * NOTE: MUST NOT be called from interrupt context. 874 + */ 875 + int __mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnum, 876 + u16 val) 877 + { 878 + int err; 879 + 880 + lockdep_assert_held_once(&bus->mdio_lock); 881 + 882 + if (bus->write_c45) 883 + err = bus->write_c45(bus, addr, devad, regnum, val); 884 + else 885 + err = bus->write(bus, addr, mdiobus_c45_addr(devad, regnum), 886 + val); 887 + 888 + trace_mdio_access(bus, 0, addr, regnum, val, err); 889 + mdiobus_stats_acct(&bus->stats[addr], false, err); 890 + 891 + return err; 892 + } 893 + EXPORT_SYMBOL(__mdiobus_c45_write); 894 + 895 + /** 896 + * __mdiobus_c45_modify_changed - Unlocked version of the mdiobus_modify function 897 + * @bus: the mii_bus struct 898 + * @addr: the phy address 899 + * @devad: device address to read 900 + * @regnum: register number to modify 901 + * @mask: bit mask of bits to clear 902 + * @set: bit mask of bits to set 903 + * 904 + * Read, modify, and if any change, write the register value back to the 905 + * device. Any error returns a negative number. 906 + * 907 + * NOTE: MUST NOT be called from interrupt context. 908 + */ 909 + static int __mdiobus_c45_modify_changed(struct mii_bus *bus, int addr, 910 + int devad, u32 regnum, u16 mask, 911 + u16 set) 912 + { 913 + int new, ret; 914 + 915 + ret = __mdiobus_c45_read(bus, addr, devad, regnum); 916 + if (ret < 0) 917 + return ret; 918 + 919 + new = (ret & ~mask) | set; 920 + if (new == ret) 921 + return 0; 922 + 923 + ret = __mdiobus_c45_write(bus, addr, devad, regnum, new); 924 + 925 + return ret < 0 ? ret : 1; 926 + } 841 927 842 928 /** 843 929 * mdiobus_read_nested - Nested version of the mdiobus_read function ··· 984 872 return retval; 985 873 } 986 874 EXPORT_SYMBOL(mdiobus_read); 875 + 876 + /** 877 + * mdiobus_c45_read - Convenience function for reading a given MII mgmt register 878 + * @bus: the mii_bus struct 879 + * @addr: the phy address 880 + * @devad: device address to read 881 + * @regnum: register number to read 882 + * 883 + * NOTE: MUST NOT be called from interrupt context, 884 + * because the bus read/write functions may wait for an interrupt 885 + * to conclude the operation. 886 + */ 887 + int mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum) 888 + { 889 + int retval; 890 + 891 + mutex_lock(&bus->mdio_lock); 892 + retval = __mdiobus_c45_read(bus, addr, devad, regnum); 893 + mutex_unlock(&bus->mdio_lock); 894 + 895 + return retval; 896 + } 897 + EXPORT_SYMBOL(mdiobus_c45_read); 898 + 899 + /** 900 + * mdiobus_c45_read_nested - Nested version of the mdiobus_c45_read function 901 + * @bus: the mii_bus struct 902 + * @addr: the phy address 903 + * @devad: device address to read 904 + * @regnum: register number to read 905 + * 906 + * In case of nested MDIO bus access avoid lockdep false positives by 907 + * using mutex_lock_nested(). 908 + * 909 + * NOTE: MUST NOT be called from interrupt context, 910 + * because the bus read/write functions may wait for an interrupt 911 + * to conclude the operation. 912 + */ 913 + int mdiobus_c45_read_nested(struct mii_bus *bus, int addr, int devad, 914 + u32 regnum) 915 + { 916 + int retval; 917 + 918 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 919 + retval = __mdiobus_c45_read(bus, addr, devad, regnum); 920 + mutex_unlock(&bus->mdio_lock); 921 + 922 + return retval; 923 + } 924 + EXPORT_SYMBOL(mdiobus_c45_read_nested); 987 925 988 926 /** 989 927 * mdiobus_write_nested - Nested version of the mdiobus_write function ··· 1085 923 EXPORT_SYMBOL(mdiobus_write); 1086 924 1087 925 /** 926 + * mdiobus_c45_write - Convenience function for writing a given MII mgmt register 927 + * @bus: the mii_bus struct 928 + * @addr: the phy address 929 + * @devad: device address to read 930 + * @regnum: register number to write 931 + * @val: value to write to @regnum 932 + * 933 + * NOTE: MUST NOT be called from interrupt context, 934 + * because the bus read/write functions may wait for an interrupt 935 + * to conclude the operation. 936 + */ 937 + int mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnum, 938 + u16 val) 939 + { 940 + int err; 941 + 942 + mutex_lock(&bus->mdio_lock); 943 + err = __mdiobus_c45_write(bus, addr, devad, regnum, val); 944 + mutex_unlock(&bus->mdio_lock); 945 + 946 + return err; 947 + } 948 + EXPORT_SYMBOL(mdiobus_c45_write); 949 + 950 + /** 951 + * mdiobus_c45_write_nested - Nested version of the mdiobus_c45_write function 952 + * @bus: the mii_bus struct 953 + * @addr: the phy address 954 + * @devad: device address to read 955 + * @regnum: register number to write 956 + * @val: value to write to @regnum 957 + * 958 + * In case of nested MDIO bus access avoid lockdep false positives by 959 + * using mutex_lock_nested(). 960 + * 961 + * NOTE: MUST NOT be called from interrupt context, 962 + * because the bus read/write functions may wait for an interrupt 963 + * to conclude the operation. 964 + */ 965 + int mdiobus_c45_write_nested(struct mii_bus *bus, int addr, int devad, 966 + u32 regnum, u16 val) 967 + { 968 + int err; 969 + 970 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 971 + err = __mdiobus_c45_write(bus, addr, devad, regnum, val); 972 + mutex_unlock(&bus->mdio_lock); 973 + 974 + return err; 975 + } 976 + EXPORT_SYMBOL(mdiobus_c45_write_nested); 977 + 978 + /** 1088 979 * mdiobus_modify - Convenience function for modifying a given mdio device 1089 980 * register 1090 981 * @bus: the mii_bus struct ··· 1157 942 return err < 0 ? err : 0; 1158 943 } 1159 944 EXPORT_SYMBOL_GPL(mdiobus_modify); 945 + 946 + /** 947 + * mdiobus_c45_modify - Convenience function for modifying a given mdio device 948 + * register 949 + * @bus: the mii_bus struct 950 + * @addr: the phy address 951 + * @devad: device address to read 952 + * @regnum: register number to write 953 + * @mask: bit mask of bits to clear 954 + * @set: bit mask of bits to set 955 + */ 956 + int mdiobus_c45_modify(struct mii_bus *bus, int addr, int devad, u32 regnum, 957 + u16 mask, u16 set) 958 + { 959 + int err; 960 + 961 + mutex_lock(&bus->mdio_lock); 962 + err = __mdiobus_c45_modify_changed(bus, addr, devad, regnum, 963 + mask, set); 964 + mutex_unlock(&bus->mdio_lock); 965 + 966 + return err < 0 ? err : 0; 967 + } 968 + EXPORT_SYMBOL_GPL(mdiobus_c45_modify); 1160 969 1161 970 /** 1162 971 * mdiobus_modify_changed - Convenience function for modifying a given mdio ··· 1203 964 return err; 1204 965 } 1205 966 EXPORT_SYMBOL_GPL(mdiobus_modify_changed); 967 + 968 + /** 969 + * mdiobus_c45_modify_changed - Convenience function for modifying a given mdio 970 + * device register and returning if it changed 971 + * @bus: the mii_bus struct 972 + * @addr: the phy address 973 + * @devad: device address to read 974 + * @regnum: register number to write 975 + * @mask: bit mask of bits to clear 976 + * @set: bit mask of bits to set 977 + */ 978 + int mdiobus_c45_modify_changed(struct mii_bus *bus, int devad, int addr, 979 + u32 regnum, u16 mask, u16 set) 980 + { 981 + int err; 982 + 983 + mutex_lock(&bus->mdio_lock); 984 + err = __mdiobus_c45_modify_changed(bus, addr, devad, regnum, mask, set); 985 + mutex_unlock(&bus->mdio_lock); 986 + 987 + return err; 988 + } 989 + EXPORT_SYMBOL_GPL(mdiobus_c45_modify_changed); 1206 990 1207 991 /** 1208 992 * mdio_bus_match - determine if given MDIO driver supports the given

+4 -2

include/linux/mdio-bitbang.h

··· 38 38 u8 op_c22_write; 39 39 }; 40 40 41 - int mdiobb_read(struct mii_bus *bus, int phy, int reg); 42 - int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val); 41 + int mdiobb_read_c22(struct mii_bus *bus, int phy, int reg); 42 + int mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val); 43 + int mdiobb_read_c45(struct mii_bus *bus, int devad, int phy, int reg); 44 + int mdiobb_write_c45(struct mii_bus *bus, int devad, int phy, int reg, u16 val); 43 45 44 46 /* The returned bus is not yet registered with the phy layer. */ 45 47 struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl);

+24 -24

include/linux/mdio.h

··· 423 423 u16 set); 424 424 int mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum, 425 425 u16 mask, u16 set); 426 + int __mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum); 427 + int mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum); 428 + int mdiobus_c45_read_nested(struct mii_bus *bus, int addr, int devad, 429 + u32 regnum); 430 + int __mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnum, 431 + u16 val); 432 + int mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnum, 433 + u16 val); 434 + int mdiobus_c45_write_nested(struct mii_bus *bus, int addr, int devad, 435 + u32 regnum, u16 val); 436 + int mdiobus_c45_modify(struct mii_bus *bus, int addr, int devad, u32 regnum, 437 + u16 mask, u16 set); 438 + 439 + int mdiobus_c45_modify_changed(struct mii_bus *bus, int addr, int devad, 440 + u32 regnum, u16 mask, u16 set); 426 441 427 442 static inline int mdiodev_read(struct mdio_device *mdiodev, u32 regnum) 428 443 { ··· 463 448 mask, set); 464 449 } 465 450 466 - static inline u32 mdiobus_c45_addr(int devad, u16 regnum) 467 - { 468 - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; 469 - } 470 - 471 451 static inline u16 mdiobus_c45_regad(u32 regnum) 472 452 { 473 453 return FIELD_GET(MII_REGADDR_C45_MASK, regnum); ··· 473 463 return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); 474 464 } 475 465 476 - static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, 477 - u16 regnum) 466 + static inline int mdiodev_c45_modify(struct mdio_device *mdiodev, int devad, 467 + u32 regnum, u16 mask, u16 set) 478 468 { 479 - return __mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum)); 469 + return mdiobus_c45_modify(mdiodev->bus, mdiodev->addr, devad, regnum, 470 + mask, set); 480 471 } 481 472 482 - static inline int __mdiobus_c45_write(struct mii_bus *bus, int prtad, int devad, 483 - u16 regnum, u16 val) 473 + static inline int mdiodev_c45_modify_changed(struct mdio_device *mdiodev, 474 + int devad, u32 regnum, u16 mask, 475 + u16 set) 484 476 { 485 - return __mdiobus_write(bus, prtad, mdiobus_c45_addr(devad, regnum), 486 - val); 487 - } 488 - 489 - static inline int mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, 490 - u16 regnum) 491 - { 492 - return mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum)); 493 - } 494 - 495 - static inline int mdiobus_c45_write(struct mii_bus *bus, int prtad, int devad, 496 - u16 regnum, u16 val) 497 - { 498 - return mdiobus_write(bus, prtad, mdiobus_c45_addr(devad, regnum), val); 477 + return mdiobus_c45_modify_changed(mdiodev->bus, mdiodev->addr, devad, 478 + regnum, mask, set); 499 479 } 500 480 501 481 static inline int mdiodev_c45_read(struct mdio_device *mdiodev, int devad,

+5

include/linux/phy.h

··· 364 364 int (*read)(struct mii_bus *bus, int addr, int regnum); 365 365 /** @write: Perform a write transfer on the bus */ 366 366 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val); 367 + /** @read_c45: Perform a C45 read transfer on the bus */ 368 + int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum); 369 + /** @write_c45: Perform a C45 write transfer on the bus */ 370 + int (*write_c45)(struct mii_bus *bus, int addr, int devnum, 371 + int regnum, u16 val); 367 372 /** @reset: Perform a reset of the bus */ 368 373 int (*reset)(struct mii_bus *bus); 369 374

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