Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
"Hopefully last set of changes for ARC for 4.10:
- fix for unaligned access emulation corner case
- fix for udelay loop inline asm regression
- fix irq affinity finally for AXS103 board [Yuriy]
- final fixes for setting IO-coherency sanely in SMP"
* tag 'arc-4.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: [arcompact] handle unaligned access delay slot corner case
ARCv2: smp-boot: wake_flag polling by non-Masters needs to be uncached
ARC: smp-boot: Decouple Non masters waiting API from jump to entry point
ARCv2: MCIP: update the BCR per current changes
ARC: udelay: fix inline assembler by adding LP_COUNT to clobber list
ARCv2: MCIP: Deprecate setting of affinity in Device Tree
+66
-54
+3
Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
+3
Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
···
15
15
Second cell specifies the irq distribution mode to cores
16
16
0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
17
17
18
+
The second cell in interrupts property is deprecated and may be ignored by
19
+
the kernel.
20
+
18
21
intc accessed via the special ARC AUX register interface, hence "reg" property
19
22
is not specified.
20
23
+3
-1
arch/arc/include/asm/delay.h
+3
-1
arch/arc/include/asm/delay.h
+7
-7
arch/arc/kernel/head.S
+7
-7
arch/arc/kernel/head.S
···
71
71
GET_CPU_ID r5
72
72
cmp r5, 0
73
73
mov.nz r0, r5
74
-
#ifdef CONFIG_ARC_SMP_HALT_ON_RESET
75
-
; Non-Master can proceed as system would be booted sufficiently
76
-
jnz first_lines_of_secondary
77
-
#else
74
+
bz .Lmaster_proceed
75
+
78
76
; Non-Masters wait for Master to boot enough and bring them up
79
-
jnz arc_platform_smp_wait_to_boot
80
-
#endif
81
-
; Master falls thru
77
+
; when they resume, tail-call to entry point
78
+
mov blink, @first_lines_of_secondary
79
+
j arc_platform_smp_wait_to_boot
80
+
81
+
.Lmaster_proceed:
82
82
#endif
83
83
84
84
; Clear BSS before updating any globals
+23
-32
arch/arc/kernel/mcip.c
+23
-32
arch/arc/kernel/mcip.c
···
93
93
READ_BCR(ARC_REG_MCIP_BCR, mp);
94
94
95
95
sprintf(smp_cpuinfo_buf,
96
-
"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",
96
+
"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
97
97
mp.ver, mp.num_cores,
98
98
IS_AVAIL1(mp.ipi, "IPI "),
99
99
IS_AVAIL1(mp.idu, "IDU "),
100
-
IS_AVAIL1(mp.llm, "LLM "),
101
100
IS_AVAIL1(mp.dbg, "DEBUG "),
102
101
IS_AVAIL1(mp.gfrc, "GFRC"));
103
102
···
174
175
raw_spin_unlock_irqrestore(&mcip_lock, flags);
175
176
}
176
177
177
-
#ifdef CONFIG_SMP
178
178
static int
179
179
idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
180
180
bool force)
···
203
205
204
206
return IRQ_SET_MASK_OK;
205
207
}
206
-
#endif
208
+
209
+
static void idu_irq_enable(struct irq_data *data)
210
+
{
211
+
/*
212
+
* By default send all common interrupts to all available online CPUs.
213
+
* The affinity of common interrupts in IDU must be set manually since
214
+
* in some cases the kernel will not call irq_set_affinity() by itself:
215
+
* 1. When the kernel is not configured with support of SMP.
216
+
* 2. When the kernel is configured with support of SMP but upper
217
+
* interrupt controllers does not support setting of the affinity
218
+
* and cannot propagate it to IDU.
219
+
*/
220
+
idu_irq_set_affinity(data, cpu_online_mask, false);
221
+
idu_irq_unmask(data);
222
+
}
207
223
208
224
static struct irq_chip idu_irq_chip = {
209
225
.name = "MCIP IDU Intc",
210
226
.irq_mask = idu_irq_mask,
211
227
.irq_unmask = idu_irq_unmask,
228
+
.irq_enable = idu_irq_enable,
212
229
#ifdef CONFIG_SMP
213
230
.irq_set_affinity = idu_irq_set_affinity,
214
231
#endif
···
256
243
const u32 *intspec, unsigned int intsize,
257
244
irq_hw_number_t *out_hwirq, unsigned int *out_type)
258
245
{
259
-
irq_hw_number_t hwirq = *out_hwirq = intspec[0];
260
-
int distri = intspec[1];
261
-
unsigned long flags;
262
-
246
+
/*
247
+
* Ignore value of interrupt distribution mode for common interrupts in
248
+
* IDU which resides in intspec[1] since setting an affinity using value
249
+
* from Device Tree is deprecated in ARC.
250
+
*/
251
+
*out_hwirq = intspec[0];
263
252
*out_type = IRQ_TYPE_NONE;
264
-
265
-
/* XXX: validate distribution scheme again online cpu mask */
266
-
if (distri == 0) {
267
-
/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
268
-
raw_spin_lock_irqsave(&mcip_lock, flags);
269
-
idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
270
-
idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
271
-
raw_spin_unlock_irqrestore(&mcip_lock, flags);
272
-
} else {
273
-
/*
274
-
* DEST based distribution for Level Triggered intr can only
275
-
* have 1 CPU, so generalize it to always contain 1 cpu
276
-
*/
277
-
int cpu = ffs(distri);
278
-
279
-
if (cpu != fls(distri))
280
-
pr_warn("IDU irq %lx distri mode set to cpu %x\n",
281
-
hwirq, cpu);
282
-
283
-
raw_spin_lock_irqsave(&mcip_lock, flags);
284
-
idu_set_dest(hwirq, cpu);
285
-
idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
286
-
raw_spin_unlock_irqrestore(&mcip_lock, flags);
287
-
}
288
253
289
254
return 0;
290
255
}
+20
-5
arch/arc/kernel/smp.c
+20
-5
arch/arc/kernel/smp.c
···
90
90
*/
91
91
static volatile int wake_flag;
92
92
93
+
#ifdef CONFIG_ISA_ARCOMPACT
94
+
95
+
#define __boot_read(f) f
96
+
#define __boot_write(f, v) f = v
97
+
98
+
#else
99
+
100
+
#define __boot_read(f) arc_read_uncached_32(&f)
101
+
#define __boot_write(f, v) arc_write_uncached_32(&f, v)
102
+
103
+
#endif
104
+
93
105
static void arc_default_smp_cpu_kick(int cpu, unsigned long pc)
94
106
{
95
107
BUG_ON(cpu == 0);
96
-
wake_flag = cpu;
108
+
109
+
__boot_write(wake_flag, cpu);
97
110
}
98
111
99
112
void arc_platform_smp_wait_to_boot(int cpu)
100
113
{
101
-
while (wake_flag != cpu)
114
+
/* for halt-on-reset, we've waited already */
115
+
if (IS_ENABLED(CONFIG_ARC_SMP_HALT_ON_RESET))
116
+
return;
117
+
118
+
while (__boot_read(wake_flag) != cpu)
102
119
;
103
120
104
-
wake_flag = 0;
105
-
__asm__ __volatile__("j @first_lines_of_secondary \n");
121
+
__boot_write(wake_flag, 0);
106
122
}
107
-
108
123
109
124
const char *arc_platform_smp_cpuinfo(void)
110
125
{
+2
-1
arch/arc/kernel/unaligned.c
+2
-1
arch/arc/kernel/unaligned.c
+8
-8
include/soc/arc/mcip.h
+8
-8
include/soc/arc/mcip.h
···
55
55
56
56
struct mcip_bcr {
57
57
#ifdef CONFIG_CPU_BIG_ENDIAN
58
-
unsigned int pad3:8,
59
-
idu:1, llm:1, num_cores:6,
60
-
iocoh:1, gfrc:1, dbg:1, pad2:1,
61
-
msg:1, sem:1, ipi:1, pad:1,
58
+
unsigned int pad4:6, pw_dom:1, pad3:1,
59
+
idu:1, pad2:1, num_cores:6,
60
+
pad:1, gfrc:1, dbg:1, pw:1,
61
+
msg:1, sem:1, ipi:1, slv:1,
62
62
ver:8;
63
63
#else
64
64
unsigned int ver:8,
65
-
pad:1, ipi:1, sem:1, msg:1,
66
-
pad2:1, dbg:1, gfrc:1, iocoh:1,
67
-
num_cores:6, llm:1, idu:1,
68
-
pad3:8;
65
+
slv:1, ipi:1, sem:1, msg:1,
66
+
pw:1, dbg:1, gfrc:1, pad:1,
67
+
num_cores:6, pad2:1, idu:1,
68
+
pad3:1, pw_dom:1, pad4:6;
69
69
#endif
70
70
};
71
71