Merge branch 'sh/for-2.6.33' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

+2 -2

arch/sh/boards/mach-ecovec24/setup.c

··· 128 128 129 129 /* SH Eth */ 130 130 #define SH_ETH_ADDR (0xA4600000) 131 - #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) 132 - #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) 133 131 static struct resource sh_eth_resources[] = { 134 132 [0] = { 135 133 .start = SH_ETH_ADDR, ··· 507 509 508 510 #else 509 511 512 + /* MMC SPI */ 510 513 static int mmc_spi_get_ro(struct device *dev) 511 514 { 512 515 return gpio_get_value(GPIO_PTY6); ··· 541 542 }, 542 543 }; 543 544 545 + /* MSIOF0 */ 544 546 static struct sh_msiof_spi_info msiof0_data = { 545 547 .num_chipselect = 1, 546 548 };

+4 -2

arch/sh/include/asm/dma.h

··· 19 19 #include <asm-generic/dma.h> 20 20 21 21 #ifdef CONFIG_NR_DMA_CHANNELS 22 - # define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) 22 + # define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) 23 + #elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS) 24 + # define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 23 25 #else 24 - # define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 26 + # define MAX_DMA_CHANNELS 0 25 27 #endif 26 28 27 29 /*

+4 -4

arch/sh/include/cpu-sh4/cpu/dma-sh4a.h

··· 19 19 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 20 20 defined(CONFIG_CPU_SUBTYPE_SH7724) 21 21 #define DMTE0_IRQ 48 /* DMAC0A*/ 22 - #define DMTE4_IRQ 40 /* DMAC0B */ 23 - #define DMTE6_IRQ 42 24 - #define DMTE8_IRQ 76 /* DMAC1A */ 25 - #define DMTE9_IRQ 77 22 + #define DMTE4_IRQ 76 /* DMAC0B */ 23 + #define DMTE6_IRQ 40 24 + #define DMTE8_IRQ 42 /* DMAC1A */ 25 + #define DMTE9_IRQ 43 26 26 #define DMTE10_IRQ 72 /* DMAC1B */ 27 27 #define DMTE11_IRQ 73 28 28 #define DMAE0_IRQ 78 /* DMA Error IRQ*/

+15

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

··· 23 23 #include <linux/notifier.h> 24 24 #include <asm/suspend.h> 25 25 #include <asm/clock.h> 26 + #include <asm/dma-sh.h> 26 27 #include <asm/mmzone.h> 27 28 #include <cpu/sh7724.h> 29 + 30 + /* DMA */ 31 + static struct sh_dmae_pdata dma_platform_data = { 32 + .mode = SHDMA_DMAOR1, 33 + }; 34 + 35 + static struct platform_device dma_device = { 36 + .name = "sh-dma-engine", 37 + .id = -1, 38 + .dev = { 39 + .platform_data = &dma_platform_data, 40 + }, 41 + }; 28 42 29 43 /* Serial */ 30 44 static struct plat_sci_port scif0_platform_data = { ··· 663 649 &tmu3_device, 664 650 &tmu4_device, 665 651 &tmu5_device, 652 + &dma_device, 666 653 &rtc_device, 667 654 &iic0_device, 668 655 &iic1_device,

+14

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

··· 14 14 #include <linux/io.h> 15 15 #include <linux/mm.h> 16 16 #include <linux/sh_timer.h> 17 + #include <asm/dma-sh.h> 17 18 #include <asm/mmzone.h> 18 19 19 20 static struct plat_sci_port scif0_platform_data = { ··· 295 294 .num_resources = ARRAY_SIZE(tmu5_resources), 296 295 }; 297 296 297 + static struct sh_dmae_pdata dma_platform_data = { 298 + .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), 299 + }; 300 + 301 + static struct platform_device dma_device = { 302 + .name = "sh-dma-engine", 303 + .id = -1, 304 + .dev = { 305 + .platform_data = &dma_platform_data, 306 + }, 307 + }; 308 + 298 309 static struct platform_device *sh7785_devices[] __initdata = { 299 310 &scif0_device, 300 311 &scif1_device, ··· 320 307 &tmu3_device, 321 308 &tmu4_device, 322 309 &tmu5_device, 310 + &dma_device, 323 311 }; 324 312 325 313 static int __init sh7785_devices_setup(void)

+2

arch/sh/kernel/idle.c

··· 62 62 clear_thread_flag(TIF_POLLING_NRFLAG); 63 63 smp_mb__after_clear_bit(); 64 64 65 + set_bl_bit(); 65 66 if (!need_resched()) { 66 67 local_irq_enable(); 67 68 cpu_sleep(); ··· 70 69 local_irq_enable(); 71 70 72 71 set_thread_flag(TIF_POLLING_NRFLAG); 72 + clear_bl_bit(); 73 73 } else 74 74 poll_idle(); 75 75 }

+2 -6

arch/sh/mm/cache.c

··· 133 133 page = pfn_to_page(pfn); 134 134 if (pfn_valid(pfn)) { 135 135 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); 136 - if (dirty) { 137 - unsigned long addr = (unsigned long)page_address(page); 138 - 139 - if (pages_do_alias(addr, address & PAGE_MASK)) 140 - __flush_purge_region((void *)addr, PAGE_SIZE); 141 - } 136 + if (dirty) 137 + __flush_purge_region(page_address(page), PAGE_SIZE); 142 138 } 143 139 } 144 140

+15 -5

drivers/serial/sh-sci.c

··· 222 222 Set SCP6MD1,0 = {01} (output) */ 223 223 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); 224 224 225 - data = ctrl_inb(SCPDR); 225 + data = __raw_readb(SCPDR); 226 226 /* Set /RTS2 (bit6) = 0 */ 227 - ctrl_outb(data & 0xbf, SCPDR); 227 + __raw_writeb(data & 0xbf, SCPDR); 228 228 } 229 229 } 230 230 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) ··· 897 897 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 898 898 struct ktermios *old) 899 899 { 900 - unsigned int status, baud, smr_val; 900 + unsigned int status, baud, smr_val, max_baud; 901 901 int t = -1; 902 902 903 - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 904 - if (likely(baud)) 903 + /* 904 + * earlyprintk comes here early on with port->uartclk set to zero. 905 + * the clock framework is not up and running at this point so here 906 + * we assume that 115200 is the maximum baud rate. please note that 907 + * the baud rate is not programmed during earlyprintk - it is assumed 908 + * that the previous boot loader has enabled required clocks and 909 + * setup the baud rate generator hardware for us already. 910 + */ 911 + max_baud = port->uartclk ? port->uartclk / 16 : 115200; 912 + 913 + baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 914 + if (likely(baud && port->uartclk)) 905 915 t = SCBRR_VALUE(baud, port->uartclk); 906 916 907 917 do {

+59 -59

drivers/serial/sh-sci.h

··· 517 517 static inline int sci_rxd_in(struct uart_port *port) 518 518 { 519 519 if (port->mapbase == 0xfffffe80) 520 - return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 520 + return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 521 521 if (port->mapbase == 0xa4000150) 522 - return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 522 + return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 523 523 if (port->mapbase == 0xa4000140) 524 - return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 524 + return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 525 525 return 1; 526 526 } 527 527 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 528 528 static inline int sci_rxd_in(struct uart_port *port) 529 529 { 530 530 if (port->mapbase == SCIF0) 531 - return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 531 + return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 532 532 if (port->mapbase == SCIF2) 533 - return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 533 + return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 534 534 return 1; 535 535 } 536 536 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) ··· 557 557 static inline int sci_rxd_in(struct uart_port *port) 558 558 { 559 559 if (port->mapbase == 0xffe00000) 560 - return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 560 + return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 561 561 if (port->mapbase == 0xffe80000) 562 - return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 562 + return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 563 563 return 1; 564 564 } 565 565 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 566 566 static inline int sci_rxd_in(struct uart_port *port) 567 567 { 568 568 if (port->mapbase == 0xffe80000) 569 - return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 569 + return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 570 570 return 1; 571 571 } 572 572 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) 573 573 static inline int sci_rxd_in(struct uart_port *port) 574 574 { 575 575 if (port->mapbase == 0xfe4b0000) 576 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; 576 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; 577 577 if (port->mapbase == 0xfe4c0000) 578 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; 578 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; 579 579 if (port->mapbase == 0xfe4d0000) 580 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; 580 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; 581 581 } 582 582 #elif defined(CONFIG_CPU_SUBTYPE_SH7760) 583 583 static inline int sci_rxd_in(struct uart_port *port) 584 584 { 585 585 if (port->mapbase == 0xfe600000) 586 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 586 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 587 587 if (port->mapbase == 0xfe610000) 588 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 588 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 589 589 if (port->mapbase == 0xfe620000) 590 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 590 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 591 591 return 1; 592 592 } 593 593 #elif defined(CONFIG_CPU_SUBTYPE_SH7343) 594 594 static inline int sci_rxd_in(struct uart_port *port) 595 595 { 596 596 if (port->mapbase == 0xffe00000) 597 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 597 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 598 598 if (port->mapbase == 0xffe10000) 599 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 599 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 600 600 if (port->mapbase == 0xffe20000) 601 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 601 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 602 602 if (port->mapbase == 0xffe30000) 603 - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 603 + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 604 604 return 1; 605 605 } 606 606 #elif defined(CONFIG_CPU_SUBTYPE_SH7366) 607 607 static inline int sci_rxd_in(struct uart_port *port) 608 608 { 609 609 if (port->mapbase == 0xffe00000) 610 - return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 610 + return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 611 611 return 1; 612 612 } 613 613 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 614 614 static inline int sci_rxd_in(struct uart_port *port) 615 615 { 616 616 if (port->mapbase == 0xffe00000) 617 - return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ 617 + return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ 618 618 if (port->mapbase == 0xffe10000) 619 - return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ 619 + return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ 620 620 if (port->mapbase == 0xffe20000) 621 - return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ 621 + return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ 622 622 623 623 return 1; 624 624 } ··· 626 626 static inline int sci_rxd_in(struct uart_port *port) 627 627 { 628 628 if (port->mapbase == 0xffe00000) 629 - return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ 629 + return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ 630 630 if (port->mapbase == 0xffe10000) 631 - return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ 631 + return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ 632 632 if (port->mapbase == 0xffe20000) 633 - return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ 633 + return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ 634 634 if (port->mapbase == 0xa4e30000) 635 - return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ 635 + return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ 636 636 if (port->mapbase == 0xa4e40000) 637 - return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ 637 + return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ 638 638 if (port->mapbase == 0xa4e50000) 639 - return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ 639 + return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ 640 640 return 1; 641 641 } 642 642 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) ··· 645 645 static inline int sci_rxd_in(struct uart_port *port) 646 646 { 647 647 if (port->type == PORT_SCIF) 648 - return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; 648 + return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; 649 649 if (port->type == PORT_SCIFA) 650 - return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; 650 + return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; 651 651 return 1; 652 652 } 653 653 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) ··· 665 665 static inline int sci_rxd_in(struct uart_port *port) 666 666 { 667 667 if (port->mapbase == 0xffe00000) 668 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 668 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 669 669 if (port->mapbase == 0xffe08000) 670 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 670 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 671 671 if (port->mapbase == 0xffe10000) 672 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ 672 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ 673 673 674 674 return 1; 675 675 } ··· 677 677 static inline int sci_rxd_in(struct uart_port *port) 678 678 { 679 679 if (port->mapbase == 0xff923000) 680 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 680 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 681 681 if (port->mapbase == 0xff924000) 682 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 682 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 683 683 if (port->mapbase == 0xff925000) 684 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 684 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 685 685 return 1; 686 686 } 687 687 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 688 688 static inline int sci_rxd_in(struct uart_port *port) 689 689 { 690 690 if (port->mapbase == 0xffe00000) 691 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 691 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 692 692 if (port->mapbase == 0xffe10000) 693 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 693 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 694 694 return 1; 695 695 } 696 696 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ ··· 698 698 static inline int sci_rxd_in(struct uart_port *port) 699 699 { 700 700 if (port->mapbase == 0xffea0000) 701 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 701 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 702 702 if (port->mapbase == 0xffeb0000) 703 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 703 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 704 704 if (port->mapbase == 0xffec0000) 705 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 705 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 706 706 if (port->mapbase == 0xffed0000) 707 - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 707 + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 708 708 if (port->mapbase == 0xffee0000) 709 - return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ 709 + return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ 710 710 if (port->mapbase == 0xffef0000) 711 - return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ 711 + return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ 712 712 return 1; 713 713 } 714 714 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ ··· 718 718 static inline int sci_rxd_in(struct uart_port *port) 719 719 { 720 720 if (port->mapbase == 0xfffe8000) 721 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 721 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 722 722 if (port->mapbase == 0xfffe8800) 723 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 723 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 724 724 if (port->mapbase == 0xfffe9000) 725 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 725 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 726 726 if (port->mapbase == 0xfffe9800) 727 - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 727 + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 728 728 #if defined(CONFIG_CPU_SUBTYPE_SH7201) 729 729 if (port->mapbase == 0xfffeA000) 730 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 730 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 731 731 if (port->mapbase == 0xfffeA800) 732 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 732 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 733 733 if (port->mapbase == 0xfffeB000) 734 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 734 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 735 735 if (port->mapbase == 0xfffeB800) 736 - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 736 + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 737 737 #endif 738 738 return 1; 739 739 } ··· 741 741 static inline int sci_rxd_in(struct uart_port *port) 742 742 { 743 743 if (port->mapbase == 0xf8400000) 744 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 744 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 745 745 if (port->mapbase == 0xf8410000) 746 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 746 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 747 747 if (port->mapbase == 0xf8420000) 748 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 748 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 749 749 return 1; 750 750 } 751 751 #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 752 752 static inline int sci_rxd_in(struct uart_port *port) 753 753 { 754 754 if (port->mapbase == 0xffc30000) 755 - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 755 + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 756 756 if (port->mapbase == 0xffc40000) 757 - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 757 + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 758 758 if (port->mapbase == 0xffc50000) 759 - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 759 + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 760 760 if (port->mapbase == 0xffc60000) 761 - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 761 + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 762 762 return 1; 763 763 } 764 764 #endif

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