Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add CAMCC driver support for SM4450
Add Camera Clock Controller (CAMCC) support for SM4450 platform.
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-6-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Ajit Pandey
and committed by
Bjorn Andersson
ef404007
76f05f1e
+1697
+8
drivers/clk/qcom/Kconfig
+8
drivers/clk/qcom/Kconfig
···
810
810
Say Y if you want to use peripheral devices such as UART,
811
811
SPI, I2C, USB, SD/eMMC, PCIe etc.
812
812
813
+
config SM_CAMCC_4450
814
+
tristate "SM4450 Camera Clock Controller"
815
+
depends on ARM64 || COMPILE_TEST
816
+
select SM_GCC_4450
817
+
help
818
+
Support for the camera clock controller on SM4450 devices.
819
+
Say Y if you want to support camera devices and camera functionality.
820
+
813
821
config SM_CAMCC_6350
814
822
tristate "SM6350 Camera Clock Controller"
815
823
depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
107
107
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
108
108
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
109
109
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
110
+
obj-$(CONFIG_SM_CAMCC_4450) += camcc-sm4450.o
110
111
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
111
112
obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o
112
113
obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o
+1688
drivers/clk/qcom/camcc-sm4450.c
+1688
drivers/clk/qcom/camcc-sm4450.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/mod_devicetable.h>
9
+
#include <linux/of.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/regmap.h>
12
+
13
+
#include <dt-bindings/clock/qcom,sm4450-camcc.h>
14
+
15
+
#include "clk-alpha-pll.h"
16
+
#include "clk-branch.h"
17
+
#include "clk-pll.h"
18
+
#include "clk-rcg.h"
19
+
#include "clk-regmap.h"
20
+
#include "common.h"
21
+
#include "gdsc.h"
22
+
#include "reset.h"
23
+
24
+
enum {
25
+
DT_BI_TCXO,
26
+
};
27
+
28
+
enum {
29
+
P_BI_TCXO,
30
+
P_CAM_CC_PLL0_OUT_EVEN,
31
+
P_CAM_CC_PLL0_OUT_MAIN,
32
+
P_CAM_CC_PLL0_OUT_ODD,
33
+
P_CAM_CC_PLL1_OUT_EVEN,
34
+
P_CAM_CC_PLL1_OUT_MAIN,
35
+
P_CAM_CC_PLL2_OUT_EVEN,
36
+
P_CAM_CC_PLL2_OUT_MAIN,
37
+
P_CAM_CC_PLL3_OUT_EVEN,
38
+
P_CAM_CC_PLL4_OUT_EVEN,
39
+
P_CAM_CC_PLL4_OUT_MAIN,
40
+
};
41
+
42
+
static const struct pll_vco lucid_evo_vco[] = {
43
+
{ 249600000, 2020000000, 0 },
44
+
};
45
+
46
+
static const struct pll_vco rivian_evo_vco[] = {
47
+
{ 864000000, 1056000000, 0 },
48
+
};
49
+
50
+
/* 1200.0 MHz Configuration */
51
+
static const struct alpha_pll_config cam_cc_pll0_config = {
52
+
.l = 0x3e,
53
+
.alpha = 0x8000,
54
+
.config_ctl_val = 0x20485699,
55
+
.config_ctl_hi_val = 0x00182261,
56
+
.config_ctl_hi1_val = 0x32aa299c,
57
+
.user_ctl_val = 0x00008400,
58
+
.user_ctl_hi_val = 0x00000805,
59
+
};
60
+
61
+
static struct clk_alpha_pll cam_cc_pll0 = {
62
+
.offset = 0x0,
63
+
.vco_table = lucid_evo_vco,
64
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
65
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
66
+
.clkr = {
67
+
.hw.init = &(const struct clk_init_data) {
68
+
.name = "cam_cc_pll0",
69
+
.parent_data = &(const struct clk_parent_data) {
70
+
.index = DT_BI_TCXO,
71
+
},
72
+
.num_parents = 1,
73
+
.ops = &clk_alpha_pll_lucid_evo_ops,
74
+
},
75
+
},
76
+
};
77
+
78
+
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
79
+
{ 0x1, 2 },
80
+
{ }
81
+
};
82
+
83
+
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
84
+
.offset = 0x0,
85
+
.post_div_shift = 10,
86
+
.post_div_table = post_div_table_cam_cc_pll0_out_even,
87
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
88
+
.width = 4,
89
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
90
+
.clkr.hw.init = &(const struct clk_init_data) {
91
+
.name = "cam_cc_pll0_out_even",
92
+
.parent_hws = (const struct clk_hw*[]) {
93
+
&cam_cc_pll0.clkr.hw,
94
+
},
95
+
.num_parents = 1,
96
+
.flags = CLK_SET_RATE_PARENT,
97
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
98
+
},
99
+
};
100
+
101
+
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
102
+
{ 0x2, 3 },
103
+
{ }
104
+
};
105
+
106
+
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
107
+
.offset = 0x0,
108
+
.post_div_shift = 14,
109
+
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
110
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
111
+
.width = 4,
112
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
113
+
.clkr.hw.init = &(const struct clk_init_data) {
114
+
.name = "cam_cc_pll0_out_odd",
115
+
.parent_hws = (const struct clk_hw*[]) {
116
+
&cam_cc_pll0.clkr.hw,
117
+
},
118
+
.num_parents = 1,
119
+
.flags = CLK_SET_RATE_PARENT,
120
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
121
+
},
122
+
};
123
+
124
+
/* 600.0 MHz Configuration */
125
+
static const struct alpha_pll_config cam_cc_pll1_config = {
126
+
.l = 0x1f,
127
+
.alpha = 0x4000,
128
+
.config_ctl_val = 0x20485699,
129
+
.config_ctl_hi_val = 0x00182261,
130
+
.config_ctl_hi1_val = 0x32aa299c,
131
+
.user_ctl_val = 0x00000400,
132
+
.user_ctl_hi_val = 0x00000805,
133
+
};
134
+
135
+
static struct clk_alpha_pll cam_cc_pll1 = {
136
+
.offset = 0x1000,
137
+
.vco_table = lucid_evo_vco,
138
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
139
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
140
+
.clkr = {
141
+
.hw.init = &(const struct clk_init_data) {
142
+
.name = "cam_cc_pll1",
143
+
.parent_data = &(const struct clk_parent_data) {
144
+
.index = DT_BI_TCXO,
145
+
},
146
+
.num_parents = 1,
147
+
.ops = &clk_alpha_pll_lucid_evo_ops,
148
+
},
149
+
},
150
+
};
151
+
152
+
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
153
+
{ 0x1, 2 },
154
+
{ }
155
+
};
156
+
157
+
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
158
+
.offset = 0x1000,
159
+
.post_div_shift = 10,
160
+
.post_div_table = post_div_table_cam_cc_pll1_out_even,
161
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
162
+
.width = 4,
163
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
164
+
.clkr.hw.init = &(const struct clk_init_data) {
165
+
.name = "cam_cc_pll1_out_even",
166
+
.parent_hws = (const struct clk_hw*[]) {
167
+
&cam_cc_pll1.clkr.hw,
168
+
},
169
+
.num_parents = 1,
170
+
.flags = CLK_SET_RATE_PARENT,
171
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
172
+
},
173
+
};
174
+
175
+
/* 960.0 MHz Configuration */
176
+
static const struct alpha_pll_config cam_cc_pll2_config = {
177
+
.l = 0x32,
178
+
.alpha = 0x0,
179
+
.config_ctl_val = 0x90008820,
180
+
.config_ctl_hi_val = 0x00890263,
181
+
.config_ctl_hi1_val = 0x00000247,
182
+
.user_ctl_val = 0x00000400,
183
+
.user_ctl_hi_val = 0x00400000,
184
+
};
185
+
186
+
static struct clk_alpha_pll cam_cc_pll2 = {
187
+
.offset = 0x2000,
188
+
.vco_table = rivian_evo_vco,
189
+
.num_vco = ARRAY_SIZE(rivian_evo_vco),
190
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
191
+
.clkr = {
192
+
.hw.init = &(const struct clk_init_data) {
193
+
.name = "cam_cc_pll2",
194
+
.parent_data = &(const struct clk_parent_data) {
195
+
.index = DT_BI_TCXO,
196
+
},
197
+
.num_parents = 1,
198
+
.ops = &clk_alpha_pll_rivian_evo_ops,
199
+
},
200
+
},
201
+
};
202
+
203
+
static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = {
204
+
{ 0x1, 2 },
205
+
{ }
206
+
};
207
+
208
+
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
209
+
.offset = 0x2000,
210
+
.post_div_shift = 10,
211
+
.post_div_table = post_div_table_cam_cc_pll2_out_even,
212
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even),
213
+
.width = 4,
214
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
215
+
.clkr.hw.init = &(const struct clk_init_data) {
216
+
.name = "cam_cc_pll2_out_even",
217
+
.parent_hws = (const struct clk_hw*[]) {
218
+
&cam_cc_pll2.clkr.hw,
219
+
},
220
+
.num_parents = 1,
221
+
.flags = CLK_SET_RATE_PARENT,
222
+
.ops = &clk_alpha_pll_postdiv_rivian_evo_ops,
223
+
},
224
+
};
225
+
226
+
/* 600.0 MHz Configuration */
227
+
static const struct alpha_pll_config cam_cc_pll3_config = {
228
+
.l = 0x1f,
229
+
.alpha = 0x4000,
230
+
.config_ctl_val = 0x20485699,
231
+
.config_ctl_hi_val = 0x00182261,
232
+
.config_ctl_hi1_val = 0x32aa299c,
233
+
.user_ctl_val = 0x00000400,
234
+
.user_ctl_hi_val = 0x00000805,
235
+
};
236
+
237
+
static struct clk_alpha_pll cam_cc_pll3 = {
238
+
.offset = 0x3000,
239
+
.vco_table = lucid_evo_vco,
240
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
241
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
242
+
.clkr = {
243
+
.hw.init = &(const struct clk_init_data) {
244
+
.name = "cam_cc_pll3",
245
+
.parent_data = &(const struct clk_parent_data) {
246
+
.index = DT_BI_TCXO,
247
+
},
248
+
.num_parents = 1,
249
+
.ops = &clk_alpha_pll_lucid_evo_ops,
250
+
},
251
+
},
252
+
};
253
+
254
+
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
255
+
{ 0x1, 2 },
256
+
{ }
257
+
};
258
+
259
+
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
260
+
.offset = 0x3000,
261
+
.post_div_shift = 10,
262
+
.post_div_table = post_div_table_cam_cc_pll3_out_even,
263
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
264
+
.width = 4,
265
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
266
+
.clkr.hw.init = &(const struct clk_init_data) {
267
+
.name = "cam_cc_pll3_out_even",
268
+
.parent_hws = (const struct clk_hw*[]) {
269
+
&cam_cc_pll3.clkr.hw,
270
+
},
271
+
.num_parents = 1,
272
+
.flags = CLK_SET_RATE_PARENT,
273
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
274
+
},
275
+
};
276
+
277
+
/* 700.0 MHz Configuration */
278
+
static const struct alpha_pll_config cam_cc_pll4_config = {
279
+
.l = 0x24,
280
+
.alpha = 0x7555,
281
+
.config_ctl_val = 0x20485699,
282
+
.config_ctl_hi_val = 0x00182261,
283
+
.config_ctl_hi1_val = 0x32aa299c,
284
+
.user_ctl_val = 0x00000400,
285
+
.user_ctl_hi_val = 0x00000805,
286
+
};
287
+
288
+
static struct clk_alpha_pll cam_cc_pll4 = {
289
+
.offset = 0x4000,
290
+
.vco_table = lucid_evo_vco,
291
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
292
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
293
+
.clkr = {
294
+
.hw.init = &(const struct clk_init_data) {
295
+
.name = "cam_cc_pll4",
296
+
.parent_data = &(const struct clk_parent_data) {
297
+
.index = DT_BI_TCXO,
298
+
},
299
+
.num_parents = 1,
300
+
.ops = &clk_alpha_pll_lucid_evo_ops,
301
+
},
302
+
},
303
+
};
304
+
305
+
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
306
+
{ 0x1, 2 },
307
+
{ }
308
+
};
309
+
310
+
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
311
+
.offset = 0x4000,
312
+
.post_div_shift = 10,
313
+
.post_div_table = post_div_table_cam_cc_pll4_out_even,
314
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
315
+
.width = 4,
316
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
317
+
.clkr.hw.init = &(const struct clk_init_data) {
318
+
.name = "cam_cc_pll4_out_even",
319
+
.parent_hws = (const struct clk_hw*[]) {
320
+
&cam_cc_pll4.clkr.hw,
321
+
},
322
+
.num_parents = 1,
323
+
.flags = CLK_SET_RATE_PARENT,
324
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
325
+
},
326
+
};
327
+
328
+
static const struct parent_map cam_cc_parent_map_0[] = {
329
+
{ P_BI_TCXO, 0 },
330
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
331
+
{ P_CAM_CC_PLL0_OUT_ODD, 5 },
332
+
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
333
+
};
334
+
335
+
static const struct clk_parent_data cam_cc_parent_data_0[] = {
336
+
{ .index = DT_BI_TCXO },
337
+
{ .hw = &cam_cc_pll0.clkr.hw },
338
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
339
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
340
+
};
341
+
342
+
static const struct parent_map cam_cc_parent_map_1[] = {
343
+
{ P_BI_TCXO, 0 },
344
+
{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
345
+
{ P_CAM_CC_PLL2_OUT_MAIN, 4 },
346
+
};
347
+
348
+
static const struct clk_parent_data cam_cc_parent_data_1[] = {
349
+
{ .index = DT_BI_TCXO },
350
+
{ .hw = &cam_cc_pll2_out_even.clkr.hw },
351
+
{ .hw = &cam_cc_pll2.clkr.hw },
352
+
};
353
+
354
+
static const struct parent_map cam_cc_parent_map_2[] = {
355
+
{ P_BI_TCXO, 0 },
356
+
{ P_CAM_CC_PLL0_OUT_ODD, 5 },
357
+
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
358
+
};
359
+
360
+
static const struct clk_parent_data cam_cc_parent_data_2[] = {
361
+
{ .index = DT_BI_TCXO },
362
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
363
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
364
+
};
365
+
366
+
static const struct parent_map cam_cc_parent_map_3[] = {
367
+
{ P_BI_TCXO, 0 },
368
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
369
+
{ P_CAM_CC_PLL4_OUT_EVEN, 2 },
370
+
{ P_CAM_CC_PLL4_OUT_MAIN, 3 },
371
+
{ P_CAM_CC_PLL0_OUT_ODD, 5 },
372
+
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
373
+
};
374
+
375
+
static const struct clk_parent_data cam_cc_parent_data_3[] = {
376
+
{ .index = DT_BI_TCXO },
377
+
{ .hw = &cam_cc_pll0.clkr.hw },
378
+
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
379
+
{ .hw = &cam_cc_pll4.clkr.hw },
380
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
381
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
382
+
};
383
+
384
+
static const struct parent_map cam_cc_parent_map_4[] = {
385
+
{ P_BI_TCXO, 0 },
386
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
387
+
{ P_CAM_CC_PLL1_OUT_MAIN, 2 },
388
+
{ P_CAM_CC_PLL1_OUT_EVEN, 3 },
389
+
{ P_CAM_CC_PLL0_OUT_ODD, 5 },
390
+
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
391
+
};
392
+
393
+
static const struct clk_parent_data cam_cc_parent_data_4[] = {
394
+
{ .index = DT_BI_TCXO },
395
+
{ .hw = &cam_cc_pll0.clkr.hw },
396
+
{ .hw = &cam_cc_pll1.clkr.hw },
397
+
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
398
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
399
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
400
+
};
401
+
402
+
static const struct parent_map cam_cc_parent_map_5[] = {
403
+
{ P_BI_TCXO, 0 },
404
+
{ P_CAM_CC_PLL1_OUT_MAIN, 2 },
405
+
{ P_CAM_CC_PLL1_OUT_EVEN, 3 },
406
+
};
407
+
408
+
static const struct clk_parent_data cam_cc_parent_data_5[] = {
409
+
{ .index = DT_BI_TCXO },
410
+
{ .hw = &cam_cc_pll1.clkr.hw },
411
+
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
412
+
};
413
+
414
+
static const struct parent_map cam_cc_parent_map_6[] = {
415
+
{ P_BI_TCXO, 0 },
416
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
417
+
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
418
+
};
419
+
420
+
static const struct clk_parent_data cam_cc_parent_data_6[] = {
421
+
{ .index = DT_BI_TCXO },
422
+
{ .hw = &cam_cc_pll0.clkr.hw },
423
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
424
+
};
425
+
426
+
static const struct parent_map cam_cc_parent_map_7[] = {
427
+
{ P_BI_TCXO, 0 },
428
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
429
+
{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
430
+
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
431
+
};
432
+
433
+
static const struct clk_parent_data cam_cc_parent_data_7[] = {
434
+
{ .index = DT_BI_TCXO },
435
+
{ .hw = &cam_cc_pll0.clkr.hw },
436
+
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
437
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
438
+
};
439
+
440
+
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
441
+
F(19200000, P_BI_TCXO, 1, 0, 0),
442
+
F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
443
+
F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
444
+
F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
445
+
F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
446
+
F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
447
+
{ }
448
+
};
449
+
450
+
static struct clk_rcg2 cam_cc_bps_clk_src = {
451
+
.cmd_rcgr = 0xa004,
452
+
.mnd_width = 0,
453
+
.hid_width = 5,
454
+
.parent_map = cam_cc_parent_map_4,
455
+
.freq_tbl = ftbl_cam_cc_bps_clk_src,
456
+
.clkr.hw.init = &(const struct clk_init_data) {
457
+
.name = "cam_cc_bps_clk_src",
458
+
.parent_data = cam_cc_parent_data_4,
459
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
460
+
.flags = CLK_SET_RATE_PARENT,
461
+
.ops = &clk_rcg2_shared_ops,
462
+
},
463
+
};
464
+
465
+
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
466
+
F(19200000, P_BI_TCXO, 1, 0, 0),
467
+
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
468
+
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
469
+
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
470
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
471
+
{ }
472
+
};
473
+
474
+
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
475
+
.cmd_rcgr = 0x13014,
476
+
.mnd_width = 0,
477
+
.hid_width = 5,
478
+
.parent_map = cam_cc_parent_map_0,
479
+
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
480
+
.clkr.hw.init = &(const struct clk_init_data) {
481
+
.name = "cam_cc_camnoc_axi_clk_src",
482
+
.parent_data = cam_cc_parent_data_0,
483
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
484
+
.flags = CLK_SET_RATE_PARENT,
485
+
.ops = &clk_rcg2_shared_ops,
486
+
},
487
+
};
488
+
489
+
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
490
+
F(19200000, P_BI_TCXO, 1, 0, 0),
491
+
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
492
+
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
493
+
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
494
+
{ }
495
+
};
496
+
497
+
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
498
+
.cmd_rcgr = 0x10004,
499
+
.mnd_width = 8,
500
+
.hid_width = 5,
501
+
.parent_map = cam_cc_parent_map_2,
502
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
503
+
.clkr.hw.init = &(const struct clk_init_data) {
504
+
.name = "cam_cc_cci_0_clk_src",
505
+
.parent_data = cam_cc_parent_data_2,
506
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
507
+
.flags = CLK_SET_RATE_PARENT,
508
+
.ops = &clk_rcg2_shared_ops,
509
+
},
510
+
};
511
+
512
+
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
513
+
.cmd_rcgr = 0x11004,
514
+
.mnd_width = 8,
515
+
.hid_width = 5,
516
+
.parent_map = cam_cc_parent_map_2,
517
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
518
+
.clkr.hw.init = &(const struct clk_init_data) {
519
+
.name = "cam_cc_cci_1_clk_src",
520
+
.parent_data = cam_cc_parent_data_2,
521
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
522
+
.flags = CLK_SET_RATE_PARENT,
523
+
.ops = &clk_rcg2_shared_ops,
524
+
},
525
+
};
526
+
527
+
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
528
+
F(19200000, P_BI_TCXO, 1, 0, 0),
529
+
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
530
+
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
531
+
{ }
532
+
};
533
+
534
+
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
535
+
.cmd_rcgr = 0xc054,
536
+
.mnd_width = 0,
537
+
.hid_width = 5,
538
+
.parent_map = cam_cc_parent_map_0,
539
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
540
+
.clkr.hw.init = &(const struct clk_init_data) {
541
+
.name = "cam_cc_cphy_rx_clk_src",
542
+
.parent_data = cam_cc_parent_data_0,
543
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
544
+
.flags = CLK_SET_RATE_PARENT,
545
+
.ops = &clk_rcg2_shared_ops,
546
+
},
547
+
};
548
+
549
+
static struct clk_rcg2 cam_cc_cre_clk_src = {
550
+
.cmd_rcgr = 0x16004,
551
+
.mnd_width = 0,
552
+
.hid_width = 5,
553
+
.parent_map = cam_cc_parent_map_5,
554
+
.freq_tbl = ftbl_cam_cc_bps_clk_src,
555
+
.clkr.hw.init = &(const struct clk_init_data) {
556
+
.name = "cam_cc_cre_clk_src",
557
+
.parent_data = cam_cc_parent_data_5,
558
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
559
+
.flags = CLK_SET_RATE_PARENT,
560
+
.ops = &clk_rcg2_shared_ops,
561
+
},
562
+
};
563
+
564
+
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
565
+
F(19200000, P_BI_TCXO, 1, 0, 0),
566
+
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
567
+
{ }
568
+
};
569
+
570
+
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
571
+
.cmd_rcgr = 0x9004,
572
+
.mnd_width = 0,
573
+
.hid_width = 5,
574
+
.parent_map = cam_cc_parent_map_0,
575
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
576
+
.clkr.hw.init = &(const struct clk_init_data) {
577
+
.name = "cam_cc_csi0phytimer_clk_src",
578
+
.parent_data = cam_cc_parent_data_0,
579
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
580
+
.flags = CLK_SET_RATE_PARENT,
581
+
.ops = &clk_rcg2_shared_ops,
582
+
},
583
+
};
584
+
585
+
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
586
+
.cmd_rcgr = 0x9028,
587
+
.mnd_width = 0,
588
+
.hid_width = 5,
589
+
.parent_map = cam_cc_parent_map_0,
590
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
591
+
.clkr.hw.init = &(const struct clk_init_data) {
592
+
.name = "cam_cc_csi1phytimer_clk_src",
593
+
.parent_data = cam_cc_parent_data_0,
594
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
595
+
.flags = CLK_SET_RATE_PARENT,
596
+
.ops = &clk_rcg2_shared_ops,
597
+
},
598
+
};
599
+
600
+
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
601
+
.cmd_rcgr = 0x904c,
602
+
.mnd_width = 0,
603
+
.hid_width = 5,
604
+
.parent_map = cam_cc_parent_map_0,
605
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
606
+
.clkr.hw.init = &(const struct clk_init_data) {
607
+
.name = "cam_cc_csi2phytimer_clk_src",
608
+
.parent_data = cam_cc_parent_data_0,
609
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
610
+
.flags = CLK_SET_RATE_PARENT,
611
+
.ops = &clk_rcg2_shared_ops,
612
+
},
613
+
};
614
+
615
+
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
616
+
F(19200000, P_BI_TCXO, 1, 0, 0),
617
+
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
618
+
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
619
+
F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0),
620
+
F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0),
621
+
{ }
622
+
};
623
+
624
+
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
625
+
.cmd_rcgr = 0xa02c,
626
+
.mnd_width = 0,
627
+
.hid_width = 5,
628
+
.parent_map = cam_cc_parent_map_0,
629
+
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
630
+
.clkr.hw.init = &(const struct clk_init_data) {
631
+
.name = "cam_cc_fast_ahb_clk_src",
632
+
.parent_data = cam_cc_parent_data_0,
633
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
634
+
.flags = CLK_SET_RATE_PARENT,
635
+
.ops = &clk_rcg2_shared_ops,
636
+
},
637
+
};
638
+
639
+
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
640
+
F(19200000, P_BI_TCXO, 1, 0, 0),
641
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
642
+
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
643
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
644
+
{ }
645
+
};
646
+
647
+
static struct clk_rcg2 cam_cc_icp_clk_src = {
648
+
.cmd_rcgr = 0xf014,
649
+
.mnd_width = 0,
650
+
.hid_width = 5,
651
+
.parent_map = cam_cc_parent_map_6,
652
+
.freq_tbl = ftbl_cam_cc_icp_clk_src,
653
+
.clkr.hw.init = &(const struct clk_init_data) {
654
+
.name = "cam_cc_icp_clk_src",
655
+
.parent_data = cam_cc_parent_data_6,
656
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
657
+
.flags = CLK_SET_RATE_PARENT,
658
+
.ops = &clk_rcg2_shared_ops,
659
+
},
660
+
};
661
+
662
+
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
663
+
F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50),
664
+
F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
665
+
F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0),
666
+
{ }
667
+
};
668
+
669
+
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
670
+
.cmd_rcgr = 0x8004,
671
+
.mnd_width = 8,
672
+
.hid_width = 5,
673
+
.parent_map = cam_cc_parent_map_1,
674
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
675
+
.clkr.hw.init = &(const struct clk_init_data) {
676
+
.name = "cam_cc_mclk0_clk_src",
677
+
.parent_data = cam_cc_parent_data_1,
678
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
679
+
.flags = CLK_SET_RATE_PARENT,
680
+
.ops = &clk_rcg2_shared_ops,
681
+
},
682
+
};
683
+
684
+
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
685
+
.cmd_rcgr = 0x8024,
686
+
.mnd_width = 8,
687
+
.hid_width = 5,
688
+
.parent_map = cam_cc_parent_map_1,
689
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
690
+
.clkr.hw.init = &(const struct clk_init_data) {
691
+
.name = "cam_cc_mclk1_clk_src",
692
+
.parent_data = cam_cc_parent_data_1,
693
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
694
+
.flags = CLK_SET_RATE_PARENT,
695
+
.ops = &clk_rcg2_shared_ops,
696
+
},
697
+
};
698
+
699
+
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
700
+
.cmd_rcgr = 0x8044,
701
+
.mnd_width = 8,
702
+
.hid_width = 5,
703
+
.parent_map = cam_cc_parent_map_1,
704
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
705
+
.clkr.hw.init = &(const struct clk_init_data) {
706
+
.name = "cam_cc_mclk2_clk_src",
707
+
.parent_data = cam_cc_parent_data_1,
708
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
709
+
.flags = CLK_SET_RATE_PARENT,
710
+
.ops = &clk_rcg2_shared_ops,
711
+
},
712
+
};
713
+
714
+
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
715
+
.cmd_rcgr = 0x8064,
716
+
.mnd_width = 8,
717
+
.hid_width = 5,
718
+
.parent_map = cam_cc_parent_map_1,
719
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
720
+
.clkr.hw.init = &(const struct clk_init_data) {
721
+
.name = "cam_cc_mclk3_clk_src",
722
+
.parent_data = cam_cc_parent_data_1,
723
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
724
+
.flags = CLK_SET_RATE_PARENT,
725
+
.ops = &clk_rcg2_shared_ops,
726
+
},
727
+
};
728
+
729
+
static const struct freq_tbl ftbl_cam_cc_ope_0_clk_src[] = {
730
+
F(19200000, P_BI_TCXO, 1, 0, 0),
731
+
F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
732
+
F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
733
+
F(460000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
734
+
F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
735
+
F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
736
+
{ }
737
+
};
738
+
739
+
static struct clk_rcg2 cam_cc_ope_0_clk_src = {
740
+
.cmd_rcgr = 0xb004,
741
+
.mnd_width = 0,
742
+
.hid_width = 5,
743
+
.parent_map = cam_cc_parent_map_7,
744
+
.freq_tbl = ftbl_cam_cc_ope_0_clk_src,
745
+
.clkr.hw.init = &(const struct clk_init_data) {
746
+
.name = "cam_cc_ope_0_clk_src",
747
+
.parent_data = cam_cc_parent_data_7,
748
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
749
+
.flags = CLK_SET_RATE_PARENT,
750
+
.ops = &clk_rcg2_shared_ops,
751
+
},
752
+
};
753
+
754
+
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
755
+
F(19200000, P_BI_TCXO, 1, 0, 0),
756
+
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
757
+
{ }
758
+
};
759
+
760
+
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
761
+
.cmd_rcgr = 0xa048,
762
+
.mnd_width = 0,
763
+
.hid_width = 5,
764
+
.parent_map = cam_cc_parent_map_0,
765
+
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
766
+
.clkr.hw.init = &(const struct clk_init_data) {
767
+
.name = "cam_cc_slow_ahb_clk_src",
768
+
.parent_data = cam_cc_parent_data_0,
769
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
770
+
.flags = CLK_SET_RATE_PARENT,
771
+
.ops = &clk_rcg2_shared_ops,
772
+
},
773
+
};
774
+
775
+
static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = {
776
+
F(19200000, P_BI_TCXO, 1, 0, 0),
777
+
F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
778
+
F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
779
+
F(548000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
780
+
F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
781
+
{ }
782
+
};
783
+
784
+
static struct clk_rcg2 cam_cc_tfe_0_clk_src = {
785
+
.cmd_rcgr = 0xc004,
786
+
.mnd_width = 0,
787
+
.hid_width = 5,
788
+
.parent_map = cam_cc_parent_map_3,
789
+
.freq_tbl = ftbl_cam_cc_tfe_0_clk_src,
790
+
.clkr.hw.init = &(const struct clk_init_data) {
791
+
.name = "cam_cc_tfe_0_clk_src",
792
+
.parent_data = cam_cc_parent_data_3,
793
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
794
+
.flags = CLK_SET_RATE_PARENT,
795
+
.ops = &clk_rcg2_shared_ops,
796
+
},
797
+
};
798
+
799
+
static struct clk_rcg2 cam_cc_tfe_0_csid_clk_src = {
800
+
.cmd_rcgr = 0xc02c,
801
+
.mnd_width = 0,
802
+
.hid_width = 5,
803
+
.parent_map = cam_cc_parent_map_0,
804
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
805
+
.clkr.hw.init = &(const struct clk_init_data) {
806
+
.name = "cam_cc_tfe_0_csid_clk_src",
807
+
.parent_data = cam_cc_parent_data_0,
808
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
809
+
.flags = CLK_SET_RATE_PARENT,
810
+
.ops = &clk_rcg2_shared_ops,
811
+
},
812
+
};
813
+
814
+
static struct clk_rcg2 cam_cc_tfe_1_clk_src = {
815
+
.cmd_rcgr = 0xd004,
816
+
.mnd_width = 0,
817
+
.hid_width = 5,
818
+
.parent_map = cam_cc_parent_map_3,
819
+
.freq_tbl = ftbl_cam_cc_tfe_0_clk_src,
820
+
.clkr.hw.init = &(const struct clk_init_data) {
821
+
.name = "cam_cc_tfe_1_clk_src",
822
+
.parent_data = cam_cc_parent_data_3,
823
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
824
+
.flags = CLK_SET_RATE_PARENT,
825
+
.ops = &clk_rcg2_shared_ops,
826
+
},
827
+
};
828
+
829
+
static struct clk_rcg2 cam_cc_tfe_1_csid_clk_src = {
830
+
.cmd_rcgr = 0xd024,
831
+
.mnd_width = 0,
832
+
.hid_width = 5,
833
+
.parent_map = cam_cc_parent_map_0,
834
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
835
+
.clkr.hw.init = &(const struct clk_init_data) {
836
+
.name = "cam_cc_tfe_1_csid_clk_src",
837
+
.parent_data = cam_cc_parent_data_0,
838
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
839
+
.flags = CLK_SET_RATE_PARENT,
840
+
.ops = &clk_rcg2_shared_ops,
841
+
},
842
+
};
843
+
844
+
static struct clk_branch cam_cc_bps_ahb_clk = {
845
+
.halt_reg = 0xa060,
846
+
.halt_check = BRANCH_HALT,
847
+
.clkr = {
848
+
.enable_reg = 0xa060,
849
+
.enable_mask = BIT(0),
850
+
.hw.init = &(const struct clk_init_data) {
851
+
.name = "cam_cc_bps_ahb_clk",
852
+
.parent_hws = (const struct clk_hw*[]) {
853
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
854
+
},
855
+
.num_parents = 1,
856
+
.flags = CLK_SET_RATE_PARENT,
857
+
.ops = &clk_branch2_ops,
858
+
},
859
+
},
860
+
};
861
+
862
+
static struct clk_branch cam_cc_bps_areg_clk = {
863
+
.halt_reg = 0xa044,
864
+
.halt_check = BRANCH_HALT,
865
+
.clkr = {
866
+
.enable_reg = 0xa044,
867
+
.enable_mask = BIT(0),
868
+
.hw.init = &(const struct clk_init_data) {
869
+
.name = "cam_cc_bps_areg_clk",
870
+
.parent_hws = (const struct clk_hw*[]) {
871
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
872
+
},
873
+
.num_parents = 1,
874
+
.flags = CLK_SET_RATE_PARENT,
875
+
.ops = &clk_branch2_ops,
876
+
},
877
+
},
878
+
};
879
+
880
+
static struct clk_branch cam_cc_bps_clk = {
881
+
.halt_reg = 0xa01c,
882
+
.halt_check = BRANCH_HALT,
883
+
.clkr = {
884
+
.enable_reg = 0xa01c,
885
+
.enable_mask = BIT(0),
886
+
.hw.init = &(const struct clk_init_data) {
887
+
.name = "cam_cc_bps_clk",
888
+
.parent_hws = (const struct clk_hw*[]) {
889
+
&cam_cc_bps_clk_src.clkr.hw,
890
+
},
891
+
.num_parents = 1,
892
+
.flags = CLK_SET_RATE_PARENT,
893
+
.ops = &clk_branch2_ops,
894
+
},
895
+
},
896
+
};
897
+
898
+
static struct clk_branch cam_cc_camnoc_atb_clk = {
899
+
.halt_reg = 0x13034,
900
+
.halt_check = BRANCH_HALT,
901
+
.clkr = {
902
+
.enable_reg = 0x13034,
903
+
.enable_mask = BIT(0),
904
+
.hw.init = &(const struct clk_init_data) {
905
+
.name = "cam_cc_camnoc_atb_clk",
906
+
.ops = &clk_branch2_ops,
907
+
},
908
+
},
909
+
};
910
+
911
+
static struct clk_branch cam_cc_camnoc_axi_clk = {
912
+
.halt_reg = 0x1302c,
913
+
.halt_check = BRANCH_HALT,
914
+
.clkr = {
915
+
.enable_reg = 0x1302c,
916
+
.enable_mask = BIT(0),
917
+
.hw.init = &(const struct clk_init_data) {
918
+
.name = "cam_cc_camnoc_axi_clk",
919
+
.parent_hws = (const struct clk_hw*[]) {
920
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
921
+
},
922
+
.num_parents = 1,
923
+
.flags = CLK_SET_RATE_PARENT,
924
+
.ops = &clk_branch2_ops,
925
+
},
926
+
},
927
+
};
928
+
929
+
static struct clk_branch cam_cc_camnoc_axi_hf_clk = {
930
+
.halt_reg = 0x1300c,
931
+
.halt_check = BRANCH_HALT,
932
+
.clkr = {
933
+
.enable_reg = 0x1300c,
934
+
.enable_mask = BIT(0),
935
+
.hw.init = &(const struct clk_init_data) {
936
+
.name = "cam_cc_camnoc_axi_hf_clk",
937
+
.ops = &clk_branch2_ops,
938
+
},
939
+
},
940
+
};
941
+
942
+
static struct clk_branch cam_cc_camnoc_axi_sf_clk = {
943
+
.halt_reg = 0x13004,
944
+
.halt_check = BRANCH_HALT,
945
+
.clkr = {
946
+
.enable_reg = 0x13004,
947
+
.enable_mask = BIT(0),
948
+
.hw.init = &(const struct clk_init_data) {
949
+
.name = "cam_cc_camnoc_axi_sf_clk",
950
+
.ops = &clk_branch2_ops,
951
+
},
952
+
},
953
+
};
954
+
955
+
static struct clk_branch cam_cc_cci_0_clk = {
956
+
.halt_reg = 0x1001c,
957
+
.halt_check = BRANCH_HALT,
958
+
.clkr = {
959
+
.enable_reg = 0x1001c,
960
+
.enable_mask = BIT(0),
961
+
.hw.init = &(const struct clk_init_data) {
962
+
.name = "cam_cc_cci_0_clk",
963
+
.parent_hws = (const struct clk_hw*[]) {
964
+
&cam_cc_cci_0_clk_src.clkr.hw,
965
+
},
966
+
.num_parents = 1,
967
+
.flags = CLK_SET_RATE_PARENT,
968
+
.ops = &clk_branch2_ops,
969
+
},
970
+
},
971
+
};
972
+
973
+
static struct clk_branch cam_cc_cci_1_clk = {
974
+
.halt_reg = 0x1101c,
975
+
.halt_check = BRANCH_HALT,
976
+
.clkr = {
977
+
.enable_reg = 0x1101c,
978
+
.enable_mask = BIT(0),
979
+
.hw.init = &(const struct clk_init_data) {
980
+
.name = "cam_cc_cci_1_clk",
981
+
.parent_hws = (const struct clk_hw*[]) {
982
+
&cam_cc_cci_1_clk_src.clkr.hw,
983
+
},
984
+
.num_parents = 1,
985
+
.flags = CLK_SET_RATE_PARENT,
986
+
.ops = &clk_branch2_ops,
987
+
},
988
+
},
989
+
};
990
+
991
+
static struct clk_branch cam_cc_core_ahb_clk = {
992
+
.halt_reg = 0x1401c,
993
+
.halt_check = BRANCH_HALT_DELAY,
994
+
.clkr = {
995
+
.enable_reg = 0x1401c,
996
+
.enable_mask = BIT(0),
997
+
.hw.init = &(const struct clk_init_data) {
998
+
.name = "cam_cc_core_ahb_clk",
999
+
.parent_hws = (const struct clk_hw*[]) {
1000
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1001
+
},
1002
+
.num_parents = 1,
1003
+
.flags = CLK_SET_RATE_PARENT,
1004
+
.ops = &clk_branch2_ops,
1005
+
},
1006
+
},
1007
+
};
1008
+
1009
+
static struct clk_branch cam_cc_cpas_ahb_clk = {
1010
+
.halt_reg = 0x12004,
1011
+
.halt_check = BRANCH_HALT,
1012
+
.clkr = {
1013
+
.enable_reg = 0x12004,
1014
+
.enable_mask = BIT(0),
1015
+
.hw.init = &(const struct clk_init_data) {
1016
+
.name = "cam_cc_cpas_ahb_clk",
1017
+
.parent_hws = (const struct clk_hw*[]) {
1018
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1019
+
},
1020
+
.num_parents = 1,
1021
+
.flags = CLK_SET_RATE_PARENT,
1022
+
.ops = &clk_branch2_ops,
1023
+
},
1024
+
},
1025
+
};
1026
+
1027
+
static struct clk_branch cam_cc_cre_ahb_clk = {
1028
+
.halt_reg = 0x16020,
1029
+
.halt_check = BRANCH_HALT,
1030
+
.clkr = {
1031
+
.enable_reg = 0x16020,
1032
+
.enable_mask = BIT(0),
1033
+
.hw.init = &(const struct clk_init_data) {
1034
+
.name = "cam_cc_cre_ahb_clk",
1035
+
.parent_hws = (const struct clk_hw*[]) {
1036
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1037
+
},
1038
+
.num_parents = 1,
1039
+
.flags = CLK_SET_RATE_PARENT,
1040
+
.ops = &clk_branch2_ops,
1041
+
},
1042
+
},
1043
+
};
1044
+
1045
+
static struct clk_branch cam_cc_cre_clk = {
1046
+
.halt_reg = 0x1601c,
1047
+
.halt_check = BRANCH_HALT,
1048
+
.clkr = {
1049
+
.enable_reg = 0x1601c,
1050
+
.enable_mask = BIT(0),
1051
+
.hw.init = &(const struct clk_init_data) {
1052
+
.name = "cam_cc_cre_clk",
1053
+
.parent_hws = (const struct clk_hw*[]) {
1054
+
&cam_cc_cre_clk_src.clkr.hw,
1055
+
},
1056
+
.num_parents = 1,
1057
+
.flags = CLK_SET_RATE_PARENT,
1058
+
.ops = &clk_branch2_ops,
1059
+
},
1060
+
},
1061
+
};
1062
+
1063
+
static struct clk_branch cam_cc_csi0phytimer_clk = {
1064
+
.halt_reg = 0x901c,
1065
+
.halt_check = BRANCH_HALT,
1066
+
.clkr = {
1067
+
.enable_reg = 0x901c,
1068
+
.enable_mask = BIT(0),
1069
+
.hw.init = &(const struct clk_init_data) {
1070
+
.name = "cam_cc_csi0phytimer_clk",
1071
+
.parent_hws = (const struct clk_hw*[]) {
1072
+
&cam_cc_csi0phytimer_clk_src.clkr.hw,
1073
+
},
1074
+
.num_parents = 1,
1075
+
.flags = CLK_SET_RATE_PARENT,
1076
+
.ops = &clk_branch2_ops,
1077
+
},
1078
+
},
1079
+
};
1080
+
1081
+
static struct clk_branch cam_cc_csi1phytimer_clk = {
1082
+
.halt_reg = 0x9040,
1083
+
.halt_check = BRANCH_HALT,
1084
+
.clkr = {
1085
+
.enable_reg = 0x9040,
1086
+
.enable_mask = BIT(0),
1087
+
.hw.init = &(const struct clk_init_data) {
1088
+
.name = "cam_cc_csi1phytimer_clk",
1089
+
.parent_hws = (const struct clk_hw*[]) {
1090
+
&cam_cc_csi1phytimer_clk_src.clkr.hw,
1091
+
},
1092
+
.num_parents = 1,
1093
+
.flags = CLK_SET_RATE_PARENT,
1094
+
.ops = &clk_branch2_ops,
1095
+
},
1096
+
},
1097
+
};
1098
+
1099
+
static struct clk_branch cam_cc_csi2phytimer_clk = {
1100
+
.halt_reg = 0x9064,
1101
+
.halt_check = BRANCH_HALT,
1102
+
.clkr = {
1103
+
.enable_reg = 0x9064,
1104
+
.enable_mask = BIT(0),
1105
+
.hw.init = &(const struct clk_init_data) {
1106
+
.name = "cam_cc_csi2phytimer_clk",
1107
+
.parent_hws = (const struct clk_hw*[]) {
1108
+
&cam_cc_csi2phytimer_clk_src.clkr.hw,
1109
+
},
1110
+
.num_parents = 1,
1111
+
.flags = CLK_SET_RATE_PARENT,
1112
+
.ops = &clk_branch2_ops,
1113
+
},
1114
+
},
1115
+
};
1116
+
1117
+
static struct clk_branch cam_cc_csiphy0_clk = {
1118
+
.halt_reg = 0x9020,
1119
+
.halt_check = BRANCH_HALT,
1120
+
.clkr = {
1121
+
.enable_reg = 0x9020,
1122
+
.enable_mask = BIT(0),
1123
+
.hw.init = &(const struct clk_init_data) {
1124
+
.name = "cam_cc_csiphy0_clk",
1125
+
.parent_hws = (const struct clk_hw*[]) {
1126
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1127
+
},
1128
+
.num_parents = 1,
1129
+
.flags = CLK_SET_RATE_PARENT,
1130
+
.ops = &clk_branch2_ops,
1131
+
},
1132
+
},
1133
+
};
1134
+
1135
+
static struct clk_branch cam_cc_csiphy1_clk = {
1136
+
.halt_reg = 0x9044,
1137
+
.halt_check = BRANCH_HALT,
1138
+
.clkr = {
1139
+
.enable_reg = 0x9044,
1140
+
.enable_mask = BIT(0),
1141
+
.hw.init = &(const struct clk_init_data) {
1142
+
.name = "cam_cc_csiphy1_clk",
1143
+
.parent_hws = (const struct clk_hw*[]) {
1144
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1145
+
},
1146
+
.num_parents = 1,
1147
+
.flags = CLK_SET_RATE_PARENT,
1148
+
.ops = &clk_branch2_ops,
1149
+
},
1150
+
},
1151
+
};
1152
+
1153
+
static struct clk_branch cam_cc_csiphy2_clk = {
1154
+
.halt_reg = 0x9068,
1155
+
.halt_check = BRANCH_HALT,
1156
+
.clkr = {
1157
+
.enable_reg = 0x9068,
1158
+
.enable_mask = BIT(0),
1159
+
.hw.init = &(const struct clk_init_data) {
1160
+
.name = "cam_cc_csiphy2_clk",
1161
+
.parent_hws = (const struct clk_hw*[]) {
1162
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1163
+
},
1164
+
.num_parents = 1,
1165
+
.flags = CLK_SET_RATE_PARENT,
1166
+
.ops = &clk_branch2_ops,
1167
+
},
1168
+
},
1169
+
};
1170
+
1171
+
static struct clk_branch cam_cc_icp_atb_clk = {
1172
+
.halt_reg = 0xf004,
1173
+
.halt_check = BRANCH_HALT,
1174
+
.clkr = {
1175
+
.enable_reg = 0xf004,
1176
+
.enable_mask = BIT(0),
1177
+
.hw.init = &(const struct clk_init_data) {
1178
+
.name = "cam_cc_icp_atb_clk",
1179
+
.ops = &clk_branch2_ops,
1180
+
},
1181
+
},
1182
+
};
1183
+
1184
+
static struct clk_branch cam_cc_icp_clk = {
1185
+
.halt_reg = 0xf02c,
1186
+
.halt_check = BRANCH_HALT,
1187
+
.clkr = {
1188
+
.enable_reg = 0xf02c,
1189
+
.enable_mask = BIT(0),
1190
+
.hw.init = &(const struct clk_init_data) {
1191
+
.name = "cam_cc_icp_clk",
1192
+
.parent_hws = (const struct clk_hw*[]) {
1193
+
&cam_cc_icp_clk_src.clkr.hw,
1194
+
},
1195
+
.num_parents = 1,
1196
+
.flags = CLK_SET_RATE_PARENT,
1197
+
.ops = &clk_branch2_ops,
1198
+
},
1199
+
},
1200
+
};
1201
+
1202
+
static struct clk_branch cam_cc_icp_cti_clk = {
1203
+
.halt_reg = 0xf008,
1204
+
.halt_check = BRANCH_HALT,
1205
+
.clkr = {
1206
+
.enable_reg = 0xf008,
1207
+
.enable_mask = BIT(0),
1208
+
.hw.init = &(const struct clk_init_data) {
1209
+
.name = "cam_cc_icp_cti_clk",
1210
+
.ops = &clk_branch2_ops,
1211
+
},
1212
+
},
1213
+
};
1214
+
1215
+
static struct clk_branch cam_cc_icp_ts_clk = {
1216
+
.halt_reg = 0xf00c,
1217
+
.halt_check = BRANCH_HALT,
1218
+
.clkr = {
1219
+
.enable_reg = 0xf00c,
1220
+
.enable_mask = BIT(0),
1221
+
.hw.init = &(const struct clk_init_data) {
1222
+
.name = "cam_cc_icp_ts_clk",
1223
+
.ops = &clk_branch2_ops,
1224
+
},
1225
+
},
1226
+
};
1227
+
1228
+
static struct clk_branch cam_cc_mclk0_clk = {
1229
+
.halt_reg = 0x801c,
1230
+
.halt_check = BRANCH_HALT,
1231
+
.clkr = {
1232
+
.enable_reg = 0x801c,
1233
+
.enable_mask = BIT(0),
1234
+
.hw.init = &(const struct clk_init_data) {
1235
+
.name = "cam_cc_mclk0_clk",
1236
+
.parent_hws = (const struct clk_hw*[]) {
1237
+
&cam_cc_mclk0_clk_src.clkr.hw,
1238
+
},
1239
+
.num_parents = 1,
1240
+
.flags = CLK_SET_RATE_PARENT,
1241
+
.ops = &clk_branch2_ops,
1242
+
},
1243
+
},
1244
+
};
1245
+
1246
+
static struct clk_branch cam_cc_mclk1_clk = {
1247
+
.halt_reg = 0x803c,
1248
+
.halt_check = BRANCH_HALT,
1249
+
.clkr = {
1250
+
.enable_reg = 0x803c,
1251
+
.enable_mask = BIT(0),
1252
+
.hw.init = &(const struct clk_init_data) {
1253
+
.name = "cam_cc_mclk1_clk",
1254
+
.parent_hws = (const struct clk_hw*[]) {
1255
+
&cam_cc_mclk1_clk_src.clkr.hw,
1256
+
},
1257
+
.num_parents = 1,
1258
+
.flags = CLK_SET_RATE_PARENT,
1259
+
.ops = &clk_branch2_ops,
1260
+
},
1261
+
},
1262
+
};
1263
+
1264
+
static struct clk_branch cam_cc_mclk2_clk = {
1265
+
.halt_reg = 0x805c,
1266
+
.halt_check = BRANCH_HALT,
1267
+
.clkr = {
1268
+
.enable_reg = 0x805c,
1269
+
.enable_mask = BIT(0),
1270
+
.hw.init = &(const struct clk_init_data) {
1271
+
.name = "cam_cc_mclk2_clk",
1272
+
.parent_hws = (const struct clk_hw*[]) {
1273
+
&cam_cc_mclk2_clk_src.clkr.hw,
1274
+
},
1275
+
.num_parents = 1,
1276
+
.flags = CLK_SET_RATE_PARENT,
1277
+
.ops = &clk_branch2_ops,
1278
+
},
1279
+
},
1280
+
};
1281
+
1282
+
static struct clk_branch cam_cc_mclk3_clk = {
1283
+
.halt_reg = 0x807c,
1284
+
.halt_check = BRANCH_HALT,
1285
+
.clkr = {
1286
+
.enable_reg = 0x807c,
1287
+
.enable_mask = BIT(0),
1288
+
.hw.init = &(const struct clk_init_data) {
1289
+
.name = "cam_cc_mclk3_clk",
1290
+
.parent_hws = (const struct clk_hw*[]) {
1291
+
&cam_cc_mclk3_clk_src.clkr.hw,
1292
+
},
1293
+
.num_parents = 1,
1294
+
.flags = CLK_SET_RATE_PARENT,
1295
+
.ops = &clk_branch2_ops,
1296
+
},
1297
+
},
1298
+
};
1299
+
1300
+
static struct clk_branch cam_cc_ope_0_ahb_clk = {
1301
+
.halt_reg = 0xb030,
1302
+
.halt_check = BRANCH_HALT,
1303
+
.clkr = {
1304
+
.enable_reg = 0xb030,
1305
+
.enable_mask = BIT(0),
1306
+
.hw.init = &(const struct clk_init_data) {
1307
+
.name = "cam_cc_ope_0_ahb_clk",
1308
+
.parent_hws = (const struct clk_hw*[]) {
1309
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1310
+
},
1311
+
.num_parents = 1,
1312
+
.flags = CLK_SET_RATE_PARENT,
1313
+
.ops = &clk_branch2_ops,
1314
+
},
1315
+
},
1316
+
};
1317
+
1318
+
static struct clk_branch cam_cc_ope_0_areg_clk = {
1319
+
.halt_reg = 0xb02c,
1320
+
.halt_check = BRANCH_HALT,
1321
+
.clkr = {
1322
+
.enable_reg = 0xb02c,
1323
+
.enable_mask = BIT(0),
1324
+
.hw.init = &(const struct clk_init_data) {
1325
+
.name = "cam_cc_ope_0_areg_clk",
1326
+
.parent_hws = (const struct clk_hw*[]) {
1327
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1328
+
},
1329
+
.num_parents = 1,
1330
+
.flags = CLK_SET_RATE_PARENT,
1331
+
.ops = &clk_branch2_ops,
1332
+
},
1333
+
},
1334
+
};
1335
+
1336
+
static struct clk_branch cam_cc_ope_0_clk = {
1337
+
.halt_reg = 0xb01c,
1338
+
.halt_check = BRANCH_HALT,
1339
+
.clkr = {
1340
+
.enable_reg = 0xb01c,
1341
+
.enable_mask = BIT(0),
1342
+
.hw.init = &(const struct clk_init_data) {
1343
+
.name = "cam_cc_ope_0_clk",
1344
+
.parent_hws = (const struct clk_hw*[]) {
1345
+
&cam_cc_ope_0_clk_src.clkr.hw,
1346
+
},
1347
+
.num_parents = 1,
1348
+
.flags = CLK_SET_RATE_PARENT,
1349
+
.ops = &clk_branch2_ops,
1350
+
},
1351
+
},
1352
+
};
1353
+
1354
+
static struct clk_branch cam_cc_soc_ahb_clk = {
1355
+
.halt_reg = 0x14018,
1356
+
.halt_check = BRANCH_HALT,
1357
+
.clkr = {
1358
+
.enable_reg = 0x14018,
1359
+
.enable_mask = BIT(0),
1360
+
.hw.init = &(const struct clk_init_data) {
1361
+
.name = "cam_cc_soc_ahb_clk",
1362
+
.ops = &clk_branch2_ops,
1363
+
},
1364
+
},
1365
+
};
1366
+
1367
+
static struct clk_branch cam_cc_sys_tmr_clk = {
1368
+
.halt_reg = 0xf034,
1369
+
.halt_check = BRANCH_HALT,
1370
+
.clkr = {
1371
+
.enable_reg = 0xf034,
1372
+
.enable_mask = BIT(0),
1373
+
.hw.init = &(const struct clk_init_data) {
1374
+
.name = "cam_cc_sys_tmr_clk",
1375
+
.ops = &clk_branch2_ops,
1376
+
},
1377
+
},
1378
+
};
1379
+
1380
+
static struct clk_branch cam_cc_tfe_0_ahb_clk = {
1381
+
.halt_reg = 0xc070,
1382
+
.halt_check = BRANCH_HALT,
1383
+
.clkr = {
1384
+
.enable_reg = 0xc070,
1385
+
.enable_mask = BIT(0),
1386
+
.hw.init = &(const struct clk_init_data) {
1387
+
.name = "cam_cc_tfe_0_ahb_clk",
1388
+
.parent_hws = (const struct clk_hw*[]) {
1389
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1390
+
},
1391
+
.num_parents = 1,
1392
+
.flags = CLK_SET_RATE_PARENT,
1393
+
.ops = &clk_branch2_ops,
1394
+
},
1395
+
},
1396
+
};
1397
+
1398
+
static struct clk_branch cam_cc_tfe_0_clk = {
1399
+
.halt_reg = 0xc01c,
1400
+
.halt_check = BRANCH_HALT,
1401
+
.clkr = {
1402
+
.enable_reg = 0xc01c,
1403
+
.enable_mask = BIT(0),
1404
+
.hw.init = &(const struct clk_init_data) {
1405
+
.name = "cam_cc_tfe_0_clk",
1406
+
.parent_hws = (const struct clk_hw*[]) {
1407
+
&cam_cc_tfe_0_clk_src.clkr.hw,
1408
+
},
1409
+
.num_parents = 1,
1410
+
.flags = CLK_SET_RATE_PARENT,
1411
+
.ops = &clk_branch2_ops,
1412
+
},
1413
+
},
1414
+
};
1415
+
1416
+
static struct clk_branch cam_cc_tfe_0_cphy_rx_clk = {
1417
+
.halt_reg = 0xc06c,
1418
+
.halt_check = BRANCH_HALT,
1419
+
.clkr = {
1420
+
.enable_reg = 0xc06c,
1421
+
.enable_mask = BIT(0),
1422
+
.hw.init = &(const struct clk_init_data) {
1423
+
.name = "cam_cc_tfe_0_cphy_rx_clk",
1424
+
.parent_hws = (const struct clk_hw*[]) {
1425
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1426
+
},
1427
+
.num_parents = 1,
1428
+
.flags = CLK_SET_RATE_PARENT,
1429
+
.ops = &clk_branch2_ops,
1430
+
},
1431
+
},
1432
+
};
1433
+
1434
+
static struct clk_branch cam_cc_tfe_0_csid_clk = {
1435
+
.halt_reg = 0xc044,
1436
+
.halt_check = BRANCH_HALT,
1437
+
.clkr = {
1438
+
.enable_reg = 0xc044,
1439
+
.enable_mask = BIT(0),
1440
+
.hw.init = &(const struct clk_init_data) {
1441
+
.name = "cam_cc_tfe_0_csid_clk",
1442
+
.parent_hws = (const struct clk_hw*[]) {
1443
+
&cam_cc_tfe_0_csid_clk_src.clkr.hw,
1444
+
},
1445
+
.num_parents = 1,
1446
+
.flags = CLK_SET_RATE_PARENT,
1447
+
.ops = &clk_branch2_ops,
1448
+
},
1449
+
},
1450
+
};
1451
+
1452
+
static struct clk_branch cam_cc_tfe_1_ahb_clk = {
1453
+
.halt_reg = 0xd048,
1454
+
.halt_check = BRANCH_HALT,
1455
+
.clkr = {
1456
+
.enable_reg = 0xd048,
1457
+
.enable_mask = BIT(0),
1458
+
.hw.init = &(const struct clk_init_data) {
1459
+
.name = "cam_cc_tfe_1_ahb_clk",
1460
+
.parent_hws = (const struct clk_hw*[]) {
1461
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1462
+
},
1463
+
.num_parents = 1,
1464
+
.flags = CLK_SET_RATE_PARENT,
1465
+
.ops = &clk_branch2_ops,
1466
+
},
1467
+
},
1468
+
};
1469
+
1470
+
static struct clk_branch cam_cc_tfe_1_clk = {
1471
+
.halt_reg = 0xd01c,
1472
+
.halt_check = BRANCH_HALT,
1473
+
.clkr = {
1474
+
.enable_reg = 0xd01c,
1475
+
.enable_mask = BIT(0),
1476
+
.hw.init = &(const struct clk_init_data) {
1477
+
.name = "cam_cc_tfe_1_clk",
1478
+
.parent_hws = (const struct clk_hw*[]) {
1479
+
&cam_cc_tfe_1_clk_src.clkr.hw,
1480
+
},
1481
+
.num_parents = 1,
1482
+
.flags = CLK_SET_RATE_PARENT,
1483
+
.ops = &clk_branch2_ops,
1484
+
},
1485
+
},
1486
+
};
1487
+
1488
+
static struct clk_branch cam_cc_tfe_1_cphy_rx_clk = {
1489
+
.halt_reg = 0xd044,
1490
+
.halt_check = BRANCH_HALT,
1491
+
.clkr = {
1492
+
.enable_reg = 0xd044,
1493
+
.enable_mask = BIT(0),
1494
+
.hw.init = &(const struct clk_init_data) {
1495
+
.name = "cam_cc_tfe_1_cphy_rx_clk",
1496
+
.parent_hws = (const struct clk_hw*[]) {
1497
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1498
+
},
1499
+
.num_parents = 1,
1500
+
.flags = CLK_SET_RATE_PARENT,
1501
+
.ops = &clk_branch2_ops,
1502
+
},
1503
+
},
1504
+
};
1505
+
1506
+
static struct clk_branch cam_cc_tfe_1_csid_clk = {
1507
+
.halt_reg = 0xd03c,
1508
+
.halt_check = BRANCH_HALT,
1509
+
.clkr = {
1510
+
.enable_reg = 0xd03c,
1511
+
.enable_mask = BIT(0),
1512
+
.hw.init = &(const struct clk_init_data) {
1513
+
.name = "cam_cc_tfe_1_csid_clk",
1514
+
.parent_hws = (const struct clk_hw*[]) {
1515
+
&cam_cc_tfe_1_csid_clk_src.clkr.hw,
1516
+
},
1517
+
.num_parents = 1,
1518
+
.flags = CLK_SET_RATE_PARENT,
1519
+
.ops = &clk_branch2_ops,
1520
+
},
1521
+
},
1522
+
};
1523
+
1524
+
static struct gdsc cam_cc_camss_top_gdsc = {
1525
+
.gdscr = 0x14004,
1526
+
.en_rest_wait_val = 0x2,
1527
+
.en_few_wait_val = 0x2,
1528
+
.clk_dis_wait_val = 0xf,
1529
+
.pd = {
1530
+
.name = "cam_cc_camss_top_gdsc",
1531
+
},
1532
+
.pwrsts = PWRSTS_OFF_ON,
1533
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1534
+
};
1535
+
1536
+
static struct clk_regmap *cam_cc_sm4450_clocks[] = {
1537
+
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
1538
+
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
1539
+
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
1540
+
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
1541
+
[CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr,
1542
+
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1543
+
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
1544
+
[CAM_CC_CAMNOC_AXI_HF_CLK] = &cam_cc_camnoc_axi_hf_clk.clkr,
1545
+
[CAM_CC_CAMNOC_AXI_SF_CLK] = &cam_cc_camnoc_axi_sf_clk.clkr,
1546
+
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
1547
+
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
1548
+
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
1549
+
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
1550
+
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
1551
+
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1552
+
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1553
+
[CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
1554
+
[CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
1555
+
[CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
1556
+
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1557
+
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1558
+
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1559
+
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1560
+
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1561
+
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1562
+
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1563
+
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1564
+
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1565
+
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
1566
+
[CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr,
1567
+
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
1568
+
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
1569
+
[CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr,
1570
+
[CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr,
1571
+
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
1572
+
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
1573
+
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
1574
+
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
1575
+
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
1576
+
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
1577
+
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
1578
+
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
1579
+
[CAM_CC_OPE_0_AHB_CLK] = &cam_cc_ope_0_ahb_clk.clkr,
1580
+
[CAM_CC_OPE_0_AREG_CLK] = &cam_cc_ope_0_areg_clk.clkr,
1581
+
[CAM_CC_OPE_0_CLK] = &cam_cc_ope_0_clk.clkr,
1582
+
[CAM_CC_OPE_0_CLK_SRC] = &cam_cc_ope_0_clk_src.clkr,
1583
+
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1584
+
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
1585
+
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
1586
+
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
1587
+
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
1588
+
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1589
+
[CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr,
1590
+
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1591
+
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
1592
+
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
1593
+
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
1594
+
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1595
+
[CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
1596
+
[CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
1597
+
[CAM_CC_TFE_0_AHB_CLK] = &cam_cc_tfe_0_ahb_clk.clkr,
1598
+
[CAM_CC_TFE_0_CLK] = &cam_cc_tfe_0_clk.clkr,
1599
+
[CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr,
1600
+
[CAM_CC_TFE_0_CPHY_RX_CLK] = &cam_cc_tfe_0_cphy_rx_clk.clkr,
1601
+
[CAM_CC_TFE_0_CSID_CLK] = &cam_cc_tfe_0_csid_clk.clkr,
1602
+
[CAM_CC_TFE_0_CSID_CLK_SRC] = &cam_cc_tfe_0_csid_clk_src.clkr,
1603
+
[CAM_CC_TFE_1_AHB_CLK] = &cam_cc_tfe_1_ahb_clk.clkr,
1604
+
[CAM_CC_TFE_1_CLK] = &cam_cc_tfe_1_clk.clkr,
1605
+
[CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr,
1606
+
[CAM_CC_TFE_1_CPHY_RX_CLK] = &cam_cc_tfe_1_cphy_rx_clk.clkr,
1607
+
[CAM_CC_TFE_1_CSID_CLK] = &cam_cc_tfe_1_csid_clk.clkr,
1608
+
[CAM_CC_TFE_1_CSID_CLK_SRC] = &cam_cc_tfe_1_csid_clk_src.clkr,
1609
+
};
1610
+
1611
+
static struct gdsc *cam_cc_sm4450_gdscs[] = {
1612
+
[CAM_CC_CAMSS_TOP_GDSC] = &cam_cc_camss_top_gdsc,
1613
+
};
1614
+
1615
+
static const struct qcom_reset_map cam_cc_sm4450_resets[] = {
1616
+
[CAM_CC_BPS_BCR] = { 0xa000 },
1617
+
[CAM_CC_CAMNOC_BCR] = { 0x13000 },
1618
+
[CAM_CC_CAMSS_TOP_BCR] = { 0x14000 },
1619
+
[CAM_CC_CCI_0_BCR] = { 0x10000 },
1620
+
[CAM_CC_CCI_1_BCR] = { 0x11000 },
1621
+
[CAM_CC_CPAS_BCR] = { 0x12000 },
1622
+
[CAM_CC_CRE_BCR] = { 0x16000 },
1623
+
[CAM_CC_CSI0PHY_BCR] = { 0x9000 },
1624
+
[CAM_CC_CSI1PHY_BCR] = { 0x9024 },
1625
+
[CAM_CC_CSI2PHY_BCR] = { 0x9048 },
1626
+
[CAM_CC_ICP_BCR] = { 0xf000 },
1627
+
[CAM_CC_MCLK0_BCR] = { 0x8000 },
1628
+
[CAM_CC_MCLK1_BCR] = { 0x8020 },
1629
+
[CAM_CC_MCLK2_BCR] = { 0x8040 },
1630
+
[CAM_CC_MCLK3_BCR] = { 0x8060 },
1631
+
[CAM_CC_OPE_0_BCR] = { 0xb000 },
1632
+
[CAM_CC_TFE_0_BCR] = { 0xc000 },
1633
+
[CAM_CC_TFE_1_BCR] = { 0xd000 },
1634
+
};
1635
+
1636
+
static const struct regmap_config cam_cc_sm4450_regmap_config = {
1637
+
.reg_bits = 32,
1638
+
.reg_stride = 4,
1639
+
.val_bits = 32,
1640
+
.max_register = 0x16024,
1641
+
.fast_io = true,
1642
+
};
1643
+
1644
+
static struct qcom_cc_desc cam_cc_sm4450_desc = {
1645
+
.config = &cam_cc_sm4450_regmap_config,
1646
+
.clks = cam_cc_sm4450_clocks,
1647
+
.num_clks = ARRAY_SIZE(cam_cc_sm4450_clocks),
1648
+
.resets = cam_cc_sm4450_resets,
1649
+
.num_resets = ARRAY_SIZE(cam_cc_sm4450_resets),
1650
+
.gdscs = cam_cc_sm4450_gdscs,
1651
+
.num_gdscs = ARRAY_SIZE(cam_cc_sm4450_gdscs),
1652
+
};
1653
+
1654
+
static const struct of_device_id cam_cc_sm4450_match_table[] = {
1655
+
{ .compatible = "qcom,sm4450-camcc" },
1656
+
{ }
1657
+
};
1658
+
MODULE_DEVICE_TABLE(of, cam_cc_sm4450_match_table);
1659
+
1660
+
static int cam_cc_sm4450_probe(struct platform_device *pdev)
1661
+
{
1662
+
struct regmap *regmap;
1663
+
1664
+
regmap = qcom_cc_map(pdev, &cam_cc_sm4450_desc);
1665
+
if (IS_ERR(regmap))
1666
+
return PTR_ERR(regmap);
1667
+
1668
+
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
1669
+
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
1670
+
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
1671
+
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
1672
+
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
1673
+
1674
+
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm4450_desc, regmap);
1675
+
}
1676
+
1677
+
static struct platform_driver cam_cc_sm4450_driver = {
1678
+
.probe = cam_cc_sm4450_probe,
1679
+
.driver = {
1680
+
.name = "camcc-sm4450",
1681
+
.of_match_table = cam_cc_sm4450_match_table,
1682
+
},
1683
+
};
1684
+
1685
+
module_platform_driver(cam_cc_sm4450_driver);
1686
+
1687
+
MODULE_DESCRIPTION("QTI CAMCC SM4450 Driver");
1688
+
MODULE_LICENSE("GPL");