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memory: tegra: Add support for DBB clock on Tegra264

The DBB clock is needed by many IP blocks in order to access system
memory via the data backbone. The memory controller and external memory
controllers are the central place where these accesses are managed, so
make sure that the clock can be controlled from the corresponding
driver.

Note that not all drivers fully register bandwidth requests, and hence
the EMC driver doesn't have enough information to know when it's safe to
switch the clock off, so for now it will be kept on permanently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260116123732.140813-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

authored by

Thierry Reding and committed by
Krzysztof Kozlowski ef4d7b99 6de23f81

+8
+8
drivers/memory/tegra/tegra186-emc.c
··· 22 22 struct tegra_bpmp *bpmp; 23 23 struct device *dev; 24 24 struct clk *clk; 25 + struct clk *clk_dbb; 25 26 26 27 struct tegra186_emc_dvfs *dvfs; 27 28 unsigned int num_dvfs; ··· 326 325 if (IS_ERR(emc->clk)) { 327 326 err = dev_err_probe(&pdev->dev, PTR_ERR(emc->clk), 328 327 "failed to get EMC clock\n"); 328 + goto put_bpmp; 329 + } 330 + 331 + emc->clk_dbb = devm_clk_get_optional_enabled(&pdev->dev, "dbb"); 332 + if (IS_ERR(emc->clk_dbb)) { 333 + err = dev_err_probe(&pdev->dev, PTR_ERR(emc->clk_dbb), 334 + "failed to get DBB clock\n"); 329 335 goto put_bpmp; 330 336 } 331 337