tjh.dev / kernel
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drm/i915/lt_phy: Readout lane count

Readout lane count back from HW. Reuse existing function
for Cx0 for LT PHY case with minor modification to add
lanes as function parameters.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-20-mika.kahola@intel.com

Mika Kahola ef5aa934 7049d9a7

+9 -4
+6 -4
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 2180 2180 return 0; 2181 2181 } 2182 2182 2183 - static int readout_enabled_lane_count(struct intel_encoder *encoder) 2183 + int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1) 2184 2184 { 2185 2185 struct intel_display *display = to_intel_display(encoder); 2186 2186 u8 enabled_tx_lane_count = 0; ··· 2212 2212 max_tx_lane_count = round_up(max_tx_lane_count, 2); 2213 2213 2214 2214 for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) { 2215 - u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; 2215 + u8 phy_lane_mask = tx_lane < 2 ? lane0 : lane1; 2216 2216 int tx = tx_lane % 2 + 1; 2217 2217 u8 val; 2218 2218 ··· 2252 2252 */ 2253 2253 intel_c10_msgbus_access_begin(encoder, lane); 2254 2254 2255 - cx0pll_state->lane_count = readout_enabled_lane_count(encoder); 2255 + cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0, 2256 + INTEL_CX0_LANE1); 2256 2257 2257 2258 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) 2258 2259 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); ··· 2708 2707 2709 2708 wakeref = intel_cx0_phy_transaction_begin(encoder); 2710 2709 2711 - cx0pll_state->lane_count = readout_enabled_lane_count(encoder); 2710 + cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0, 2711 + INTEL_CX0_LANE1); 2712 2712 2713 2713 /* 1. Read VDR params and current context selection */ 2714 2714 intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
+1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
··· 28 28 void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder, 29 29 int lane); 30 30 bool intel_encoder_is_c10phy(struct intel_encoder *encoder); 31 + int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1); 31 32 void intel_mtl_pll_enable(struct intel_encoder *encoder, 32 33 struct intel_dpll *pll, 33 34 const struct intel_dpll_hw_state *dpll_hw_state);
+2
drivers/gpu/drm/i915/display/intel_lt_phy.c
··· 2232 2232 lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1; 2233 2233 wakeref = intel_lt_phy_transaction_begin(encoder); 2234 2234 2235 + pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_LT_PHY_LANE0, 2236 + INTEL_LT_PHY_LANE1); 2235 2237 pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG); 2236 2238 pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG); 2237 2239 pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);