tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2019-11-08' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Weekly fixes for drm: amdgpu has a few but they are pretty scattered
fixes, the fbdev one is a build regression fix that we didn't want to
risk leaving out, otherwise a couple of i915, one radeon and a core
atomic fix.

core:
- add missing documentation for GEM shmem madvise helpers
- Fix for a state dereference in atomic self-refresh helpers

fbdev:
- One compilation fix for c2p fbdev helpers

amdgpu:
- Fix navi14 display issue root cause and revert workaround
- GPU reset scheduler interaction fix
- Fix fan boost on multi-GPU
- Gfx10 and sdma5 fixes for navi
- GFXOFF fix for renoir
- Add navi14 PCI ID
- GPUVM fix for arcturus

radeon:
- Port an SI power fix from amdgpu

i915:
- Fix HPD poll to avoid kworker consuming a lot of cpu cycles.
- Do not use TBT type for non Type-C ports"

* tag 'drm-fixes-2019-11-08' of git://anongit.freedesktop.org/drm/drm:
drm/radeon: fix si_enable_smc_cac() failed issue
drm/amdgpu/renoir: move gfxoff handling into gfx9 module
drm/amdgpu: add warning for GRBM 1-cycle delay issue in gfx9
drm/amdgpu: add dummy read by engines for some GCVM status registers in gfx10
drm/amdgpu: register gpu instance before fan boost feature enablment
drm/amd/swSMU: fix smu workload bit map error
drm/shmem: Add docbook comments for drm_gem_shmem_object madvise fields
drm/amdgpu: add navi14 PCI ID
Revert "drm/amd/display: setting the DIG_MODE to the correct value."
drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14
drm/amdgpu: dont schedule jobs while in reset
drm/amdgpu/arcturus: properly set BANK_SELECT and FRAGMENT_SIZE
drm/atomic: fix self-refresh helpers crtc state dereference
drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
drm/i915: Avoid HPD poll detect triggering a new detect cycle
fbdev: c2p: Fix link failure on non-inlining

Linus Torvalds efc61f7c d988f887

+174 -38
+4 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 604 604 continue; 605 605 } 606 606 607 - for (i = 0; i < num_entities; i++) 607 + for (i = 0; i < num_entities; i++) { 608 + mutex_lock(&ctx->adev->lock_reset); 608 609 drm_sched_entity_fini(&ctx->entities[0][i].entity); 610 + mutex_unlock(&ctx->adev->lock_reset); 611 + } 609 612 } 610 613 } 611 614
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 2885 2885 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); 2886 2886 } 2887 2887 2888 + /* 2889 + * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. 2890 + * Otherwise the mgpu fan boost feature will be skipped due to the 2891 + * gpu instance is counted less. 2892 + */ 2893 + amdgpu_register_gpu_instance(adev); 2894 + 2888 2895 /* enable clockgating, etc. after ib tests, etc. since some blocks require 2889 2896 * explicit gating rather than handling it automatically. 2890 2897 */
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 1016 1016 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1017 1017 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1018 1018 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1019 + {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1019 1020 1020 1021 /* Renoir */ 1021 1022 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
··· 289 289 uint32_t mec2_feature_version; 290 290 bool mec_fw_write_wait; 291 291 bool me_fw_write_wait; 292 + bool cp_fw_write_wait; 292 293 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 293 294 unsigned num_gfx_rings; 294 295 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 190 190 pm_runtime_put_autosuspend(dev->dev); 191 191 } 192 192 193 - amdgpu_register_gpu_instance(adev); 194 193 out: 195 194 if (r) { 196 195 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+48
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 564 564 kfree(adev->gfx.rlc.register_list_format); 565 565 } 566 566 567 + static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 568 + { 569 + adev->gfx.cp_fw_write_wait = false; 570 + 571 + switch (adev->asic_type) { 572 + case CHIP_NAVI10: 573 + case CHIP_NAVI12: 574 + case CHIP_NAVI14: 575 + if ((adev->gfx.me_fw_version >= 0x00000046) && 576 + (adev->gfx.me_feature_version >= 27) && 577 + (adev->gfx.pfp_fw_version >= 0x00000068) && 578 + (adev->gfx.pfp_feature_version >= 27) && 579 + (adev->gfx.mec_fw_version >= 0x0000005b) && 580 + (adev->gfx.mec_feature_version >= 27)) 581 + adev->gfx.cp_fw_write_wait = true; 582 + break; 583 + default: 584 + break; 585 + } 586 + 587 + if (adev->gfx.cp_fw_write_wait == false) 588 + DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \ 589 + GRBM requires 1-cycle delay in cp firmware\n"); 590 + } 591 + 592 + 567 593 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 568 594 { 569 595 const struct rlc_firmware_header_v2_1 *rlc_hdr; ··· 858 832 } 859 833 } 860 834 835 + gfx_v10_0_check_fw_write_wait(adev); 861 836 out: 862 837 if (err) { 863 838 dev_err(adev->dev, ··· 4792 4765 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4793 4766 } 4794 4767 4768 + static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4769 + uint32_t reg0, uint32_t reg1, 4770 + uint32_t ref, uint32_t mask) 4771 + { 4772 + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4773 + struct amdgpu_device *adev = ring->adev; 4774 + bool fw_version_ok = false; 4775 + 4776 + fw_version_ok = adev->gfx.cp_fw_write_wait; 4777 + 4778 + if (fw_version_ok) 4779 + gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4780 + ref, mask, 0x20); 4781 + else 4782 + amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4783 + ref, mask); 4784 + } 4785 + 4795 4786 static void 4796 4787 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4797 4788 uint32_t me, uint32_t pipe, ··· 5200 5155 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5201 5156 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5202 5157 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5158 + .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5203 5159 }; 5204 5160 5205 5161 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { ··· 5234 5188 .pad_ib = amdgpu_ring_generic_pad_ib, 5235 5189 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5236 5190 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5191 + .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5237 5192 }; 5238 5193 5239 5194 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { ··· 5265 5218 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5266 5219 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5267 5220 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5221 + .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5268 5222 }; 5269 5223 5270 5224 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
+13
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 973 973 adev->gfx.me_fw_write_wait = false; 974 974 adev->gfx.mec_fw_write_wait = false; 975 975 976 + if ((adev->gfx.mec_fw_version < 0x000001a5) || 977 + (adev->gfx.mec_feature_version < 46) || 978 + (adev->gfx.pfp_fw_version < 0x000000b7) || 979 + (adev->gfx.pfp_feature_version < 46)) 980 + DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \ 981 + GRBM requires 1-cycle delay in cp firmware\n"); 982 + 976 983 switch (adev->asic_type) { 977 984 case CHIP_VEGA10: 978 985 if ((adev->gfx.me_fw_version >= 0x0000009c) && ··· 1046 1039 !adev->gfx.rlc.is_rlc_v2_1)) 1047 1040 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1048 1041 1042 + if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1043 + adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1044 + AMD_PG_SUPPORT_CP | 1045 + AMD_PG_SUPPORT_RLC_SMU_HS; 1046 + break; 1047 + case CHIP_RENOIR: 1049 1048 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1050 1049 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1051 1050 AMD_PG_SUPPORT_CP |
+3 -5
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 344 344 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 345 345 upper_32_bits(pd_addr)); 346 346 347 - amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req); 348 - 349 - /* wait for the invalidate to complete */ 350 - amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng, 351 - 1 << vmid, 1 << vmid); 347 + amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 348 + hub->vm_inv_eng0_ack + eng, 349 + req, 1 << vmid); 352 350 353 351 return pd_addr; 354 352 }
+9
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
··· 219 219 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 220 220 221 221 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT; 222 + if (adev->gmc.translate_further) { 223 + tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12); 224 + tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, 225 + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 226 + } else { 227 + tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9); 228 + tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, 229 + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 230 + } 222 231 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 223 232 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 224 233
+12 -1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1173 1173 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1174 1174 } 1175 1175 1176 + static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1177 + uint32_t reg0, uint32_t reg1, 1178 + uint32_t ref, uint32_t mask) 1179 + { 1180 + amdgpu_ring_emit_wreg(ring, reg0, ref); 1181 + /* wait for a cycle to reset vm_inv_eng*_ack */ 1182 + amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1183 + amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1184 + } 1185 + 1176 1186 static int sdma_v5_0_early_init(void *handle) 1177 1187 { 1178 1188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; ··· 1598 1588 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1599 1589 /* sdma_v5_0_ring_emit_vm_flush */ 1600 1590 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1601 - SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1591 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1602 1592 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1603 1593 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1604 1594 .emit_ib = sdma_v5_0_ring_emit_ib, ··· 1612 1602 .pad_ib = sdma_v5_0_ring_pad_ib, 1613 1603 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1614 1604 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1605 + .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1615 1606 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1616 1607 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1617 1608 .preempt_ib = sdma_v5_0_ring_preempt_ib,
-5
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 1186 1186 AMD_PG_SUPPORT_VCN | 1187 1187 AMD_PG_SUPPORT_VCN_DPG; 1188 1188 adev->external_rev_id = adev->rev_id + 0x91; 1189 - 1190 - if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1191 - adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1192 - AMD_PG_SUPPORT_CP | 1193 - AMD_PG_SUPPORT_RLC_SMU_HS; 1194 1189 break; 1195 1190 default: 1196 1191 /* FIXME: not supported yet */
-9
drivers/gpu/drm/amd/display/dc/core/dc_link.c
··· 2767 2767 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2768 2768 COLOR_DEPTH_UNDEFINED); 2769 2769 2770 - /* This second call is needed to reconfigure the DIG 2771 - * as a workaround for the incorrect value being applied 2772 - * from transmitter control. 2773 - */ 2774 - if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 2775 - stream->link->link_enc->funcs->setup( 2776 - stream->link->link_enc, 2777 - pipe_ctx->stream->signal); 2778 - 2779 2770 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 2780 2771 if (pipe_ctx->stream->timing.flags.DSC) { 2781 2772 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+5
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 1107 1107 if (!enc1) 1108 1108 return NULL; 1109 1109 1110 + if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1111 + if (eng_id >= ENGINE_ID_DIGD) 1112 + eng_id++; 1113 + } 1114 + 1110 1115 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1111 1116 &stream_enc_regs[eng_id], 1112 1117 &se_shift, &se_mask);
+1 -1
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
··· 205 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 206 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 207 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 208 - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), 208 + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 209 209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 210 210 }; 211 211
+1 -1
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
··· 219 219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 220 220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 221 221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 222 - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), 222 + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 223 223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 224 224 }; 225 225
+14 -1
drivers/gpu/drm/drm_atomic_helper.c
··· 1581 1581 { 1582 1582 struct drm_device *dev = old_state->dev; 1583 1583 const struct drm_mode_config_helper_funcs *funcs; 1584 + struct drm_crtc_state *new_crtc_state; 1585 + struct drm_crtc *crtc; 1584 1586 ktime_t start; 1585 1587 s64 commit_time_ms; 1588 + unsigned int i, new_self_refresh_mask = 0; 1586 1589 1587 1590 funcs = dev->mode_config.helper_private; 1588 1591 ··· 1605 1602 1606 1603 drm_atomic_helper_wait_for_dependencies(old_state); 1607 1604 1605 + /* 1606 + * We cannot safely access new_crtc_state after 1607 + * drm_atomic_helper_commit_hw_done() so figure out which crtc's have 1608 + * self-refresh active beforehand: 1609 + */ 1610 + for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) 1611 + if (new_crtc_state->self_refresh_active) 1612 + new_self_refresh_mask |= BIT(i); 1613 + 1608 1614 if (funcs && funcs->atomic_commit_tail) 1609 1615 funcs->atomic_commit_tail(old_state); 1610 1616 else ··· 1622 1610 commit_time_ms = ktime_ms_delta(ktime_get(), start); 1623 1611 if (commit_time_ms > 0) 1624 1612 drm_self_refresh_helper_update_avg_times(old_state, 1625 - (unsigned long)commit_time_ms); 1613 + (unsigned long)commit_time_ms, 1614 + new_self_refresh_mask); 1626 1615 1627 1616 drm_atomic_helper_commit_cleanup_done(old_state); 1628 1617
+11 -7
drivers/gpu/drm/drm_self_refresh_helper.c
··· 133 133 * drm_self_refresh_helper_update_avg_times - Updates a crtc's SR time averages 134 134 * @state: the state which has just been applied to hardware 135 135 * @commit_time_ms: the amount of time in ms that this commit took to complete 136 + * @new_self_refresh_mask: bitmask of crtc's that have self_refresh_active in 137 + * new state 136 138 * 137 139 * Called after &drm_mode_config_funcs.atomic_commit_tail, this function will 138 140 * update the average entry/exit self refresh times on self refresh transitions. 139 141 * These averages will be used when calculating how long to delay before 140 142 * entering self refresh mode after activity. 141 143 */ 142 - void drm_self_refresh_helper_update_avg_times(struct drm_atomic_state *state, 143 - unsigned int commit_time_ms) 144 + void 145 + drm_self_refresh_helper_update_avg_times(struct drm_atomic_state *state, 146 + unsigned int commit_time_ms, 147 + unsigned int new_self_refresh_mask) 144 148 { 145 149 struct drm_crtc *crtc; 146 - struct drm_crtc_state *old_crtc_state, *new_crtc_state; 150 + struct drm_crtc_state *old_crtc_state; 147 151 int i; 148 152 149 - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 150 - new_crtc_state, i) { 153 + for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { 154 + bool new_self_refresh_active = new_self_refresh_mask & BIT(i); 151 155 struct drm_self_refresh_data *sr_data = crtc->self_refresh_data; 152 156 struct ewma_psr_time *time; 153 157 154 158 if (old_crtc_state->self_refresh_active == 155 - new_crtc_state->self_refresh_active) 159 + new_self_refresh_active) 156 160 continue; 157 161 158 - if (new_crtc_state->self_refresh_active) 162 + if (new_self_refresh_active) 159 163 time = &sr_data->entry_avg_ms; 160 164 else 161 165 time = &sr_data->exit_avg_ms;
+7
drivers/gpu/drm/i915/display/intel_crt.c
··· 864 864 865 865 out: 866 866 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 867 + 868 + /* 869 + * Make sure the refs for power wells enabled during detect are 870 + * dropped to avoid a new detect cycle triggered by HPD polling. 871 + */ 872 + intel_display_power_flush_work(dev_priv); 873 + 867 874 return status; 868 875 } 869 876
+11 -1
drivers/gpu/drm/i915/display/intel_dp.c
··· 1256 1256 u32 unused) 1257 1257 { 1258 1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1259 + struct drm_i915_private *i915 = 1260 + to_i915(intel_dig_port->base.base.dev); 1261 + enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); 1259 1262 u32 ret; 1260 1263 1261 1264 ret = DP_AUX_CH_CTL_SEND_BUSY | ··· 1271 1268 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 1272 1269 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 1273 1270 1274 - if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 1271 + if (intel_phy_is_tc(i915, phy) && 1272 + intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 1275 1273 ret |= DP_AUX_CH_CTL_TBT_IO; 1276 1274 1277 1275 return ret; ··· 5439 5435 out: 5440 5436 if (status != connector_status_connected && !intel_dp->is_mst) 5441 5437 intel_dp_unset_edid(intel_dp); 5438 + 5439 + /* 5440 + * Make sure the refs for power wells enabled during detect are 5441 + * dropped to avoid a new detect cycle triggered by HPD polling. 5442 + */ 5443 + intel_display_power_flush_work(dev_priv); 5442 5444 5443 5445 return status; 5444 5446 }
+6
drivers/gpu/drm/i915/display/intel_hdmi.c
··· 2565 2565 if (status != connector_status_connected) 2566 2566 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2567 2567 2568 + /* 2569 + * Make sure the refs for power wells enabled during detect are 2570 + * dropped to avoid a new detect cycle triggered by HPD polling. 2571 + */ 2572 + intel_display_power_flush_work(dev_priv); 2573 + 2568 2574 return status; 2569 2575 } 2570 2576
+1
drivers/gpu/drm/radeon/si_dpm.c
··· 1958 1958 case 0x682C: 1959 1959 si_pi->cac_weights = cac_weights_cape_verde_pro; 1960 1960 si_pi->dte_data = dte_data_sun_xt; 1961 + update_dte_from_pl2 = true; 1961 1962 break; 1962 1963 case 0x6825: 1963 1964 case 0x6827:
+4 -4
drivers/video/fbdev/c2p_core.h
··· 29 29 30 30 extern void c2p_unsupported(void); 31 31 32 - static inline u32 get_mask(unsigned int n) 32 + static __always_inline u32 get_mask(unsigned int n) 33 33 { 34 34 switch (n) { 35 35 case 1: ··· 57 57 * Transpose operations on 8 32-bit words 58 58 */ 59 59 60 - static inline void transp8(u32 d[], unsigned int n, unsigned int m) 60 + static __always_inline void transp8(u32 d[], unsigned int n, unsigned int m) 61 61 { 62 62 u32 mask = get_mask(n); 63 63 ··· 99 99 * Transpose operations on 4 32-bit words 100 100 */ 101 101 102 - static inline void transp4(u32 d[], unsigned int n, unsigned int m) 102 + static __always_inline void transp4(u32 d[], unsigned int n, unsigned int m) 103 103 { 104 104 u32 mask = get_mask(n); 105 105 ··· 126 126 * Transpose operations on 4 32-bit words (reverse order) 127 127 */ 128 128 129 - static inline void transp4x(u32 d[], unsigned int n, unsigned int m) 129 + static __always_inline void transp4x(u32 d[], unsigned int n, unsigned int m) 130 130 { 131 131 u32 mask = get_mask(n); 132 132
+13
include/drm/drm_gem_shmem_helper.h
··· 44 44 */ 45 45 unsigned int pages_use_count; 46 46 47 + /** 48 + * @madv: State for madvise 49 + * 50 + * 0 is active/inuse. 51 + * A negative value is the object is purged. 52 + * Positive values are driver specific and not used by the helpers. 53 + */ 47 54 int madv; 55 + 56 + /** 57 + * @madv_list: List entry for madvise tracking 58 + * 59 + * Typically used by drivers to track purgeable objects 60 + */ 48 61 struct list_head madv_list; 49 62 50 63 /**
+2 -1
include/drm/drm_self_refresh_helper.h
··· 13 13 14 14 void drm_self_refresh_helper_alter_state(struct drm_atomic_state *state); 15 15 void drm_self_refresh_helper_update_avg_times(struct drm_atomic_state *state, 16 - unsigned int commit_time_ms); 16 + unsigned int commit_time_ms, 17 + unsigned int new_self_refresh_mask); 17 18 18 19 int drm_self_refresh_helper_init(struct drm_crtc *crtc); 19 20 void drm_self_refresh_helper_cleanup(struct drm_crtc *crtc);