Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'imx-dt-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX ARM device tree change for 6.11:
- A few changes from Krzysztof Kozlowski to fix dtschema issues
- A series from Michael Walle to improve kontron-samx6i SoM support by
fixing various errors and add kontron-samx6i-ads2 board
- Add LVDS port data mapping for M53 Menlo board
- Convert NVMEM usage to layout syntax on MBA6 boards
* tag 'imx-dt-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6qdl-kontron-samx6i: add actual device trees
ARM: dts: imx6qdl-kontron-samx6i: remove wake-up-gpio property
ARM: dts: imx6qdl-kontron-samx6i: fix PCIe reset polarity
ARM: dts: imx6qdl-kontron-samx6i: fix node names
ARM: dts: imx6qdl-kontron-samx6i: add SDIO_PWR_EN support
ARM: dts: imx6qdl-kontron-samx6i: always enable eMMC
ARM: dts: imx6qdl-kontron-samx6i: fix product name
ARM: dts: imx6qdl-kontron-samx6i: fix SPI0 chip selects
ARM: dts: imx6qdl-kontron-samx6i: cleanup the PMIC node
ARM: dts: imx6qdl-kontron-samx6i: fix board reset
ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset
ARM: dts: imx6qdl-kontron-samx6i: fix phy-mode
ARM: dts: nxp: imx6: convert NVMEM content to layout syntax
ARM: dts: e60k02: fix aliases for mmc
ARM: dts: imx: Add LVDS port data mapping on M53 Menlo
ARM: dts: imx28-tx28: drop redundant 'panel-name' property
ARM: dts: imx: drop redundant 'u-boot,panel-name' property
ARM: dts: imx6dl-aristainetos2_4: drop redundant 'power-on-delay' property
ARM: dts: imx: correct choice of panel native mode
ARM: dts: imx: align panel timings node name with dtschema
Link: https://lore.kernel.org/r/20240702142153.413061-3-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+287
-123
+2
arch/arm/boot/dts/nxp/imx/Makefile
+2
arch/arm/boot/dts/nxp/imx/Makefile
···
99
99
imx6dl-icore.dtb \
100
100
imx6dl-icore-mipi.dtb \
101
101
imx6dl-icore-rqs.dtb \
102
+
imx6dl-kontron-samx6i-ads2.dtb \
102
103
imx6dl-lanmcu.dtb \
103
104
imx6dl-mamoj.dtb \
104
105
imx6dl-mba6a.dtb \
···
208
207
imx6q-icore-ofcap10.dtb \
209
208
imx6q-icore-ofcap12.dtb \
210
209
imx6q-icore-rqs.dtb \
210
+
imx6q-kontron-samx6i-ads2.dtb \
211
211
imx6q-kp-tpc.dtb \
212
212
imx6q-logicpd.dtb \
213
213
imx6q-marsboard.dtb \
+4
arch/arm/boot/dts/nxp/imx/e60k02.dtsi
+4
arch/arm/boot/dts/nxp/imx/e60k02.dtsi
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts
+1
-1
arch/arm/boot/dts/nxp/imx/imx51-babbage.dts
+1
-1
arch/arm/boot/dts/nxp/imx/imx51-babbage.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts
+1
arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts
+1
arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts
+7
-7
arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts
+7
-7
arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts
···
67
67
};
68
68
69
69
display-timings {
70
-
VGA {
70
+
timing-vga {
71
71
clock-frequency = <25200000>;
72
72
hactive = <640>;
73
73
vactive = <480>;
···
83
83
pixelclk-active = <0>;
84
84
};
85
85
86
-
ETV570 {
86
+
timing-etc570 {
87
87
clock-frequency = <25200000>;
88
88
hactive = <640>;
89
89
vactive = <480>;
···
99
99
pixelclk-active = <0>;
100
100
};
101
101
102
-
ET0350 {
102
+
timing-et0350 {
103
103
clock-frequency = <6413760>;
104
104
hactive = <320>;
105
105
vactive = <240>;
···
115
115
pixelclk-active = <0>;
116
116
};
117
117
118
-
ET0430 {
118
+
timing-et0430 {
119
119
clock-frequency = <9009000>;
120
120
hactive = <480>;
121
121
vactive = <272>;
···
131
131
pixelclk-active = <1>;
132
132
};
133
133
134
-
ET0500 {
134
+
timing-et0500 {
135
135
clock-frequency = <33264000>;
136
136
hactive = <800>;
137
137
vactive = <480>;
···
147
147
pixelclk-active = <0>;
148
148
};
149
149
150
-
ET0700 { /* same as ET0500 */
150
+
timing-et0700 { /* same as ET0500 */
151
151
clock-frequency = <33264000>;
152
152
hactive = <800>;
153
153
vactive = <480>;
···
163
163
pixelclk-active = <0>;
164
164
};
165
165
166
-
ETQ570 {
166
+
timing-etq570 {
167
167
clock-frequency = <6596040>;
168
168
hactive = <320>;
169
169
vactive = <240>;
+3
-3
arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts
+3
-3
arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts
···
191
191
display-timings {
192
192
native-mode = <&lvds0_timing0>;
193
193
194
-
lvds0_timing0: hsd100pxn1 {
194
+
lvds0_timing0: timing-hsd100pxn1 {
195
195
clock-frequency = <65000000>;
196
196
hactive = <1024>;
197
197
vactive = <768>;
···
207
207
pixelclk-active = <1>;
208
208
};
209
209
210
-
lvds0_timing1: nl12880bc20 {
210
+
lvds0_timing1: timing-nl12880bc20 {
211
211
clock-frequency = <71000000>;
212
212
hactive = <1280>;
213
213
vactive = <800>;
···
233
233
display-timings {
234
234
native-mode = <&lvds1_timing0>;
235
235
236
-
lvds1_timing0: hsd100pxn1 {
236
+
lvds1_timing0: timing-hsd100pxn1 {
237
237
clock-frequency = <65000000>;
238
238
hactive = <1024>;
239
239
vactive = <768>;
+2
-3
arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts
+2
-3
arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts
···
82
82
compatible = "lg,lg4573";
83
83
spi-max-frequency = <10000000>;
84
84
reg = <0>;
85
-
power-on-delay = <10>;
86
85
87
86
display-timings {
88
-
480x800p57 {
89
-
native-mode;
87
+
native-mode = <&timing0>;
88
+
timing0: timing-480x800p57 {
90
89
clock-frequency = <27000027>;
91
90
hactive = <480>;
92
91
vactive = <800>;
+2
-2
arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts
+12
arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts
+12
arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR X11
2
+
3
+
/dts-v1/;
4
+
5
+
#include "imx6dl.dtsi"
6
+
#include "imx6qdl-kontron-samx6i.dtsi"
7
+
#include "imx6qdl-kontron-samx6i-ads2.dtsi"
8
+
9
+
/ {
10
+
model = "Kontron SMARC-sAMX6i Dual-Lite/Solo on SMARC Eval 2.0 carrier";
11
+
compatible = "kontron,imx6dl-samx6i-ads2", "kontron,imx6dl-samx6i", "fsl,imx6dl";
12
+
};
+1
-1
arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi
+12
arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts
+12
arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR X11
2
+
3
+
/dts-v1/;
4
+
5
+
#include "imx6q.dtsi"
6
+
#include "imx6qdl-kontron-samx6i.dtsi"
7
+
#include "imx6qdl-kontron-samx6i-ads2.dtsi"
8
+
9
+
/ {
10
+
model = "Kontron SMARC-sAMX6i Quad/Dual on SMARC Eval 2.0 carrier";
11
+
compatible = "kontron,imx6q-samx6i-ads2", "kontron,imx6q-samx6i", "fsl,imx6q";
12
+
};
+1
-24
arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi
+1
-24
arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi
···
5
5
6
6
#include "imx6q.dtsi"
7
7
#include "imx6qdl-kontron-samx6i.dtsi"
8
-
#include <dt-bindings/gpio/gpio.h>
9
8
10
9
/ {
11
-
model = "Kontron SMARC sAMX6i Quad/Dual";
10
+
model = "Kontron SMARC-sAMX6i Quad/Dual";
12
11
compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
13
-
};
14
-
15
-
/* Quad/Dual SoMs have 3 chip-select signals */
16
-
&ecspi4 {
17
-
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
18
-
<&gpio3 29 GPIO_ACTIVE_LOW>,
19
-
<&gpio3 25 GPIO_ACTIVE_LOW>;
20
-
};
21
-
22
-
&pinctrl_ecspi4 {
23
-
fsl,pins = <
24
-
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
25
-
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
26
-
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
27
-
28
-
/* SPI4_IMX_CS2# - connected to internal flash */
29
-
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
30
-
/* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */
31
-
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
32
-
/* SPI4_CS3# - connected to SMARC SPI0_CS1# */
33
-
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
34
-
>;
35
12
};
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi
+148
arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi
+148
arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Device Tree include for the Kontron SMARC-sAMX6i board on a SMARC Eval
4
+
* 2.0 carrier (ADS2).
5
+
*
6
+
*/
7
+
8
+
/ {
9
+
chosen {
10
+
stdout-path = "serial0:115200n8";
11
+
};
12
+
13
+
sound {
14
+
#address-cells = <1>;
15
+
#size-cells = <0>;
16
+
compatible = "simple-audio-card";
17
+
simple-audio-card,format = "i2s";
18
+
simple-audio-card,bitclock-master = <&dailink_master>;
19
+
simple-audio-card,frame-master = <&dailink_master>;
20
+
simple-audio-card,widgets =
21
+
"Headphone", "Headphone Jack",
22
+
"Line", "Line Out Jack",
23
+
"Microphone", "Microphone Jack",
24
+
"Line", "Line In Jack";
25
+
simple-audio-card,routing =
26
+
"Line Out Jack", "LINEOUTR",
27
+
"Line Out Jack", "LINEOUTL",
28
+
"Headphone Jack", "HPOUTR",
29
+
"Headphone Jack", "HPOUTL",
30
+
"IN1L", "Line In Jack",
31
+
"IN1R", "Line In Jack",
32
+
"Microphone Jack", "MICBIAS",
33
+
"IN2L", "Microphone Jack",
34
+
"IN2R", "Microphone Jack";
35
+
36
+
simple-audio-card,cpu {
37
+
sound-dai = <&ssi1>;
38
+
};
39
+
40
+
dailink_master: simple-audio-card,codec {
41
+
sound-dai = <&wm8904>;
42
+
};
43
+
};
44
+
45
+
reg_codec_mic: regulator-codec-mic {
46
+
compatible = "regulator-fixed";
47
+
regulator-name = "V_3V3_MIC";
48
+
regulator-min-microvolt = <3300000>;
49
+
regulator-max-microvolt = <3300000>;
50
+
regulator-always-on;
51
+
regulator-boot-on;
52
+
};
53
+
54
+
reg_codec_1p8v: regulator-codec-1p8v {
55
+
compatible = "regulator-fixed";
56
+
regulator-name = "V_1V8_S0_CODEC";
57
+
regulator-min-microvolt = <1800000>;
58
+
regulator-max-microvolt = <1800000>;
59
+
regulator-always-on;
60
+
regulator-boot-on;
61
+
};
62
+
};
63
+
64
+
&audmux {
65
+
status = "okay";
66
+
};
67
+
68
+
&can1 {
69
+
status = "okay";
70
+
};
71
+
72
+
&can2 {
73
+
status = "okay";
74
+
};
75
+
76
+
&ecspi4 {
77
+
flash@1 {
78
+
compatible = "jedec,spi-nor";
79
+
reg = <1>;
80
+
spi-max-frequency = <100000000>;
81
+
m25p,fast-read;
82
+
};
83
+
};
84
+
85
+
&fec {
86
+
status = "okay";
87
+
};
88
+
89
+
&i2c1 {
90
+
status = "okay";
91
+
92
+
wm8904: audio-codec@1a {
93
+
compatible = "wlf,wm8904";
94
+
reg = <0x1a>;
95
+
#sound-dai-cells = <0>;
96
+
clocks = <&clks IMX6QDL_CLK_CKO2>;
97
+
clock-names = "mclk";
98
+
AVDD-supply = <®_codec_1p8v>;
99
+
CPVDD-supply = <®_codec_1p8v>;
100
+
DBVDD-supply = <®_codec_1p8v>;
101
+
DCVDD-supply = <®_codec_1p8v>;
102
+
MICVDD-supply = <®_codec_mic>;
103
+
};
104
+
};
105
+
106
+
&i2c3 {
107
+
eeprom@57 {
108
+
compatible = "atmel,24c64";
109
+
reg = <0x57>;
110
+
pagesize = <32>;
111
+
};
112
+
};
113
+
114
+
&pcie {
115
+
status = "okay";
116
+
};
117
+
118
+
&ssi1 {
119
+
status = "okay";
120
+
};
121
+
122
+
&uart1 {
123
+
status = "okay";
124
+
};
125
+
126
+
&uart2 {
127
+
status = "okay";
128
+
};
129
+
130
+
&uart4 {
131
+
status = "okay";
132
+
};
133
+
134
+
&uart5 {
135
+
status = "okay";
136
+
};
137
+
138
+
&usbh1 {
139
+
status = "okay";
140
+
};
141
+
142
+
&usbotg {
143
+
status = "okay";
144
+
};
145
+
146
+
&usdhc3 {
147
+
status = "okay";
148
+
};
+37
-21
arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi
+37
-21
arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi
···
61
61
vin-supply = <®_smarc_suppy>;
62
62
};
63
63
64
+
reg_sdio: regulator-sdio {
65
+
compatible = "regulator-fixed";
66
+
pinctrl-names = "default";
67
+
pinctrl-0 = <&pinctrl_reg_sdio>;
68
+
regulator-name = "V_3V3_SD";
69
+
regulator-min-microvolt = <3300000>;
70
+
regulator-max-microvolt = <3300000>;
71
+
gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
72
+
enable-active-high;
73
+
off-on-delay-us = <20000>;
74
+
};
75
+
64
76
reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
65
77
compatible = "regulator-fixed";
66
78
pinctrl-names = "default";
···
149
137
status = "disabled";
150
138
};
151
139
152
-
i2c_intern: i2c-gpio-intern {
140
+
i2c_intern: i2c-0 {
153
141
compatible = "i2c-gpio";
154
142
pinctrl-names = "default";
155
143
pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
···
160
148
#size-cells = <0>;
161
149
};
162
150
163
-
i2c_lcd: i2c-gpio-lcd {
151
+
i2c_lcd: i2c-1 {
164
152
compatible = "i2c-gpio";
165
153
pinctrl-names = "default";
166
154
pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
···
172
160
status = "disabled";
173
161
};
174
162
175
-
i2c_cam: i2c-gpio-cam {
163
+
i2c_cam: i2c-2 {
176
164
compatible = "i2c-gpio";
177
165
pinctrl-names = "default";
178
166
pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
···
190
178
pinctrl-names = "default";
191
179
pinctrl-0 = <&pinctrl_audmux>;
192
180
193
-
audmux_ssi1 {
181
+
mux-ssi1 {
194
182
fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
195
183
fsl,port-config = <
196
184
(IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
···
202
190
>;
203
191
};
204
192
205
-
audmux_adu3 {
193
+
mux-aud3 {
206
194
fsl,audmux-port = <MX51_AUDMUX_PORT3>;
207
195
fsl,port-config = <
208
196
IMX_AUDMUX_V2_PTCR_SYN
···
210
198
>;
211
199
};
212
200
213
-
audmux_ssi2 {
201
+
mux-ssi2 {
214
202
fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
215
203
fsl,port-config = <
216
204
(IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
···
222
210
>;
223
211
};
224
212
225
-
audmux_adu4 {
213
+
mux-aud4 {
226
214
fsl,audmux-port = <MX51_AUDMUX_PORT4>;
227
215
fsl,port-config = <
228
216
IMX_AUDMUX_V2_PTCR_SYN
···
256
244
pinctrl-names = "default";
257
245
pinctrl-0 = <&pinctrl_ecspi4>;
258
246
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
259
-
<&gpio3 29 GPIO_ACTIVE_LOW>;
247
+
<&gpio3 29 GPIO_ACTIVE_LOW>,
248
+
<&gpio3 25 GPIO_ACTIVE_LOW>;
260
249
status = "okay";
261
250
262
251
/* default boot source: workaround #1 for errata ERR006282 */
···
272
259
&fec {
273
260
pinctrl-names = "default";
274
261
pinctrl-0 = <&pinctrl_enet>;
275
-
phy-mode = "rgmii";
262
+
phy-connection-type = "rgmii-id";
276
263
phy-handle = <ðphy>;
277
264
278
265
mdio {
···
282
269
ethphy: ethernet-phy@1 {
283
270
compatible = "ethernet-phy-ieee802.3-c22";
284
271
reg = <1>;
285
-
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
272
+
reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
286
273
reset-assert-us = <1000>;
287
274
};
288
275
};
···
369
356
regulator-always-on;
370
357
};
371
358
372
-
/*
373
-
* Per schematics, of all VGEN's, only VGEN5 has some
374
-
* usage ... but even that - over DNI resistor
375
-
*/
376
359
vgen1 {
377
360
regulator-min-microvolt = <800000>;
378
361
regulator-max-microvolt = <1550000>;
···
389
380
regulator-max-microvolt = <3300000>;
390
381
};
391
382
392
-
reg_2p5v_s0: vgen5 {
393
-
regulator-name = "V_2V5_S0";
383
+
vgen5 {
394
384
regulator-min-microvolt = <1800000>;
395
385
regulator-max-microvolt = <3300000>;
396
386
};
···
472
464
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
473
465
/* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
474
466
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
467
+
/* SPI4_CS3# - connected to SMARC SPI0_CS1# */
468
+
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
475
469
>;
476
470
};
477
471
···
526
516
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
527
517
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
528
518
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
529
-
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
519
+
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */
530
520
>;
531
521
};
532
522
···
652
642
>;
653
643
};
654
644
645
+
pinctrl_reg_sdio: reg-sdiogrp {
646
+
fsl,pins = <
647
+
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* SDIO_PWR_EN */
648
+
>;
649
+
};
650
+
655
651
pinctrl_uart1: uart1grp {
656
652
fsl,pins = <
657
653
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
···
710
694
711
695
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
712
696
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
713
-
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
714
697
>;
715
698
};
716
699
···
743
728
&pcie {
744
729
pinctrl-names = "default";
745
730
pinctrl-0 = <&pinctrl_pcie>;
746
-
wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
747
-
reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
731
+
reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
748
732
};
749
733
750
734
/* LCD_BKLT_PWM */
···
811
797
pinctrl-0 = <&pinctrl_usdhc3>;
812
798
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
813
799
wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
800
+
vmmc-supply = <®_sdio>;
814
801
no-1-8-v;
815
802
};
816
803
817
804
/* SDMMC */
818
805
&usdhc4 {
819
-
/* Internal eMMC, optional on some boards */
820
806
pinctrl-names = "default";
821
807
pinctrl-0 = <&pinctrl_usdhc4>;
822
808
bus-width = <8>;
···
825
811
non-removable;
826
812
vmmc-supply = <®_3p3v_s0>;
827
813
vqmmc-supply = <®_1p8v_s0>;
814
+
status = "okay";
828
815
};
829
816
830
817
&wdog1 {
831
818
/* CPLD is feeded by watchdog (hardwired) */
832
819
pinctrl-names = "default";
833
820
pinctrl-0 = <&pinctrl_wdog1>;
821
+
fsl,ext-reset-output;
834
822
status = "okay";
835
823
};
+8
-4
arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi
+8
-4
arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi
···
22
22
compatible = "atmel,24c64";
23
23
reg = <0x57>;
24
24
pagesize = <32>;
25
-
#address-cells = <1>;
26
-
#size-cells = <1>;
27
25
vcc-supply = <®_mba6_3p3v>;
28
26
29
-
mba_mac_address: mac-address@20 {
30
-
reg = <0x20 0x6>;
27
+
nvmem-layout {
28
+
compatible = "fixed-layout";
29
+
#address-cells = <1>;
30
+
#size-cells = <1>;
31
+
32
+
mba_mac_address: mac-address@20 {
33
+
reg = <0x20 0x6>;
34
+
};
31
35
};
32
36
};
33
37
+8
-4
arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi
+8
-4
arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi
···
32
32
compatible = "atmel,24c64";
33
33
reg = <0x57>;
34
34
pagesize = <32>;
35
-
#address-cells = <1>;
36
-
#size-cells = <1>;
37
35
vcc-supply = <®_mba6_3p3v>;
38
36
39
-
mba_mac_address: mac-address@20 {
40
-
reg = <0x20 0x6>;
37
+
nvmem-layout {
38
+
compatible = "fixed-layout";
39
+
#address-cells = <1>;
40
+
#size-cells = <1>;
41
+
42
+
mba_mac_address: mac-address@20 {
43
+
reg = <0x20 0x6>;
44
+
};
41
45
};
42
46
};
43
47
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi
+8
-13
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi
+8
-13
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi
···
110
110
};
111
111
112
112
display-timings {
113
-
VGA {
113
+
timing-vga {
114
114
clock-frequency = <25200000>;
115
115
hactive = <640>;
116
116
vactive = <480>;
···
126
126
pixelclk-active = <0>;
127
127
};
128
128
129
-
ETV570 {
130
-
u-boot,panel-name = "edt,et057090dhu";
129
+
timing-etv570 {
131
130
clock-frequency = <25200000>;
132
131
hactive = <640>;
133
132
vactive = <480>;
···
142
143
pixelclk-active = <0>;
143
144
};
144
145
145
-
ET0350 {
146
-
u-boot,panel-name = "edt,et0350g0dh6";
146
+
timing-et0350 {
147
147
clock-frequency = <6413760>;
148
148
hactive = <320>;
149
149
vactive = <240>;
···
158
160
pixelclk-active = <0>;
159
161
};
160
162
161
-
ET0430 {
162
-
u-boot,panel-name = "edt,et0430g0dh6";
163
+
timing-et0430 {
163
164
clock-frequency = <9009000>;
164
165
hactive = <480>;
165
166
vactive = <272>;
···
174
177
pixelclk-active = <1>;
175
178
};
176
179
177
-
ET0500 {
180
+
timing-et0500 {
178
181
clock-frequency = <33264000>;
179
182
hactive = <800>;
180
183
vactive = <480>;
···
190
193
pixelclk-active = <0>;
191
194
};
192
195
193
-
ET0700 { /* same as ET0500 */
194
-
u-boot,panel-name = "edt,etm0700g0dh6";
196
+
timing-et0700 { /* same as ET0500 */
195
197
clock-frequency = <33264000>;
196
198
hactive = <800>;
197
199
vactive = <480>;
···
206
210
pixelclk-active = <0>;
207
211
};
208
212
209
-
ETQ570 {
213
+
timing-etq570 {
210
214
clock-frequency = <6596040>;
211
215
hactive = <320>;
212
216
vactive = <240>;
···
222
226
pixelclk-active = <0>;
223
227
};
224
228
225
-
CoMTFT { /* same as ET0700 but with inverted pixel clock */
226
-
u-boot,panel-name = "edt,etm0700g0edh6";
229
+
timing-comtft { /* same as ET0700 but with inverted pixel clock */
227
230
clock-frequency = <33264000>;
228
231
hactive = <800>;
229
232
vactive = <480>;
+8
-12
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi
+8
-12
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi
···
127
127
};
128
128
129
129
display-timings {
130
-
hsd100pxn1 {
131
-
u-boot,panel-name = "hannstar,hsd100pxn1";
130
+
timing-hsd100pxn1 {
132
131
clock-frequency = <65000000>;
133
132
hactive = <1024>;
134
133
vactive = <768>;
···
141
142
pixelclk-active = <1>;
142
143
};
143
144
144
-
VGA {
145
+
timing-vga {
145
146
clock-frequency = <25200000>;
146
147
hactive = <640>;
147
148
vactive = <480>;
···
157
158
pixelclk-active = <0>;
158
159
};
159
160
160
-
nl12880bc20 {
161
-
u-boot,panel-name = "nlt,nl12880bc20-spwg-24";
161
+
timing-nl12880bc20 {
162
162
clock-frequency = <71000000>;
163
163
hactive = <1280>;
164
164
vactive = <800>;
···
173
175
pixelclk-active = <1>;
174
176
};
175
177
176
-
ET0700 {
177
-
u-boot,panel-name = "edt,etm0700g0dh6";
178
+
timing-et0700 {
178
179
clock-frequency = <33264000>;
179
180
hactive = <800>;
180
181
vactive = <480>;
···
189
192
pixelclk-active = <0>;
190
193
};
191
194
192
-
ETV570 {
193
-
u-boot,panel-name = "edt,et057090dhu";
195
+
timing-etv570 {
194
196
clock-frequency = <25200000>;
195
197
hactive = <640>;
196
198
vactive = <480>;
···
220
224
};
221
225
222
226
display-timings {
223
-
hsd100pxn1 {
227
+
timing-hsd100pxn1 {
224
228
clock-frequency = <65000000>;
225
229
hactive = <1024>;
226
230
vactive = <768>;
···
234
238
pixelclk-active = <1>;
235
239
};
236
240
237
-
VGA {
241
+
timing-vga {
238
242
clock-frequency = <25200000>;
239
243
hactive = <640>;
240
244
vactive = <480>;
···
250
254
pixelclk-active = <0>;
251
255
};
252
256
253
-
nl12880bc20 {
257
+
timing-nl12880bc20 {
254
258
clock-frequency = <71000000>;
255
259
hactive = <1280>;
256
260
vactive = <800>;
+7
-7
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
+7
-7
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
···
405
405
status = "okay";
406
406
407
407
display-timings {
408
-
VGA {
408
+
timing-vga {
409
409
clock-frequency = <25200000>;
410
410
hactive = <640>;
411
411
vactive = <480>;
···
421
421
pixelclk-active = <1>;
422
422
};
423
423
424
-
ETV570 {
424
+
timing-etv570 {
425
425
clock-frequency = <25200000>;
426
426
hactive = <640>;
427
427
vactive = <480>;
···
437
437
pixelclk-active = <1>;
438
438
};
439
439
440
-
ET0350 {
440
+
timing-et0350 {
441
441
clock-frequency = <6413760>;
442
442
hactive = <320>;
443
443
vactive = <240>;
···
453
453
pixelclk-active = <1>;
454
454
};
455
455
456
-
ET0430 {
456
+
timing-et0430 {
457
457
clock-frequency = <9009000>;
458
458
hactive = <480>;
459
459
vactive = <272>;
···
469
469
pixelclk-active = <0>;
470
470
};
471
471
472
-
ET0500 {
472
+
timing-et0500 {
473
473
clock-frequency = <33264000>;
474
474
hactive = <800>;
475
475
vactive = <480>;
···
485
485
pixelclk-active = <1>;
486
486
};
487
487
488
-
ET0700 { /* same as ET0500 */
488
+
timing-et0700 { /* same as ET0500 */
489
489
clock-frequency = <33264000>;
490
490
hactive = <800>;
491
491
vactive = <480>;
···
501
501
pixelclk-active = <1>;
502
502
};
503
503
504
-
ETQ570 {
504
+
timing-etq570 {
505
505
clock-frequency = <6596040>;
506
506
hactive = <320>;
507
507
vactive = <240>;
-6
arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts
-6
arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts
···
323
323
display-timings {
324
324
native-mode = <&timing5>;
325
325
timing0: timing0 {
326
-
panel-name = "VGA";
327
326
clock-frequency = <25175000>;
328
327
hactive = <640>;
329
328
vactive = <480>;
···
339
340
};
340
341
341
342
timing1: timing1 {
342
-
panel-name = "ETV570";
343
343
clock-frequency = <25175000>;
344
344
hactive = <640>;
345
345
vactive = <480>;
···
355
357
};
356
358
357
359
timing2: timing2 {
358
-
panel-name = "ET0350";
359
360
clock-frequency = <6500000>;
360
361
hactive = <320>;
361
362
vactive = <240>;
···
371
374
};
372
375
373
376
timing3: timing3 {
374
-
panel-name = "ET0430";
375
377
clock-frequency = <9000000>;
376
378
hactive = <480>;
377
379
vactive = <272>;
···
387
391
};
388
392
389
393
timing4: timing4 {
390
-
panel-name = "ET0500", "ET0700";
391
394
clock-frequency = <33260000>;
392
395
hactive = <800>;
393
396
vactive = <480>;
···
403
408
};
404
409
405
410
timing5: timing5 {
406
-
panel-name = "ETQ570";
407
411
clock-frequency = <6400000>;
408
412
hactive = <320>;
409
413
vactive = <240>;