Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
- Minor updates and fixes to the Octeon ethernet driver in staging
- A fix to VGA_MAP_MEM() for 64 bit platforms
- Fix a workaround for 74K/1074K processors
- The symlink arch/mips/boot/dts/include/dt-bindings was pointing to a
a file with a name ending in \n. I think this may have been caused
by a git bug with with patches sent by email
- A build fix for VGA console on BCM1480-based systems
- Fix PCI device access via "/sys/bus/pci/.../resource0" or similar
work for Alchemy platforms
- Fix potential data leak on MIPS R5 cores. This doesn't add proper
support for any R5 features, just ensures a kernel without such
support will be secure to run
- Adding a macros for the CP0 Config5 register to be used by the R5 fix
- Make get_cycles() actually return something useful where possible
This also requires a preparatory patch for performance sake
- Fix a warning about the use of smp_processor_id() in preemptible
code. Again this includes a preparatory patch adding the
infrastructure to be used by the actual patch
- Finally remove pointless one-line comment
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Fix invalid symbolic link file
MIPS: PCI: pci-bcm1480: Include missing vt.h header
MIPS: Disable usermode switching of the FR bit for MIPS R5 CPUs.
MIPS: Add MIPS R5 config5 register.
MIPS: PCI: Use pci_resource_to_user to map pci memory space properly
MIPS: 74K/1074K: Correct erratum workaround.
MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks
MIPS: Remove useless comment about kprobe from arch/mips/Makefile
MIPS: Fix VGA_MAP_MEM macro.
MIPS: Reimplement get_cycles().
MIPS: Optimize current_cpu_type() for better code.
MIPS: Fix accessing to per-cpu data when flushing the cache
MIPS: Provide nice way to access boot CPU's data.
staging: octeon-ethernet: rgmii: enable interrupts that we can handle
staging: octeon-ethernet: remove skb alloc failure warnings
staging: octeon-ethernet: make dropped packets to consume NAPI budget
+403
-86
-3
arch/mips/Makefile
-3
arch/mips/Makefile
+2
-1
arch/mips/alchemy/common/usb.c
+2
-1
arch/mips/alchemy/common/usb.c
···
14
14
#include <linux/module.h>
15
15
#include <linux/spinlock.h>
16
16
#include <linux/syscore_ops.h>
17
+
#include <asm/cpu.h>
17
18
#include <asm/mach-au1x00/au1000.h>
18
19
19
20
/* control register offsets */
···
359
358
{
360
359
#if defined(CONFIG_DMA_COHERENT)
361
360
/* Au1200 AB USB does not support coherent memory */
362
-
if (!(read_c0_prid() & 0xff)) {
361
+
if (!(read_c0_prid() & PRID_REV_MASK)) {
363
362
printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
364
363
printk(KERN_INFO "Au1200 USB: update your board or re-configure"
365
364
" the kernel\n");
+2
-2
arch/mips/bcm63xx/cpu.c
+2
-2
arch/mips/bcm63xx/cpu.c
···
306
306
307
307
switch (c->cputype) {
308
308
case CPU_BMIPS3300:
309
-
if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
309
+
if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
310
310
__cpu_name[cpu] = "Broadcom BCM6338";
311
311
/* fall-through */
312
312
case CPU_BMIPS32:
313
313
chipid_reg = BCM_6345_PERF_BASE;
314
314
break;
315
315
case CPU_BMIPS4350:
316
-
switch ((read_c0_prid() & 0xff)) {
316
+
switch ((read_c0_prid() & PRID_REV_MASK)) {
317
317
case 0x04:
318
318
chipid_reg = BCM_3368_PERF_BASE;
319
319
break;
+1
arch/mips/cavium-octeon/csrc-octeon.c
+1
arch/mips/cavium-octeon/csrc-octeon.c
+1
arch/mips/dec/prom/init.c
+1
arch/mips/dec/prom/init.c
-6
arch/mips/include/asm/cpu-features.h
-6
arch/mips/include/asm/cpu-features.h
···
13
13
#include <asm/cpu-info.h>
14
14
#include <cpu-feature-overrides.h>
15
15
16
-
#ifndef current_cpu_type
17
-
#define current_cpu_type() current_cpu_data.cputype
18
-
#endif
19
-
20
-
#define boot_cpu_type() cpu_data[0].cputype
21
-
22
16
/*
23
17
* SMP assumption: Options of CPU 0 are a superset of all processors.
24
18
* This is true for all known MIPS systems.
+1
arch/mips/include/asm/cpu-info.h
+1
arch/mips/include/asm/cpu-info.h
+203
arch/mips/include/asm/cpu-type.h
+203
arch/mips/include/asm/cpu-type.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2003, 2004 Ralf Baechle
7
+
* Copyright (C) 2004 Maciej W. Rozycki
8
+
*/
9
+
#ifndef __ASM_CPU_TYPE_H
10
+
#define __ASM_CPU_TYPE_H
11
+
12
+
#include <linux/smp.h>
13
+
#include <linux/compiler.h>
14
+
15
+
static inline int __pure __get_cpu_type(const int cpu_type)
16
+
{
17
+
switch (cpu_type) {
18
+
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
19
+
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
20
+
case CPU_LOONGSON2:
21
+
#endif
22
+
23
+
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
24
+
case CPU_LOONGSON1:
25
+
#endif
26
+
27
+
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
28
+
case CPU_4KC:
29
+
case CPU_ALCHEMY:
30
+
case CPU_BMIPS3300:
31
+
case CPU_BMIPS4350:
32
+
case CPU_PR4450:
33
+
case CPU_BMIPS32:
34
+
case CPU_JZRISC:
35
+
#endif
36
+
37
+
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
38
+
defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
39
+
case CPU_4KEC:
40
+
#endif
41
+
42
+
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
43
+
case CPU_4KSC:
44
+
case CPU_24K:
45
+
case CPU_34K:
46
+
case CPU_1004K:
47
+
case CPU_74K:
48
+
case CPU_M14KC:
49
+
case CPU_M14KEC:
50
+
#endif
51
+
52
+
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
53
+
case CPU_5KC:
54
+
case CPU_5KE:
55
+
case CPU_20KC:
56
+
case CPU_25KF:
57
+
case CPU_SB1:
58
+
case CPU_SB1A:
59
+
#endif
60
+
61
+
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
62
+
/*
63
+
* All MIPS64 R2 processors have their own special symbols. That is,
64
+
* there currently is no pure R2 core
65
+
*/
66
+
#endif
67
+
68
+
#ifdef CONFIG_SYS_HAS_CPU_R3000
69
+
case CPU_R2000:
70
+
case CPU_R3000:
71
+
case CPU_R3000A:
72
+
case CPU_R3041:
73
+
case CPU_R3051:
74
+
case CPU_R3052:
75
+
case CPU_R3081:
76
+
case CPU_R3081E:
77
+
#endif
78
+
79
+
#ifdef CONFIG_SYS_HAS_CPU_TX39XX
80
+
case CPU_TX3912:
81
+
case CPU_TX3922:
82
+
case CPU_TX3927:
83
+
#endif
84
+
85
+
#ifdef CONFIG_SYS_HAS_CPU_VR41XX
86
+
case CPU_VR41XX:
87
+
case CPU_VR4111:
88
+
case CPU_VR4121:
89
+
case CPU_VR4122:
90
+
case CPU_VR4131:
91
+
case CPU_VR4133:
92
+
case CPU_VR4181:
93
+
case CPU_VR4181A:
94
+
#endif
95
+
96
+
#ifdef CONFIG_SYS_HAS_CPU_R4300
97
+
case CPU_R4300:
98
+
case CPU_R4310:
99
+
#endif
100
+
101
+
#ifdef CONFIG_SYS_HAS_CPU_R4X00
102
+
case CPU_R4000PC:
103
+
case CPU_R4000SC:
104
+
case CPU_R4000MC:
105
+
case CPU_R4200:
106
+
case CPU_R4400PC:
107
+
case CPU_R4400SC:
108
+
case CPU_R4400MC:
109
+
case CPU_R4600:
110
+
case CPU_R4700:
111
+
case CPU_R4640:
112
+
case CPU_R4650:
113
+
#endif
114
+
115
+
#ifdef CONFIG_SYS_HAS_CPU_TX49XX
116
+
case CPU_TX49XX:
117
+
#endif
118
+
119
+
#ifdef CONFIG_SYS_HAS_CPU_R5000
120
+
case CPU_R5000:
121
+
#endif
122
+
123
+
#ifdef CONFIG_SYS_HAS_CPU_R5432
124
+
case CPU_R5432:
125
+
#endif
126
+
127
+
#ifdef CONFIG_SYS_HAS_CPU_R5500
128
+
case CPU_R5500:
129
+
#endif
130
+
131
+
#ifdef CONFIG_SYS_HAS_CPU_R6000
132
+
case CPU_R6000:
133
+
case CPU_R6000A:
134
+
#endif
135
+
136
+
#ifdef CONFIG_SYS_HAS_CPU_NEVADA
137
+
case CPU_NEVADA:
138
+
#endif
139
+
140
+
#ifdef CONFIG_SYS_HAS_CPU_R8000
141
+
case CPU_R8000:
142
+
#endif
143
+
144
+
#ifdef CONFIG_SYS_HAS_CPU_R10000
145
+
case CPU_R10000:
146
+
case CPU_R12000:
147
+
case CPU_R14000:
148
+
#endif
149
+
#ifdef CONFIG_SYS_HAS_CPU_RM7000
150
+
case CPU_RM7000:
151
+
case CPU_SR71000:
152
+
#endif
153
+
#ifdef CONFIG_SYS_HAS_CPU_RM9000
154
+
case CPU_RM9000:
155
+
#endif
156
+
#ifdef CONFIG_SYS_HAS_CPU_SB1
157
+
case CPU_SB1:
158
+
case CPU_SB1A:
159
+
#endif
160
+
#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
161
+
case CPU_CAVIUM_OCTEON:
162
+
case CPU_CAVIUM_OCTEON_PLUS:
163
+
case CPU_CAVIUM_OCTEON2:
164
+
#endif
165
+
166
+
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
167
+
case CPU_BMIPS4380:
168
+
#endif
169
+
170
+
#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
171
+
case CPU_BMIPS5000:
172
+
#endif
173
+
174
+
#ifdef CONFIG_SYS_HAS_CPU_XLP
175
+
case CPU_XLP:
176
+
#endif
177
+
178
+
#ifdef CONFIG_SYS_HAS_CPU_XLR
179
+
case CPU_XLR:
180
+
#endif
181
+
break;
182
+
default:
183
+
unreachable();
184
+
}
185
+
186
+
return cpu_type;
187
+
}
188
+
189
+
static inline int __pure current_cpu_type(void)
190
+
{
191
+
const int cpu_type = current_cpu_data.cputype;
192
+
193
+
return __get_cpu_type(cpu_type);
194
+
}
195
+
196
+
static inline int __pure boot_cpu_type(void)
197
+
{
198
+
const int cpu_type = cpu_data[0].cputype;
199
+
200
+
return __get_cpu_type(cpu_type);
201
+
}
202
+
203
+
#endif /* __ASM_CPU_TYPE_H */
+29
-9
arch/mips/include/asm/cpu.h
+29
-9
arch/mips/include/asm/cpu.h
···
3
3
* various MIPS cpu types.
4
4
*
5
5
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6
-
* Copyright (C) 2004 Maciej W. Rozycki
6
+
* Copyright (C) 2004, 2013 Maciej W. Rozycki
7
7
*/
8
8
#ifndef _ASM_CPU_H
9
9
#define _ASM_CPU_H
10
10
11
-
/* Assigned Company values for bits 23:16 of the PRId Register
12
-
(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
13
-
MTI, the PRId register is defined in this (backwards compatible)
14
-
way:
11
+
/*
12
+
As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
13
+
register 15, select 0) is defined in this (backwards compatible) way:
15
14
16
15
+----------------+----------------+----------------+----------------+
17
16
| Company Options| Company ID | Processor ID | Revision |
···
21
22
that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
22
23
spec.
23
24
*/
25
+
26
+
#define PRID_OPT_MASK 0xff000000
27
+
28
+
/*
29
+
* Assigned Company values for bits 23:16 of the PRId register.
30
+
*/
31
+
32
+
#define PRID_COMP_MASK 0xff0000
24
33
25
34
#define PRID_COMP_LEGACY 0x000000
26
35
#define PRID_COMP_MIPS 0x010000
···
45
38
#define PRID_COMP_INGENIC 0xd00000
46
39
47
40
/*
48
-
* Assigned values for the product ID register. In order to detect a
49
-
* certain CPU type exactly eventually additional registers may need to
50
-
* be examined. These are valid when 23:16 == PRID_COMP_LEGACY
41
+
* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
42
+
* register. In order to detect a certain CPU type exactly eventually
43
+
* additional registers may need to be examined.
51
44
*/
45
+
46
+
#define PRID_IMP_MASK 0xff00
47
+
48
+
/*
49
+
* These are valid when 23:16 == PRID_COMP_LEGACY
50
+
*/
51
+
52
52
#define PRID_IMP_R2000 0x0100
53
53
#define PRID_IMP_AU1_REV1 0x0100
54
54
#define PRID_IMP_AU1_REV2 0x0200
···
196
182
#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
197
183
198
184
/*
199
-
* Definitions for 7:0 on legacy processors
185
+
* Particular Revision values for bits 7:0 of the PRId register.
200
186
*/
201
187
202
188
#define PRID_REV_MASK 0x00ff
189
+
190
+
/*
191
+
* Definitions for 7:0 on legacy processors
192
+
*/
203
193
204
194
#define PRID_REV_TX4927 0x0022
205
195
#define PRID_REV_TX4937 0x0030
···
244
226
* +---------------------------------+----------------+----------------+
245
227
* 31 16 15 8 7 0
246
228
*/
229
+
230
+
#define FPIR_IMP_MASK 0xff00
247
231
248
232
#define FPIR_IMP_NONE 0x0000
249
233
+3
-1
arch/mips/include/asm/mach-au1x00/au1000.h
+3
-1
arch/mips/include/asm/mach-au1x00/au1000.h
···
43
43
#include <linux/io.h>
44
44
#include <linux/irq.h>
45
45
46
+
#include <asm/cpu.h>
47
+
46
48
/* cpu pipeline flush */
47
49
void static inline au_sync(void)
48
50
{
···
142
140
143
141
static inline int alchemy_get_cputype(void)
144
142
{
145
-
switch (read_c0_prid() & 0xffff0000) {
143
+
switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
146
144
case 0x00030000:
147
145
return ALCHEMY_CPU_AU1000;
148
146
break;
+2
arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+2
arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+2
arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+2
arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+2
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+2
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+7
arch/mips/include/asm/mipsregs.h
+7
arch/mips/include/asm/mipsregs.h
···
603
603
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
604
604
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
605
605
606
+
#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
607
+
#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
608
+
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
609
+
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
610
+
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
611
+
#define MIPS_CONF5_K (_ULCAST_(1) << 30)
612
+
606
613
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
607
614
608
615
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
+12
arch/mips/include/asm/pci.h
+12
arch/mips/include/asm/pci.h
···
83
83
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
84
84
enum pci_mmap_state mmap_state, int write_combine);
85
85
86
+
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
87
+
88
+
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
89
+
const struct resource *rsrc, resource_size_t *start,
90
+
resource_size_t *end)
91
+
{
92
+
phys_t size = resource_size(rsrc);
93
+
94
+
*start = fixup_bigphys_addr(rsrc->start, size);
95
+
*end = rsrc->start + size;
96
+
}
97
+
86
98
/*
87
99
* Dynamic DMA mapping stuff.
88
100
* MIPS has everything mapped statically.
+32
-1
arch/mips/include/asm/timex.h
+32
-1
arch/mips/include/asm/timex.h
···
10
10
11
11
#ifdef __KERNEL__
12
12
13
+
#include <asm/cpu-features.h>
13
14
#include <asm/mipsregs.h>
15
+
#include <asm/cpu-type.h>
14
16
15
17
/*
16
18
* This is the clock rate of the i8253 PIT. A MIPS system may not have
···
35
33
36
34
typedef unsigned int cycles_t;
37
35
36
+
/*
37
+
* On R4000/R4400 before version 5.0 an erratum exists such that if the
38
+
* cycle counter is read in the exact moment that it is matching the
39
+
* compare register, no interrupt will be generated.
40
+
*
41
+
* There is a suggested workaround and also the erratum can't strike if
42
+
* the compare interrupt isn't being used as the clock source device.
43
+
* However for now the implementaton of this function doesn't get these
44
+
* fine details right.
45
+
*/
38
46
static inline cycles_t get_cycles(void)
39
47
{
40
-
return 0;
48
+
switch (boot_cpu_type()) {
49
+
case CPU_R4400PC:
50
+
case CPU_R4400SC:
51
+
case CPU_R4400MC:
52
+
if ((read_c0_prid() & 0xff) >= 0x0050)
53
+
return read_c0_count();
54
+
break;
55
+
56
+
case CPU_R4000PC:
57
+
case CPU_R4000SC:
58
+
case CPU_R4000MC:
59
+
break;
60
+
61
+
default:
62
+
if (cpu_has_counter)
63
+
return read_c0_count();
64
+
break;
65
+
}
66
+
67
+
return 0; /* no usable counter */
41
68
}
42
69
43
70
#endif /* __KERNEL__ */
+2
-1
arch/mips/include/asm/vga.h
+2
-1
arch/mips/include/asm/vga.h
···
6
6
#ifndef _ASM_VGA_H
7
7
#define _ASM_VGA_H
8
8
9
+
#include <asm/addrspace.h>
9
10
#include <asm/byteorder.h>
10
11
11
12
/*
···
14
13
* access the videoram directly without any black magic.
15
14
*/
16
15
17
-
#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x))
16
+
#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
18
17
19
18
#define vga_readb(x) (*(x))
20
19
#define vga_writeb(x, y) (*(y) = (x))
+37
-21
arch/mips/kernel/cpu-probe.c
+37
-21
arch/mips/kernel/cpu-probe.c
···
20
20
21
21
#include <asm/bugs.h>
22
22
#include <asm/cpu.h>
23
+
#include <asm/cpu-type.h>
23
24
#include <asm/fpu.h>
24
25
#include <asm/mipsregs.h>
25
26
#include <asm/watch.h>
···
56
55
{
57
56
struct cpuinfo_mips *c = ¤t_cpu_data;
58
57
59
-
switch (c->cputype) {
58
+
switch (current_cpu_type()) {
60
59
case CPU_34K:
61
60
/*
62
61
* Erratum "RPS May Cause Incorrect Instruction Execution"
···
123
122
*/
124
123
static inline int __cpu_has_fpu(void)
125
124
{
126
-
return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
125
+
return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
127
126
}
128
127
129
128
static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
···
291
290
return config4 & MIPS_CONF_M;
292
291
}
293
292
293
+
static inline unsigned int decode_config5(struct cpuinfo_mips *c)
294
+
{
295
+
unsigned int config5;
296
+
297
+
config5 = read_c0_config5();
298
+
config5 &= ~MIPS_CONF5_UFR;
299
+
write_c0_config5(config5);
300
+
301
+
return config5 & MIPS_CONF_M;
302
+
}
303
+
294
304
static void decode_configs(struct cpuinfo_mips *c)
295
305
{
296
306
int ok;
···
322
310
ok = decode_config3(c);
323
311
if (ok)
324
312
ok = decode_config4(c);
313
+
if (ok)
314
+
ok = decode_config5(c);
325
315
326
316
mips_probe_watch_registers(c);
327
317
···
336
322
337
323
static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
338
324
{
339
-
switch (c->processor_id & 0xff00) {
325
+
switch (c->processor_id & PRID_IMP_MASK) {
340
326
case PRID_IMP_R2000:
341
327
c->cputype = CPU_R2000;
342
328
__cpu_name[cpu] = "R2000";
···
347
333
c->tlbsize = 64;
348
334
break;
349
335
case PRID_IMP_R3000:
350
-
if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
336
+
if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
351
337
if (cpu_has_confreg()) {
352
338
c->cputype = CPU_R3081E;
353
339
__cpu_name[cpu] = "R3081";
···
367
353
break;
368
354
case PRID_IMP_R4000:
369
355
if (read_c0_config() & CONF_SC) {
370
-
if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
356
+
if ((c->processor_id & PRID_REV_MASK) >=
357
+
PRID_REV_R4400) {
371
358
c->cputype = CPU_R4400PC;
372
359
__cpu_name[cpu] = "R4400PC";
373
360
} else {
···
376
361
__cpu_name[cpu] = "R4000PC";
377
362
}
378
363
} else {
379
-
if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
364
+
if ((c->processor_id & PRID_REV_MASK) >=
365
+
PRID_REV_R4400) {
380
366
c->cputype = CPU_R4400SC;
381
367
__cpu_name[cpu] = "R4400SC";
382
368
} else {
···
470
454
__cpu_name[cpu] = "TX3927";
471
455
c->tlbsize = 64;
472
456
} else {
473
-
switch (c->processor_id & 0xff) {
457
+
switch (c->processor_id & PRID_REV_MASK) {
474
458
case PRID_REV_TX3912:
475
459
c->cputype = CPU_TX3912;
476
460
__cpu_name[cpu] = "TX3912";
···
656
640
static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
657
641
{
658
642
decode_configs(c);
659
-
switch (c->processor_id & 0xff00) {
643
+
switch (c->processor_id & PRID_IMP_MASK) {
660
644
case PRID_IMP_4KC:
661
645
c->cputype = CPU_4KC;
662
646
__cpu_name[cpu] = "MIPS 4Kc";
···
727
711
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
728
712
{
729
713
decode_configs(c);
730
-
switch (c->processor_id & 0xff00) {
714
+
switch (c->processor_id & PRID_IMP_MASK) {
731
715
case PRID_IMP_AU1_REV1:
732
716
case PRID_IMP_AU1_REV2:
733
717
c->cputype = CPU_ALCHEMY;
···
746
730
break;
747
731
case 4:
748
732
__cpu_name[cpu] = "Au1200";
749
-
if ((c->processor_id & 0xff) == 2)
733
+
if ((c->processor_id & PRID_REV_MASK) == 2)
750
734
__cpu_name[cpu] = "Au1250";
751
735
break;
752
736
case 5:
···
764
748
{
765
749
decode_configs(c);
766
750
767
-
switch (c->processor_id & 0xff00) {
751
+
switch (c->processor_id & PRID_IMP_MASK) {
768
752
case PRID_IMP_SB1:
769
753
c->cputype = CPU_SB1;
770
754
__cpu_name[cpu] = "SiByte SB1";
771
755
/* FPU in pass1 is known to have issues. */
772
-
if ((c->processor_id & 0xff) < 0x02)
756
+
if ((c->processor_id & PRID_REV_MASK) < 0x02)
773
757
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
774
758
break;
775
759
case PRID_IMP_SB1A:
···
782
766
static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
783
767
{
784
768
decode_configs(c);
785
-
switch (c->processor_id & 0xff00) {
769
+
switch (c->processor_id & PRID_IMP_MASK) {
786
770
case PRID_IMP_SR71000:
787
771
c->cputype = CPU_SR71000;
788
772
__cpu_name[cpu] = "Sandcraft SR71000";
···
795
779
static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
796
780
{
797
781
decode_configs(c);
798
-
switch (c->processor_id & 0xff00) {
782
+
switch (c->processor_id & PRID_IMP_MASK) {
799
783
case PRID_IMP_PR4450:
800
784
c->cputype = CPU_PR4450;
801
785
__cpu_name[cpu] = "Philips PR4450";
···
807
791
static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
808
792
{
809
793
decode_configs(c);
810
-
switch (c->processor_id & 0xff00) {
794
+
switch (c->processor_id & PRID_IMP_MASK) {
811
795
case PRID_IMP_BMIPS32_REV4:
812
796
case PRID_IMP_BMIPS32_REV8:
813
797
c->cputype = CPU_BMIPS32;
···
822
806
set_elf_platform(cpu, "bmips3300");
823
807
break;
824
808
case PRID_IMP_BMIPS43XX: {
825
-
int rev = c->processor_id & 0xff;
809
+
int rev = c->processor_id & PRID_REV_MASK;
826
810
827
811
if (rev >= PRID_REV_BMIPS4380_LO &&
828
812
rev <= PRID_REV_BMIPS4380_HI) {
···
848
832
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
849
833
{
850
834
decode_configs(c);
851
-
switch (c->processor_id & 0xff00) {
835
+
switch (c->processor_id & PRID_IMP_MASK) {
852
836
case PRID_IMP_CAVIUM_CN38XX:
853
837
case PRID_IMP_CAVIUM_CN31XX:
854
838
case PRID_IMP_CAVIUM_CN30XX:
···
891
875
decode_configs(c);
892
876
/* JZRISC does not implement the CP0 counter. */
893
877
c->options &= ~MIPS_CPU_COUNTER;
894
-
switch (c->processor_id & 0xff00) {
878
+
switch (c->processor_id & PRID_IMP_MASK) {
895
879
case PRID_IMP_JZRISC:
896
880
c->cputype = CPU_JZRISC;
897
881
__cpu_name[cpu] = "Ingenic JZRISC";
···
906
890
{
907
891
decode_configs(c);
908
892
909
-
if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
893
+
if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
910
894
c->cputype = CPU_ALCHEMY;
911
895
__cpu_name[cpu] = "Au1300";
912
896
/* following stuff is not for Alchemy */
···
921
905
MIPS_CPU_EJTAG |
922
906
MIPS_CPU_LLSC);
923
907
924
-
switch (c->processor_id & 0xff00) {
908
+
switch (c->processor_id & PRID_IMP_MASK) {
925
909
case PRID_IMP_NETLOGIC_XLP2XX:
926
910
c->cputype = CPU_XLP;
927
911
__cpu_name[cpu] = "Broadcom XLPII";
···
1000
984
c->cputype = CPU_UNKNOWN;
1001
985
1002
986
c->processor_id = read_c0_prid();
1003
-
switch (c->processor_id & 0xff0000) {
987
+
switch (c->processor_id & PRID_COMP_MASK) {
1004
988
case PRID_COMP_LEGACY:
1005
989
cpu_probe_legacy(c, cpu);
1006
990
break;
+2
-1
arch/mips/kernel/idle.c
+2
-1
arch/mips/kernel/idle.c
···
18
18
#include <linux/sched.h>
19
19
#include <asm/cpu.h>
20
20
#include <asm/cpu-info.h>
21
+
#include <asm/cpu-type.h>
21
22
#include <asm/idle.h>
22
23
#include <asm/mipsregs.h>
23
24
···
137
136
return;
138
137
}
139
138
140
-
switch (c->cputype) {
139
+
switch (current_cpu_type()) {
141
140
case CPU_R3081:
142
141
case CPU_R3081E:
143
142
cpu_wait = r3081_wait;
+1
arch/mips/kernel/time.c
+1
arch/mips/kernel/time.c
+2
-1
arch/mips/kernel/traps.c
+2
-1
arch/mips/kernel/traps.c
···
39
39
#include <asm/break.h>
40
40
#include <asm/cop2.h>
41
41
#include <asm/cpu.h>
42
+
#include <asm/cpu-type.h>
42
43
#include <asm/dsp.h>
43
44
#include <asm/fpu.h>
44
45
#include <asm/fpu_emulator.h>
···
623
622
regs->regs[rt] = read_c0_count();
624
623
return 0;
625
624
case 3: /* Count register resolution */
626
-
switch (current_cpu_data.cputype) {
625
+
switch (current_cpu_type()) {
627
626
case CPU_20KC:
628
627
case CPU_25KF:
629
628
regs->regs[rt] = 1;
+4
-2
arch/mips/mm/c-octeon.c
+4
-2
arch/mips/mm/c-octeon.c
···
19
19
#include <asm/bootinfo.h>
20
20
#include <asm/cacheops.h>
21
21
#include <asm/cpu-features.h>
22
+
#include <asm/cpu-type.h>
22
23
#include <asm/page.h>
23
24
#include <asm/pgtable.h>
24
25
#include <asm/r4kcache.h>
···
187
186
unsigned long dcache_size;
188
187
unsigned int config1;
189
188
struct cpuinfo_mips *c = ¤t_cpu_data;
189
+
int cputype = current_cpu_type();
190
190
191
191
config1 = read_c0_config1();
192
-
switch (c->cputype) {
192
+
switch (cputype) {
193
193
case CPU_CAVIUM_OCTEON:
194
194
case CPU_CAVIUM_OCTEON_PLUS:
195
195
c->icache.linesz = 2 << ((config1 >> 19) & 7);
···
201
199
c->icache.sets * c->icache.ways * c->icache.linesz;
202
200
c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
203
201
c->dcache.linesz = 128;
204
-
if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
202
+
if (cputype == CPU_CAVIUM_OCTEON_PLUS)
205
203
c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
206
204
else
207
205
c->dcache.sets = 1; /* CN3XXX has one Dcache set */
+32
-16
arch/mips/mm/c-r4k.c
+32
-16
arch/mips/mm/c-r4k.c
···
12
12
#include <linux/highmem.h>
13
13
#include <linux/kernel.h>
14
14
#include <linux/linkage.h>
15
+
#include <linux/preempt.h>
15
16
#include <linux/sched.h>
16
17
#include <linux/smp.h>
17
18
#include <linux/mm.h>
···
25
24
#include <asm/cacheops.h>
26
25
#include <asm/cpu.h>
27
26
#include <asm/cpu-features.h>
27
+
#include <asm/cpu-type.h>
28
28
#include <asm/io.h>
29
29
#include <asm/page.h>
30
30
#include <asm/pgtable.h>
···
603
601
/* Catch bad driver code */
604
602
BUG_ON(size == 0);
605
603
604
+
preempt_disable();
606
605
if (cpu_has_inclusive_pcaches) {
607
606
if (size >= scache_size)
608
607
r4k_blast_scache();
···
624
621
R4600_HIT_CACHEOP_WAR_IMPL;
625
622
blast_dcache_range(addr, addr + size);
626
623
}
624
+
preempt_enable();
627
625
628
626
bc_wback_inv(addr, size);
629
627
__sync();
···
635
631
/* Catch bad driver code */
636
632
BUG_ON(size == 0);
637
633
634
+
preempt_disable();
638
635
if (cpu_has_inclusive_pcaches) {
639
636
if (size >= scache_size)
640
637
r4k_blast_scache();
···
660
655
R4600_HIT_CACHEOP_WAR_IMPL;
661
656
blast_inv_dcache_range(addr, addr + size);
662
657
}
658
+
preempt_enable();
663
659
664
660
bc_inv(addr, size);
665
661
__sync();
···
786
780
787
781
static inline void alias_74k_erratum(struct cpuinfo_mips *c)
788
782
{
783
+
unsigned int imp = c->processor_id & PRID_IMP_MASK;
784
+
unsigned int rev = c->processor_id & PRID_REV_MASK;
785
+
789
786
/*
790
787
* Early versions of the 74K do not update the cache tags on a
791
788
* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
792
789
* aliases. In this case it is better to treat the cache as always
793
790
* having aliases.
794
791
*/
795
-
if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
796
-
c->dcache.flags |= MIPS_CACHE_VTAG;
797
-
if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
798
-
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
799
-
if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
800
-
((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
801
-
c->dcache.flags |= MIPS_CACHE_VTAG;
802
-
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
792
+
switch (imp) {
793
+
case PRID_IMP_74K:
794
+
if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
795
+
c->dcache.flags |= MIPS_CACHE_VTAG;
796
+
if (rev == PRID_REV_ENCODE_332(2, 4, 0))
797
+
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
798
+
break;
799
+
case PRID_IMP_1074K:
800
+
if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
801
+
c->dcache.flags |= MIPS_CACHE_VTAG;
802
+
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
803
+
}
804
+
break;
805
+
default:
806
+
BUG();
803
807
}
804
808
}
805
809
···
825
809
unsigned long config1;
826
810
unsigned int lsize;
827
811
828
-
switch (c->cputype) {
812
+
switch (current_cpu_type()) {
829
813
case CPU_R4600: /* QED style two way caches? */
830
814
case CPU_R4700:
831
815
case CPU_R5000:
···
1041
1025
* presumably no vendor is shipping his hardware in the "bad"
1042
1026
* configuration.
1043
1027
*/
1044
-
if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1028
+
if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1029
+
(prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1045
1030
!(config & CONF_SC) && c->icache.linesz != 16 &&
1046
1031
PAGE_SIZE <= 0x8000)
1047
1032
panic("Improper R4000SC processor configuration detected");
···
1062
1045
* normally they'd suffer from aliases but magic in the hardware deals
1063
1046
* with that for us so we don't need to take care ourselves.
1064
1047
*/
1065
-
switch (c->cputype) {
1048
+
switch (current_cpu_type()) {
1066
1049
case CPU_20KC:
1067
1050
case CPU_25KF:
1068
1051
case CPU_SB1:
···
1082
1065
case CPU_34K:
1083
1066
case CPU_74K:
1084
1067
case CPU_1004K:
1085
-
if (c->cputype == CPU_74K)
1068
+
if (current_cpu_type() == CPU_74K)
1086
1069
alias_74k_erratum(c);
1087
1070
if ((read_c0_config7() & (1 << 16))) {
1088
1071
/* effectively physically indexed dcache,
···
1095
1078
c->dcache.flags |= MIPS_CACHE_ALIASES;
1096
1079
}
1097
1080
1098
-
switch (c->cputype) {
1081
+
switch (current_cpu_type()) {
1099
1082
case CPU_20KC:
1100
1083
/*
1101
1084
* Some older 20Kc chips doesn't have the 'VI' bit in
···
1224
1207
* processors don't have a S-cache that would be relevant to the
1225
1208
* Linux memory management.
1226
1209
*/
1227
-
switch (c->cputype) {
1210
+
switch (current_cpu_type()) {
1228
1211
case CPU_R4000SC:
1229
1212
case CPU_R4000MC:
1230
1213
case CPU_R4400SC:
···
1401
1384
{
1402
1385
extern char __weak except_vec2_generic;
1403
1386
extern char __weak except_vec2_sb1;
1404
-
struct cpuinfo_mips *c = ¤t_cpu_data;
1405
1387
1406
-
switch (c->cputype) {
1388
+
switch (current_cpu_type()) {
1407
1389
case CPU_SB1:
1408
1390
case CPU_SB1A:
1409
1391
set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
+1
arch/mips/mm/dma-default.c
+1
arch/mips/mm/dma-default.c
+1
arch/mips/mm/page.c
+1
arch/mips/mm/page.c
+2
-1
arch/mips/mm/sc-mips.c
+2
-1
arch/mips/mm/sc-mips.c
···
6
6
#include <linux/sched.h>
7
7
#include <linux/mm.h>
8
8
9
+
#include <asm/cpu-type.h>
9
10
#include <asm/mipsregs.h>
10
11
#include <asm/bcache.h>
11
12
#include <asm/cacheops.h>
···
72
71
unsigned int tmp;
73
72
74
73
/* Check the bypass bit (L2B) */
75
-
switch (c->cputype) {
74
+
switch (current_cpu_type()) {
76
75
case CPU_34K:
77
76
case CPU_74K:
78
77
case CPU_1004K:
+1
arch/mips/mm/tlb-r4k.c
+1
arch/mips/mm/tlb-r4k.c
+1
arch/mips/mm/tlbex.c
+1
arch/mips/mm/tlbex.c
+3
-2
arch/mips/mti-malta/malta-time.c
+3
-2
arch/mips/mti-malta/malta-time.c
···
27
27
#include <linux/timex.h>
28
28
#include <linux/mc146818rtc.h>
29
29
30
+
#include <asm/cpu.h>
30
31
#include <asm/mipsregs.h>
31
32
#include <asm/mipsmtregs.h>
32
33
#include <asm/hardirq.h>
···
77
76
#endif
78
77
79
78
#if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
80
-
unsigned int prid = read_c0_prid() & 0xffff00;
79
+
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
81
80
82
81
/*
83
82
* XXXKYMA: hardwire the CPU frequency to Host Freq/4
···
170
169
171
170
void __init plat_time_init(void)
172
171
{
173
-
unsigned int prid = read_c0_prid() & 0xffff00;
172
+
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
174
173
unsigned int freq;
175
174
176
175
estimate_frequencies();
+2
-1
arch/mips/mti-sead3/sead3-time.c
+2
-1
arch/mips/mti-sead3/sead3-time.c
···
7
7
*/
8
8
#include <linux/init.h>
9
9
10
+
#include <asm/cpu.h>
10
11
#include <asm/setup.h>
11
12
#include <asm/time.h>
12
13
#include <asm/irq.h>
···
35
34
*/
36
35
static unsigned int __init estimate_cpu_frequency(void)
37
36
{
38
-
unsigned int prid = read_c0_prid() & 0xffff00;
37
+
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
39
38
unsigned int tick = 0;
40
39
unsigned int freq;
41
40
unsigned int orig;
+2
-1
arch/mips/netlogic/xlr/fmn-config.c
+2
-1
arch/mips/netlogic/xlr/fmn-config.c
···
36
36
#include <linux/irq.h>
37
37
#include <linux/interrupt.h>
38
38
39
+
#include <asm/cpu.h>
39
40
#include <asm/mipsregs.h>
40
41
#include <asm/netlogic/xlr/fmn.h>
41
42
#include <asm/netlogic/xlr/xlr.h>
···
188
187
int processor_id, num_core;
189
188
190
189
num_core = hweight32(nlm_current_node()->coremask);
191
-
processor_id = read_c0_prid() & 0xff00;
190
+
processor_id = read_c0_prid() & PRID_IMP_MASK;
192
191
193
192
setup_cpu_fmninfo(cpu, num_core);
194
193
switch (processor_id) {
+1
arch/mips/oprofile/common.c
+1
arch/mips/oprofile/common.c
+1
arch/mips/pci/pci-bcm1480.c
+1
arch/mips/pci/pci-bcm1480.c
+2
-1
arch/mips/sibyte/bcm1480/setup.c
+2
-1
arch/mips/sibyte/bcm1480/setup.c
···
22
22
#include <linux/string.h>
23
23
24
24
#include <asm/bootinfo.h>
25
+
#include <asm/cpu.h>
25
26
#include <asm/mipsregs.h>
26
27
#include <asm/io.h>
27
28
#include <asm/sibyte/sb1250.h>
···
120
119
uint64_t sys_rev;
121
120
int plldiv;
122
121
123
-
sb1_pass = read_c0_prid() & 0xff;
122
+
sb1_pass = read_c0_prid() & PRID_REV_MASK;
124
123
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
125
124
soc_type = SYS_SOC_TYPE(sys_rev);
126
125
part_type = G_SYS_PART(sys_rev);
+2
-1
arch/mips/sibyte/sb1250/setup.c
+2
-1
arch/mips/sibyte/sb1250/setup.c
···
22
22
#include <linux/string.h>
23
23
24
24
#include <asm/bootinfo.h>
25
+
#include <asm/cpu.h>
25
26
#include <asm/mipsregs.h>
26
27
#include <asm/io.h>
27
28
#include <asm/sibyte/sb1250.h>
···
183
182
int plldiv;
184
183
int bad_config = 0;
185
184
186
-
sb1_pass = read_c0_prid() & 0xff;
185
+
sb1_pass = read_c0_prid() & PRID_REV_MASK;
187
186
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
188
187
soc_type = SYS_SOC_TYPE(sys_rev);
189
188
soc_pass = G_SYS_REVISION(sys_rev);
+2
-1
arch/mips/sni/setup.c
+2
-1
arch/mips/sni/setup.c
···
25
25
#endif
26
26
27
27
#include <asm/bootinfo.h>
28
+
#include <asm/cpu.h>
28
29
#include <asm/io.h>
29
30
#include <asm/reboot.h>
30
31
#include <asm/sni.h>
···
174
173
system_type = "RM300-Cxx";
175
174
break;
176
175
case SNI_BRD_PCI_DESKTOP:
177
-
switch (read_c0_prid() & 0xff00) {
176
+
switch (read_c0_prid() & PRID_IMP_MASK) {
178
177
case PRID_IMP_R4600:
179
178
case PRID_IMP_R4700:
180
179
system_type = "RM200-C20";
+1
-6
drivers/staging/octeon/ethernet-mem.c
+1
-6
drivers/staging/octeon/ethernet-mem.c
···
48
48
while (freed) {
49
49
50
50
struct sk_buff *skb = dev_alloc_skb(size + 256);
51
-
if (unlikely(skb == NULL)) {
52
-
pr_warning
53
-
("Failed to allocate skb for hardware pool %d\n",
54
-
pool);
51
+
if (unlikely(skb == NULL))
55
52
break;
56
-
}
57
-
58
53
skb_reserve(skb, 256 - (((unsigned long)skb->data) & 0x7f));
59
54
*(struct sk_buff **)(skb->data - sizeof(void *)) = skb;
60
55
cvmx_fpa_free(skb->data, pool, DONT_WRITEBACK(size / 128));
+1
-3
drivers/staging/octeon/ethernet-rgmii.c
+1
-3
drivers/staging/octeon/ethernet-rgmii.c
···
373
373
* Enable interrupts on inband status changes
374
374
* for this port.
375
375
*/
376
-
gmx_rx_int_en.u64 =
377
-
cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
378
-
(index, interface));
376
+
gmx_rx_int_en.u64 = 0;
379
377
gmx_rx_int_en.s.phy_dupx = 1;
380
378
gmx_rx_int_en.s.phy_link = 1;
381
379
gmx_rx_int_en.s.phy_spd = 1;
+1
-4
drivers/staging/octeon/ethernet-rx.c
+1
-4
drivers/staging/octeon/ethernet-rx.c
···
303
303
if (backlog > budget * cores_in_use && napi != NULL)
304
304
cvm_oct_enable_one_cpu();
305
305
}
306
+
rx_count++;
306
307
307
308
skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1;
308
309
if (likely(skb_in_hw)) {
···
337
336
*/
338
337
skb = dev_alloc_skb(work->len);
339
338
if (!skb) {
340
-
printk_ratelimited("Port %d failed to allocate "
341
-
"skbuff, packet dropped\n",
342
-
work->ipprt);
343
339
cvm_oct_free_work(work);
344
340
continue;
345
341
}
···
427
429
#endif
428
430
}
429
431
netif_receive_skb(skb);
430
-
rx_count++;
431
432
} else {
432
433
/* Drop any packet received for a device that isn't up */
433
434
/*