Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Ben was on holidays for a week so a few nouveau regression fixes
backed up, but they all seem necessary.
Otherwise one i915 and one gma500 fix"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
gma500: Fix SDVO turning off randomly
drm/nv04/disp: fix framebuffer pin refcounting
drm/nouveau/mc: fix race condition between constructor and request_irq()
drm/nouveau: fix reclocking on nv40
drm/nouveau/ltcg: fix allocating memory as free
drm/nouveau/ltcg: fix ltcg memory initialization after suspend
drm/nouveau/fb: fix null derefs in nv49 and nv4e init
drm/i915: Invalidate TLBs for the rings after a reset
+114
-49
+2
-1
drivers/gpu/drm/gma500/psb_intel_sdvo.c
+2
-1
drivers/gpu/drm/gma500/psb_intel_sdvo.c
···
500
500
&status))
501
501
goto log_fail;
502
502
503
-
while (status == SDVO_CMD_STATUS_PENDING && retry--) {
503
+
while ((status == SDVO_CMD_STATUS_PENDING ||
504
+
status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) {
504
505
udelay(15);
505
506
if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
506
507
SDVO_I2C_CMD_STATUS,
+2
drivers/gpu/drm/i915/i915_reg.h
+2
drivers/gpu/drm/i915/i915_reg.h
···
752
752
will not assert AGPBUSY# and will only
753
753
be delivered when out of C3. */
754
754
#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
755
+
#define INSTPM_TLB_INVALIDATE (1<<9)
756
+
#define INSTPM_SYNC_FLUSH (1<<5)
755
757
#define ACTHD 0x020c8
756
758
#define FW_BLC 0x020d8
757
759
#define FW_BLC2 0x020dc
+12
drivers/gpu/drm/i915/intel_ringbuffer.c
+12
drivers/gpu/drm/i915/intel_ringbuffer.c
···
968
968
969
969
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
970
970
POSTING_READ(mmio);
971
+
972
+
/* Flush the TLB for this page */
973
+
if (INTEL_INFO(dev)->gen >= 6) {
974
+
u32 reg = RING_INSTPM(ring->mmio_base);
975
+
I915_WRITE(reg,
976
+
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
977
+
INSTPM_SYNC_FLUSH));
978
+
if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
979
+
1000))
980
+
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
981
+
ring->name);
982
+
}
971
983
}
972
984
973
985
static int
+4
drivers/gpu/drm/nouveau/core/core/mm.c
+4
drivers/gpu/drm/nouveau/core/core/mm.c
···
98
98
u32 splitoff;
99
99
u32 s, e;
100
100
101
+
BUG_ON(!type);
102
+
101
103
list_for_each_entry(this, &mm->free, fl_entry) {
102
104
e = this->offset + this->length;
103
105
s = this->offset;
···
163
161
{
164
162
struct nouveau_mm_node *prev, *this, *next;
165
163
u32 mask = align - 1;
164
+
165
+
BUG_ON(!type);
166
166
167
167
list_for_each_entry_reverse(this, &mm->free, fl_entry) {
168
168
u32 e = this->offset + this->length;
+4
-3
drivers/gpu/drm/nouveau/core/include/subdev/mc.h
+4
-3
drivers/gpu/drm/nouveau/core/include/subdev/mc.h
···
20
20
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC];
21
21
}
22
22
23
-
#define nouveau_mc_create(p,e,o,d) \
24
-
nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
23
+
#define nouveau_mc_create(p,e,o,m,d) \
24
+
nouveau_mc_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
25
25
#define nouveau_mc_destroy(p) ({ \
26
26
struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \
27
27
})
···
33
33
})
34
34
35
35
int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
36
-
struct nouveau_oclass *, int, void **);
36
+
struct nouveau_oclass *, const struct nouveau_mc_intr *,
37
+
int, void **);
37
38
void _nouveau_mc_dtor(struct nouveau_object *);
38
39
int _nouveau_mc_init(struct nouveau_object *);
39
40
int _nouveau_mc_fini(struct nouveau_object *, bool);
+6
-6
drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
+6
-6
drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
···
40
40
return ret;
41
41
42
42
switch (pfb914 & 0x00000003) {
43
-
case 0x00000000: pfb->ram->type = NV_MEM_TYPE_DDR1; break;
44
-
case 0x00000001: pfb->ram->type = NV_MEM_TYPE_DDR2; break;
45
-
case 0x00000002: pfb->ram->type = NV_MEM_TYPE_GDDR3; break;
43
+
case 0x00000000: ram->type = NV_MEM_TYPE_DDR1; break;
44
+
case 0x00000001: ram->type = NV_MEM_TYPE_DDR2; break;
45
+
case 0x00000002: ram->type = NV_MEM_TYPE_GDDR3; break;
46
46
case 0x00000003: break;
47
47
}
48
48
49
-
pfb->ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
50
-
pfb->ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
51
-
pfb->ram->tags = nv_rd32(pfb, 0x100320);
49
+
ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
50
+
ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
51
+
ram->tags = nv_rd32(pfb, 0x100320);
52
52
return 0;
53
53
}
54
54
+2
-2
drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
+2
-2
drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
+24
-10
drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
+24
-10
drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
···
30
30
struct nouveau_ltcg base;
31
31
u32 part_nr;
32
32
u32 subp_nr;
33
-
struct nouveau_mm tags;
34
33
u32 num_tags;
34
+
u32 tag_base;
35
+
struct nouveau_mm tags;
35
36
struct nouveau_mm_node *tag_ram;
36
37
};
37
38
···
118
117
u32 tag_size, tag_margin, tag_align;
119
118
int ret;
120
119
121
-
nv_wr32(priv, 0x17e8d8, priv->part_nr);
122
-
if (nv_device(pfb)->card_type >= NV_E0)
123
-
nv_wr32(priv, 0x17e000, priv->part_nr);
124
-
125
120
/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
126
121
priv->num_tags = (pfb->ram->size >> 17) / 4;
127
122
if (priv->num_tags > (1 << 17))
···
139
142
tag_size += tag_align;
140
143
tag_size = (tag_size + 0xfff) >> 12; /* round up */
141
144
142
-
ret = nouveau_mm_tail(&pfb->vram, 0, tag_size, tag_size, 1,
145
+
ret = nouveau_mm_tail(&pfb->vram, 1, tag_size, tag_size, 1,
143
146
&priv->tag_ram);
144
147
if (ret) {
145
148
priv->num_tags = 0;
···
149
152
tag_base += tag_align - 1;
150
153
ret = do_div(tag_base, tag_align);
151
154
152
-
nv_wr32(priv, 0x17e8d4, tag_base);
155
+
priv->tag_base = tag_base;
153
156
}
154
157
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
155
158
···
179
182
}
180
183
priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
181
184
182
-
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
183
-
184
185
ret = nvc0_ltcg_init_tag_ram(pfb, priv);
185
186
if (ret)
186
187
return ret;
···
204
209
nouveau_ltcg_destroy(ltcg);
205
210
}
206
211
212
+
static int
213
+
nvc0_ltcg_init(struct nouveau_object *object)
214
+
{
215
+
struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
216
+
struct nvc0_ltcg_priv *priv = (struct nvc0_ltcg_priv *)ltcg;
217
+
int ret;
218
+
219
+
ret = nouveau_ltcg_init(ltcg);
220
+
if (ret)
221
+
return ret;
222
+
223
+
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
224
+
nv_wr32(priv, 0x17e8d8, priv->part_nr);
225
+
if (nv_device(ltcg)->card_type >= NV_E0)
226
+
nv_wr32(priv, 0x17e000, priv->part_nr);
227
+
nv_wr32(priv, 0x17e8d4, priv->tag_base);
228
+
return 0;
229
+
}
230
+
207
231
struct nouveau_oclass
208
232
nvc0_ltcg_oclass = {
209
233
.handle = NV_SUBDEV(LTCG, 0xc0),
210
234
.ofuncs = &(struct nouveau_ofuncs) {
211
235
.ctor = nvc0_ltcg_ctor,
212
236
.dtor = nvc0_ltcg_dtor,
213
-
.init = _nouveau_ltcg_init,
237
+
.init = nvc0_ltcg_init,
214
238
.fini = _nouveau_ltcg_fini,
215
239
},
216
240
};
+5
-1
drivers/gpu/drm/nouveau/core/subdev/mc/base.c
+5
-1
drivers/gpu/drm/nouveau/core/subdev/mc/base.c
···
80
80
81
81
int
82
82
nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
83
-
struct nouveau_oclass *oclass, int length, void **pobject)
83
+
struct nouveau_oclass *oclass,
84
+
const struct nouveau_mc_intr *intr_map,
85
+
int length, void **pobject)
84
86
{
85
87
struct nouveau_device *device = nv_device(parent);
86
88
struct nouveau_mc *pmc;
···
93
91
pmc = *pobject;
94
92
if (ret)
95
93
return ret;
94
+
95
+
pmc->intr_map = intr_map;
96
96
97
97
ret = request_irq(device->pdev->irq, nouveau_mc_intr,
98
98
IRQF_SHARED, "nouveau", pmc);
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c
···
50
50
struct nv04_mc_priv *priv;
51
51
int ret;
52
52
53
-
ret = nouveau_mc_create(parent, engine, oclass, &priv);
53
+
ret = nouveau_mc_create(parent, engine, oclass, nv04_mc_intr, &priv);
54
54
*pobject = nv_object(priv);
55
55
if (ret)
56
56
return ret;
57
57
58
-
priv->base.intr_map = nv04_mc_intr;
59
58
return 0;
60
59
}
61
60
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
···
36
36
struct nv44_mc_priv *priv;
37
37
int ret;
38
38
39
-
ret = nouveau_mc_create(parent, engine, oclass, &priv);
39
+
ret = nouveau_mc_create(parent, engine, oclass, nv04_mc_intr, &priv);
40
40
*pobject = nv_object(priv);
41
41
if (ret)
42
42
return ret;
43
43
44
-
priv->base.intr_map = nv04_mc_intr;
45
44
return 0;
46
45
}
47
46
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
···
53
53
struct nv50_mc_priv *priv;
54
54
int ret;
55
55
56
-
ret = nouveau_mc_create(parent, engine, oclass, &priv);
56
+
ret = nouveau_mc_create(parent, engine, oclass, nv50_mc_intr, &priv);
57
57
*pobject = nv_object(priv);
58
58
if (ret)
59
59
return ret;
60
60
61
-
priv->base.intr_map = nv50_mc_intr;
62
61
return 0;
63
62
}
64
63
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
···
54
54
struct nv98_mc_priv *priv;
55
55
int ret;
56
56
57
-
ret = nouveau_mc_create(parent, engine, oclass, &priv);
57
+
ret = nouveau_mc_create(parent, engine, oclass, nv98_mc_intr, &priv);
58
58
*pobject = nv_object(priv);
59
59
if (ret)
60
60
return ret;
61
61
62
-
priv->base.intr_map = nv98_mc_intr;
63
62
return 0;
64
63
}
65
64
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+1
-2
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
···
57
57
struct nvc0_mc_priv *priv;
58
58
int ret;
59
59
60
-
ret = nouveau_mc_create(parent, engine, oclass, &priv);
60
+
ret = nouveau_mc_create(parent, engine, oclass, nvc0_mc_intr, &priv);
61
61
*pobject = nv_object(priv);
62
62
if (ret)
63
63
return ret;
64
64
65
-
priv->base.intr_map = nvc0_mc_intr;
66
65
return 0;
67
66
}
68
67
+43
-15
drivers/gpu/drm/nouveau/dispnv04/crtc.c
+43
-15
drivers/gpu/drm/nouveau/dispnv04/crtc.c
···
606
606
regp->ramdac_a34 = 0x1;
607
607
}
608
608
609
+
static int
610
+
nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
611
+
{
612
+
struct nv04_display *disp = nv04_display(crtc->dev);
613
+
struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
614
+
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
615
+
int ret;
616
+
617
+
ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
618
+
if (ret == 0) {
619
+
if (disp->image[nv_crtc->index])
620
+
nouveau_bo_unpin(disp->image[nv_crtc->index]);
621
+
nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);
622
+
}
623
+
624
+
return ret;
625
+
}
626
+
609
627
/**
610
628
* Sets up registers for the given mode/adjusted_mode pair.
611
629
*
···
640
622
struct drm_device *dev = crtc->dev;
641
623
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
642
624
struct nouveau_drm *drm = nouveau_drm(dev);
625
+
int ret;
643
626
644
627
NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
645
628
drm_mode_debug_printmodeline(adjusted_mode);
629
+
630
+
ret = nv_crtc_swap_fbs(crtc, old_fb);
631
+
if (ret)
632
+
return ret;
646
633
647
634
/* unlock must come after turning off FP_TG_CONTROL in output_prepare */
648
635
nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
···
745
722
746
723
static void nv_crtc_destroy(struct drm_crtc *crtc)
747
724
{
725
+
struct nv04_display *disp = nv04_display(crtc->dev);
748
726
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
749
727
750
728
if (!nv_crtc)
751
729
return;
752
730
753
731
drm_crtc_cleanup(crtc);
732
+
733
+
if (disp->image[nv_crtc->index])
734
+
nouveau_bo_unpin(disp->image[nv_crtc->index]);
735
+
nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
754
736
755
737
nouveau_bo_unmap(nv_crtc->cursor.nvbo);
756
738
nouveau_bo_unpin(nv_crtc->cursor.nvbo);
···
779
751
}
780
752
781
753
nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
754
+
}
755
+
756
+
static void
757
+
nv_crtc_disable(struct drm_crtc *crtc)
758
+
{
759
+
struct nv04_display *disp = nv04_display(crtc->dev);
760
+
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
761
+
if (disp->image[nv_crtc->index])
762
+
nouveau_bo_unpin(disp->image[nv_crtc->index]);
763
+
nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
782
764
}
783
765
784
766
static void
···
829
791
struct drm_framebuffer *drm_fb;
830
792
struct nouveau_framebuffer *fb;
831
793
int arb_burst, arb_lwm;
832
-
int ret;
833
794
834
795
NV_DEBUG(drm, "index %d\n", nv_crtc->index);
835
796
···
838
801
return 0;
839
802
}
840
803
841
-
842
804
/* If atomic, we want to switch to the fb we were passed, so
843
-
* now we update pointers to do that. (We don't pin; just
844
-
* assume we're already pinned and update the base address.)
805
+
* now we update pointers to do that.
845
806
*/
846
807
if (atomic) {
847
808
drm_fb = passed_fb;
···
847
812
} else {
848
813
drm_fb = crtc->fb;
849
814
fb = nouveau_framebuffer(crtc->fb);
850
-
/* If not atomic, we can go ahead and pin, and unpin the
851
-
* old fb we were passed.
852
-
*/
853
-
ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
854
-
if (ret)
855
-
return ret;
856
-
857
-
if (passed_fb) {
858
-
struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
859
-
nouveau_bo_unpin(ofb->nvbo);
860
-
}
861
815
}
862
816
863
817
nv_crtc->fb.offset = fb->nvbo->bo.offset;
···
901
877
nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
902
878
struct drm_framebuffer *old_fb)
903
879
{
880
+
int ret = nv_crtc_swap_fbs(crtc, old_fb);
881
+
if (ret)
882
+
return ret;
904
883
return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
905
884
}
906
885
···
1054
1027
.mode_set_base = nv04_crtc_mode_set_base,
1055
1028
.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1056
1029
.load_lut = nv_crtc_gamma_load,
1030
+
.disable = nv_crtc_disable,
1057
1031
};
1058
1032
1059
1033
int
+1
drivers/gpu/drm/nouveau/dispnv04/disp.h
+1
drivers/gpu/drm/nouveau/dispnv04/disp.h
+3
drivers/gpu/drm/nouveau/nouveau_display.c
+3
drivers/gpu/drm/nouveau/nouveau_display.c
···
577
577
ret = nv50_display_flip_next(crtc, fb, chan, 0);
578
578
if (ret)
579
579
goto fail_unreserve;
580
+
} else {
581
+
struct nv04_display *dispnv04 = nv04_display(dev);
582
+
nouveau_bo_ref(new_bo, &dispnv04->image[nouveau_crtc(crtc)->index]);
580
583
}
581
584
582
585
ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);