Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: reset: Add bindings for MT6795 Helio X10 reset controllers
Add the reset controller bindings for MT6795.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220921091455.41327-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
authored by
AngeloGioacchino Del Regno
and committed by
Chen-Yu Tsai
f098c088
32ccd1ab
+53
+53
include/dt-bindings/reset/mediatek,mt6795-resets.h
+53
include/dt-bindings/reset/mediatek,mt6795-resets.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795
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#define _DT_BINDINGS_RESET_CONTROLLER_MT6795
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/* INFRACFG resets */
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#define MT6795_INFRA_RST0_SCPSYS_RST 0
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#define MT6795_INFRA_RST0_PMIC_WRAP_RST 1
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#define MT6795_INFRA_RST1_MIPI_DSI_RST 2
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#define MT6795_INFRA_RST1_MIPI_CSI_RST 3
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#define MT6795_INFRA_RST1_MM_IOMMU_RST 4
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/* MMSYS resets */
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#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0
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#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1
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#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2
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#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3
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#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4
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#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5
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#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6
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#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7
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#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8
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#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9
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#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10
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#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11
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#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12
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#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13
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/* PERICFG resets */
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#define MT6795_PERI_NFI_SW_RST 0
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#define MT6795_PERI_THERM_SW_RST 1
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#define MT6795_PERI_MSDC1_SW_RST 2
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/* TOPRGU resets */
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#define MT6795_TOPRGU_INFRA_SW_RST 0
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#define MT6795_TOPRGU_MM_SW_RST 1
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#define MT6795_TOPRGU_MFG_SW_RST 2
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#define MT6795_TOPRGU_VENC_SW_RST 3
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#define MT6795_TOPRGU_VDEC_SW_RST 4
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#define MT6795_TOPRGU_IMG_SW_RST 5
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#define MT6795_TOPRGU_DDRPHY_SW_RST 6
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#define MT6795_TOPRGU_MD_SW_RST 7
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#define MT6795_TOPRGU_INFRA_AO_SW_RST 8
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#define MT6795_TOPRGU_MD_LITE_SW_RST 9
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#define MT6795_TOPRGU_APMIXED_SW_RST 10
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#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11
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#define MT6795_TOPRGU_SW_RST_NUM 12
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */