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Merge branch 'net-dsa-lantiq_gswip-use-regmap-for-register-access'

Daniel Golle says:

====================
net: dsa: lantiq_gswip: use regmap for register access

This series refactors the lantiq_gswip driver to utilize the regmap API
for register access, replacing the previous approach of open-coding
register operations.

Using regmap paves the way for supporting different busses to access the
switch registers, for example it makes it easier to use an MDIO-based
method required to access the registers of the MaxLinear GSW1xx series
of dedicated switch ICs.

Apart from that, the use of regmap improves readability and
maintainability of the driver by standardizing register access.

When ever possible changes were made using Coccinelle semantic patches,
sometimes adjusting white space and adding line breaks when needed.
The remaining changes which were not done using semantic patches are
small and should be easy to review and verify.

The whole series has been
Tested-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
====================

Link: https://patch.msgid.link/cover.1761045000.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski f0a24b25 05774d7e

+242 -234
+1
drivers/net/dsa/lantiq/Kconfig
··· 2 2 tristate "Lantiq / Intel GSWIP" 3 3 depends on HAS_IOMEM 4 4 select NET_DSA_TAG_GSWIP 5 + select REGMAP 5 6 help 6 7 This enables support for the Lantiq / Intel GSWIP 2.1 found in 7 8 the xrx200 / VR9 SoC.
+238 -231
drivers/net/dsa/lantiq/lantiq_gswip.c
··· 111 111 MIB_DESC(2, 0x0E, "TxGoodBytes"), 112 112 }; 113 113 114 - static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 115 - { 116 - return __raw_readl(priv->gswip + (offset * 4)); 117 - } 118 - 119 - static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 120 - { 121 - __raw_writel(val, priv->gswip + (offset * 4)); 122 - } 123 - 124 - static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 125 - u32 offset) 126 - { 127 - u32 val = gswip_switch_r(priv, offset); 128 - 129 - val &= ~(clear); 130 - val |= set; 131 - gswip_switch_w(priv, val, offset); 132 - } 133 - 134 114 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 135 115 u32 cleared) 136 116 { 137 117 u32 val; 138 118 139 - return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 140 - (val & cleared) == 0, 20, 50000); 119 + return regmap_read_poll_timeout(priv->gswip, offset, val, 120 + !(val & cleared), 20, 50000); 141 121 } 142 122 143 - static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 144 - { 145 - return __raw_readl(priv->mdio + (offset * 4)); 146 - } 147 - 148 - static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 149 - { 150 - __raw_writel(val, priv->mdio + (offset * 4)); 151 - } 152 - 153 - static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 154 - u32 offset) 155 - { 156 - u32 val = gswip_mdio_r(priv, offset); 157 - 158 - val &= ~(clear); 159 - val |= set; 160 - gswip_mdio_w(priv, val, offset); 161 - } 162 - 163 - static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 164 - { 165 - return __raw_readl(priv->mii + (offset * 4)); 166 - } 167 - 168 - static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 169 - { 170 - __raw_writel(val, priv->mii + (offset * 4)); 171 - } 172 - 173 - static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 174 - u32 offset) 175 - { 176 - u32 val = gswip_mii_r(priv, offset); 177 - 178 - val &= ~(clear); 179 - val |= set; 180 - gswip_mii_w(priv, val, offset); 181 - } 182 - 183 - static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 123 + static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set, 184 124 int port) 185 125 { 186 126 int reg_port; ··· 131 191 132 192 reg_port = port + priv->hw_info->mii_port_reg_offset; 133 193 134 - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port)); 194 + regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask, 195 + set); 135 196 } 136 197 137 - static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 198 + static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 mask, u32 set, 138 199 int port) 139 200 { 140 201 int reg_port; ··· 148 207 149 208 switch (reg_port) { 150 209 case 0: 151 - gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 210 + regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, mask, set); 152 211 break; 153 212 case 1: 154 - gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 213 + regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, mask, set); 155 214 break; 156 215 case 5: 157 - gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 216 + regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, mask, set); 158 217 break; 159 218 } 160 219 } 161 220 162 221 static int gswip_mdio_poll(struct gswip_priv *priv) 163 222 { 164 - int cnt = 100; 223 + u32 ctrl; 165 224 166 - while (likely(cnt--)) { 167 - u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 168 - 169 - if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 170 - return 0; 171 - usleep_range(20, 40); 172 - } 173 - 174 - return -ETIMEDOUT; 225 + return regmap_read_poll_timeout(priv->mdio, GSWIP_MDIO_CTRL, ctrl, 226 + !(ctrl & GSWIP_MDIO_CTRL_BUSY), 40, 4000); 175 227 } 176 228 177 229 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) ··· 178 244 return err; 179 245 } 180 246 181 - gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 182 - gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 183 - ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 184 - (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 185 - GSWIP_MDIO_CTRL); 247 + regmap_write(priv->mdio, GSWIP_MDIO_WRITE, val); 248 + regmap_write(priv->mdio, GSWIP_MDIO_CTRL, 249 + GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 250 + ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 251 + (reg & GSWIP_MDIO_CTRL_REGAD_MASK)); 186 252 187 253 return 0; 188 254 } ··· 190 256 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 191 257 { 192 258 struct gswip_priv *priv = bus->priv; 259 + u32 val; 193 260 int err; 194 261 195 262 err = gswip_mdio_poll(priv); ··· 199 264 return err; 200 265 } 201 266 202 - gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 203 - ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 204 - (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 205 - GSWIP_MDIO_CTRL); 267 + regmap_write(priv->mdio, GSWIP_MDIO_CTRL, 268 + GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 269 + ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 270 + (reg & GSWIP_MDIO_CTRL_REGAD_MASK)); 206 271 207 272 err = gswip_mdio_poll(priv); 208 273 if (err) { ··· 210 275 return err; 211 276 } 212 277 213 - return gswip_mdio_r(priv, GSWIP_MDIO_READ); 278 + err = regmap_read(priv->mdio, GSWIP_MDIO_READ, &val); 279 + if (err) 280 + return err; 281 + 282 + return val; 214 283 } 215 284 216 285 static int gswip_mdio(struct gswip_priv *priv) ··· 257 318 { 258 319 int i; 259 320 int err; 260 - u16 crtl; 321 + u32 crtl; 322 + u32 tmp; 261 323 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 262 324 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 263 325 ··· 266 326 267 327 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 268 328 GSWIP_PCE_TBL_CTRL_BAS); 269 - if (err) { 270 - mutex_unlock(&priv->pce_table_lock); 271 - return err; 272 - } 329 + if (err) 330 + goto out_unlock; 273 331 274 - gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 275 - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 276 - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 277 - tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 278 - GSWIP_PCE_TBL_CTRL); 332 + regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); 333 + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, 334 + GSWIP_PCE_TBL_CTRL_ADDR_MASK | 335 + GSWIP_PCE_TBL_CTRL_OPMOD_MASK | 336 + GSWIP_PCE_TBL_CTRL_BAS, 337 + tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS); 279 338 280 339 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 281 340 GSWIP_PCE_TBL_CTRL_BAS); 282 - if (err) { 283 - mutex_unlock(&priv->pce_table_lock); 284 - return err; 341 + if (err) 342 + goto out_unlock; 343 + 344 + for (i = 0; i < ARRAY_SIZE(tbl->key); i++) { 345 + err = regmap_read(priv->gswip, GSWIP_PCE_TBL_KEY(i), &tmp); 346 + if (err) 347 + goto out_unlock; 348 + tbl->key[i] = tmp; 349 + } 350 + for (i = 0; i < ARRAY_SIZE(tbl->val); i++) { 351 + err = regmap_read(priv->gswip, GSWIP_PCE_TBL_VAL(i), &tmp); 352 + if (err) 353 + goto out_unlock; 354 + tbl->val[i] = tmp; 285 355 } 286 356 287 - for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 288 - tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 357 + err = regmap_read(priv->gswip, GSWIP_PCE_TBL_MASK, &tmp); 358 + if (err) 359 + goto out_unlock; 289 360 290 - for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 291 - tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 292 - 293 - tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 294 - 295 - crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 361 + tbl->mask = tmp; 362 + err = regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &crtl); 363 + if (err) 364 + goto out_unlock; 296 365 297 366 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 298 367 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 299 368 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 300 369 370 + out_unlock: 301 371 mutex_unlock(&priv->pce_table_lock); 302 372 303 - return 0; 373 + return err; 304 374 } 305 375 306 376 static int gswip_pce_table_entry_write(struct gswip_priv *priv, ··· 318 368 { 319 369 int i; 320 370 int err; 321 - u16 crtl; 371 + u32 crtl; 322 372 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 323 373 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 324 374 ··· 331 381 return err; 332 382 } 333 383 334 - gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 335 - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 336 - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 337 - tbl->table | addr_mode, 338 - GSWIP_PCE_TBL_CTRL); 384 + regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); 385 + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, 386 + GSWIP_PCE_TBL_CTRL_ADDR_MASK | 387 + GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 388 + tbl->table | addr_mode); 339 389 340 390 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 341 - gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 391 + regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]); 342 392 343 393 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 344 - gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 394 + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]); 345 395 346 - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 347 - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 348 - tbl->table | addr_mode, 349 - GSWIP_PCE_TBL_CTRL); 396 + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, 397 + GSWIP_PCE_TBL_CTRL_ADDR_MASK | 398 + GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 399 + tbl->table | addr_mode); 350 400 351 - gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 401 + regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask); 352 402 353 - crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 403 + regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &crtl); 354 404 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 355 405 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 356 406 if (tbl->type) ··· 359 409 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 360 410 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 361 411 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 362 - gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 412 + regmap_write(priv->gswip, GSWIP_PCE_TBL_CTRL, crtl); 363 413 364 414 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 365 415 GSWIP_PCE_TBL_CTRL_BAS); ··· 433 483 if (phydev) 434 484 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 435 485 436 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 437 - GSWIP_MDIO_PHYp(port)); 486 + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), 487 + GSWIP_MDIO_PHY_ADDR_MASK, 488 + mdio_phy); 438 489 } 439 490 440 491 /* RMON Counter Enable for port */ 441 - gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 492 + regmap_write(priv->gswip, GSWIP_BM_PCFGp(port), GSWIP_BM_PCFG_CNTEN); 442 493 443 494 /* enable port fetch/store dma & VLAN Modification */ 444 - gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 445 - GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 446 - GSWIP_FDMA_PCTRLp(port)); 447 - gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 448 - GSWIP_SDMA_PCTRLp(port)); 495 + regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port), 496 + GSWIP_FDMA_PCTRL_EN | GSWIP_FDMA_PCTRL_VLANMOD_BOTH); 497 + regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), 498 + GSWIP_SDMA_PCTRL_EN); 449 499 450 500 return 0; 451 501 } ··· 454 504 { 455 505 struct gswip_priv *priv = ds->priv; 456 506 457 - gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 458 - GSWIP_FDMA_PCTRLp(port)); 459 - gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 460 - GSWIP_SDMA_PCTRLp(port)); 507 + regmap_clear_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port), 508 + GSWIP_FDMA_PCTRL_EN); 509 + regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), 510 + GSWIP_SDMA_PCTRL_EN); 461 511 } 462 512 463 513 static int gswip_pce_load_microcode(struct gswip_priv *priv) ··· 465 515 int i; 466 516 int err; 467 517 468 - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 469 - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 470 - GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 471 - gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 518 + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, 519 + GSWIP_PCE_TBL_CTRL_ADDR_MASK | 520 + GSWIP_PCE_TBL_CTRL_OPMOD_MASK | 521 + GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, 522 + GSWIP_PCE_TBL_CTRL_OPMOD_ADWR); 523 + regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0); 472 524 473 525 for (i = 0; i < priv->hw_info->pce_microcode_size; i++) { 474 - gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 475 - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_0, 476 - GSWIP_PCE_TBL_VAL(0)); 477 - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_1, 478 - GSWIP_PCE_TBL_VAL(1)); 479 - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_2, 480 - GSWIP_PCE_TBL_VAL(2)); 481 - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_3, 482 - GSWIP_PCE_TBL_VAL(3)); 526 + regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, i); 527 + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(0), 528 + (*priv->hw_info->pce_microcode)[i].val_0); 529 + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(1), 530 + (*priv->hw_info->pce_microcode)[i].val_1); 531 + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(2), 532 + (*priv->hw_info->pce_microcode)[i].val_2); 533 + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(3), 534 + (*priv->hw_info->pce_microcode)[i].val_3); 483 535 484 536 /* start the table access: */ 485 - gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 486 - GSWIP_PCE_TBL_CTRL); 537 + regmap_set_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, 538 + GSWIP_PCE_TBL_CTRL_BAS); 487 539 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 488 540 GSWIP_PCE_TBL_CTRL_BAS); 489 541 if (err) ··· 493 541 } 494 542 495 543 /* tell the switch that the microcode is loaded */ 496 - gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 497 - GSWIP_PCE_GCTRL_0); 544 + regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0, 545 + GSWIP_PCE_GCTRL_0_MC_VALID); 498 546 499 547 return 0; 500 548 } ··· 536 584 } 537 585 538 586 vinr = idx ? GSWIP_PCE_VCTRL_VINR_ALL : GSWIP_PCE_VCTRL_VINR_TAGGED; 539 - gswip_switch_mask(priv, GSWIP_PCE_VCTRL_VINR, 540 - FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr), 541 - GSWIP_PCE_VCTRL(port)); 587 + regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port), 588 + GSWIP_PCE_VCTRL_VINR, 589 + FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr)); 542 590 543 - /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 544 - gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 591 + /* Note that in GSWIP 2.2 VLAN mode the VID needs to be programmed 592 + * directly instead of referencing the index in the Active VLAN Tablet. 593 + * However, without the VLANMD bit (9) in PCE_GCTRL_1 (0x457) even 594 + * GSWIP 2.2 and newer hardware maintain the GSWIP 2.1 behavior. 595 + */ 596 + regmap_write(priv->gswip, GSWIP_PCE_DEFPVID(port), idx); 545 597 } 546 598 547 599 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, ··· 556 600 557 601 if (vlan_filtering) { 558 602 /* Use tag based VLAN */ 559 - gswip_switch_mask(priv, 560 - GSWIP_PCE_VCTRL_VSR, 561 - GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 562 - GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VID0, 563 - GSWIP_PCE_VCTRL(port)); 564 - gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 565 - GSWIP_PCE_PCTRL_0p(port)); 603 + regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port), 604 + GSWIP_PCE_VCTRL_VSR | 605 + GSWIP_PCE_VCTRL_UVR | 606 + GSWIP_PCE_VCTRL_VIMR | 607 + GSWIP_PCE_VCTRL_VEMR | 608 + GSWIP_PCE_VCTRL_VID0, 609 + GSWIP_PCE_VCTRL_UVR | 610 + GSWIP_PCE_VCTRL_VIMR | 611 + GSWIP_PCE_VCTRL_VEMR | 612 + GSWIP_PCE_VCTRL_VID0); 613 + regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), 614 + GSWIP_PCE_PCTRL_0_TVM); 566 615 } else { 567 616 /* Use port based VLAN */ 568 - gswip_switch_mask(priv, 569 - GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 570 - GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VID0, 617 + regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port), 618 + GSWIP_PCE_VCTRL_UVR | 619 + GSWIP_PCE_VCTRL_VIMR | 620 + GSWIP_PCE_VCTRL_VEMR | 621 + GSWIP_PCE_VCTRL_VID0 | 571 622 GSWIP_PCE_VCTRL_VSR, 572 - GSWIP_PCE_VCTRL(port)); 573 - gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 574 - GSWIP_PCE_PCTRL_0p(port)); 623 + GSWIP_PCE_VCTRL_VSR); 624 + regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), 625 + GSWIP_PCE_PCTRL_0_TVM); 575 626 } 576 627 577 628 gswip_port_commit_pvid(priv, port); ··· 593 630 struct dsa_port *cpu_dp; 594 631 int err, i; 595 632 596 - gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 633 + regmap_write(priv->gswip, GSWIP_SWRES, GSWIP_SWRES_R0); 597 634 usleep_range(5000, 10000); 598 - gswip_switch_w(priv, 0, GSWIP_SWRES); 635 + regmap_write(priv->gswip, GSWIP_SWRES, 0); 599 636 600 637 /* disable port fetch/store dma on all ports */ 601 638 for (i = 0; i < priv->hw_info->max_ports; i++) { ··· 604 641 } 605 642 606 643 /* enable Switch */ 607 - gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 644 + regmap_set_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE); 608 645 609 646 err = gswip_pce_load_microcode(priv); 610 647 if (err) { ··· 613 650 } 614 651 615 652 /* Default unknown Broadcast/Multicast/Unicast port maps */ 616 - gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP1); 617 - gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP2); 618 - gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP3); 653 + regmap_write(priv->gswip, GSWIP_PCE_PMAP1, cpu_ports); 654 + regmap_write(priv->gswip, GSWIP_PCE_PMAP2, cpu_ports); 655 + regmap_write(priv->gswip, GSWIP_PCE_PMAP3, cpu_ports); 619 656 620 657 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 621 658 * interoperability problem with this auto polling mechanism because ··· 633 670 * Testing shows that when PHY auto polling is disabled these problems 634 671 * go away. 635 672 */ 636 - gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 673 + regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0); 637 674 638 675 /* Configure the MDIO Clock 2.5 MHz */ 639 - gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 676 + regmap_write_bits(priv->mdio, GSWIP_MDIO_MDC_CFG1, 0xff, 0x09); 640 677 641 678 /* bring up the mdio bus */ 642 679 err = gswip_mdio(priv); ··· 653 690 654 691 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 655 692 /* enable special tag insertion on cpu port */ 656 - gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 657 - GSWIP_FDMA_PCTRLp(cpu_dp->index)); 693 + regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(cpu_dp->index), 694 + GSWIP_FDMA_PCTRL_STEN); 658 695 659 696 /* accept special tag in ingress direction */ 660 - gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 661 - GSWIP_PCE_PCTRL_0p(cpu_dp->index)); 697 + regmap_set_bits(priv->gswip, 698 + GSWIP_PCE_PCTRL_0p(cpu_dp->index), 699 + GSWIP_PCE_PCTRL_0_INGRESS); 662 700 } 663 701 664 - gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 665 - GSWIP_BM_QUEUE_GCTRL); 702 + regmap_set_bits(priv->gswip, GSWIP_BM_QUEUE_GCTRL, 703 + GSWIP_BM_QUEUE_GCTRL_GL_MOD); 666 704 667 705 /* VLAN aware Switching */ 668 - gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 706 + regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0, 707 + GSWIP_PCE_GCTRL_0_VLAN); 669 708 670 709 /* Flush MAC Table */ 671 - gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 710 + regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0, 711 + GSWIP_PCE_GCTRL_0_MTFL); 672 712 673 713 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 674 714 GSWIP_PCE_GCTRL_0_MTFL); ··· 1057 1091 1058 1092 switch (state) { 1059 1093 case BR_STATE_DISABLED: 1060 - gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1061 - GSWIP_SDMA_PCTRLp(port)); 1094 + regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), 1095 + GSWIP_SDMA_PCTRL_EN); 1062 1096 return; 1063 1097 case BR_STATE_BLOCKING: 1064 1098 case BR_STATE_LISTENING: ··· 1075 1109 return; 1076 1110 } 1077 1111 1078 - gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1079 - GSWIP_SDMA_PCTRLp(port)); 1080 - gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1081 - GSWIP_PCE_PCTRL_0p(port)); 1112 + regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), 1113 + GSWIP_SDMA_PCTRL_EN); 1114 + regmap_write_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), 1115 + GSWIP_PCE_PCTRL_0_PSTATE_MASK, 1116 + stp_state); 1082 1117 } 1083 1118 1084 1119 static int gswip_port_fdb(struct dsa_switch *ds, int port, ··· 1206 1239 */ 1207 1240 if (dsa_is_cpu_port(ds, port)) { 1208 1241 new_mtu += 8; 1209 - gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, 1210 - GSWIP_MAC_FLEN); 1242 + regmap_write(priv->gswip, GSWIP_MAC_FLEN, 1243 + VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN); 1211 1244 } 1212 1245 1213 1246 /* Enable MLEN for ports with non-standard MTUs, including the special 1214 1247 * header on the CPU port added above. 1215 1248 */ 1216 1249 if (new_mtu != ETH_DATA_LEN) 1217 - gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 1218 - GSWIP_MAC_CTRL_2p(port)); 1250 + regmap_set_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port), 1251 + GSWIP_MAC_CTRL_2_MLEN); 1219 1252 else 1220 - gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, 1221 - GSWIP_MAC_CTRL_2p(port)); 1253 + regmap_clear_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port), 1254 + GSWIP_MAC_CTRL_2_MLEN); 1222 1255 1223 1256 return 0; 1224 1257 } ··· 1308 1341 else 1309 1342 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1310 1343 1311 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1312 - GSWIP_MDIO_PHYp(port)); 1344 + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), 1345 + GSWIP_MDIO_PHY_LINK_MASK, mdio_phy); 1313 1346 } 1314 1347 1315 1348 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, ··· 1349 1382 break; 1350 1383 } 1351 1384 1352 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1353 - GSWIP_MDIO_PHYp(port)); 1385 + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), 1386 + GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy); 1354 1387 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1355 - gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1356 - GSWIP_MAC_CTRL_0p(port)); 1388 + regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port), 1389 + GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0); 1357 1390 } 1358 1391 1359 1392 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) ··· 1368 1401 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1369 1402 } 1370 1403 1371 - gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1372 - GSWIP_MAC_CTRL_0p(port)); 1373 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1374 - GSWIP_MDIO_PHYp(port)); 1404 + regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port), 1405 + GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0); 1406 + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), 1407 + GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy); 1375 1408 } 1376 1409 1377 1410 static void gswip_port_set_pause(struct gswip_priv *priv, int port, ··· 1397 1430 GSWIP_MDIO_PHY_FCONRX_DIS; 1398 1431 } 1399 1432 1400 - gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1401 - mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1402 - gswip_mdio_mask(priv, 1403 - GSWIP_MDIO_PHY_FCONTX_MASK | 1404 - GSWIP_MDIO_PHY_FCONRX_MASK, 1405 - mdio_phy, GSWIP_MDIO_PHYp(port)); 1433 + regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port), 1434 + GSWIP_MAC_CTRL_0_FCON_MASK, mac_ctrl_0); 1435 + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), 1436 + GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK, 1437 + mdio_phy); 1406 1438 } 1407 1439 1408 1440 static void gswip_phylink_mac_config(struct phylink_config *config, ··· 1498 1532 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1499 1533 } 1500 1534 1501 - gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1535 + gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, GSWIP_MII_CFG_EN, port); 1502 1536 } 1503 1537 1504 1538 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, ··· 1516 1550 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1517 1551 u32 index) 1518 1552 { 1519 - u32 result; 1553 + u32 result, val; 1520 1554 int err; 1521 1555 1522 - gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1523 - gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1524 - GSWIP_BM_RAM_CTRL_OPMOD, 1525 - table | GSWIP_BM_RAM_CTRL_BAS, 1526 - GSWIP_BM_RAM_CTRL); 1556 + regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index); 1557 + regmap_write_bits(priv->gswip, GSWIP_BM_RAM_CTRL, 1558 + GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD | 1559 + GSWIP_BM_RAM_CTRL_BAS, 1560 + table | GSWIP_BM_RAM_CTRL_BAS); 1527 1561 1528 1562 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1529 1563 GSWIP_BM_RAM_CTRL_BAS); ··· 1533 1567 return 0; 1534 1568 } 1535 1569 1536 - result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1537 - result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1570 + regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(0), &result); 1571 + regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(1), &val); 1572 + result |= val << 16; 1538 1573 1539 1574 return result; 1540 1575 } ··· 1856 1889 return 0; 1857 1890 } 1858 1891 1892 + static const struct regmap_config sw_regmap_config = { 1893 + .name = "switch", 1894 + .reg_bits = 32, 1895 + .val_bits = 32, 1896 + .reg_shift = REGMAP_UPSHIFT(2), 1897 + .val_format_endian = REGMAP_ENDIAN_NATIVE, 1898 + .max_register = GSWIP_SDMA_PCTRLp(6), 1899 + }; 1900 + 1901 + static const struct regmap_config mdio_regmap_config = { 1902 + .name = "mdio", 1903 + .reg_bits = 32, 1904 + .val_bits = 32, 1905 + .reg_shift = REGMAP_UPSHIFT(2), 1906 + .val_format_endian = REGMAP_ENDIAN_NATIVE, 1907 + .max_register = GSWIP_MDIO_PHYp(0), 1908 + }; 1909 + 1910 + static const struct regmap_config mii_regmap_config = { 1911 + .name = "mii", 1912 + .reg_bits = 32, 1913 + .val_bits = 32, 1914 + .reg_shift = REGMAP_UPSHIFT(2), 1915 + .val_format_endian = REGMAP_ENDIAN_NATIVE, 1916 + .max_register = GSWIP_MII_CFGp(6), 1917 + }; 1918 + 1859 1919 static int gswip_probe(struct platform_device *pdev) 1860 1920 { 1861 1921 struct device_node *np, *gphy_fw_np; 1922 + __iomem void *gswip, *mdio, *mii; 1862 1923 struct device *dev = &pdev->dev; 1863 1924 struct gswip_priv *priv; 1864 1925 int err; ··· 1897 1902 if (!priv) 1898 1903 return -ENOMEM; 1899 1904 1900 - priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1905 + gswip = devm_platform_ioremap_resource(pdev, 0); 1906 + if (IS_ERR(gswip)) 1907 + return PTR_ERR(gswip); 1908 + 1909 + mdio = devm_platform_ioremap_resource(pdev, 1); 1910 + if (IS_ERR(mdio)) 1911 + return PTR_ERR(mdio); 1912 + 1913 + mii = devm_platform_ioremap_resource(pdev, 2); 1914 + if (IS_ERR(mii)) 1915 + return PTR_ERR(mii); 1916 + 1917 + priv->gswip = devm_regmap_init_mmio(dev, gswip, &sw_regmap_config); 1901 1918 if (IS_ERR(priv->gswip)) 1902 1919 return PTR_ERR(priv->gswip); 1903 1920 1904 - priv->mdio = devm_platform_ioremap_resource(pdev, 1); 1921 + priv->mdio = devm_regmap_init_mmio(dev, mdio, &mdio_regmap_config); 1905 1922 if (IS_ERR(priv->mdio)) 1906 1923 return PTR_ERR(priv->mdio); 1907 1924 1908 - priv->mii = devm_platform_ioremap_resource(pdev, 2); 1925 + priv->mii = devm_regmap_init_mmio(dev, mii, &mii_regmap_config); 1909 1926 if (IS_ERR(priv->mii)) 1910 1927 return PTR_ERR(priv->mii); 1911 1928 ··· 1936 1929 priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops; 1937 1930 priv->dev = dev; 1938 1931 mutex_init(&priv->pce_table_lock); 1939 - version = gswip_switch_r(priv, GSWIP_VERSION); 1932 + regmap_read(priv->gswip, GSWIP_VERSION, &version); 1940 1933 1941 1934 /* The hardware has the 'major/minor' version bytes in the wrong order 1942 1935 * preventing numerical comparisons. Construct a 16-bit unsigned integer ··· 1993 1986 return 0; 1994 1987 1995 1988 disable_switch: 1996 - gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1989 + regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE); 1997 1990 dsa_unregister_switch(priv->ds); 1998 1991 gphy_fw_remove: 1999 1992 for (i = 0; i < priv->num_gphy_fw; i++) ··· 2010 2003 return; 2011 2004 2012 2005 /* disable the switch */ 2013 - gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2006 + regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE); 2014 2007 2015 2008 dsa_unregister_switch(priv->ds); 2016 2009
+3 -3
drivers/net/dsa/lantiq/lantiq_gswip.h
··· 263 263 }; 264 264 265 265 struct gswip_priv { 266 - __iomem void *gswip; 267 - __iomem void *mdio; 268 - __iomem void *mii; 266 + struct regmap *gswip; 267 + struct regmap *mdio; 268 + struct regmap *mii; 269 269 const struct gswip_hw_info *hw_info; 270 270 const struct xway_gphy_match_data *gphy_fw_name_cfg; 271 271 struct dsa_switch *ds;