Merge tag 'dmaengine-fix-4.10-rc4' of git://git.infradead.org/users/vkoul/slave-dma

+9 -8

MAINTAINERS

··· 2193 2193 S: Supported 2194 2194 F: sound/soc/atmel 2195 2195 2196 - ATMEL DMA DRIVER 2197 - M: Nicolas Ferre <nicolas.ferre@atmel.com> 2198 - L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 2199 - S: Supported 2200 - F: drivers/dma/at_hdmac.c 2201 - F: drivers/dma/at_hdmac_regs.h 2202 - F: include/linux/platform_data/dma-atmel.h 2203 - 2204 2196 ATMEL XDMA DRIVER 2205 2197 M: Ludovic Desroches <ludovic.desroches@atmel.com> 2206 2198 L: linux-arm-kernel@lists.infradead.org ··· 8169 8177 S: Maintained 8170 8178 F: drivers/tty/serial/atmel_serial.c 8171 8179 F: include/linux/atmel_serial.h 8180 + 8181 + MICROCHIP / ATMEL DMA DRIVER 8182 + M: Ludovic Desroches <ludovic.desroches@microchip.com> 8183 + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 8184 + L: dmaengine@vger.kernel.org 8185 + S: Supported 8186 + F: drivers/dma/at_hdmac.c 8187 + F: drivers/dma/at_hdmac_regs.h 8188 + F: include/linux/platform_data/dma-atmel.h 8172 8189 8173 8190 MICROCHIP / ATMEL ISC DRIVER 8174 8191 M: Songjun Wu <songjun.wu@microchip.com>

+1 -1

drivers/dma/dw/Kconfig

··· 24 24 select DW_DMAC_CORE 25 25 help 26 26 Support the Synopsys DesignWare AHB DMA controller on the 27 - platfroms that enumerate it as a PCI device. For example, 27 + platforms that enumerate it as a PCI device. For example, 28 28 Intel Medfield has integrated this GPDMA controller.

+2

drivers/dma/ioat/hw.h

··· 64 64 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e 65 65 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f 66 66 67 + #define PCI_DEVICE_ID_INTEL_IOAT_SKX 0x2021 68 + 67 69 #define IOAT_VER_1_2 0x12 /* Version 1.2 */ 68 70 #define IOAT_VER_2_0 0x20 /* Version 2.0 */ 69 71 #define IOAT_VER_3_0 0x30 /* Version 3.0 */

+12 -3

drivers/dma/ioat/init.c

··· 106 106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 107 107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 108 108 109 + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) }, 110 + 109 111 /* I/OAT v3.3 platforms */ 110 112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 111 113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, ··· 245 243 } 246 244 } 247 245 246 + static inline bool is_skx_ioat(struct pci_dev *pdev) 247 + { 248 + return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false; 249 + } 250 + 248 251 static bool is_xeon_cb32(struct pci_dev *pdev) 249 252 { 250 253 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 251 - is_hsw_ioat(pdev) || is_bdx_ioat(pdev); 254 + is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev); 252 255 } 253 256 254 257 bool is_bwd_ioat(struct pci_dev *pdev) ··· 700 693 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 701 694 ioat_chan->completion = 702 695 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, 703 - GFP_KERNEL, &ioat_chan->completion_dma); 696 + GFP_NOWAIT, &ioat_chan->completion_dma); 704 697 if (!ioat_chan->completion) 705 698 return -ENOMEM; 706 699 ··· 710 703 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 711 704 712 705 order = IOAT_MAX_ORDER; 713 - ring = ioat_alloc_ring(c, order, GFP_KERNEL); 706 + ring = ioat_alloc_ring(c, order, GFP_NOWAIT); 714 707 if (!ring) 715 708 return -ENOMEM; 716 709 ··· 1364 1357 1365 1358 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1366 1359 if (device->version >= IOAT_VER_3_0) { 1360 + if (is_skx_ioat(pdev)) 1361 + device->version = IOAT_VER_3_2; 1367 1362 err = ioat3_dma_probe(device, ioat_dca_enabled); 1368 1363 1369 1364 if (device->version >= IOAT_VER_3_3)

+42 -29

drivers/dma/omap-dma.c

··· 938 938 d->ccr |= CCR_DST_AMODE_POSTINC; 939 939 if (port_window) { 940 940 d->ccr |= CCR_SRC_AMODE_DBLIDX; 941 + 942 + if (port_window_bytes >= 64) 943 + d->csdp |= CSDP_SRC_BURST_64; 944 + else if (port_window_bytes >= 32) 945 + d->csdp |= CSDP_SRC_BURST_32; 946 + else if (port_window_bytes >= 16) 947 + d->csdp |= CSDP_SRC_BURST_16; 948 + 949 + } else { 950 + d->ccr |= CCR_SRC_AMODE_CONSTANT; 951 + } 952 + } else { 953 + d->csdp = CSDP_SRC_BURST_64 | CSDP_SRC_PACKED; 954 + 955 + d->ccr |= CCR_SRC_AMODE_POSTINC; 956 + if (port_window) { 957 + d->ccr |= CCR_DST_AMODE_DBLIDX; 941 958 d->ei = 1; 942 959 /* 943 960 * One frame covers the port_window and by configure ··· 965 948 d->fi = -(port_window_bytes - 1); 966 949 967 950 if (port_window_bytes >= 64) 968 - d->csdp = CSDP_SRC_BURST_64 | CSDP_SRC_PACKED; 951 + d->csdp |= CSDP_DST_BURST_64; 969 952 else if (port_window_bytes >= 32) 970 - d->csdp = CSDP_SRC_BURST_32 | CSDP_SRC_PACKED; 953 + d->csdp |= CSDP_DST_BURST_32; 971 954 else if (port_window_bytes >= 16) 972 - d->csdp = CSDP_SRC_BURST_16 | CSDP_SRC_PACKED; 973 - } else { 974 - d->ccr |= CCR_SRC_AMODE_CONSTANT; 975 - } 976 - } else { 977 - d->csdp = CSDP_SRC_BURST_64 | CSDP_SRC_PACKED; 978 - 979 - d->ccr |= CCR_SRC_AMODE_POSTINC; 980 - if (port_window) { 981 - d->ccr |= CCR_DST_AMODE_DBLIDX; 982 - 983 - if (port_window_bytes >= 64) 984 - d->csdp = CSDP_DST_BURST_64 | CSDP_DST_PACKED; 985 - else if (port_window_bytes >= 32) 986 - d->csdp = CSDP_DST_BURST_32 | CSDP_DST_PACKED; 987 - else if (port_window_bytes >= 16) 988 - d->csdp = CSDP_DST_BURST_16 | CSDP_DST_PACKED; 955 + d->csdp |= CSDP_DST_BURST_16; 989 956 } else { 990 957 d->ccr |= CCR_DST_AMODE_CONSTANT; 991 958 } ··· 1018 1017 osg->addr = sg_dma_address(sgent); 1019 1018 osg->en = en; 1020 1019 osg->fn = sg_dma_len(sgent) / frame_bytes; 1021 - if (port_window && dir == DMA_MEM_TO_DEV) { 1020 + if (port_window && dir == DMA_DEV_TO_MEM) { 1022 1021 osg->ei = 1; 1023 1022 /* 1024 1023 * One frame covers the port_window and by configure ··· 1453 1452 struct omap_dmadev *od; 1454 1453 struct resource *res; 1455 1454 int rc, i, irq; 1455 + u32 lch_count; 1456 1456 1457 1457 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); 1458 1458 if (!od) ··· 1496 1494 spin_lock_init(&od->lock); 1497 1495 spin_lock_init(&od->irq_lock); 1498 1496 1499 - if (!pdev->dev.of_node) { 1500 - od->dma_requests = od->plat->dma_attr->lch_count; 1501 - if (unlikely(!od->dma_requests)) 1502 - od->dma_requests = OMAP_SDMA_REQUESTS; 1503 - } else if (of_property_read_u32(pdev->dev.of_node, "dma-requests", 1504 - &od->dma_requests)) { 1497 + /* Number of DMA requests */ 1498 + od->dma_requests = OMAP_SDMA_REQUESTS; 1499 + if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node, 1500 + "dma-requests", 1501 + &od->dma_requests)) { 1505 1502 dev_info(&pdev->dev, 1506 1503 "Missing dma-requests property, using %u.\n", 1507 1504 OMAP_SDMA_REQUESTS); 1508 - od->dma_requests = OMAP_SDMA_REQUESTS; 1509 1505 } 1510 1506 1511 - od->lch_map = devm_kcalloc(&pdev->dev, od->dma_requests, 1512 - sizeof(*od->lch_map), GFP_KERNEL); 1507 + /* Number of available logical channels */ 1508 + if (!pdev->dev.of_node) { 1509 + lch_count = od->plat->dma_attr->lch_count; 1510 + if (unlikely(!lch_count)) 1511 + lch_count = OMAP_SDMA_CHANNELS; 1512 + } else if (of_property_read_u32(pdev->dev.of_node, "dma-channels", 1513 + &lch_count)) { 1514 + dev_info(&pdev->dev, 1515 + "Missing dma-channels property, using %u.\n", 1516 + OMAP_SDMA_CHANNELS); 1517 + lch_count = OMAP_SDMA_CHANNELS; 1518 + } 1519 + 1520 + od->lch_map = devm_kcalloc(&pdev->dev, lch_count, sizeof(*od->lch_map), 1521 + GFP_KERNEL); 1513 1522 if (!od->lch_map) 1514 1523 return -ENOMEM; 1515 1524

+11

drivers/dma/pl330.c

··· 448 448 449 449 /* for cyclic capability */ 450 450 bool cyclic; 451 + 452 + /* for runtime pm tracking */ 453 + bool active; 451 454 }; 452 455 453 456 struct pl330_dmac { ··· 2036 2033 _stop(pch->thread); 2037 2034 spin_unlock(&pch->thread->dmac->lock); 2038 2035 power_down = true; 2036 + pch->active = false; 2039 2037 } else { 2040 2038 /* Make sure the PL330 Channel thread is active */ 2041 2039 spin_lock(&pch->thread->dmac->lock); ··· 2056 2052 desc->status = PREP; 2057 2053 list_move_tail(&desc->node, &pch->work_list); 2058 2054 if (power_down) { 2055 + pch->active = true; 2059 2056 spin_lock(&pch->thread->dmac->lock); 2060 2057 _start(pch->thread); 2061 2058 spin_unlock(&pch->thread->dmac->lock); ··· 2171 2166 unsigned long flags; 2172 2167 struct pl330_dmac *pl330 = pch->dmac; 2173 2168 LIST_HEAD(list); 2169 + bool power_down = false; 2174 2170 2175 2171 pm_runtime_get_sync(pl330->ddma.dev); 2176 2172 spin_lock_irqsave(&pch->lock, flags); ··· 2182 2176 pch->thread->req[0].desc = NULL; 2183 2177 pch->thread->req[1].desc = NULL; 2184 2178 pch->thread->req_running = -1; 2179 + power_down = pch->active; 2180 + pch->active = false; 2185 2181 2186 2182 /* Mark all desc done */ 2187 2183 list_for_each_entry(desc, &pch->submitted_list, node) { ··· 2201 2193 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2202 2194 spin_unlock_irqrestore(&pch->lock, flags); 2203 2195 pm_runtime_mark_last_busy(pl330->ddma.dev); 2196 + if (power_down) 2197 + pm_runtime_put_autosuspend(pl330->ddma.dev); 2204 2198 pm_runtime_put_autosuspend(pl330->ddma.dev); 2205 2199 2206 2200 return 0; ··· 2367 2357 * updated on work_list emptiness status. 2368 2358 */ 2369 2359 WARN_ON(list_empty(&pch->submitted_list)); 2360 + pch->active = true; 2370 2361 pm_runtime_get_sync(pch->dmac->ddma.dev); 2371 2362 } 2372 2363 list_splice_tail_init(&pch->submitted_list, &pch->work_list);

+8

drivers/dma/sh/rcar-dmac.c

··· 986 986 { 987 987 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); 988 988 struct rcar_dmac *dmac = to_rcar_dmac(chan->device); 989 + struct rcar_dmac_chan_map *map = &rchan->map; 989 990 struct rcar_dmac_desc_page *page, *_page; 990 991 struct rcar_dmac_desc *desc; 991 992 LIST_HEAD(list); ··· 1018 1017 list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) { 1019 1018 list_del(&page->node); 1020 1019 free_page((unsigned long)page); 1020 + } 1021 + 1022 + /* Remove slave mapping if present. */ 1023 + if (map->slave.xfer_size) { 1024 + dma_unmap_resource(chan->device->dev, map->addr, 1025 + map->slave.xfer_size, map->dir, 0); 1026 + map->slave.xfer_size = 0; 1021 1027 } 1022 1028 1023 1029 pm_runtime_put(chan->device->dev);

+5 -12

drivers/dma/stm32-dma.c

··· 880 880 struct virt_dma_desc *vdesc; 881 881 enum dma_status status; 882 882 unsigned long flags; 883 - u32 residue; 883 + u32 residue = 0; 884 884 885 885 status = dma_cookie_status(c, cookie, state); 886 886 if ((status == DMA_COMPLETE) || (!state)) ··· 888 888 889 889 spin_lock_irqsave(&chan->vchan.lock, flags); 890 890 vdesc = vchan_find_desc(&chan->vchan, cookie); 891 - if (cookie == chan->desc->vdesc.tx.cookie) { 891 + if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) 892 892 residue = stm32_dma_desc_residue(chan, chan->desc, 893 893 chan->next_sg); 894 - } else if (vdesc) { 894 + else if (vdesc) 895 895 residue = stm32_dma_desc_residue(chan, 896 896 to_stm32_dma_desc(vdesc), 0); 897 - } else { 898 - residue = 0; 899 - } 900 - 901 897 dma_set_residue(state, residue); 902 898 903 899 spin_unlock_irqrestore(&chan->vchan.lock, flags); ··· 968 972 struct stm32_dma_chan *chan; 969 973 struct dma_chan *c; 970 974 971 - if (dma_spec->args_count < 3) 975 + if (dma_spec->args_count < 4) 972 976 return NULL; 973 977 974 978 cfg.channel_id = dma_spec->args[0]; 975 979 cfg.request_line = dma_spec->args[1]; 976 980 cfg.stream_config = dma_spec->args[2]; 977 - cfg.threshold = 0; 981 + cfg.threshold = dma_spec->args[3]; 978 982 979 983 if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) || (cfg.request_line >= 980 984 STM32_DMA_MAX_REQUEST_ID)) 981 985 return NULL; 982 - 983 - if (dma_spec->args_count > 3) 984 - cfg.threshold = dma_spec->args[3]; 985 986 986 987 chan = &dmadev->chan[cfg.channel_id]; 987 988

+2

drivers/dma/ti-dma-crossbar.c

··· 149 149 match = of_match_node(ti_am335x_master_match, dma_node); 150 150 if (!match) { 151 151 dev_err(&pdev->dev, "DMA master is not supported\n"); 152 + of_node_put(dma_node); 152 153 return -EINVAL; 153 154 } 154 155 ··· 340 339 match = of_match_node(ti_dra7_master_match, dma_node); 341 340 if (!match) { 342 341 dev_err(&pdev->dev, "DMA master is not supported\n"); 342 + of_node_put(dma_node); 343 343 return -EINVAL; 344 344 } 345 345

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