Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for it so that those IRQs can then
be linked to the related GPIOs.
Link: https://lore.kernel.org/r/63f19db21a91729d91b3df336a56a7eb4206e561.1767804922.git.chleroy@kernel.org
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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drivers/soc/fsl/qe/Makefile
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drivers/soc/fsl/qe/Makefile
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drivers/soc/fsl/qe/qe_ports_ic.c
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drivers/soc/fsl/qe/qe_ports_ic.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* QUICC ENGINE I/O Ports Interrupt Controller
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*
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* Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@csgroup.eu)
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*/
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/platform_device.h>
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/* QE IC registers offset */
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#define CEPIER 0x0c
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#define CEPIMR 0x10
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#define CEPICR 0x14
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struct qepic_data {
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void __iomem *reg;
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struct irq_domain *host;
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};
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static void qepic_mask(struct irq_data *d)
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{
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struct qepic_data *data = irq_data_get_irq_chip_data(d);
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clrbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d)));
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}
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static void qepic_unmask(struct irq_data *d)
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{
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struct qepic_data *data = irq_data_get_irq_chip_data(d);
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setbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d)));
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}
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static void qepic_end(struct irq_data *d)
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{
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struct qepic_data *data = irq_data_get_irq_chip_data(d);
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out_be32(data->reg + CEPIER, 1 << (31 - irqd_to_hwirq(d)));
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}
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static int qepic_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct qepic_data *data = irq_data_get_irq_chip_data(d);
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unsigned int vec = (unsigned int)irqd_to_hwirq(d);
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switch (flow_type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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setbits32(data->reg + CEPICR, 1 << (31 - vec));
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return 0;
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case IRQ_TYPE_EDGE_BOTH:
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case IRQ_TYPE_NONE:
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clrbits32(data->reg + CEPICR, 1 << (31 - vec));
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return 0;
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}
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return -EINVAL;
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}
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static struct irq_chip qepic = {
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.name = "QEPIC",
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.irq_mask = qepic_mask,
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.irq_unmask = qepic_unmask,
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.irq_eoi = qepic_end,
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.irq_set_type = qepic_set_type,
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};
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static int qepic_get_irq(struct irq_desc *desc)
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{
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struct qepic_data *data = irq_desc_get_handler_data(desc);
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u32 event = in_be32(data->reg + CEPIER);
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if (!event)
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return -1;
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return irq_find_mapping(data->host, 32 - ffs(event));
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}
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static void qepic_cascade(struct irq_desc *desc)
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{
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generic_handle_irq(qepic_get_irq(desc));
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}
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static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw)
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{
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &qepic, handle_fasteoi_irq);
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return 0;
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}
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static const struct irq_domain_ops qepic_host_ops = {
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.map = qepic_host_map,
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};
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static int qepic_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct qepic_data *data;
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int irq;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->reg))
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return PTR_ERR(data->reg);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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data->host = irq_domain_add_linear(dev->of_node, 32, &qepic_host_ops, data);
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if (!data->host)
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return -ENODEV;
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irq_set_handler_data(irq, data);
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irq_set_chained_handler(irq, qepic_cascade);
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return 0;
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}
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static const struct of_device_id qepic_match[] = {
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{
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.compatible = "fsl,mpc8323-qe-ports-ic",
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},
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{},
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};
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static struct platform_driver qepic_driver = {
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.driver = {
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.name = "qe_ports_ic",
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.of_match_table = qepic_match,
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},
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.probe = qepic_probe,
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};
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static int __init qepic_init(void)
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{
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return platform_driver_register(&qepic_driver);
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}
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arch_initcall(qepic_init);