Merge tag 'imx-dt64-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

+13 -1

arch/arm64/boot/dts/freescale/Makefile

··· 75 75 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb 76 76 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb 77 77 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb 78 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7905-0x.dtb 78 79 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb 79 80 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb 80 81 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb ··· 94 93 dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb 95 94 dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb 96 95 dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb 96 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb 97 97 dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb 98 98 dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb 99 99 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb ··· 102 100 dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb 103 101 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb 104 102 dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb 103 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb 104 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb 105 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb 105 106 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb 106 107 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb 107 108 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb ··· 146 141 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb 147 142 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb 148 143 dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb 144 + dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb 149 145 150 - imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo 146 + imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo 147 + imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo 151 148 imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo 152 149 imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo 153 150 imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo 154 151 imx8mm-venice-gw73xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo 152 + imx8mm-venice-gw73xx-0x-rpidsi-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rpidsi.dtbo 155 153 imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo 156 154 imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo 157 155 imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo 156 + imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo 158 157 159 158 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb 159 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rpidsi.dtb 160 160 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb 161 161 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb 162 162 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb 163 163 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtb 164 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rpidsi.dtb 164 165 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb 165 166 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb 166 167 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb 168 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb 167 169 168 170 dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb 169 171 dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb

+12

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts

··· 56 56 }; 57 57 58 58 &enetc_port2 { 59 + nvmem-cells = <&base_mac_address 2>; 60 + nvmem-cell-names = "mac-address"; 59 61 status = "okay"; 60 62 }; 61 63 62 64 &enetc_port3 { 65 + nvmem-cells = <&base_mac_address 3>; 66 + nvmem-cell-names = "mac-address"; 63 67 status = "okay"; 64 68 }; 65 69 ··· 84 80 managed = "in-band-status"; 85 81 phy-handle = <&qsgmii_phy0>; 86 82 phy-mode = "qsgmii"; 83 + nvmem-cells = <&base_mac_address 4>; 84 + nvmem-cell-names = "mac-address"; 87 85 status = "okay"; 88 86 }; 89 87 ··· 94 88 managed = "in-band-status"; 95 89 phy-handle = <&qsgmii_phy1>; 96 90 phy-mode = "qsgmii"; 91 + nvmem-cells = <&base_mac_address 5>; 92 + nvmem-cell-names = "mac-address"; 97 93 status = "okay"; 98 94 }; 99 95 ··· 104 96 managed = "in-band-status"; 105 97 phy-handle = <&qsgmii_phy2>; 106 98 phy-mode = "qsgmii"; 99 + nvmem-cells = <&base_mac_address 6>; 100 + nvmem-cell-names = "mac-address"; 107 101 status = "okay"; 108 102 }; 109 103 ··· 114 104 managed = "in-band-status"; 115 105 phy-handle = <&qsgmii_phy3>; 116 106 phy-mode = "qsgmii"; 107 + nvmem-cells = <&base_mac_address 7>; 108 + nvmem-cell-names = "mac-address"; 117 109 status = "okay"; 118 110 }; 119 111

+2

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts

··· 55 55 &enetc_port1 { 56 56 phy-handle = <&phy0>; 57 57 phy-mode = "rgmii-id"; 58 + nvmem-cells = <&base_mac_address 0>; 59 + nvmem-cell-names = "mac-address"; 58 60 status = "okay"; 59 61 };

+8

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts

··· 36 36 }; 37 37 38 38 &enetc_port2 { 39 + nvmem-cells = <&base_mac_address 2>; 40 + nvmem-cell-names = "mac-address"; 39 41 status = "okay"; 40 42 }; 41 43 42 44 &enetc_port3 { 45 + nvmem-cells = <&base_mac_address 3>; 46 + nvmem-cell-names = "mac-address"; 43 47 status = "okay"; 44 48 }; 45 49 ··· 56 52 managed = "in-band-status"; 57 53 phy-handle = <&phy0>; 58 54 phy-mode = "sgmii"; 55 + nvmem-cells = <&base_mac_address 0>; 56 + nvmem-cell-names = "mac-address"; 59 57 status = "okay"; 60 58 }; 61 59 ··· 66 60 managed = "in-band-status"; 67 61 phy-handle = <&phy1>; 68 62 phy-mode = "sgmii"; 63 + nvmem-cells = <&base_mac_address 1>; 64 + nvmem-cell-names = "mac-address"; 69 65 status = "okay"; 70 66 }; 71 67

+2

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts

··· 43 43 &enetc_port1 { 44 44 phy-handle = <&phy1>; 45 45 phy-mode = "rgmii-id"; 46 + nvmem-cells = <&base_mac_address 1>; 47 + nvmem-cell-names = "mac-address"; 46 48 status = "okay"; 47 49 };

+17

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts

··· 92 92 phy-handle = <&phy0>; 93 93 phy-mode = "sgmii"; 94 94 managed = "in-band-status"; 95 + nvmem-cells = <&base_mac_address 0>; 96 + nvmem-cell-names = "mac-address"; 95 97 status = "okay"; 96 98 }; 97 99 ··· 154 152 partition@3e0000 { 155 153 reg = <0x3e0000 0x020000>; 156 154 label = "bootloader environment"; 155 + }; 156 + }; 157 + 158 + otp-1 { 159 + compatible = "user-otp"; 160 + 161 + nvmem-layout { 162 + compatible = "kontron,sl28-vpd"; 163 + 164 + serial_number: serial-number { 165 + }; 166 + 167 + base_mac_address: base-mac-address { 168 + #nvmem-cell-cells = <1>; 169 + }; 157 170 }; 158 171 }; 159 172 };

+15

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

··· 28 28 reg = <0x0>; 29 29 enable-method = "psci"; 30 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 + i-cache-size = <0xc000>; 32 + i-cache-line-size = <64>; 33 + i-cache-sets = <256>; 34 + d-cache-size = <0x8000>; 35 + d-cache-line-size = <64>; 36 + d-cache-sets = <256>; 31 37 next-level-cache = <&l2>; 32 38 cpu-idle-states = <&CPU_PW20>; 33 39 #cooling-cells = <2>; ··· 45 39 reg = <0x1>; 46 40 enable-method = "psci"; 47 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 + i-cache-size = <0xc000>; 43 + i-cache-line-size = <64>; 44 + i-cache-sets = <256>; 45 + d-cache-size = <0x8000>; 46 + d-cache-line-size = <64>; 47 + d-cache-sets = <256>; 48 48 next-level-cache = <&l2>; 49 49 cpu-idle-states = <&CPU_PW20>; 50 50 #cooling-cells = <2>; ··· 60 48 compatible = "cache"; 61 49 cache-level = <2>; 62 50 cache-unified; 51 + cache-size = <0x100000>; 52 + cache-line-size = <64>; 53 + cache-sets = <1024>; 63 54 }; 64 55 }; 65 56

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi

··· 69 69 mdio-parent-bus = <&emdio1>; 70 70 reg = <0x54 1>; /* BRDCFG4 */ 71 71 mux-mask = <0xe0>; /* EMI1_MDIO */ 72 - #address-cells=<1>; 72 + #address-cells = <1>; 73 73 #size-cells = <0>; 74 74 75 75 /* Child MDIO buses, one for each riser card:

+3 -3

arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi

··· 684 684 }; 685 685 686 686 /* Messaging Units */ 687 - &mu_m0{ 687 + &mu_m0 { 688 688 status = "okay"; 689 689 }; 690 690 691 - &mu1_m0{ 691 + &mu1_m0 { 692 692 status = "okay"; 693 693 }; 694 694 695 - &mu2_m0{ 695 + &mu2_m0 { 696 696 status = "okay"; 697 697 }; 698 698

+4 -6

arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi

··· 157 157 158 158 usbotg3_cdns3: usb@5b120000 { 159 159 compatible = "cdns,usb3"; 160 - reg = <0x5b130000 0x10000>, /* memory area for HOST registers */ 161 - <0x5b140000 0x10000>, /* memory area for DEVICE registers */ 162 - <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */ 163 - reg-names = "xhci", "dev", "otg"; 164 - #address-cells = <1>; 165 - #size-cells = <1>; 160 + reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */ 161 + <0x5b130000 0x10000>, /* memory area for HOST registers */ 162 + <0x5b140000 0x10000>; /* memory area for DEVICE registers */ 163 + reg-names = "otg", "xhci", "dev"; 166 164 interrupt-parent = <&gic>; 167 165 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 168 166 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,

-1

arch/arm64/boot/dts/freescale/imx8dxl-evk.dts

··· 362 362 }; 363 363 364 364 &lpspi3 { 365 - fsl,spi-num-chipselects = <1>; 366 365 fsl,spi-only-use-cs1-sel; 367 366 pinctrl-names = "default"; 368 367 pinctrl-0 = <&pinctrl_lpspi3>;

+4 -4

arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

··· 36 36 }; 37 37 38 38 &lpuart0 { 39 - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 39 + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 40 40 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 41 41 }; 42 42 43 43 &lpuart1 { 44 - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 44 + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 45 45 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 46 46 }; 47 47 48 48 &lpuart2 { 49 - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 49 + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 50 50 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 51 51 }; 52 52 53 53 &lpuart3 { 54 - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 54 + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 55 55 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 56 56 }; 57 57

+2 -3

arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi

··· 141 141 pinctrl-0 = <&pinctrl_i2c2>; 142 142 status = "okay"; 143 143 144 - camera@3c { 144 + camera@10 { 145 145 compatible = "ovti,ov5640"; 146 146 pinctrl-names = "default"; 147 147 pinctrl-0 = <&pinctrl_ov5640>; 148 - reg = <0x3c>; 148 + reg = <0x10>; 149 149 clocks = <&clk IMX8MM_CLK_CLKO1>; 150 150 clock-names = "xclk"; 151 151 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; ··· 289 289 }; 290 290 291 291 &usbotg2 { 292 - pinctrl-names = "default"; 293 292 disable-over-current; 294 293 dr_mode = "host"; 295 294 status = "okay";

+131

arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts

··· 16 16 chosen { 17 17 stdout-path = &uart2; 18 18 }; 19 + 20 + connector { 21 + compatible = "hdmi-connector"; 22 + type = "a"; 23 + 24 + port { 25 + hdmi_connector_in: endpoint { 26 + remote-endpoint = <&adv7535_out>; 27 + }; 28 + }; 29 + }; 30 + 31 + reg_hdmi: regulator-hdmi-dvdd { 32 + compatible = "regulator-fixed"; 33 + pinctrl-names = "default"; 34 + pinctrl-0 = <&pinctrl_reg_hdmi>; 35 + regulator-name = "hdmi_pwr_en"; 36 + regulator-min-microvolt = <3300000>; 37 + regulator-max-microvolt = <3300000>; 38 + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 39 + enable-active-high; 40 + startup-delay-us = <70000>; 41 + regulator-always-on; 42 + }; 43 + 44 + sound-hdmi { 45 + compatible = "simple-audio-card"; 46 + simple-audio-card,name = "sound-hdmi"; 47 + simple-audio-card,format = "i2s"; 48 + 49 + simple-audio-card,cpu { 50 + sound-dai = <&sai5>; 51 + system-clock-direction-out; 52 + }; 53 + 54 + simple-audio-card,codec { 55 + sound-dai = <&adv_bridge>; 56 + }; 57 + }; 58 + }; 59 + 60 + &i2c2 { 61 + adv_bridge: hdmi@3d { 62 + compatible = "adi,adv7535"; 63 + pinctrl-names = "default"; 64 + pinctrl-0 = <&pinctrl_hdmi_bridge>; 65 + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 66 + reg-names = "main", "cec", "edid", "packet"; 67 + adi,dsi-lanes = <4>; 68 + avdd-supply = <&reg_hdmi>; 69 + a2vdd-supply = <&reg_hdmi>; 70 + dvdd-supply = <&reg_hdmi>; 71 + pvdd-supply = <&reg_hdmi>; 72 + v1p2-supply = <&reg_hdmi>; 73 + v3p3-supply = <&reg_hdmi>; 74 + interrupt-parent = <&gpio1>; 75 + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 76 + #sound-dai-cells = <0>; 77 + 78 + ports { 79 + #address-cells = <1>; 80 + #size-cells = <0>; 81 + 82 + port@0 { 83 + reg = <0>; 84 + 85 + adv7535_in: endpoint { 86 + remote-endpoint = <&dsi_out>; 87 + }; 88 + }; 89 + 90 + port@1 { 91 + reg = <1>; 92 + 93 + adv7535_out: endpoint { 94 + remote-endpoint = <&hdmi_connector_in>; 95 + }; 96 + }; 97 + }; 98 + }; 99 + }; 100 + 101 + &lcdif { 102 + status = "okay"; 103 + }; 104 + 105 + &mipi_dsi { 106 + samsung,esc-clock-frequency = <20000000>; 107 + status = "okay"; 108 + 109 + ports { 110 + port@1 { 111 + reg = <1>; 112 + 113 + dsi_out: endpoint { 114 + remote-endpoint = <&adv7535_in>; 115 + }; 116 + }; 117 + }; 118 + }; 119 + 120 + &sai5 { 121 + pinctrl-names = "default"; 122 + pinctrl-0 = <&pinctrl_sai5>; 123 + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; 124 + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 125 + assigned-clock-rates = <24576000>; 126 + #sound-dai-cells = <0>; 127 + status = "okay"; 128 + }; 129 + 130 + &iomuxc { 131 + pinctrl_hdmi_bridge: hdmibridgegrp { 132 + fsl,pins = < 133 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 134 + >; 135 + }; 136 + 137 + pinctrl_reg_hdmi: reghdmigrp { 138 + fsl,pins = < 139 + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 140 + >; 141 + }; 142 + 143 + pinctrl_sai5: sai5grp { 144 + fsl,pins = < 145 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 146 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 147 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 148 + >; 149 + }; 19 150 };

+1 -1

arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi

··· 112 112 rohm,reset-snvs-powered; 113 113 114 114 #clock-cells = <0>; 115 - clocks = <&osc_32k 0>; 115 + clocks = <&osc_32k>; 116 116 clock-output-names = "clk-32k-out"; 117 117 118 118 regulators {

+11 -13

arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi

··· 108 108 }; 109 109 110 110 &iomuxc { 111 - pinctrl-names = "default"; 112 - 113 111 pinctrl_csi_pwn: csi-pwn-grp { 114 112 fsl,pins = < 115 113 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 ··· 409 411 410 412 regulators { 411 413 buck1_reg: BUCK1 { 412 - regulator-name = "BUCK1"; 414 + regulator-name = "buck1"; 413 415 regulator-min-microvolt = <700000>; 414 416 regulator-max-microvolt = <1300000>; 415 417 regulator-boot-on; ··· 418 420 }; 419 421 420 422 buck2_reg: BUCK2 { 421 - regulator-name = "BUCK2"; 423 + regulator-name = "buck2"; 422 424 regulator-min-microvolt = <700000>; 423 425 regulator-max-microvolt = <1300000>; 424 426 regulator-boot-on; ··· 430 432 431 433 buck3_reg: BUCK3 { 432 434 // BUCK5 in datasheet 433 - regulator-name = "BUCK3"; 435 + regulator-name = "buck3"; 434 436 regulator-min-microvolt = <700000>; 435 437 regulator-max-microvolt = <1350000>; 436 438 regulator-boot-on; ··· 439 441 440 442 buck4_reg: BUCK4 { 441 443 // BUCK6 in datasheet 442 - regulator-name = "BUCK4"; 444 + regulator-name = "buck4"; 443 445 regulator-min-microvolt = <3000000>; 444 446 regulator-max-microvolt = <3300000>; 445 447 regulator-boot-on; ··· 448 450 449 451 buck5_reg: BUCK5 { 450 452 // BUCK7 in datasheet 451 - regulator-name = "BUCK5"; 453 + regulator-name = "buck5"; 452 454 regulator-min-microvolt = <1605000>; 453 455 regulator-max-microvolt = <1995000>; 454 456 regulator-boot-on; ··· 457 459 458 460 buck6_reg: BUCK6 { 459 461 // BUCK8 in datasheet 460 - regulator-name = "BUCK6"; 462 + regulator-name = "buck6"; 461 463 regulator-min-microvolt = <800000>; 462 464 regulator-max-microvolt = <1400000>; 463 465 regulator-boot-on; ··· 465 467 }; 466 468 467 469 ldo1_reg: LDO1 { 468 - regulator-name = "LDO1"; 470 + regulator-name = "ldo1"; 469 471 regulator-min-microvolt = <1600000>; 470 472 regulator-max-microvolt = <1900000>; 471 473 regulator-boot-on; ··· 473 475 }; 474 476 475 477 ldo2_reg: LDO2 { 476 - regulator-name = "LDO2"; 478 + regulator-name = "ldo2"; 477 479 regulator-min-microvolt = <800000>; 478 480 regulator-max-microvolt = <900000>; 479 481 regulator-boot-on; ··· 481 483 }; 482 484 483 485 ldo3_reg: LDO3 { 484 - regulator-name = "LDO3"; 486 + regulator-name = "ldo3"; 485 487 regulator-min-microvolt = <1800000>; 486 488 regulator-max-microvolt = <3300000>; 487 489 regulator-boot-on; ··· 489 491 }; 490 492 491 493 ldo4_reg: LDO4 { 492 - regulator-name = "LDO4"; 494 + regulator-name = "ldo4"; 493 495 regulator-min-microvolt = <900000>; 494 496 regulator-max-microvolt = <1800000>; 495 497 regulator-boot-on; ··· 497 499 }; 498 500 499 501 ldo6_reg: LDO6 { 500 - regulator-name = "LDO6"; 502 + regulator-name = "ldo6"; 501 503 regulator-min-microvolt = <900000>; 502 504 regulator-max-microvolt = <1800000>; 503 505 regulator-boot-on;

+48

arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

··· 380 380 }; 381 381 }; 382 382 383 + 384 + &csi { 385 + status = "okay"; 386 + }; 387 + 383 388 &i2c3 { 384 389 clock-frequency = <400000>; 385 390 pinctrl-names = "default"; ··· 398 393 #gpio-cells = <2>; 399 394 vcc-supply = <&buck4_reg>; 400 395 }; 396 + 397 + camera@3c { 398 + compatible = "ovti,ov5640"; 399 + reg = <0x3c>; 400 + pinctrl-names = "default"; 401 + pinctrl-0 = <&pinctrl_camera>; 402 + clocks = <&clk IMX8MM_CLK_CLKO1>; 403 + clock-names = "xclk"; 404 + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; 405 + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; 406 + assigned-clock-rates = <24000000>; 407 + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 408 + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 409 + 410 + port { 411 + ov5640_to_mipi_csi2: endpoint { 412 + remote-endpoint = <&imx8mm_mipi_csi_in>; 413 + clock-lanes = <0>; 414 + data-lanes = <1 2>; 415 + }; 416 + }; 417 + }; 401 418 }; 402 419 403 420 &lcdif { 404 421 status = "okay"; 422 + }; 423 + 424 + &mipi_csi { 425 + status = "okay"; 426 + 427 + ports { 428 + port@0 { 429 + imx8mm_mipi_csi_in: endpoint { 430 + remote-endpoint = <&ov5640_to_mipi_csi2>; 431 + data-lanes = <1 2>; 432 + }; 433 + }; 434 + }; 405 435 }; 406 436 407 437 &mipi_dsi { ··· 722 682 pinctrl_backlight: backlightgrp { 723 683 fsl,pins = < 724 684 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 685 + >; 686 + }; 687 + 688 + pinctrl_camera: cameragrp { 689 + fsl,pins = < 690 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 691 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 692 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 725 693 >; 726 694 }; 727 695 };

+48 -3

arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts

··· 140 140 }; 141 141 }; 142 142 143 + /* TPM */ 144 + &ecspi2 { 145 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 146 + pinctrl-names = "default"; 147 + pinctrl-0 = <&pinctrl_ecspi2>; 148 + #address-cells = <1>; 149 + #size-cells = <0>; 150 + status = "okay"; 151 + 152 + tpm: tpm@0 { 153 + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 154 + interrupt-parent = <&gpio2>; 155 + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 156 + pinctrl-names = "default"; 157 + pinctrl-0 = <&pinctrl_tpm>; 158 + reg = <0>; 159 + spi-max-frequency = <43000000>; 160 + }; 161 + }; 162 + 143 163 &gpio1 { 144 164 gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", 145 165 "", "", "", "RESET_ETHPHY", ··· 190 170 191 171 &i2c4 { 192 172 clock-frequency = <400000>; 193 - pinctrl-names = "default"; 173 + pinctrl-names = "default", "gpio"; 194 174 pinctrl-0 = <&pinctrl_i2c4>; 175 + pinctrl-1 = <&pinctrl_i2c4_gpio>; 176 + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 177 + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 195 178 }; 196 179 197 180 /* PCIe */ ··· 356 333 >; 357 334 }; 358 335 336 + pinctrl_ecspi2: ecspi2grp { 337 + fsl,pins = < 338 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x80 339 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x80 340 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x80 341 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 342 + >; 343 + }; 344 + 359 345 pinctrl_fan: fan0grp { 360 346 fsl,pins = < 361 347 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 ··· 375 343 fsl,pins = < 376 344 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 377 345 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 346 + >; 347 + }; 348 + 349 + pinctrl_i2c4_gpio: i2c4gpiogrp { 350 + fsl,pins = < 351 + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e2 352 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e2 378 353 >; 379 354 }; 380 355 ··· 407 368 >; 408 369 }; 409 370 371 + pinctrl_tpm: tpmgrp { 372 + fsl,pins = < 373 + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 374 + >; 375 + }; 376 + 410 377 pinctrl_uart1: uart1grp { 411 378 fsl,pins = < 412 379 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 ··· 433 388 434 389 pinctrl_uart3: uart3grp { 435 390 fsl,pins = < 436 - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 437 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 391 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 392 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 438 393 >; 439 394 }; 440 395

+2 -1

arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi

··· 102 102 status = "okay"; 103 103 104 104 som_flash: flash@0 { 105 + #address-cells = <1>; 106 + #size-cells = <1>; 105 107 compatible = "jedec,spi-nor"; 106 108 reg = <0>; 107 109 spi-max-frequency = <80000000>; ··· 151 149 regulator-max-microvolt = <3300000>; 152 150 regulator-min-microvolt = <1800000>; 153 151 regulator-name = "NVCC_SD2 (LDO2)"; 154 - vselect-en; 155 152 156 153 regulator-state-mem { 157 154 regulator-off-in-suspend;

+1 -1

arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi

··· 142 142 rohm,reset-snvs-powered; 143 143 144 144 #clock-cells = <0>; 145 - clocks = <&osc_32k 0>; 145 + clocks = <&osc_32k>; 146 146 clock-output-names = "clk-32k-out"; 147 147 148 148 regulators {

+90

arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + 8 + #include "imx8mm-pinfunc.h" 9 + 10 + /dts-v1/; 11 + /plugin/; 12 + 13 + &{/} { 14 + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; 15 + 16 + panel { 17 + compatible = "powertip,ph800480t013-idf02"; 18 + power-supply = <&attiny>; 19 + backlight = <&attiny>; 20 + 21 + port { 22 + panel_in: endpoint { 23 + remote-endpoint = <&bridge_out>; 24 + }; 25 + }; 26 + }; 27 + }; 28 + 29 + &i2c3 { 30 + #address-cells = <1>; 31 + #size-cells = <0>; 32 + 33 + attiny: regulator@45 { 34 + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; 35 + reg = <0x45>; 36 + }; 37 + }; 38 + 39 + &lcdif { 40 + status = "okay"; 41 + }; 42 + 43 + &mipi_dsi { 44 + samsung,burst-clock-frequency = <891000000>; 45 + samsung,esc-clock-frequency = <54000000>; 46 + samsung,pll-clock-frequency = <27000000>; 47 + #address-cells = <1>; 48 + #size-cells = <0>; 49 + status = "okay"; 50 + 51 + bridge@0 { 52 + compatible = "toshiba,tc358762"; 53 + reg = <0>; 54 + vddc-supply = <&attiny>; 55 + 56 + ports { 57 + #address-cells = <1>; 58 + #size-cells = <0>; 59 + 60 + port@0 { 61 + reg = <0>; 62 + 63 + bridge_in: endpoint { 64 + remote-endpoint = <&dsi_out>; 65 + }; 66 + }; 67 + 68 + port@1 { 69 + reg = <1>; 70 + 71 + bridge_out: endpoint { 72 + remote-endpoint = <&panel_in>; 73 + }; 74 + }; 75 + }; 76 + }; 77 + 78 + ports { 79 + #address-cells = <1>; 80 + #size-cells = <0>; 81 + 82 + port@1 { 83 + reg = <1>; 84 + 85 + dsi_out: endpoint { 86 + remote-endpoint = <&bridge_in>; 87 + }; 88 + }; 89 + }; 90 + };

+90

arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + 8 + #include "imx8mm-pinfunc.h" 9 + 10 + /dts-v1/; 11 + /plugin/; 12 + 13 + &{/} { 14 + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; 15 + 16 + panel { 17 + compatible = "powertip,ph800480t013-idf02"; 18 + power-supply = <&attiny>; 19 + backlight = <&attiny>; 20 + 21 + port { 22 + panel_in: endpoint { 23 + remote-endpoint = <&bridge_out>; 24 + }; 25 + }; 26 + }; 27 + }; 28 + 29 + &i2c3 { 30 + #address-cells = <1>; 31 + #size-cells = <0>; 32 + 33 + attiny: regulator@45 { 34 + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; 35 + reg = <0x45>; 36 + }; 37 + }; 38 + 39 + &lcdif { 40 + status = "okay"; 41 + }; 42 + 43 + &mipi_dsi { 44 + samsung,burst-clock-frequency = <891000000>; 45 + samsung,esc-clock-frequency = <54000000>; 46 + samsung,pll-clock-frequency = <27000000>; 47 + #address-cells = <1>; 48 + #size-cells = <0>; 49 + status = "okay"; 50 + 51 + bridge@0 { 52 + compatible = "toshiba,tc358762"; 53 + reg = <0>; 54 + vddc-supply = <&attiny>; 55 + 56 + ports { 57 + #address-cells = <1>; 58 + #size-cells = <0>; 59 + 60 + port@0 { 61 + reg = <0>; 62 + 63 + bridge_in: endpoint { 64 + remote-endpoint = <&dsi_out>; 65 + }; 66 + }; 67 + 68 + port@1 { 69 + reg = <1>; 70 + 71 + bridge_out: endpoint { 72 + remote-endpoint = <&panel_in>; 73 + }; 74 + }; 75 + }; 76 + }; 77 + 78 + ports { 79 + #address-cells = <1>; 80 + #size-cells = <0>; 81 + 82 + port@1 { 83 + reg = <1>; 84 + 85 + dsi_out: endpoint { 86 + remote-endpoint = <&bridge_in>; 87 + }; 88 + }; 89 + }; 90 + };

+50 -3

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts

··· 242 242 }; 243 243 }; 244 244 245 + &A53_0 { 246 + cpu-supply = <&buck2>; 247 + }; 248 + 249 + &A53_1 { 250 + cpu-supply = <&buck2>; 251 + }; 252 + 253 + &A53_2 { 254 + cpu-supply = <&buck2>; 255 + }; 256 + 257 + &A53_3 { 258 + cpu-supply = <&buck2>; 259 + }; 260 + 245 261 &ddrc { 246 262 operating-points-v2 = <&ddrc_opp_table>; 247 263 ··· 512 496 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 513 497 rohm,reset-snvs-powered; 514 498 #clock-cells = <0>; 515 - clocks = <&osc_32k 0>; 499 + clocks = <&osc_32k>; 516 500 clock-output-names = "clk-32k-out"; 517 501 518 502 regulators { ··· 527 511 }; 528 512 529 513 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 530 - BUCK2 { 514 + buck2: BUCK2 { 531 515 regulator-name = "buck2"; 532 516 regulator-min-microvolt = <700000>; 533 517 regulator-max-microvolt = <1300000>; ··· 789 773 790 774 /* SDIO WiFi */ 791 775 &usdhc1 { 792 - pinctrl-names = "default"; 776 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 793 777 pinctrl-0 = <&pinctrl_usdhc1>; 778 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 779 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 794 780 bus-width = <4>; 795 781 non-removable; 796 782 vmmc-supply = <&reg_wifi>; 783 + #address-cells = <1>; 784 + #size-cells = <0>; 797 785 status = "okay"; 786 + 787 + wifi@0 { 788 + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 789 + reg = <0>; 790 + }; 798 791 }; 799 792 800 793 /* microSD */ ··· 1060 1035 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 1061 1036 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 1062 1037 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 1038 + >; 1039 + }; 1040 + 1041 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1042 + fsl,pins = < 1043 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 1044 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 1045 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 1046 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 1047 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 1048 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 1049 + >; 1050 + }; 1051 + 1052 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1053 + fsl,pins = < 1054 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 1055 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 1056 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 1057 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 1058 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 1059 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 1063 1060 >; 1064 1061 }; 1065 1062

+33 -2

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

··· 431 431 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 432 432 rohm,reset-snvs-powered; 433 433 #clock-cells = <0>; 434 - clocks = <&osc_32k 0>; 434 + clocks = <&osc_32k>; 435 435 clock-output-names = "clk-32k-out"; 436 436 437 437 regulators { ··· 714 714 715 715 /* SDIO WiFi */ 716 716 &usdhc2 { 717 - pinctrl-names = "default"; 717 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 718 718 pinctrl-0 = <&pinctrl_usdhc2>; 719 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 720 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 719 721 bus-width = <4>; 720 722 non-removable; 721 723 vmmc-supply = <&reg_wifi>; 724 + #address-cells = <1>; 725 + #size-cells = <0>; 722 726 status = "okay"; 727 + 728 + wifi@0 { 729 + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 730 + reg = <0>; 731 + }; 723 732 }; 724 733 725 734 /* eMMC */ ··· 998 989 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 999 990 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 1000 991 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 992 + >; 993 + }; 994 + 995 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 996 + fsl,pins = < 997 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 998 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 999 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 1000 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 1001 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 1002 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 1003 + >; 1004 + }; 1005 + 1006 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1007 + fsl,pins = < 1008 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 1009 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 1010 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 1011 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 1012 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 1013 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 1001 1014 >; 1002 1015 }; 1003 1016

+1 -1

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts

··· 416 416 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 417 417 rohm,reset-snvs-powered; 418 418 #clock-cells = <0>; 419 - clocks = <&osc_32k 0>; 419 + clocks = <&osc_32k>; 420 420 clock-output-names = "clk-32k-out"; 421 421 422 422 regulators {

+5 -15

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts

··· 460 460 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 461 461 rohm,reset-snvs-powered; 462 462 #clock-cells = <0>; 463 - clocks = <&osc_32k 0>; 463 + clocks = <&osc_32k>; 464 464 clock-output-names = "clk-32k-out"; 465 465 466 466 regulators { ··· 636 636 &uart1 { 637 637 pinctrl-names = "default"; 638 638 pinctrl-0 = <&pinctrl_uart1>; 639 + cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 640 + rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 639 641 status = "okay"; 640 642 }; 641 643 ··· 645 643 &uart2 { 646 644 pinctrl-names = "default"; 647 645 pinctrl-0 = <&pinctrl_uart2>; 648 - status = "okay"; 649 - }; 650 - 651 - /* off-board RS232 */ 652 - &uart3 { 653 - pinctrl-names = "default"; 654 - pinctrl-0 = <&pinctrl_uart3>; 655 646 status = "okay"; 656 647 }; 657 648 ··· 809 814 fsl,pins = < 810 815 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 811 816 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 817 + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */ 818 + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */ 812 819 >; 813 820 }; 814 821 ··· 818 821 fsl,pins = < 819 822 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 820 823 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 821 - >; 822 - }; 823 - 824 - pinctrl_uart3: uart3grp { 825 - fsl,pins = < 826 - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 827 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 828 824 >; 829 825 }; 830 826

+28

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mm.dtsi" 9 + #include "imx8mm-venice-gw700x.dtsi" 10 + #include "imx8mm-venice-gw7905.dtsi" 11 + 12 + / { 13 + model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; 14 + compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; 15 + 16 + chosen { 17 + stdout-path = &uart2; 18 + }; 19 + }; 20 + 21 + /* Disable SOM interfaces not used on baseboard */ 22 + &fec1 { 23 + status = "disabled"; 24 + }; 25 + 26 + &usdhc1 { 27 + status = "disabled"; 28 + };

+303

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include <dt-bindings/leds/common.h> 8 + #include <dt-bindings/phy/phy-imx8-pcie.h> 9 + 10 + / { 11 + led-controller { 12 + compatible = "gpio-leds"; 13 + pinctrl-names = "default"; 14 + pinctrl-0 = <&pinctrl_gpio_leds>; 15 + 16 + led-0 { 17 + function = LED_FUNCTION_STATUS; 18 + color = <LED_COLOR_ID_GREEN>; 19 + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 20 + default-state = "on"; 21 + linux,default-trigger = "heartbeat"; 22 + }; 23 + 24 + led-1 { 25 + function = LED_FUNCTION_STATUS; 26 + color = <LED_COLOR_ID_RED>; 27 + gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; 28 + default-state = "off"; 29 + }; 30 + }; 31 + 32 + pcie0_refclk: clock-pcie0 { 33 + compatible = "fixed-clock"; 34 + #clock-cells = <0>; 35 + clock-frequency = <100000000>; 36 + }; 37 + 38 + pps { 39 + compatible = "pps-gpio"; 40 + pinctrl-names = "default"; 41 + pinctrl-0 = <&pinctrl_pps>; 42 + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 43 + status = "okay"; 44 + }; 45 + 46 + reg_usb2_vbus: regulator-usb2-vbus { 47 + compatible = "regulator-fixed"; 48 + pinctrl-names = "default"; 49 + pinctrl-0 = <&pinctrl_reg_usb2_en>; 50 + regulator-name = "usb2_vbus"; 51 + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 52 + enable-active-high; 53 + regulator-min-microvolt = <5000000>; 54 + regulator-max-microvolt = <5000000>; 55 + }; 56 + 57 + reg_usdhc2_vmmc: regulator-usdhc2 { 58 + compatible = "regulator-fixed"; 59 + pinctrl-names = "default"; 60 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 61 + regulator-name = "SD2_3P3V"; 62 + regulator-min-microvolt = <3300000>; 63 + regulator-max-microvolt = <3300000>; 64 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 65 + enable-active-high; 66 + }; 67 + }; 68 + 69 + /* off-board header */ 70 + &ecspi2 { 71 + pinctrl-names = "default"; 72 + pinctrl-0 = <&pinctrl_spi2>; 73 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 74 + status = "okay"; 75 + }; 76 + 77 + &gpio1 { 78 + gpio-line-names = 79 + "", "", "", "", 80 + "", "", "", "", 81 + "", "", "", "", 82 + "", "gpioa", "gpiob", "", 83 + "", "", "", "", 84 + "", "", "", "", 85 + "", "", "", "", 86 + "", "", "", ""; 87 + }; 88 + 89 + &gpio4 { 90 + gpio-line-names = 91 + "", "", "", "pci_usb_sel", 92 + "", "", "", "pci_wdis#", 93 + "", "", "", "", 94 + "", "", "", "", 95 + "", "", "", "", 96 + "", "", "", "", 97 + "", "", "", "", 98 + "", "", "", ""; 99 + }; 100 + 101 + &gpio5 { 102 + gpio-line-names = 103 + "", "", "", "", 104 + "gpioc", "gpiod", "", "", 105 + "", "", "", "", 106 + "", "", "", "", 107 + "", "", "", "", 108 + "", "", "", "", 109 + "", "", "", "", 110 + "", "", "", ""; 111 + }; 112 + 113 + &i2c2 { 114 + clock-frequency = <400000>; 115 + pinctrl-names = "default"; 116 + pinctrl-0 = <&pinctrl_i2c2>; 117 + status = "okay"; 118 + 119 + eeprom@52 { 120 + compatible = "atmel,24c32"; 121 + reg = <0x52>; 122 + pagesize = <32>; 123 + }; 124 + }; 125 + 126 + /* off-board header */ 127 + &i2c3 { 128 + clock-frequency = <400000>; 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pinctrl_i2c3>; 131 + status = "okay"; 132 + }; 133 + 134 + &pcie_phy { 135 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 136 + fsl,clkreq-unsupported; 137 + clocks = <&pcie0_refclk>; 138 + clock-names = "ref"; 139 + status = "okay"; 140 + }; 141 + 142 + &pcie0 { 143 + pinctrl-names = "default"; 144 + pinctrl-0 = <&pinctrl_pcie0>; 145 + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; 146 + status = "okay"; 147 + }; 148 + 149 + /* GPS */ 150 + &uart1 { 151 + pinctrl-names = "default"; 152 + pinctrl-0 = <&pinctrl_uart1>; 153 + status = "okay"; 154 + }; 155 + 156 + /* USB1 - Type C front panel SINK port J14 */ 157 + &usbotg1 { 158 + dr_mode = "peripheral"; 159 + status = "okay"; 160 + }; 161 + 162 + /* USB2 4-port USB3.0 HUB: 163 + * P1 - USBC connector (host only) 164 + * P2 - USB2 test connector 165 + * P3 - miniPCIe full card 166 + * P4 - miniPCIe half card 167 + */ 168 + &usbotg2 { 169 + dr_mode = "host"; 170 + vbus-supply = <&reg_usb2_vbus>; 171 + status = "okay"; 172 + }; 173 + 174 + /* microSD */ 175 + &usdhc2 { 176 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 177 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 178 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 179 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 180 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 181 + vmmc-supply = <&reg_usdhc2_vmmc>; 182 + bus-width = <4>; 183 + status = "okay"; 184 + }; 185 + 186 + &iomuxc { 187 + pinctrl-names = "default"; 188 + pinctrl-0 = <&pinctrl_hog>; 189 + 190 + pinctrl_hog: hoggrp { 191 + fsl,pins = < 192 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ 193 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ 194 + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ 195 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ 196 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ 197 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ 198 + >; 199 + }; 200 + 201 + pinctrl_gpio_leds: gpioledgrp { 202 + fsl,pins = < 203 + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ 204 + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ 205 + >; 206 + }; 207 + 208 + pinctrl_i2c2: i2c2grp { 209 + fsl,pins = < 210 + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 211 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 212 + >; 213 + }; 214 + 215 + pinctrl_i2c3: i2c3grp { 216 + fsl,pins = < 217 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 218 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 219 + >; 220 + }; 221 + 222 + pinctrl_pcie0: pciegrp { 223 + fsl,pins = < 224 + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 225 + >; 226 + }; 227 + 228 + pinctrl_pps: ppsgrp { 229 + fsl,pins = < 230 + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 231 + >; 232 + }; 233 + 234 + pinctrl_reg_usb2_en: regusb2grp { 235 + fsl,pins = < 236 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ 237 + >; 238 + }; 239 + 240 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 241 + fsl,pins = < 242 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 243 + >; 244 + }; 245 + 246 + pinctrl_spi2: spi2grp { 247 + fsl,pins = < 248 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 249 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 250 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 251 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 252 + >; 253 + }; 254 + 255 + pinctrl_uart1: uart1grp { 256 + fsl,pins = < 257 + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 258 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 259 + >; 260 + }; 261 + 262 + pinctrl_usdhc2: usdhc2grp { 263 + fsl,pins = < 264 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 265 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 266 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 267 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 268 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 269 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 270 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 271 + >; 272 + }; 273 + 274 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 275 + fsl,pins = < 276 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 277 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 278 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 279 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 280 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 281 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 282 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 283 + >; 284 + }; 285 + 286 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 287 + fsl,pins = < 288 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 289 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 290 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 291 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 292 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 293 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 294 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 295 + >; 296 + }; 297 + 298 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 299 + fsl,pins = < 300 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 301 + >; 302 + }; 303 + };

+2 -2

arch/arm64/boot/dts/freescale/imx8mm.dtsi

··· 1345 1345 #size-cells = <2>; 1346 1346 device_type = "pci"; 1347 1347 bus-range = <0x00 0xff>; 1348 - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1349 - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1348 + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1349 + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1350 1350 num-lanes = <1>; 1351 1351 num-viewport = <4>; 1352 1352 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;

+133

arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts

··· 16 16 chosen { 17 17 stdout-path = &uart2; 18 18 }; 19 + 20 + connector { 21 + compatible = "hdmi-connector"; 22 + type = "a"; 23 + 24 + port { 25 + hdmi_connector_in: endpoint { 26 + remote-endpoint = <&adv7535_out>; 27 + }; 28 + }; 29 + }; 30 + 31 + reg_hdmi: regulator-hdmi-dvdd { 32 + compatible = "regulator-fixed"; 33 + pinctrl-names = "default"; 34 + pinctrl-0 = <&pinctrl_reg_hdmi>; 35 + regulator-name = "hdmi_pwr_en"; 36 + regulator-min-microvolt = <3300000>; 37 + regulator-max-microvolt = <3300000>; 38 + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 39 + enable-active-high; 40 + startup-delay-us = <70000>; 41 + regulator-always-on; 42 + }; 43 + 44 + sound-hdmi { 45 + compatible = "simple-audio-card"; 46 + simple-audio-card,name = "sound-hdmi"; 47 + simple-audio-card,format = "i2s"; 48 + 49 + simple-audio-card,cpu { 50 + sound-dai = <&sai5>; 51 + system-clock-direction-out; 52 + }; 53 + 54 + simple-audio-card,codec { 55 + sound-dai = <&adv_bridge>; 56 + }; 57 + }; 58 + }; 59 + 60 + &i2c2 { 61 + adv_bridge: hdmi@3d { 62 + compatible = "adi,adv7535"; 63 + pinctrl-names = "default"; 64 + pinctrl-0 = <&pinctrl_hdmi_bridge>; 65 + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 66 + reg-names = "main", "cec", "edid", "packet"; 67 + adi,dsi-lanes = <4>; 68 + avdd-supply = <&reg_hdmi>; 69 + a2vdd-supply = <&reg_hdmi>; 70 + dvdd-supply = <&reg_hdmi>; 71 + pvdd-supply = <&reg_hdmi>; 72 + v1p2-supply = <&reg_hdmi>; 73 + v3p3-supply = <&reg_hdmi>; 74 + interrupt-parent = <&gpio1>; 75 + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 76 + #sound-dai-cells = <0>; 77 + 78 + ports { 79 + #address-cells = <1>; 80 + #size-cells = <0>; 81 + 82 + port@0 { 83 + reg = <0>; 84 + 85 + adv7535_in: endpoint { 86 + remote-endpoint = <&dsi_out>; 87 + }; 88 + }; 89 + 90 + port@1 { 91 + reg = <1>; 92 + 93 + adv7535_out: endpoint { 94 + remote-endpoint = <&hdmi_connector_in>; 95 + }; 96 + }; 97 + }; 98 + }; 99 + }; 100 + 101 + &lcdif { 102 + assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; 103 + assigned-clock-rates = <594000000>; 104 + status = "okay"; 105 + }; 106 + 107 + &mipi_dsi { 108 + samsung,esc-clock-frequency = <20000000>; 109 + status = "okay"; 110 + 111 + ports { 112 + port@1 { 113 + reg = <1>; 114 + 115 + dsi_out: endpoint { 116 + remote-endpoint = <&adv7535_in>; 117 + }; 118 + }; 119 + }; 120 + }; 121 + 122 + &sai5 { 123 + pinctrl-names = "default"; 124 + pinctrl-0 = <&pinctrl_sai5>; 125 + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; 126 + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 127 + assigned-clock-rates = <24576000>; 128 + #sound-dai-cells = <0>; 129 + status = "okay"; 130 + }; 131 + 132 + &iomuxc { 133 + pinctrl_hdmi_bridge: hdmibridgegrp { 134 + fsl,pins = < 135 + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 136 + >; 137 + }; 138 + 139 + pinctrl_reg_hdmi: reghdmigrp { 140 + fsl,pins = < 141 + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 142 + >; 143 + }; 144 + 145 + pinctrl_sai5: sai5grp { 146 + fsl,pins = < 147 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 148 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 149 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 150 + >; 151 + }; 19 152 };

+1 -1

arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi

··· 121 121 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 122 122 rohm,reset-snvs-powered; 123 123 #clock-cells = <0>; 124 - clocks = <&osc_32k 0>; 124 + clocks = <&osc_32k>; 125 125 clock-output-names = "clk-32k-out"; 126 126 127 127 regulators {

+1 -1

arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi

··· 92 92 rohm,reset-snvs-powered; 93 93 94 94 #clock-cells = <0>; 95 - clocks = <&osc_32k 0>; 95 + clocks = <&osc_32k>; 96 96 clock-output-names = "clk-32k-out"; 97 97 98 98 regulators {

+1 -1

arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts

··· 60 60 rohm,reset-snvs-powered; 61 61 62 62 #clock-cells = <0>; 63 - clocks = <&osc_32k 0>; 63 + clocks = <&osc_32k>; 64 64 clock-output-names = "clk-32k-out"; 65 65 66 66 regulators {

+3 -3

arch/arm64/boot/dts/freescale/imx8mn-evk.dts

··· 40 40 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 41 41 42 42 regulators { 43 - buck1: BUCK1{ 43 + buck1: BUCK1 { 44 44 regulator-name = "VDD_SOC"; 45 45 regulator-min-microvolt = <850000>; 46 46 regulator-max-microvolt = <950000>; ··· 59 59 regulator-ramp-delay = <3125>; 60 60 }; 61 61 62 - buck4: BUCK4{ 62 + buck4: BUCK4 { 63 63 regulator-name = "VDD_3V3"; 64 64 regulator-min-microvolt = <3300000>; 65 65 regulator-max-microvolt = <3300000>; ··· 67 67 regulator-always-on; 68 68 }; 69 69 70 - buck5: BUCK5{ 70 + buck5: BUCK5 { 71 71 regulator-name = "VDD_1V8"; 72 72 regulator-min-microvolt = <1800000>; 73 73 regulator-max-microvolt = <1800000>;

+116 -2

arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

··· 23 23 }; 24 24 }; 25 25 26 + hdmi-connector { 27 + compatible = "hdmi-connector"; 28 + label = "hdmi"; 29 + type = "a"; 30 + 31 + port { 32 + hdmi_connector_in: endpoint { 33 + remote-endpoint = <&adv7533_out>; 34 + }; 35 + }; 36 + }; 37 + 26 38 memory@40000000 { 27 39 device_type = "memory"; 28 40 reg = <0x0 0x40000000 0 0x80000000>; ··· 175 163 pinctrl-names = "default", "gpio"; 176 164 pinctrl-0 = <&pinctrl_i2c2>; 177 165 pinctrl-1 = <&pinctrl_i2c2_gpio>; 178 - scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; 179 - sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 166 + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 167 + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 180 168 status = "okay"; 169 + 170 + hdmi@3d { 171 + compatible = "adi,adv7535"; 172 + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 173 + reg-names = "main", "cec", "edid", "packet"; 174 + adi,dsi-lanes = <4>; 175 + 176 + adi,input-depth = <8>; 177 + adi,input-colorspace = "rgb"; 178 + adi,input-clock = "1x"; 179 + adi,input-style = <1>; 180 + adi,input-justification = "evenly"; 181 + 182 + ports { 183 + #address-cells = <1>; 184 + #size-cells = <0>; 185 + 186 + port@0 { 187 + reg = <0>; 188 + 189 + adv7533_in: endpoint { 190 + remote-endpoint = <&dsi_out>; 191 + }; 192 + }; 193 + 194 + port@1 { 195 + reg = <1>; 196 + 197 + adv7533_out: endpoint { 198 + remote-endpoint = <&hdmi_connector_in>; 199 + }; 200 + }; 201 + 202 + }; 203 + }; 181 204 182 205 ptn5110: tcpc@50 { 183 206 compatible = "nxp,ptn5110"; ··· 258 211 reg = <0x20>; 259 212 gpio-controller; 260 213 #gpio-cells = <2>; 214 + }; 215 + 216 + camera@3c { 217 + compatible = "ovti,ov5640"; 218 + reg = <0x3c>; 219 + pinctrl-names = "default"; 220 + pinctrl-0 = <&pinctrl_camera>; 221 + clocks = <&clk IMX8MN_CLK_CLKO1>; 222 + clock-names = "xclk"; 223 + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; 224 + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; 225 + assigned-clock-rates = <24000000>; 226 + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 227 + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 228 + 229 + port { 230 + ov5640_to_mipi_csi2: endpoint { 231 + remote-endpoint = <&imx8mn_mipi_csi_in>; 232 + clock-lanes = <0>; 233 + data-lanes = <1 2>; 234 + }; 235 + }; 236 + }; 237 + }; 238 + 239 + &isi { 240 + status = "okay"; 241 + }; 242 + 243 + &mipi_csi { 244 + status = "okay"; 245 + 246 + ports { 247 + port@0 { 248 + imx8mn_mipi_csi_in: endpoint { 249 + remote-endpoint = <&ov5640_to_mipi_csi2>; 250 + data-lanes = <1 2>; 251 + }; 252 + }; 253 + }; 254 + }; 255 + 256 + &lcdif { 257 + status = "okay"; 258 + }; 259 + 260 + &mipi_dsi { 261 + samsung,esc-clock-frequency = <10000000>; 262 + status = "okay"; 263 + 264 + ports { 265 + port@1 { 266 + reg = <1>; 267 + 268 + dsi_out: endpoint { 269 + remote-endpoint = <&adv7533_in>; 270 + data-lanes = <1 2 3 4>; 271 + }; 272 + }; 261 273 }; 262 274 }; 263 275 ··· 432 326 }; 433 327 434 328 &iomuxc { 329 + pinctrl_camera: cameragrp { 330 + fsl,pins = < 331 + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 332 + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 333 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 334 + >; 335 + }; 336 + 435 337 pinctrl_fec1: fec1grp { 436 338 fsl,pins = < 437 339 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3

+2

arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi

··· 208 208 read-only; 209 209 reg = <0x53>; 210 210 pagesize = <16>; 211 + vcc-supply = <&reg_vcc3v3>; 211 212 }; 212 213 213 214 eeprom0: eeprom@57 { 214 215 compatible = "atmel,24c64"; 215 216 reg = <0x57>; 216 217 pagesize = <32>; 218 + vcc-supply = <&reg_vcc3v3>; 217 219 }; 218 220 }; 219 221

+30 -2

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts

··· 1 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 /* 3 + * Supports Symphony evaluation board versions >= 1.4a. 4 + * 3 5 * Copyright 2019-2020 Variscite Ltd. 4 6 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> 5 7 */ 6 8 7 9 /dts-v1/; 8 10 11 + #include <dt-bindings/usb/pd.h> 9 12 #include "imx8mn-var-som.dtsi" 10 13 11 14 / { ··· 103 100 }; 104 101 }; 105 102 103 + /* 104 + * For Symphony board version <= 1.4, the PTN5150 IRQ pin is connected 105 + * to GPIO1_IO11 on the SoM (R106 present, R132 absent). From Symphony 106 + * board version >= 1.4a, the PTN5150 ID pin is connected to GPIO1_IO11 107 + * on the SoM (R106 absent, R132 present). 108 + */ 106 109 extcon_usbotg1: typec@3d { 107 110 compatible = "nxp,ptn5150"; 108 111 reg = <0x3d>; 109 112 interrupt-parent = <&gpio1>; 110 - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 113 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 111 114 pinctrl-names = "default"; 112 115 pinctrl-0 = <&pinctrl_ptn5150>; 113 116 status = "okay"; 117 + 118 + port { 119 + typec1_dr_sw: endpoint { 120 + remote-endpoint = <&usb1_drd_sw>; 121 + }; 122 + }; 114 123 }; 115 124 }; 116 125 ··· 163 148 }; 164 149 165 150 &usbotg1 { 151 + dr_mode = "otg"; 152 + hnp-disable; 153 + srp-disable; 154 + adp-disable; 155 + usb-role-switch; 166 156 disable-over-current; 167 - extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; 157 + samsung,picophy-pre-emp-curr-control = <3>; 158 + samsung,picophy-dc-vol-level-adjust = <7>; 159 + status = "okay"; 160 + 161 + port { 162 + usb1_drd_sw: endpoint { 163 + remote-endpoint = <&typec1_dr_sw>; 164 + }; 165 + }; 168 166 }; 169 167 170 168 &iomuxc {

+33 -2

arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts

··· 429 429 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 430 430 rohm,reset-snvs-powered; 431 431 #clock-cells = <0>; 432 - clocks = <&osc_32k 0>; 432 + clocks = <&osc_32k>; 433 433 clock-output-names = "clk-32k-out"; 434 434 435 435 regulators { ··· 667 667 668 668 /* SDIO WiFi */ 669 669 &usdhc2 { 670 - pinctrl-names = "default"; 670 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 671 671 pinctrl-0 = <&pinctrl_usdhc2>; 672 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 673 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 672 674 bus-width = <4>; 673 675 non-removable; 674 676 vmmc-supply = <&reg_wifi>; 677 + #address-cells = <1>; 678 + #size-cells = <0>; 675 679 status = "okay"; 680 + 681 + wifi@0 { 682 + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 683 + reg = <0>; 684 + }; 676 685 }; 677 686 678 687 /* eMMC */ ··· 929 920 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 930 921 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 931 922 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 923 + >; 924 + }; 925 + 926 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 927 + fsl,pins = < 928 + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 929 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 930 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 931 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 932 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 933 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 934 + >; 935 + }; 936 + 937 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 938 + fsl,pins = < 939 + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 940 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 941 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 942 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 943 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 944 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 932 945 >; 933 946 }; 934 947

+2 -25

arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts

··· 129 129 nxp,dvs-standby-voltage = <850000>; 130 130 }; 131 131 132 - buck4: BUCK4{ 132 + buck4: BUCK4 { 133 133 regulator-name = "BUCK4"; 134 134 regulator-min-microvolt = <600000>; 135 135 regulator-max-microvolt = <3400000>; ··· 137 137 regulator-always-on; 138 138 }; 139 139 140 - buck5: BUCK5{ 140 + buck5: BUCK5 { 141 141 regulator-name = "BUCK5"; 142 142 regulator-min-microvolt = <600000>; 143 143 regulator-max-microvolt = <3400000>; ··· 226 226 compatible = "haoyu,hym8563"; 227 227 reg = <0x51>; 228 228 #clock-cells = <0>; 229 - clock-frequency = <32768>; 230 229 clock-output-names = "xin32k"; 231 230 interrupt-parent = <&gpio2>; 232 231 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; ··· 351 352 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f 352 353 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f 353 354 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 354 - >; 355 - }; 356 - 357 - pinctrl_fec: fecgrp { 358 - fsl,pins = < 359 - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 360 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 361 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 362 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 363 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 364 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 365 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 366 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 367 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 368 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 369 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 370 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 371 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 372 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 373 - MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f 374 - MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f 375 - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 376 355 >; 377 356 }; 378 357

+472

arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 NXP 4 + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include "imx8mp-debix-som-a.dtsi" 10 + 11 + / { 12 + model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; 13 + compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", 14 + "fsl,imx8mp"; 15 + 16 + aliases { 17 + ethernet0 = &eqos; 18 + ethernet1 = &fec; 19 + }; 20 + 21 + chosen { 22 + stdout-path = &uart2; 23 + }; 24 + 25 + reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { 26 + compatible = "regulator-fixed"; 27 + regulator-min-microvolt = <3300000>; 28 + regulator-max-microvolt = <3300000>; 29 + regulator-name = "BB_VDD3V3"; 30 + /* Required timings for ethernet phy's */ 31 + startup-delay-us = <50000>; 32 + off-on-delay-us = <110000>; 33 + gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; 34 + enable-active-high; 35 + }; 36 + 37 + reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { 38 + compatible = "regulator-fixed"; 39 + regulator-min-microvolt = <5000000>; 40 + regulator-max-microvolt = <5000000>; 41 + regulator-name = "BB_VDD5V"; 42 + gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; 43 + enable-active-high; 44 + }; 45 + 46 + regulator-som-vdd1v8 { 47 + compatible = "regulator-fixed"; 48 + regulator-min-microvolt = <1800000>; 49 + regulator-max-microvolt = <1800000>; 50 + regulator-name = "SOM_VDD1V8_SW"; 51 + gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 52 + enable-active-high; 53 + regulator-always-on; 54 + }; 55 + 56 + regulator-som-vdd3v3 { 57 + compatible = "regulator-fixed"; 58 + regulator-min-microvolt = <3300000>; 59 + regulator-max-microvolt = <3300000>; 60 + regulator-name = "SOM_VDD3V3_SW"; 61 + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; 62 + enable-active-high; 63 + regulator-always-on; 64 + }; 65 + 66 + regulator-vbus-usb20 { 67 + compatible = "regulator-fixed"; 68 + regulator-min-microvolt = <5000000>; 69 + regulator-max-microvolt = <5000000>; 70 + regulator-name = "USB20_5V"; 71 + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; 72 + enable-active-high; 73 + regulator-always-on; 74 + vin-supply = <&reg_baseboard_vdd5v0>; 75 + }; 76 + 77 + regulator-vbus-usb30 { 78 + compatible = "regulator-fixed"; 79 + regulator-min-microvolt = <5000000>; 80 + regulator-max-microvolt = <5000000>; 81 + regulator-name = "USB30_5V"; 82 + gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; 83 + enable-active-high; 84 + regulator-always-on; 85 + vin-supply = <&reg_baseboard_vdd5v0>; 86 + }; 87 + 88 + reg_vdd5v0: regulator-vdd5v0 { 89 + compatible = "regulator-fixed"; 90 + regulator-min-microvolt = <5000000>; 91 + regulator-max-microvolt = <5000000>; 92 + regulator-name = "VDD_5V"; 93 + gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; 94 + enable-active-high; 95 + }; 96 + }; 97 + 98 + &eqos { 99 + pinctrl-names = "default"; 100 + pinctrl-0 = <&pinctrl_eqos>; 101 + nvmem-cells = <&ethmac1>; 102 + nvmem-cell-names = "mac-address"; 103 + phy-supply = <&reg_baseboard_vdd3v3>; 104 + phy-handle = <&ethphy0>; 105 + phy-mode = "rgmii-id"; 106 + status = "okay"; 107 + 108 + mdio { 109 + compatible = "snps,dwmac-mdio"; 110 + #address-cells = <1>; 111 + #size-cells = <0>; 112 + 113 + ethphy0: ethernet-phy@1 { 114 + compatible = "ethernet-phy-ieee802.3-c22"; 115 + reg = <1>; 116 + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 117 + reset-assert-us = <20000>; 118 + reset-deassert-us = <150000>; 119 + eee-broken-1000t; 120 + realtek,clkout-disable; 121 + }; 122 + }; 123 + }; 124 + 125 + &fec { 126 + pinctrl-names = "default"; 127 + pinctrl-0 = <&pinctrl_fec>; 128 + nvmem-cells = <&ethmac2>; 129 + nvmem-cell-names = "mac-address"; 130 + phy-supply = <&reg_baseboard_vdd3v3>; 131 + phy-handle = <&ethphy1>; 132 + phy-mode = "rgmii-id"; 133 + fsl,magic-packet; 134 + status = "okay"; 135 + 136 + mdio { 137 + #address-cells = <1>; 138 + #size-cells = <0>; 139 + 140 + ethphy1: ethernet-phy@1 { 141 + compatible = "ethernet-phy-ieee802.3-c22"; 142 + reg = <1>; 143 + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 144 + reset-assert-us = <20000>; 145 + reset-deassert-us = <150000>; 146 + eee-broken-1000t; 147 + realtek,clkout-disable; 148 + }; 149 + }; 150 + }; 151 + 152 + &flexcan1 { 153 + pinctrl-names = "default"; 154 + pinctrl-0 = <&pinctrl_flexcan1>; 155 + xceiver-supply = <&reg_vdd5v0>; 156 + status = "okay"; 157 + }; 158 + 159 + &flexcan2 { 160 + pinctrl-names = "default"; 161 + pinctrl-0 = <&pinctrl_flexcan2>; 162 + xceiver-supply = <&reg_vdd5v0>; 163 + status = "okay"; 164 + }; 165 + 166 + &flexspi { 167 + pinctrl-names = "default"; 168 + pinctrl-0 = <&pinctrl_flexspi0>; 169 + status = "okay"; 170 + 171 + flash: flash@0 { 172 + compatible = "jedec,spi-nor"; 173 + reg = <0>; 174 + spi-max-frequency = <80000000>; 175 + spi-tx-bus-width = <1>; 176 + spi-rx-bus-width = <4>; 177 + #address-cells = <1>; 178 + #size-cells = <1>; 179 + }; 180 + }; 181 + 182 + &i2c4 { 183 + expander0: gpio@20 { 184 + compatible = "nxp,pca9535"; 185 + reg = <0x20>; 186 + gpio-controller; 187 + #gpio-cells = <0x02>; 188 + }; 189 + 190 + expander1: gpio@23 { 191 + compatible = "nxp,pca9535"; 192 + reg = <0x23>; 193 + gpio-controller; 194 + #gpio-cells = <0x02>; 195 + 196 + /* 197 + * Since USB1 is bound to peripheral mode we need to ensure 198 + * that VBUS is turned off. 199 + */ 200 + usb30-otg-hog { 201 + gpio-hog; 202 + gpios = <13 GPIO_ACTIVE_HIGH>; 203 + output-low; 204 + line-name = "USB30_OTG_EN"; 205 + }; 206 + }; 207 + 208 + rtc@51 { 209 + compatible = "haoyu,hym8563"; 210 + reg = <0x51>; 211 + pinctrl-names = "default"; 212 + pinctrl-0 = <&pinctrl_rtc>; 213 + interrupt-parent = <&gpio4>; 214 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 215 + #clock-cells = <0>; 216 + }; 217 + 218 + eeprom@52 { 219 + compatible = "atmel,24c02"; 220 + reg = <0x52>; 221 + pagesize = <16>; 222 + #address-cells = <1>; 223 + #size-cells = <0>; 224 + 225 + /* MACs stored in ASCII */ 226 + ethmac1: mac-address@0 { 227 + reg = <0x0 0xc>; 228 + }; 229 + 230 + ethmac2: mac-address@c { 231 + reg = <0xc 0xc>; 232 + }; 233 + }; 234 + }; 235 + 236 + &snvs_pwrkey { 237 + status = "okay"; 238 + }; 239 + 240 + /* Debug */ 241 + &uart2 { 242 + pinctrl-names = "default"; 243 + pinctrl-0 = <&pinctrl_uart2>; 244 + status = "okay"; 245 + }; 246 + 247 + &uart3 { 248 + pinctrl-names = "default"; 249 + pinctrl-0 = <&pinctrl_uart3>; 250 + status = "okay"; 251 + }; 252 + 253 + &uart4 { 254 + pinctrl-names = "default"; 255 + pinctrl-0 = <&pinctrl_uart4>; 256 + status = "okay"; 257 + }; 258 + 259 + &usb3_0 { 260 + status = "okay"; 261 + }; 262 + 263 + &usb3_1 { 264 + status = "okay"; 265 + }; 266 + 267 + &usb_dwc3_0 { 268 + dr_mode = "peripheral"; 269 + status = "okay"; 270 + }; 271 + 272 + &usb_dwc3_1 { 273 + dr_mode = "host"; 274 + #address-cells = <1>; 275 + #size-cells = <0>; 276 + status = "okay"; 277 + 278 + /* 2.x hub on port 1 */ 279 + usb_hub_2_x: hub@1 { 280 + compatible = "usb5e3,610"; 281 + reg = <1>; 282 + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; 283 + vdd-supply = <&reg_vdd5v0>; 284 + peer-hub = <&usb_hub_3_x>; 285 + }; 286 + 287 + /* 3.x hub on port 2 */ 288 + usb_hub_3_x: hub@2 { 289 + compatible = "usb5e3,620"; 290 + reg = <2>; 291 + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; 292 + vdd-supply = <&reg_vdd5v0>; 293 + peer-hub = <&usb_hub_2_x>; 294 + }; 295 + }; 296 + 297 + &usb3_phy0 { 298 + status = "okay"; 299 + }; 300 + 301 + &usb3_phy1 { 302 + status = "okay"; 303 + }; 304 + 305 + /* µSD Card */ 306 + &usdhc2 { 307 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 308 + pinctrl-0 = <&pinctrl_usdhc2>; 309 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 310 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 311 + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 312 + assigned-clock-rates = <400000000>; 313 + vmmc-supply = <&reg_usdhc2_vmmc>; 314 + bus-width = <4>; 315 + disable-wp; 316 + no-sdio; 317 + no-mmc; 318 + status = "okay"; 319 + }; 320 + 321 + &iomuxc { 322 + pinctrl_eqos: eqosgrp { 323 + fsl,pins = < 324 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 325 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 326 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 327 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 328 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 329 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 330 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 331 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 332 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 333 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 334 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 335 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 336 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 337 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 338 + 339 + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f 340 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 341 + >; 342 + }; 343 + 344 + pinctrl_fec: fecgrp { 345 + fsl,pins = < 346 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 347 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 348 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 349 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 350 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 351 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 352 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 353 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 354 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 355 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 356 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 357 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 358 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 359 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 360 + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f 361 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 362 + >; 363 + }; 364 + 365 + pinctrl_flexcan1: flexcan1grp { 366 + fsl,pins = < 367 + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 368 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 369 + >; 370 + }; 371 + 372 + pinctrl_flexcan2: flexcan2grp { 373 + fsl,pins = < 374 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 375 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 376 + >; 377 + }; 378 + 379 + pinctrl_flexspi0: flexspi0grp { 380 + fsl,pins = < 381 + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 382 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 383 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 384 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 385 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 386 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 387 + >; 388 + }; 389 + 390 + pinctrl_i2c1: i2c1grp { 391 + fsl,pins = < 392 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 393 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 394 + >; 395 + }; 396 + 397 + pinctrl_i2c4: i2c4grp { 398 + fsl,pins = < 399 + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 400 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 401 + >; 402 + }; 403 + 404 + pinctrl_rtc: rtcgrp { 405 + fsl,pins = < 406 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 407 + >; 408 + }; 409 + 410 + pinctrl_pmic: pmicgrp { 411 + fsl,pins = < 412 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 413 + >; 414 + }; 415 + 416 + pinctrl_uart2: uart2grp { 417 + fsl,pins = < 418 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f 419 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f 420 + >; 421 + }; 422 + 423 + pinctrl_uart3: uart3grp { 424 + fsl,pins = < 425 + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 426 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 427 + >; 428 + }; 429 + 430 + pinctrl_uart4: uart4grp { 431 + fsl,pins = < 432 + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 433 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 434 + >; 435 + }; 436 + 437 + pinctrl_usdhc2: usdhc2grp { 438 + fsl,pins = < 439 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 440 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 441 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 442 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 443 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 444 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 445 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 446 + >; 447 + }; 448 + 449 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 450 + fsl,pins = < 451 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 452 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 453 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 454 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 455 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 456 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 457 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 458 + >; 459 + }; 460 + 461 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 462 + fsl,pins = < 463 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 464 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 465 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 466 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 467 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 468 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 469 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 470 + >; 471 + }; 472 + };

+285

arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 NXP 4 + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> 5 + */ 6 + 7 + #include "imx8mp.dtsi" 8 + 9 + / { 10 + model = "Polyhex i.MX8MPlus Debix SOM A"; 11 + compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; 12 + 13 + reg_usdhc2_vmmc: regulator-usdhc2 { 14 + compatible = "regulator-fixed"; 15 + pinctrl-names = "default"; 16 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 17 + regulator-name = "VSD_3V3"; 18 + regulator-min-microvolt = <3300000>; 19 + regulator-max-microvolt = <3300000>; 20 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 21 + enable-active-high; 22 + }; 23 + }; 24 + 25 + &A53_0 { 26 + cpu-supply = <&buck2>; 27 + }; 28 + 29 + &A53_1 { 30 + cpu-supply = <&buck2>; 31 + }; 32 + 33 + &A53_2 { 34 + cpu-supply = <&buck2>; 35 + }; 36 + 37 + &A53_3 { 38 + cpu-supply = <&buck2>; 39 + }; 40 + 41 + &i2c1 { 42 + clock-frequency = <400000>; 43 + pinctrl-names = "default"; 44 + pinctrl-0 = <&pinctrl_i2c1>; 45 + status = "okay"; 46 + 47 + pmic@25 { 48 + compatible = "nxp,pca9450c"; 49 + reg = <0x25>; 50 + pinctrl-names = "default"; 51 + pinctrl-0 = <&pinctrl_pmic>; 52 + interrupt-parent = <&gpio1>; 53 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 54 + 55 + regulators { 56 + buck1: BUCK1 { 57 + regulator-name = "BUCK1"; 58 + regulator-min-microvolt = <600000>; 59 + regulator-max-microvolt = <2187500>; 60 + regulator-boot-on; 61 + regulator-always-on; 62 + regulator-ramp-delay = <3125>; 63 + }; 64 + 65 + buck2: BUCK2 { 66 + regulator-name = "BUCK2"; 67 + regulator-min-microvolt = <600000>; 68 + regulator-max-microvolt = <2187500>; 69 + regulator-boot-on; 70 + regulator-always-on; 71 + regulator-ramp-delay = <3125>; 72 + nxp,dvs-run-voltage = <950000>; 73 + nxp,dvs-standby-voltage = <850000>; 74 + }; 75 + 76 + buck4: BUCK4 { 77 + regulator-name = "BUCK4"; 78 + regulator-min-microvolt = <600000>; 79 + regulator-max-microvolt = <3400000>; 80 + regulator-boot-on; 81 + regulator-always-on; 82 + }; 83 + 84 + buck5: BUCK5 { 85 + regulator-name = "BUCK5"; 86 + regulator-min-microvolt = <600000>; 87 + regulator-max-microvolt = <3400000>; 88 + regulator-boot-on; 89 + regulator-always-on; 90 + }; 91 + 92 + buck6: BUCK6 { 93 + regulator-name = "BUCK6"; 94 + regulator-min-microvolt = <600000>; 95 + regulator-max-microvolt = <3400000>; 96 + regulator-boot-on; 97 + regulator-always-on; 98 + }; 99 + 100 + ldo1: LDO1 { 101 + regulator-name = "LDO1"; 102 + regulator-min-microvolt = <1600000>; 103 + regulator-max-microvolt = <3300000>; 104 + regulator-boot-on; 105 + regulator-always-on; 106 + }; 107 + 108 + ldo2: LDO2 { 109 + regulator-name = "LDO2"; 110 + regulator-min-microvolt = <800000>; 111 + regulator-max-microvolt = <1150000>; 112 + regulator-boot-on; 113 + regulator-always-on; 114 + }; 115 + 116 + ldo3: LDO3 { 117 + regulator-name = "LDO3"; 118 + regulator-min-microvolt = <800000>; 119 + regulator-max-microvolt = <3300000>; 120 + regulator-boot-on; 121 + regulator-always-on; 122 + }; 123 + 124 + ldo4: LDO4 { 125 + regulator-name = "LDO4"; 126 + regulator-min-microvolt = <800000>; 127 + regulator-max-microvolt = <3300000>; 128 + regulator-boot-on; 129 + regulator-always-on; 130 + }; 131 + 132 + ldo5: LDO5 { 133 + regulator-name = "LDO5"; 134 + regulator-min-microvolt = <1800000>; 135 + regulator-max-microvolt = <3300000>; 136 + regulator-boot-on; 137 + regulator-always-on; 138 + }; 139 + }; 140 + }; 141 + }; 142 + 143 + &i2c4 { 144 + clock-frequency = <400000>; 145 + pinctrl-names = "default"; 146 + pinctrl-0 = <&pinctrl_i2c4>; 147 + status = "okay"; 148 + 149 + adc@48 { 150 + compatible = "ti,ads1115"; 151 + reg = <0x48>; 152 + #address-cells = <1>; 153 + #size-cells = <0>; 154 + 155 + channel@4 { 156 + reg = <4>; 157 + ti,gain = <1>; 158 + ti,datarate = <7>; 159 + }; 160 + 161 + channel@5 { 162 + reg = <5>; 163 + ti,gain = <1>; 164 + ti,datarate = <7>; 165 + }; 166 + 167 + channel@6 { 168 + reg = <6>; 169 + ti,gain = <1>; 170 + ti,datarate = <7>; 171 + }; 172 + 173 + channel@7 { 174 + reg = <7>; 175 + ti,gain = <1>; 176 + ti,datarate = <7>; 177 + }; 178 + }; 179 + }; 180 + 181 + &snvs_pwrkey { 182 + status = "okay"; 183 + }; 184 + 185 + /* eMMC */ 186 + &usdhc3 { 187 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 188 + pinctrl-0 = <&pinctrl_usdhc3>; 189 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 190 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 191 + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 192 + assigned-clock-rates = <400000000>; 193 + bus-width = <8>; 194 + non-removable; 195 + status = "okay"; 196 + }; 197 + 198 + &wdog1 { 199 + pinctrl-names = "default"; 200 + pinctrl-0 = <&pinctrl_wdog>; 201 + fsl,ext-reset-output; 202 + status = "okay"; 203 + }; 204 + 205 + &iomuxc { 206 + pinctrl_i2c1: i2c1grp { 207 + fsl,pins = < 208 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 209 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 210 + >; 211 + }; 212 + 213 + pinctrl_i2c4: i2c4grp { 214 + fsl,pins = < 215 + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 216 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 217 + >; 218 + }; 219 + 220 + pinctrl_pmic: pmicgrp { 221 + fsl,pins = < 222 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 223 + >; 224 + }; 225 + 226 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 227 + fsl,pins = < 228 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 229 + >; 230 + }; 231 + 232 + pinctrl_usdhc3: usdhc3grp { 233 + fsl,pins = < 234 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 235 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 236 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 237 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 238 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 239 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 240 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 241 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 242 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 243 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 244 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 245 + >; 246 + }; 247 + 248 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 249 + fsl,pins = < 250 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 251 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 252 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 253 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 254 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 255 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 256 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 257 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 258 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 259 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 260 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 261 + >; 262 + }; 263 + 264 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 265 + fsl,pins = < 266 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 267 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 268 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 269 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 270 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 271 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 272 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 273 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 274 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 275 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 276 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 277 + >; 278 + }; 279 + 280 + pinctrl_wdog: wdoggrp { 281 + fsl,pins = < 282 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 283 + >; 284 + }; 285 + };

+66

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

··· 16 16 stdout-path = &uart2; 17 17 }; 18 18 19 + hdmi-connector { 20 + compatible = "hdmi-connector"; 21 + label = "hdmi"; 22 + type = "a"; 23 + 24 + port { 25 + hdmi_connector_in: endpoint { 26 + remote-endpoint = <&adv7533_out>; 27 + }; 28 + }; 29 + }; 30 + 19 31 gpio-leds { 20 32 compatible = "gpio-leds"; 21 33 pinctrl-names = "default"; ··· 390 378 pinctrl-names = "default"; 391 379 pinctrl-0 = <&pinctrl_i2c2>; 392 380 status = "okay"; 381 + 382 + hdmi@3d { 383 + compatible = "adi,adv7535"; 384 + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 385 + reg-names = "main", "cec", "edid", "packet"; 386 + adi,dsi-lanes = <4>; 387 + adi,input-depth = <8>; 388 + adi,input-colorspace = "rgb"; 389 + adi,input-clock = "1x"; 390 + adi,input-style = <1>; 391 + adi,input-justification = "evenly"; 392 + 393 + ports { 394 + #address-cells = <1>; 395 + #size-cells = <0>; 396 + 397 + port@0 { 398 + reg = <0>; 399 + 400 + adv7533_in: endpoint { 401 + remote-endpoint = <&dsi_out>; 402 + }; 403 + }; 404 + 405 + port@1 { 406 + reg = <1>; 407 + 408 + adv7533_out: endpoint { 409 + remote-endpoint = <&hdmi_connector_in>; 410 + }; 411 + }; 412 + 413 + }; 414 + }; 393 415 }; 394 416 395 417 &i2c3 { ··· 487 441 * You need to set it to high to enable I2C5 (for example, add gpio-hog 488 442 * in pca6416 node). 489 443 */ 444 + }; 445 + 446 + &lcdif1 { 447 + status = "okay"; 448 + }; 449 + 450 + &mipi_dsi { 451 + samsung,esc-clock-frequency = <10000000>; 452 + status = "okay"; 453 + 454 + ports { 455 + port@1 { 456 + reg = <1>; 457 + 458 + dsi_out: endpoint { 459 + remote-endpoint = <&adv7533_in>; 460 + data-lanes = <1 2 3 4>; 461 + }; 462 + }; 463 + }; 490 464 }; 491 465 492 466 &pcie_phy {

-1

arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts

··· 55 55 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 56 56 assigned-clock-rates = <24000000>; 57 57 clocks = <&clk IMX8MP_CLK_CLKOUT1>; 58 - clock-names = "mclk"; 59 58 #sound-dai-cells = <0>; 60 59 61 60 VDDA-supply = <&reg_vcc_3v3_audio>;

+1 -1

arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi

··· 109 109 compatible = "linux,extcon-usb-gpio"; 110 110 pinctrl-names = "default"; 111 111 pinctrl-0 = <&pinctrl_usb0_extcon>; 112 - id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; 112 + id-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 113 113 }; 114 114 }; 115 115

+5 -3

arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

··· 76 76 compatible = "nxp,pca9533"; 77 77 reg = <0x62>; 78 78 79 - led1 { 79 + led-1 { 80 80 type = <PCA9532_TYPE_LED>; 81 81 }; 82 82 83 - led2 { 83 + led-2 { 84 84 type = <PCA9532_TYPE_LED>; 85 85 }; 86 86 87 - led3 { 87 + led-3 { 88 88 type = <PCA9532_TYPE_LED>; 89 89 }; 90 90 }; ··· 103 103 104 104 /* SD-Card */ 105 105 &usdhc2 { 106 + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 107 + assigned-clock-rates = <200000000>; 106 108 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 107 109 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; 108 110 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;

+74 -81

arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi

··· 42 42 &fec { 43 43 pinctrl-names = "default"; 44 44 pinctrl-0 = <&pinctrl_fec>; 45 - phy-mode = "rgmii-id"; 46 45 phy-handle = <&ethphy1>; 46 + phy-mode = "rgmii-id"; 47 47 fsl,magic-packet; 48 48 status = "okay"; 49 49 ··· 54 54 ethphy1: ethernet-phy@0 { 55 55 compatible = "ethernet-phy-ieee802.3-c22"; 56 56 reg = <0>; 57 - interrupt-parent = <&gpio1>; 58 - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 57 + enet-phy-lane-no-swap; 58 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 59 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 60 + ti,min-output-impedance; 59 61 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 60 62 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 61 - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 62 - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 63 - ti,min-output-impedance; 64 - enet-phy-lane-no-swap; 65 63 }; 66 64 }; 67 65 }; ··· 73 75 compatible = "jedec,spi-nor"; 74 76 reg = <0>; 75 77 spi-max-frequency = <80000000>; 76 - spi-tx-bus-width = <1>; 77 78 spi-rx-bus-width = <4>; 79 + spi-tx-bus-width = <1>; 78 80 }; 79 81 }; 80 82 ··· 83 85 pinctrl-names = "default", "gpio"; 84 86 pinctrl-0 = <&pinctrl_i2c1>; 85 87 pinctrl-1 = <&pinctrl_i2c1_gpio>; 86 - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 87 88 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 89 + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 88 90 status = "okay"; 89 91 90 92 pmic: pmic@25 { 91 - reg = <0x25>; 92 93 compatible = "nxp,pca9450c"; 94 + reg = <0x25>; 95 + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 96 + interrupt-parent = <&gpio4>; 93 97 pinctrl-names = "default"; 94 98 pinctrl-0 = <&pinctrl_pmic>; 95 - interrupt-parent = <&gpio4>; 96 - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 97 99 98 100 regulators { 99 101 buck1: BUCK1 { 100 - regulator-min-microvolt = <600000>; 101 - regulator-max-microvolt = <2187500>; 102 - regulator-boot-on; 103 102 regulator-always-on; 103 + regulator-boot-on; 104 + regulator-max-microvolt = <1000000>; 105 + regulator-min-microvolt = <805000>; 106 + regulator-name = "VDD_SOC (BUCK1)"; 104 107 regulator-ramp-delay = <3125>; 105 108 }; 106 109 107 110 buck2: BUCK2 { 108 - regulator-min-microvolt = <600000>; 109 - regulator-max-microvolt = <2187500>; 110 - regulator-boot-on; 111 - regulator-always-on; 112 - regulator-ramp-delay = <3125>; 113 111 nxp,dvs-run-voltage = <950000>; 114 112 nxp,dvs-standby-voltage = <850000>; 113 + regulator-always-on; 114 + regulator-boot-on; 115 + regulator-max-microvolt = <1050000>; 116 + regulator-min-microvolt = <805000>; 117 + regulator-name = "VDD_ARM (BUCK2)"; 118 + regulator-ramp-delay = <3125>; 115 119 }; 116 120 117 121 buck4: BUCK4 { 118 - regulator-min-microvolt = <600000>; 119 - regulator-max-microvolt = <3400000>; 120 - regulator-boot-on; 121 122 regulator-always-on; 123 + regulator-boot-on; 124 + regulator-max-microvolt = <3300000>; 125 + regulator-min-microvolt = <3300000>; 126 + regulator-name = "VDD_3V3 (BUCK4)"; 122 127 }; 123 128 124 129 buck5: BUCK5 { 125 - regulator-min-microvolt = <600000>; 126 - regulator-max-microvolt = <3400000>; 127 - regulator-boot-on; 128 130 regulator-always-on; 131 + regulator-boot-on; 132 + regulator-max-microvolt = <1800000>; 133 + regulator-min-microvolt = <1800000>; 134 + regulator-name = "VDD_1V8 (BUCK5)"; 129 135 }; 130 136 131 137 buck6: BUCK6 { 132 - regulator-min-microvolt = <600000>; 133 - regulator-max-microvolt = <3400000>; 134 - regulator-boot-on; 135 138 regulator-always-on; 139 + regulator-boot-on; 140 + regulator-max-microvolt = <1155000>; 141 + regulator-min-microvolt = <1045000>; 142 + regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; 136 143 }; 137 144 138 145 ldo1: LDO1 { 139 - regulator-min-microvolt = <1600000>; 140 - regulator-max-microvolt = <3300000>; 141 - regulator-boot-on; 142 146 regulator-always-on; 143 - }; 144 - 145 - ldo2: LDO2 { 146 - regulator-min-microvolt = <800000>; 147 - regulator-max-microvolt = <1150000>; 148 147 regulator-boot-on; 149 - regulator-always-on; 148 + regulator-max-microvolt = <1950000>; 149 + regulator-min-microvolt = <1710000>; 150 + regulator-name = "NVCC_SNVS_1V8 (LDO1)"; 150 151 }; 151 152 152 153 ldo3: LDO3 { 153 - regulator-min-microvolt = <800000>; 154 - regulator-max-microvolt = <3300000>; 155 - regulator-boot-on; 156 154 regulator-always-on; 157 - }; 158 - 159 - ldo4: LDO4 { 160 - regulator-min-microvolt = <800000>; 161 - regulator-max-microvolt = <3300000>; 155 + regulator-boot-on; 156 + regulator-max-microvolt = <1800000>; 157 + regulator-min-microvolt = <1800000>; 158 + regulator-name = "VDDA_1V8 (LDO3)"; 162 159 }; 163 160 164 161 ldo5: LDO5 { 165 - regulator-min-microvolt = <1800000>; 166 - regulator-max-microvolt = <3300000>; 167 - regulator-boot-on; 168 162 regulator-always-on; 163 + regulator-boot-on; 164 + regulator-max-microvolt = <3300000>; 165 + regulator-min-microvolt = <1800000>; 166 + regulator-name = "NVCC_SD2 (LDO5)"; 169 167 }; 170 168 }; 171 169 }; ··· 202 208 &iomuxc { 203 209 pinctrl_fec: fecgrp { 204 210 fsl,pins = < 205 - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 206 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 207 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 208 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 209 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 210 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 211 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 212 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 211 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 212 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 213 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 214 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 215 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 216 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 217 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 213 218 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 214 219 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 215 220 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 216 221 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 217 222 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 218 223 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 219 - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 224 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 220 225 >; 221 226 }; 222 227 ··· 232 239 233 240 pinctrl_i2c1: i2c1grp { 234 241 fsl,pins = < 235 - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 236 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 242 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 243 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 237 244 >; 238 245 }; 239 246 240 247 pinctrl_i2c1_gpio: i2c1gpiogrp { 241 248 fsl,pins = < 242 - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 243 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 249 + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 250 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 244 251 >; 245 252 }; 246 253 247 254 pinctrl_pmic: pmicirqgrp { 248 255 fsl,pins = < 249 - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 256 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 250 257 >; 251 258 }; 252 259 253 260 pinctrl_usdhc3: usdhc3grp { 254 261 fsl,pins = < 255 - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 256 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 262 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 263 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 264 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 265 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 257 266 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 258 267 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 259 268 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 260 269 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 261 270 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 262 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 263 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 264 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 265 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 271 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 272 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 266 273 >; 267 274 }; 268 275 269 276 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 270 277 fsl,pins = < 271 - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 272 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 278 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 279 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 280 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 281 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 273 282 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 274 283 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 275 284 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 276 285 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 277 286 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 278 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 279 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 280 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 281 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 287 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 288 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 282 289 >; 283 290 }; 284 291 285 292 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 286 293 fsl,pins = < 287 - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 288 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 294 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 295 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 296 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 297 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 289 298 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 290 299 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 291 300 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 292 301 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 293 302 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 294 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 295 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 296 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 297 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 303 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 304 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 298 305 >; 299 306 }; 300 307

+19

arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp.dtsi" 9 + #include "imx8mp-venice-gw702x.dtsi" 10 + #include "imx8mp-venice-gw71xx.dtsi" 11 + 12 + / { 13 + model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit"; 14 + compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp"; 15 + 16 + chosen { 17 + stdout-path = &uart2; 18 + }; 19 + };

+236

arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include <dt-bindings/leds/common.h> 8 + #include <dt-bindings/phy/phy-imx8-pcie.h> 9 + 10 + / { 11 + led-controller { 12 + compatible = "gpio-leds"; 13 + pinctrl-names = "default"; 14 + pinctrl-0 = <&pinctrl_gpio_leds>; 15 + 16 + led-0 { 17 + function = LED_FUNCTION_STATUS; 18 + color = <LED_COLOR_ID_GREEN>; 19 + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 20 + default-state = "on"; 21 + linux,default-trigger = "heartbeat"; 22 + }; 23 + 24 + led-1 { 25 + function = LED_FUNCTION_STATUS; 26 + color = <LED_COLOR_ID_RED>; 27 + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 28 + default-state = "off"; 29 + }; 30 + }; 31 + 32 + pcie0_refclk: clock-pcie0 { 33 + compatible = "fixed-clock"; 34 + #clock-cells = <0>; 35 + clock-frequency = <100000000>; 36 + }; 37 + 38 + pps { 39 + compatible = "pps-gpio"; 40 + pinctrl-names = "default"; 41 + pinctrl-0 = <&pinctrl_pps>; 42 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 43 + status = "okay"; 44 + }; 45 + }; 46 + 47 + /* off-board header */ 48 + &ecspi2 { 49 + pinctrl-names = "default"; 50 + pinctrl-0 = <&pinctrl_spi2>; 51 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 52 + status = "okay"; 53 + }; 54 + 55 + &gpio4 { 56 + gpio-line-names = 57 + "", "", "", "", 58 + "", "", "", "", 59 + "dio1", "", "", "dio0", 60 + "", "", "pci_usb_sel", "", 61 + "", "", "", "", 62 + "", "", "", "", 63 + "dio3", "", "dio2", "", 64 + "pci_wdis#", "", "", ""; 65 + }; 66 + 67 + &i2c2 { 68 + clock-frequency = <400000>; 69 + pinctrl-names = "default"; 70 + pinctrl-0 = <&pinctrl_i2c2>; 71 + status = "okay"; 72 + 73 + accelerometer@19 { 74 + compatible = "st,lis2de12"; 75 + reg = <0x19>; 76 + pinctrl-names = "default"; 77 + pinctrl-0 = <&pinctrl_accel>; 78 + st,drdy-int-pin = <1>; 79 + interrupt-parent = <&gpio4>; 80 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 81 + interrupt-names = "INT1"; 82 + }; 83 + }; 84 + 85 + &pcie_phy { 86 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 87 + fsl,clkreq-unsupported; 88 + clocks = <&pcie0_refclk>; 89 + clock-names = "ref"; 90 + status = "okay"; 91 + }; 92 + 93 + &pcie { 94 + pinctrl-names = "default"; 95 + pinctrl-0 = <&pinctrl_pcie0>; 96 + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 97 + status = "okay"; 98 + }; 99 + 100 + /* GPS */ 101 + &uart1 { 102 + pinctrl-names = "default"; 103 + pinctrl-0 = <&pinctrl_uart1>; 104 + status = "okay"; 105 + }; 106 + 107 + /* off-board header */ 108 + &uart3 { 109 + pinctrl-names = "default"; 110 + pinctrl-0 = <&pinctrl_uart3>; 111 + status = "okay"; 112 + }; 113 + 114 + /* USB1 Type-C front panel */ 115 + &usb3_0 { 116 + pinctrl-names = "default"; 117 + pinctrl-0 = <&pinctrl_usb1>; 118 + fsl,over-current-active-low; 119 + status = "okay"; 120 + }; 121 + 122 + &usb3_phy0 { 123 + status = "okay"; 124 + }; 125 + 126 + &usb_dwc3_0 { 127 + /* dual role is implemented but not a full featured OTG */ 128 + adp-disable; 129 + hnp-disable; 130 + srp-disable; 131 + dr_mode = "otg"; 132 + usb-role-switch; 133 + role-switch-default-mode = "peripheral"; 134 + status = "okay"; 135 + 136 + connector { 137 + compatible = "gpio-usb-b-connector", "usb-b-connector"; 138 + pinctrl-names = "default"; 139 + pinctrl-0 = <&pinctrl_usbcon1>; 140 + type = "micro"; 141 + label = "Type-C"; 142 + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 143 + }; 144 + }; 145 + 146 + /* USB2 - MiniPCIe socket */ 147 + &usb3_1 { 148 + fsl,permanently-attached; 149 + fsl,disable-port-power-control; 150 + status = "okay"; 151 + }; 152 + 153 + &usb3_phy1 { 154 + status = "okay"; 155 + }; 156 + 157 + &usb_dwc3_1 { 158 + dr_mode = "host"; 159 + status = "okay"; 160 + }; 161 + 162 + &iomuxc { 163 + pinctrl-names = "default"; 164 + pinctrl-0 = <&pinctrl_hog>; 165 + 166 + pinctrl_hog: hoggrp { 167 + fsl,pins = < 168 + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 169 + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 170 + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ 171 + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */ 172 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */ 173 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ 174 + >; 175 + }; 176 + 177 + pinctrl_accel: accelgrp { 178 + fsl,pins = < 179 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ 180 + >; 181 + }; 182 + 183 + pinctrl_gpio_leds: gpioledgrp { 184 + fsl,pins = < 185 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 186 + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 187 + >; 188 + }; 189 + 190 + pinctrl_pcie0: pcie0grp { 191 + fsl,pins = < 192 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 193 + >; 194 + }; 195 + 196 + pinctrl_pps: ppsgrp { 197 + fsl,pins = < 198 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 199 + >; 200 + }; 201 + 202 + pinctrl_usb1: usb1grp { 203 + fsl,pins = < 204 + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ 205 + >; 206 + }; 207 + 208 + pinctrl_usbcon1: usbcon1grp { 209 + fsl,pins = < 210 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ 211 + >; 212 + }; 213 + 214 + pinctrl_spi2: spi2grp { 215 + fsl,pins = < 216 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 217 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 218 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 219 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 220 + >; 221 + }; 222 + 223 + pinctrl_uart1: uart1grp { 224 + fsl,pins = < 225 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 226 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 227 + >; 228 + }; 229 + 230 + pinctrl_uart3: uart3grp { 231 + fsl,pins = < 232 + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 233 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 234 + >; 235 + }; 236 + };

+19

arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp.dtsi" 9 + #include "imx8mp-venice-gw702x.dtsi" 10 + #include "imx8mp-venice-gw72xx.dtsi" 11 + 12 + / { 13 + model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit"; 14 + compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp"; 15 + 16 + chosen { 17 + stdout-path = &uart2; 18 + }; 19 + };

+371

arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include <dt-bindings/leds/common.h> 8 + #include <dt-bindings/phy/phy-imx8-pcie.h> 9 + 10 + / { 11 + led-controller { 12 + compatible = "gpio-leds"; 13 + pinctrl-names = "default"; 14 + pinctrl-0 = <&pinctrl_gpio_leds>; 15 + 16 + led-0 { 17 + function = LED_FUNCTION_STATUS; 18 + color = <LED_COLOR_ID_GREEN>; 19 + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 20 + default-state = "on"; 21 + linux,default-trigger = "heartbeat"; 22 + }; 23 + 24 + led-1 { 25 + function = LED_FUNCTION_STATUS; 26 + color = <LED_COLOR_ID_RED>; 27 + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 28 + default-state = "off"; 29 + }; 30 + }; 31 + 32 + pcie0_refclk: clock-pcie0 { 33 + compatible = "fixed-clock"; 34 + #clock-cells = <0>; 35 + clock-frequency = <100000000>; 36 + }; 37 + 38 + pps { 39 + compatible = "pps-gpio"; 40 + pinctrl-names = "default"; 41 + pinctrl-0 = <&pinctrl_pps>; 42 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 43 + status = "okay"; 44 + }; 45 + 46 + reg_usb1_vbus: regulator-usb1 { 47 + compatible = "regulator-fixed"; 48 + pinctrl-names = "default"; 49 + pinctrl-0 = <&pinctrl_reg_usb1_en>; 50 + regulator-name = "usb1_vbus"; 51 + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 52 + enable-active-high; 53 + regulator-min-microvolt = <5000000>; 54 + regulator-max-microvolt = <5000000>; 55 + }; 56 + 57 + reg_usb2_vbus: regulator-usb2 { 58 + compatible = "regulator-fixed"; 59 + pinctrl-names = "default"; 60 + pinctrl-0 = <&pinctrl_reg_usb2_en>; 61 + regulator-name = "usb2_vbus"; 62 + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 63 + enable-active-high; 64 + regulator-min-microvolt = <5000000>; 65 + regulator-max-microvolt = <5000000>; 66 + }; 67 + 68 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 69 + compatible = "regulator-fixed"; 70 + pinctrl-names = "default"; 71 + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 72 + regulator-name = "VDD_3V3_SD"; 73 + enable-active-high; 74 + gpio = <&gpio2 19 0>; /* SD2_RESET */ 75 + off-on-delay-us = <12000>; 76 + regulator-max-microvolt = <3300000>; 77 + regulator-min-microvolt = <3300000>; 78 + startup-delay-us = <100>; 79 + }; 80 + }; 81 + 82 + /* off-board header */ 83 + &ecspi2 { 84 + pinctrl-names = "default"; 85 + pinctrl-0 = <&pinctrl_spi2>; 86 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 87 + status = "okay"; 88 + }; 89 + 90 + &gpio4 { 91 + gpio-line-names = 92 + "", "", "", "", 93 + "", "", "", "", 94 + "dio1", "", "", "dio0", 95 + "", "", "pci_usb_sel", "", 96 + "", "", "", "", 97 + "", "", "rs485_en", "rs485_term", 98 + "", "", "", "rs485_half", 99 + "pci_wdis#", "", "", ""; 100 + }; 101 + 102 + &i2c2 { 103 + clock-frequency = <400000>; 104 + pinctrl-names = "default"; 105 + pinctrl-0 = <&pinctrl_i2c2>; 106 + status = "okay"; 107 + 108 + accelerometer@19 { 109 + compatible = "st,lis2de12"; 110 + reg = <0x19>; 111 + pinctrl-names = "default"; 112 + pinctrl-0 = <&pinctrl_accel>; 113 + st,drdy-int-pin = <1>; 114 + interrupt-parent = <&gpio4>; 115 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 116 + interrupt-names = "INT1"; 117 + }; 118 + }; 119 + 120 + &pcie_phy { 121 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 122 + fsl,clkreq-unsupported; 123 + clocks = <&pcie0_refclk>; 124 + clock-names = "ref"; 125 + status = "okay"; 126 + }; 127 + 128 + &pcie { 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pinctrl_pcie0>; 131 + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 132 + status = "okay"; 133 + }; 134 + 135 + /* GPS */ 136 + &uart1 { 137 + pinctrl-names = "default"; 138 + pinctrl-0 = <&pinctrl_uart1>; 139 + status = "okay"; 140 + }; 141 + 142 + /* off-board header */ 143 + &uart3 { 144 + pinctrl-names = "default"; 145 + pinctrl-0 = <&pinctrl_uart3>; 146 + status = "okay"; 147 + }; 148 + 149 + /* RS232 */ 150 + &uart4 { 151 + pinctrl-names = "default"; 152 + pinctrl-0 = <&pinctrl_uart4>; 153 + status = "okay"; 154 + }; 155 + 156 + /* USB1 - OTG */ 157 + &usb3_0 { 158 + pinctrl-names = "default"; 159 + pinctrl-0 = <&pinctrl_usb1>; 160 + fsl,over-current-active-low; 161 + status = "okay"; 162 + }; 163 + 164 + &usb3_phy0 { 165 + vbus-supply = <&reg_usb1_vbus>; 166 + status = "okay"; 167 + }; 168 + 169 + &usb_dwc3_0 { 170 + /* dual role is implemented but not a full featured OTG */ 171 + adp-disable; 172 + hnp-disable; 173 + srp-disable; 174 + dr_mode = "otg"; 175 + usb-role-switch; 176 + role-switch-default-mode = "peripheral"; 177 + status = "okay"; 178 + 179 + connector { 180 + compatible = "gpio-usb-b-connector", "usb-b-connector"; 181 + pinctrl-names = "default"; 182 + pinctrl-0 = <&pinctrl_usbcon1>; 183 + type = "micro"; 184 + label = "otg"; 185 + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 186 + }; 187 + }; 188 + 189 + /* USB2 - USB3.0 Hub */ 190 + &usb3_1 { 191 + fsl,permanently-attached; 192 + fsl,disable-port-power-control; 193 + status = "okay"; 194 + }; 195 + 196 + &usb3_phy1 { 197 + vbus-supply = <&reg_usb2_vbus>; 198 + status = "okay"; 199 + }; 200 + 201 + &usb_dwc3_1 { 202 + dr_mode = "host"; 203 + status = "okay"; 204 + }; 205 + 206 + /* microSD */ 207 + &usdhc2 { 208 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 209 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 210 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 211 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 212 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 213 + bus-width = <4>; 214 + vmmc-supply = <&reg_usdhc2_vmmc>; 215 + status = "okay"; 216 + }; 217 + 218 + &iomuxc { 219 + pinctrl-names = "default"; 220 + pinctrl-0 = <&pinctrl_hog>; 221 + 222 + pinctrl_hog: hoggrp { 223 + fsl,pins = < 224 + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 225 + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 226 + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ 227 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 228 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 229 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 230 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ 231 + >; 232 + }; 233 + 234 + pinctrl_accel: accelgrp { 235 + fsl,pins = < 236 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ 237 + >; 238 + }; 239 + 240 + pinctrl_gpio_leds: gpioledgrp { 241 + fsl,pins = < 242 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 243 + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 244 + >; 245 + }; 246 + 247 + pinctrl_pcie0: pcie0grp { 248 + fsl,pins = < 249 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 250 + >; 251 + }; 252 + 253 + pinctrl_pps: ppsgrp { 254 + fsl,pins = < 255 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 256 + >; 257 + }; 258 + 259 + pinctrl_reg_usb1_en: regusb1grp { 260 + fsl,pins = < 261 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ 262 + >; 263 + }; 264 + 265 + pinctrl_usb1: usb1grp { 266 + fsl,pins = < 267 + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ 268 + >; 269 + }; 270 + 271 + pinctrl_usbcon1: usbcon1grp { 272 + fsl,pins = < 273 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ 274 + >; 275 + }; 276 + 277 + pinctrl_reg_usb2_en: regusb2grp { 278 + fsl,pins = < 279 + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 280 + >; 281 + }; 282 + 283 + pinctrl_spi2: spi2grp { 284 + fsl,pins = < 285 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 286 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 287 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 288 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 289 + >; 290 + }; 291 + 292 + pinctrl_uart1: uart1grp { 293 + fsl,pins = < 294 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 295 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 296 + >; 297 + }; 298 + 299 + pinctrl_uart3: uart3grp { 300 + fsl,pins = < 301 + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 302 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 303 + >; 304 + }; 305 + 306 + pinctrl_uart4: uart4grp { 307 + fsl,pins = < 308 + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 309 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 310 + >; 311 + }; 312 + 313 + pinctrl_usdhc1: usdhc1grp { 314 + fsl,pins = < 315 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 316 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 317 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 318 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 319 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 320 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 321 + >; 322 + }; 323 + 324 + pinctrl_usdhc2: usdhc2grp { 325 + fsl,pins = < 326 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 327 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 328 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 329 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 330 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 331 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 332 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 333 + >; 334 + }; 335 + 336 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 337 + fsl,pins = < 338 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 339 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 340 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 341 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 342 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 343 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 344 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 345 + >; 346 + }; 347 + 348 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 349 + fsl,pins = < 350 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 351 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 352 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 353 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 354 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 355 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 356 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 357 + >; 358 + }; 359 + 360 + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 361 + fsl,pins = < 362 + MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 363 + >; 364 + }; 365 + 366 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 367 + fsl,pins = < 368 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 369 + >; 370 + }; 371 + };

+19

arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp.dtsi" 9 + #include "imx8mp-venice-gw702x.dtsi" 10 + #include "imx8mp-venice-gw73xx.dtsi" 11 + 12 + / { 13 + model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit"; 14 + compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp"; 15 + 16 + chosen { 17 + stdout-path = &uart2; 18 + }; 19 + };

+414

arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include <dt-bindings/leds/common.h> 8 + #include <dt-bindings/phy/phy-imx8-pcie.h> 9 + 10 + / { 11 + led-controller { 12 + compatible = "gpio-leds"; 13 + pinctrl-names = "default"; 14 + pinctrl-0 = <&pinctrl_gpio_leds>; 15 + 16 + led-0 { 17 + function = LED_FUNCTION_STATUS; 18 + color = <LED_COLOR_ID_GREEN>; 19 + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 20 + default-state = "on"; 21 + linux,default-trigger = "heartbeat"; 22 + }; 23 + 24 + led-1 { 25 + function = LED_FUNCTION_STATUS; 26 + color = <LED_COLOR_ID_RED>; 27 + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 28 + default-state = "off"; 29 + }; 30 + }; 31 + 32 + pcie0_refclk: clock-pcie0 { 33 + compatible = "fixed-clock"; 34 + #clock-cells = <0>; 35 + clock-frequency = <100000000>; 36 + }; 37 + 38 + pps { 39 + compatible = "pps-gpio"; 40 + pinctrl-names = "default"; 41 + pinctrl-0 = <&pinctrl_pps>; 42 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 43 + status = "okay"; 44 + }; 45 + 46 + reg_usb1_vbus: regulator-usb1 { 47 + compatible = "regulator-fixed"; 48 + pinctrl-names = "default"; 49 + pinctrl-0 = <&pinctrl_reg_usb1_en>; 50 + regulator-name = "usb1_vbus"; 51 + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 52 + enable-active-high; 53 + regulator-min-microvolt = <5000000>; 54 + regulator-max-microvolt = <5000000>; 55 + }; 56 + 57 + reg_usb2_vbus: regulator-usb2 { 58 + compatible = "regulator-fixed"; 59 + pinctrl-names = "default"; 60 + pinctrl-0 = <&pinctrl_reg_usb2_en>; 61 + regulator-name = "usb2_vbus"; 62 + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 63 + enable-active-high; 64 + regulator-min-microvolt = <5000000>; 65 + regulator-max-microvolt = <5000000>; 66 + }; 67 + 68 + reg_wifi_en: regulator-wifi-en { 69 + compatible = "regulator-fixed"; 70 + pinctrl-names = "default"; 71 + pinctrl-0 = <&pinctrl_reg_wl>; 72 + regulator-name = "wl"; 73 + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; 74 + startup-delay-us = <100>; 75 + enable-active-high; 76 + regulator-min-microvolt = <3300000>; 77 + regulator-max-microvolt = <3300000>; 78 + }; 79 + 80 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 81 + compatible = "regulator-fixed"; 82 + pinctrl-names = "default"; 83 + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 84 + regulator-name = "VDD_3V3_SD"; 85 + enable-active-high; 86 + gpio = <&gpio2 19 0>; /* SD2_RESET */ 87 + off-on-delay-us = <12000>; 88 + regulator-max-microvolt = <3300000>; 89 + regulator-min-microvolt = <3300000>; 90 + startup-delay-us = <100>; 91 + }; 92 + }; 93 + 94 + /* off-board header */ 95 + &ecspi2 { 96 + pinctrl-names = "default"; 97 + pinctrl-0 = <&pinctrl_spi2>; 98 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 99 + status = "okay"; 100 + }; 101 + 102 + &gpio4 { 103 + gpio-line-names = 104 + "", "", "", "", 105 + "", "", "", "", 106 + "dio1", "", "", "dio0", 107 + "", "", "pci_usb_sel", "", 108 + "", "", "", "", 109 + "", "", "rs485_en", "rs485_term", 110 + "", "", "", "rs485_half", 111 + "pci_wdis#", "", "", ""; 112 + }; 113 + 114 + &i2c2 { 115 + clock-frequency = <400000>; 116 + pinctrl-names = "default"; 117 + pinctrl-0 = <&pinctrl_i2c2>; 118 + status = "okay"; 119 + 120 + accelerometer@19 { 121 + compatible = "st,lis2de12"; 122 + reg = <0x19>; 123 + pinctrl-names = "default"; 124 + pinctrl-0 = <&pinctrl_accel>; 125 + st,drdy-int-pin = <1>; 126 + interrupt-parent = <&gpio4>; 127 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 128 + interrupt-names = "INT1"; 129 + }; 130 + }; 131 + 132 + &pcie_phy { 133 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 134 + fsl,clkreq-unsupported; 135 + clocks = <&pcie0_refclk>; 136 + clock-names = "ref"; 137 + status = "okay"; 138 + }; 139 + 140 + &pcie { 141 + pinctrl-names = "default"; 142 + pinctrl-0 = <&pinctrl_pcie0>; 143 + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 144 + status = "okay"; 145 + }; 146 + 147 + /* GPS */ 148 + &uart1 { 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&pinctrl_uart1>; 151 + status = "okay"; 152 + }; 153 + 154 + /* bluetooth HCI */ 155 + &uart3 { 156 + pinctrl-names = "default"; 157 + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; 158 + cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 159 + rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 160 + status = "okay"; 161 + 162 + bluetooth { 163 + compatible = "brcm,bcm4330-bt"; 164 + shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 165 + }; 166 + }; 167 + 168 + /* RS232 */ 169 + &uart4 { 170 + pinctrl-names = "default"; 171 + pinctrl-0 = <&pinctrl_uart4>; 172 + status = "okay"; 173 + }; 174 + 175 + /* USB1 - OTG */ 176 + &usb3_0 { 177 + pinctrl-names = "default"; 178 + pinctrl-0 = <&pinctrl_usb1>; 179 + fsl,over-current-active-low; 180 + status = "okay"; 181 + }; 182 + 183 + &usb3_phy0 { 184 + vbus-supply = <&reg_usb1_vbus>; 185 + status = "okay"; 186 + }; 187 + 188 + &usb_dwc3_0 { 189 + /* dual role is implemented but not a full featured OTG */ 190 + adp-disable; 191 + hnp-disable; 192 + srp-disable; 193 + dr_mode = "otg"; 194 + usb-role-switch; 195 + role-switch-default-mode = "peripheral"; 196 + status = "okay"; 197 + 198 + connector { 199 + compatible = "gpio-usb-b-connector", "usb-b-connector"; 200 + pinctrl-names = "default"; 201 + pinctrl-0 = <&pinctrl_usbcon1>; 202 + type = "micro"; 203 + label = "otg"; 204 + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 205 + }; 206 + }; 207 + 208 + /* USB2 - USB3.0 Hub */ 209 + &usb3_1 { 210 + fsl,permanently-attached; 211 + fsl,disable-port-power-control; 212 + status = "okay"; 213 + }; 214 + 215 + &usb3_phy1 { 216 + vbus-supply = <&reg_usb2_vbus>; 217 + status = "okay"; 218 + }; 219 + 220 + &usb_dwc3_1 { 221 + dr_mode = "host"; 222 + status = "okay"; 223 + }; 224 + 225 + /* SDIO WiFi */ 226 + &usdhc1 { 227 + pinctrl-names = "default"; 228 + pinctrl-0 = <&pinctrl_usdhc1>; 229 + bus-width = <4>; 230 + non-removable; 231 + vmmc-supply = <&reg_wifi_en>; 232 + status = "okay"; 233 + }; 234 + 235 + /* microSD */ 236 + &usdhc2 { 237 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 238 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 239 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 240 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 241 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 242 + bus-width = <4>; 243 + vmmc-supply = <&reg_usdhc2_vmmc>; 244 + status = "okay"; 245 + }; 246 + 247 + &iomuxc { 248 + pinctrl-names = "default"; 249 + pinctrl-0 = <&pinctrl_hog>; 250 + 251 + pinctrl_hog: hoggrp { 252 + fsl,pins = < 253 + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 254 + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 255 + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ 256 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 257 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 258 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 259 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ 260 + >; 261 + }; 262 + 263 + pinctrl_accel: accelgrp { 264 + fsl,pins = < 265 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ 266 + >; 267 + }; 268 + 269 + pinctrl_bten: btengrp { 270 + fsl,pins = < 271 + MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 272 + >; 273 + }; 274 + 275 + pinctrl_gpio_leds: gpioledgrp { 276 + fsl,pins = < 277 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 278 + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 279 + >; 280 + }; 281 + 282 + pinctrl_pcie0: pcie0grp { 283 + fsl,pins = < 284 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 285 + >; 286 + }; 287 + 288 + pinctrl_pps: ppsgrp { 289 + fsl,pins = < 290 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 291 + >; 292 + }; 293 + 294 + pinctrl_reg_wl: regwlgrp { 295 + fsl,pins = < 296 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 297 + >; 298 + }; 299 + 300 + pinctrl_reg_usb1_en: regusb1grp { 301 + fsl,pins = < 302 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ 303 + >; 304 + }; 305 + 306 + pinctrl_usb1: usb1grp { 307 + fsl,pins = < 308 + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ 309 + >; 310 + }; 311 + 312 + pinctrl_usbcon1: usbcon1grp { 313 + fsl,pins = < 314 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ 315 + >; 316 + }; 317 + 318 + pinctrl_reg_usb2_en: regusb2grp { 319 + fsl,pins = < 320 + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 321 + >; 322 + }; 323 + 324 + pinctrl_spi2: spi2grp { 325 + fsl,pins = < 326 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 327 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 328 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 329 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 330 + >; 331 + }; 332 + 333 + pinctrl_uart1: uart1grp { 334 + fsl,pins = < 335 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 336 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 337 + >; 338 + }; 339 + 340 + pinctrl_uart3: uart3grp { 341 + fsl,pins = < 342 + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 343 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 344 + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 345 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 346 + >; 347 + }; 348 + 349 + pinctrl_uart4: uart4grp { 350 + fsl,pins = < 351 + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 352 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 353 + >; 354 + }; 355 + 356 + pinctrl_usdhc1: usdhc1grp { 357 + fsl,pins = < 358 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 359 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 360 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 361 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 362 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 363 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 364 + >; 365 + }; 366 + 367 + pinctrl_usdhc2: usdhc2grp { 368 + fsl,pins = < 369 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 370 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 371 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 372 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 373 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 374 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 375 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 376 + >; 377 + }; 378 + 379 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 380 + fsl,pins = < 381 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 382 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 383 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 384 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 385 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 386 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 387 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 388 + >; 389 + }; 390 + 391 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 392 + fsl,pins = < 393 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 394 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 395 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 396 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 397 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 398 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 399 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 400 + >; 401 + }; 402 + 403 + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 404 + fsl,pins = < 405 + MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 406 + >; 407 + }; 408 + 409 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 410 + fsl,pins = < 411 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 412 + >; 413 + }; 414 + };

+87

arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Gateworks Corporation 4 + */ 5 + 6 + /dts-v1/; 7 + /plugin/; 8 + 9 + &{/} { 10 + compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; 11 + 12 + panel { 13 + compatible = "powertip,ph800480t013-idf02"; 14 + power-supply = <&attiny>; 15 + backlight = <&attiny>; 16 + 17 + port { 18 + panel_in: endpoint { 19 + remote-endpoint = <&bridge_out>; 20 + }; 21 + }; 22 + }; 23 + }; 24 + 25 + &i2c4 { 26 + #address-cells = <1>; 27 + #size-cells = <0>; 28 + 29 + attiny: regulator@45 { 30 + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; 31 + reg = <0x45>; 32 + }; 33 + }; 34 + 35 + &lcdif1 { 36 + status = "okay"; 37 + }; 38 + 39 + &mipi_dsi { 40 + samsung,burst-clock-frequency = <891000000>; 41 + samsung,esc-clock-frequency = <54000000>; 42 + samsung,pll-clock-frequency = <27000000>; 43 + #address-cells = <1>; 44 + #size-cells = <0>; 45 + status = "okay"; 46 + 47 + bridge@0 { 48 + compatible = "toshiba,tc358762"; 49 + reg = <0>; 50 + vddc-supply = <&attiny>; 51 + 52 + ports { 53 + #address-cells = <1>; 54 + #size-cells = <0>; 55 + 56 + port@0 { 57 + reg = <0>; 58 + 59 + bridge_in: endpoint { 60 + remote-endpoint = <&dsi_out>; 61 + }; 62 + }; 63 + 64 + port@1 { 65 + reg = <1>; 66 + 67 + bridge_out: endpoint { 68 + remote-endpoint = <&panel_in>; 69 + }; 70 + }; 71 + }; 72 + }; 73 + 74 + ports { 75 + #address-cells = <1>; 76 + #size-cells = <0>; 77 + 78 + port@1 { 79 + reg = <1>; 80 + 81 + dsi_out: endpoint { 82 + data-lanes = <1 2>; 83 + remote-endpoint = <&bridge_in>; 84 + }; 85 + }; 86 + }; 87 + };

+163 -104

arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts

··· 125 125 regulator-max-microvolt = <5000000>; 126 126 }; 127 127 128 + reg_can1_stby: regulator-can1-stby { 129 + compatible = "regulator-fixed"; 130 + pinctrl-names = "default"; 131 + pinctrl-0 = <&pinctrl_reg_can1>; 132 + regulator-name = "can1_stby"; 133 + gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 134 + regulator-min-microvolt = <3300000>; 135 + regulator-max-microvolt = <3300000>; 136 + }; 137 + 128 138 reg_can2_stby: regulator-can2-stby { 129 139 compatible = "regulator-fixed"; 130 140 pinctrl-names = "default"; 131 - pinctrl-0 = <&pinctrl_reg_can>; 141 + pinctrl-0 = <&pinctrl_reg_can2>; 132 142 regulator-name = "can2_stby"; 133 - gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 143 + gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; 134 144 regulator-min-microvolt = <3300000>; 135 145 regulator-max-microvolt = <3300000>; 136 146 }; ··· 172 162 173 163 &A53_3 { 174 164 cpu-supply = <&reg_arm>; 165 + }; 166 + 167 + &ecspi1 { 168 + pinctrl-names = "default"; 169 + pinctrl-0 = <&pinctrl_spi1>; 170 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 171 + status = "okay"; 172 + 173 + tpm@0 { 174 + compatible = "tcg,tpm_tis-spi"; 175 + #address-cells = <0x1>; 176 + #size-cells = <0x1>; 177 + reg = <0x0>; 178 + spi-max-frequency = <36000000>; 179 + }; 175 180 }; 176 181 177 182 /* off-board header */ ··· 229 204 }; 230 205 }; 231 206 207 + &flexcan1 { 208 + pinctrl-names = "default"; 209 + pinctrl-0 = <&pinctrl_flexcan1>; 210 + xceiver-supply = <&reg_can1_stby>; 211 + status = "okay"; 212 + }; 213 + 232 214 &flexcan2 { 233 215 pinctrl-names = "default"; 234 216 pinctrl-0 = <&pinctrl_flexcan2>; ··· 246 214 &gpio1 { 247 215 gpio-line-names = 248 216 "", "", "", "", "", "", "", "", 249 - "", "", "dio0", "", "dio1", "", "", "", 217 + "", "dio0", "", "dio1", "", "", "", "", 250 218 "", "", "", "", "", "", "", "", 251 219 "", "", "", "", "", "", "", ""; 252 220 }; 253 221 254 222 &gpio2 { 255 223 gpio-line-names = 256 - "", "", "", "", "", "", "", "", 257 - "", "", "", "", "", "", "pcie3_wdis#", "", 224 + "", "", "", "", "", "", "m2_pin20", "", 225 + "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", 258 226 "", "", "pcie2_wdis#", "", "", "", "", "", 259 227 "", "", "", "", "", "", "", ""; 260 228 }; 261 229 262 230 &gpio3 { 263 231 gpio-line-names = 264 - "m2_gdis#", "", "", "", "", "", "", "m2_rst#", 232 + "", "", "", "", "", "", "m2_rst", "", 265 233 "", "", "", "", "", "", "", "", 266 - "m2_off#", "", "", "", "", "", "", "", 234 + "", "", "", "", "", "", "", "", 267 235 "", "", "", "", "", "", "", ""; 268 236 }; 269 237 270 238 &gpio4 { 271 239 gpio-line-names = 240 + "", "", "m2_off#", "", "", "", "", "", 272 241 "", "", "", "", "", "", "", "", 273 - "", "", "", "", "", "", "", "", 274 - "", "", "", "", "m2_wdis#", "", "", "", 275 - "", "", "", "", "", "", "", "uart_rs485"; 242 + "", "", "m2_wdis#", "", "", "", "", "", 243 + "", "", "", "", "", "", "", "rs485_en"; 276 244 }; 277 245 278 246 &gpio5 { 279 247 gpio-line-names = 280 - "uart_half", "uart_term", "", "", "", "", "", "", 248 + "rs485_hd", "rs485_term", "", "", "", "", "", "", 281 249 "", "", "", "", "", "", "", "", 282 250 "", "", "", "", "", "", "", "", 283 251 "", "", "", "", "", "", "", ""; ··· 300 268 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 301 269 interrupt-controller; 302 270 #interrupt-cells = <1>; 271 + #address-cells = <1>; 272 + #size-cells = <0>; 303 273 304 274 adc { 305 275 compatible = "gw,gsc-adc"; ··· 318 284 gw,mode = <3>; 319 285 reg = <0x08>; 320 286 label = "vdd_bat"; 287 + }; 288 + 289 + channel@16 { 290 + gw,mode = <4>; 291 + reg = <0x16>; 292 + label = "fan_tach"; 321 293 }; 322 294 323 295 channel@82 { ··· 398 358 gw,voltage-divider-ohms = <10000 10000>; 399 359 }; 400 360 }; 361 + 362 + fan-controller@a { 363 + compatible = "gw,gsc-fan"; 364 + reg = <0x0a>; 365 + }; 401 366 }; 402 367 403 368 gpio: gpio@23 { ··· 412 367 #gpio-cells = <2>; 413 368 interrupt-parent = <&gsc>; 414 369 interrupts = <4>; 415 - }; 416 - 417 - pmic@25 { 418 - compatible = "nxp,pca9450c"; 419 - reg = <0x25>; 420 - pinctrl-names = "default"; 421 - pinctrl-0 = <&pinctrl_pmic>; 422 - interrupt-parent = <&gpio3>; 423 - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 424 - 425 - regulators { 426 - BUCK1 { 427 - regulator-name = "BUCK1"; 428 - regulator-min-microvolt = <720000>; 429 - regulator-max-microvolt = <1000000>; 430 - regulator-boot-on; 431 - regulator-always-on; 432 - regulator-ramp-delay = <3125>; 433 - }; 434 - 435 - reg_arm: BUCK2 { 436 - regulator-name = "BUCK2"; 437 - regulator-min-microvolt = <720000>; 438 - regulator-max-microvolt = <1025000>; 439 - regulator-boot-on; 440 - regulator-always-on; 441 - regulator-ramp-delay = <3125>; 442 - nxp,dvs-run-voltage = <950000>; 443 - nxp,dvs-standby-voltage = <850000>; 444 - }; 445 - 446 - BUCK4 { 447 - regulator-name = "BUCK4"; 448 - regulator-min-microvolt = <3000000>; 449 - regulator-max-microvolt = <3600000>; 450 - regulator-boot-on; 451 - regulator-always-on; 452 - }; 453 - 454 - BUCK5 { 455 - regulator-name = "BUCK5"; 456 - regulator-min-microvolt = <1650000>; 457 - regulator-max-microvolt = <1950000>; 458 - regulator-boot-on; 459 - regulator-always-on; 460 - }; 461 - 462 - BUCK6 { 463 - regulator-name = "BUCK6"; 464 - regulator-min-microvolt = <1045000>; 465 - regulator-max-microvolt = <1155000>; 466 - regulator-boot-on; 467 - regulator-always-on; 468 - }; 469 - 470 - LDO1 { 471 - regulator-name = "LDO1"; 472 - regulator-min-microvolt = <1650000>; 473 - regulator-max-microvolt = <1950000>; 474 - regulator-boot-on; 475 - regulator-always-on; 476 - }; 477 - 478 - LDO3 { 479 - regulator-name = "LDO3"; 480 - regulator-min-microvolt = <1710000>; 481 - regulator-max-microvolt = <1890000>; 482 - regulator-boot-on; 483 - regulator-always-on; 484 - }; 485 - 486 - LDO5 { 487 - regulator-name = "LDO5"; 488 - regulator-min-microvolt = <1800000>; 489 - regulator-max-microvolt = <3300000>; 490 - regulator-boot-on; 491 - regulator-always-on; 492 - }; 493 - }; 494 370 }; 495 371 496 372 eeprom@50 { ··· 525 559 }; 526 560 }; 527 561 528 - /* off-board header */ 529 562 &i2c3 { 530 563 clock-frequency = <400000>; 531 564 pinctrl-names = "default", "gpio"; ··· 533 568 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 534 569 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 535 570 status = "okay"; 571 + 572 + pmic@25 { 573 + compatible = "nxp,pca9450c"; 574 + reg = <0x25>; 575 + pinctrl-names = "default"; 576 + pinctrl-0 = <&pinctrl_pmic>; 577 + interrupt-parent = <&gpio3>; 578 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 579 + 580 + regulators { 581 + BUCK1 { 582 + regulator-name = "BUCK1"; 583 + regulator-min-microvolt = <720000>; 584 + regulator-max-microvolt = <1000000>; 585 + regulator-boot-on; 586 + regulator-always-on; 587 + regulator-ramp-delay = <3125>; 588 + }; 589 + 590 + reg_arm: BUCK2 { 591 + regulator-name = "BUCK2"; 592 + regulator-min-microvolt = <720000>; 593 + regulator-max-microvolt = <1025000>; 594 + regulator-boot-on; 595 + regulator-always-on; 596 + regulator-ramp-delay = <3125>; 597 + nxp,dvs-run-voltage = <950000>; 598 + nxp,dvs-standby-voltage = <850000>; 599 + }; 600 + 601 + BUCK4 { 602 + regulator-name = "BUCK4"; 603 + regulator-min-microvolt = <3000000>; 604 + regulator-max-microvolt = <3600000>; 605 + regulator-boot-on; 606 + regulator-always-on; 607 + }; 608 + 609 + BUCK5 { 610 + regulator-name = "BUCK5"; 611 + regulator-min-microvolt = <1650000>; 612 + regulator-max-microvolt = <1950000>; 613 + regulator-boot-on; 614 + regulator-always-on; 615 + }; 616 + 617 + BUCK6 { 618 + regulator-name = "BUCK6"; 619 + regulator-min-microvolt = <1045000>; 620 + regulator-max-microvolt = <1155000>; 621 + regulator-boot-on; 622 + regulator-always-on; 623 + }; 624 + 625 + LDO1 { 626 + regulator-name = "LDO1"; 627 + regulator-min-microvolt = <1650000>; 628 + regulator-max-microvolt = <1950000>; 629 + regulator-boot-on; 630 + regulator-always-on; 631 + }; 632 + 633 + LDO3 { 634 + regulator-name = "LDO3"; 635 + regulator-min-microvolt = <1710000>; 636 + regulator-max-microvolt = <1890000>; 637 + regulator-boot-on; 638 + regulator-always-on; 639 + }; 640 + 641 + LDO5 { 642 + regulator-name = "LDO5"; 643 + regulator-min-microvolt = <1800000>; 644 + regulator-max-microvolt = <3300000>; 645 + regulator-boot-on; 646 + regulator-always-on; 647 + }; 648 + }; 649 + }; 536 650 }; 537 651 538 652 /* off-board header */ ··· 737 693 status = "okay"; 738 694 739 695 wifi@0 { 740 - compatible = "cypress,cyw4373-fmac"; 696 + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 741 697 reg = <0>; 742 698 }; 743 699 }; ··· 770 726 fsl,pins = < 771 727 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ 772 728 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ 773 - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ 774 - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 775 - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 776 - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 729 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ 777 730 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ 778 - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ 731 + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ 732 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ 733 + MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ 734 + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 735 + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 736 + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 779 737 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 780 738 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 781 739 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ ··· 827 781 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 828 782 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 829 783 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 784 + >; 785 + }; 786 + 787 + pinctrl_flexcan1: flexcan1grp { 788 + fsl,pins = < 789 + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 790 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 830 791 >; 831 792 }; 832 793 ··· 922 869 923 870 pinctrl_pcie0: pciegrp { 924 871 fsl,pins = < 925 - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 872 + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 926 873 >; 927 874 }; 928 875 ··· 938 885 >; 939 886 }; 940 887 941 - pinctrl_reg_can: regcangrp { 888 + pinctrl_reg_can1: regcan1grp { 942 889 fsl,pins = < 943 890 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 891 + >; 892 + }; 893 + 894 + pinctrl_reg_can2: regcan2grp { 895 + fsl,pins = < 896 + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 944 897 >; 945 898 }; 946 899 ··· 962 903 >; 963 904 }; 964 905 965 - pinctrl_sai2: sai2grp { 906 + pinctrl_spi1: spi1grp { 966 907 fsl,pins = < 967 - MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 968 - MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 969 - MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 970 - MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 908 + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 909 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 910 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 911 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 971 912 >; 972 913 }; 973 914

+53 -3

arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi

··· 3 3 * Copyright 2022 Toradex 4 4 */ 5 5 6 - /* TODO: Audio Codec */ 6 + / { 7 + sound { 8 + compatible = "simple-audio-card"; 9 + simple-audio-card,bitclock-master = <&codec_dai>; 10 + simple-audio-card,format = "i2s"; 11 + simple-audio-card,frame-master = <&codec_dai>; 12 + simple-audio-card,mclk-fs = <256>; 13 + simple-audio-card,name = "imx8mp-wm8904"; 14 + simple-audio-card,routing = 15 + "Headphone Jack", "HPOUTL", 16 + "Headphone Jack", "HPOUTR", 17 + "IN2L", "Line In Jack", 18 + "IN2R", "Line In Jack", 19 + "Headphone Jack", "MICBIAS", 20 + "IN1L", "Headphone Jack"; 21 + simple-audio-card,widgets = 22 + "Microphone", "Headphone Jack", 23 + "Headphone", "Headphone Jack", 24 + "Line", "Line In Jack"; 25 + 26 + codec_dai: simple-audio-card,codec { 27 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; 28 + sound-dai = <&wm8904_1a>; 29 + }; 30 + 31 + simple-audio-card,cpu { 32 + sound-dai = <&sai1>; 33 + }; 34 + }; 35 + }; 7 36 8 37 &backlight { 9 38 power-supply = <&reg_3p3v>; ··· 93 64 &i2c4 { 94 65 status = "okay"; 95 66 96 - /* TODO: Audio Codec */ 67 + /* Audio Codec */ 68 + wm8904_1a: audio-codec@1a { 69 + compatible = "wlf,wm8904"; 70 + reg = <0x1a>; 71 + pinctrl-names = "default"; 72 + pinctrl-0 = <&pinctrl_sai1>; 73 + #sound-dai-cells = <0>; 74 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; 75 + clock-names = "mclk"; 76 + AVDD-supply = <&reg_1p8v>; 77 + CPVDD-supply = <&reg_1p8v>; 78 + DBVDD-supply = <&reg_1p8v>; 79 + DCVDD-supply = <&reg_1p8v>; 80 + MICVDD-supply = <&reg_1p8v>; 81 + }; 97 82 }; 98 83 99 84 /* Verdin PCIE_1 */ ··· 138 95 vin-supply = <&reg_3p3v>; 139 96 }; 140 97 141 - /* TODO: Verdin I2S_1 */ 98 + /* Verdin I2S_1 */ 99 + &sai1 { 100 + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; 101 + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 102 + assigned-clock-rates = <24576000>; 103 + fsl,sai-mclk-direction-output; 104 + status = "okay"; 105 + }; 142 106 143 107 /* Verdin UART_1 */ 144 108 &uart1 {

+51 -4

arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi

··· 4 4 */ 5 5 6 6 / { 7 - /* TODO: Audio Codec */ 8 - 9 7 reg_eth2phy: regulator-eth2phy { 10 8 compatible = "regulator-fixed"; 11 9 enable-active-high; ··· 14 16 regulator-name = "+V3.3_ETH"; 15 17 startup-delay-us = <200000>; 16 18 vin-supply = <&reg_3p3v>; 19 + }; 20 + 21 + sound { 22 + compatible = "simple-audio-card"; 23 + simple-audio-card,bitclock-master = <&codec_dai>; 24 + simple-audio-card,format = "i2s"; 25 + simple-audio-card,frame-master = <&codec_dai>; 26 + simple-audio-card,mclk-fs = <256>; 27 + simple-audio-card,name = "imx8mp-nau8822"; 28 + simple-audio-card,routing = 29 + "Headphones", "LHP", 30 + "Headphones", "RHP", 31 + "Speaker", "LSPK", 32 + "Speaker", "RSPK", 33 + "Line Out", "AUXOUT1", 34 + "Line Out", "AUXOUT2", 35 + "LAUX", "Line In", 36 + "RAUX", "Line In", 37 + "LMICP", "Mic In", 38 + "RMICP", "Mic In"; 39 + simple-audio-card,widgets = 40 + "Headphones", "Headphones", 41 + "Line Out", "Line Out", 42 + "Speaker", "Speaker", 43 + "Microphone", "Mic In", 44 + "Line", "Line In"; 45 + 46 + codec_dai: simple-audio-card,codec { 47 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; 48 + sound-dai = <&nau8822_1a>; 49 + }; 50 + 51 + simple-audio-card,cpu { 52 + sound-dai = <&sai1>; 53 + }; 17 54 }; 18 55 }; 19 56 ··· 121 88 &i2c4 { 122 89 status = "okay"; 123 90 124 - /* TODO: Audio Codec */ 91 + /* Audio Codec */ 92 + nau8822_1a: audio-codec@1a { 93 + compatible = "nuvoton,nau8822"; 94 + reg = <0x1a>; 95 + pinctrl-names = "default"; 96 + pinctrl-0 = <&pinctrl_sai1>; 97 + #sound-dai-cells = <0>; 98 + }; 125 99 }; 126 100 127 101 /* Verdin PCIE_1 */ ··· 159 119 vin-supply = <&reg_3p3v>; 160 120 }; 161 121 162 - /* TODO: Verdin I2C_1 with Audio Codec */ 122 + /* Verdin I2S_1 */ 123 + &sai1 { 124 + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; 125 + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 126 + assigned-clock-rates = <24576000>; 127 + fsl,sai-mclk-direction-output; 128 + status = "okay"; 129 + }; 163 130 164 131 /* Verdin UART_1, connector X50 through RS485 transceiver */ 165 132 &uart1 {

+8 -12

arch/arm64/boot/dts/freescale/imx8mp.dtsi

··· 306 306 307 307 etm0: etm@28440000 { 308 308 compatible = "arm,coresight-etm4x", "arm,primecell"; 309 - reg = <0x28440000 0x10000>; 310 - arm,primecell-periphid = <0xbb95d>; 309 + reg = <0x28440000 0x1000>; 311 310 cpu = <&A53_0>; 312 311 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 313 312 clock-names = "apb_pclk"; ··· 322 323 323 324 etm1: etm@28540000 { 324 325 compatible = "arm,coresight-etm4x", "arm,primecell"; 325 - reg = <0x28540000 0x10000>; 326 - arm,primecell-periphid = <0xbb95d>; 326 + reg = <0x28540000 0x1000>; 327 327 cpu = <&A53_1>; 328 328 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 329 329 clock-names = "apb_pclk"; ··· 338 340 339 341 etm2: etm@28640000 { 340 342 compatible = "arm,coresight-etm4x", "arm,primecell"; 341 - reg = <0x28640000 0x10000>; 342 - arm,primecell-periphid = <0xbb95d>; 343 + reg = <0x28640000 0x1000>; 343 344 cpu = <&A53_2>; 344 345 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 345 346 clock-names = "apb_pclk"; ··· 354 357 355 358 etm3: etm@28740000 { 356 359 compatible = "arm,coresight-etm4x", "arm,primecell"; 357 - reg = <0x28740000 0x10000>; 358 - arm,primecell-periphid = <0xbb95d>; 360 + reg = <0x28740000 0x1000>; 359 361 cpu = <&A53_3>; 360 362 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 361 363 clock-names = "apb_pclk"; ··· 697 701 698 702 snvs_rtc: snvs-rtc-lp { 699 703 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 700 - regmap =<&snvs>; 704 + regmap = <&snvs>; 701 705 offset = <0x34>; 702 706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 703 707 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; ··· 850 854 pgc_vpumix: power-domain@19 { 851 855 #power-domain-cells = <0>; 852 856 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 853 - clocks =<&clk IMX8MP_CLK_VPU_ROOT>; 857 + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 854 858 }; 855 859 856 860 pgc_vpu_g1: power-domain@20 { ··· 1842 1846 #size-cells = <2>; 1843 1847 device_type = "pci"; 1844 1848 bus-range = <0x00 0xff>; 1845 - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1846 - <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1849 + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1850 + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1847 1851 num-lanes = <1>; 1848 1852 num-viewport = <4>; 1849 1853 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

+14 -18

arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts

··· 139 139 regulator-always-on; 140 140 }; 141 141 142 - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 143 - compatible = "regulator-fixed"; 144 - pinctrl-names = "default"; 145 - pinctrl-0 = <&pinctrl_usdhc2_pwr>; 146 - regulator-name = "VSD_3V3"; 147 - regulator-min-microvolt = <3300000>; 148 - regulator-max-microvolt = <3300000>; 149 - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 150 - enable-active-high; 151 - regulator-always-on; 152 - }; 153 - 154 142 wwan_codec: sound-wwan-codec { 155 143 compatible = "option,gtm601"; 156 144 #sound-dai-cells = <0>; ··· 230 242 enable-active-high; 231 243 regulator-always-on; 232 244 }; 245 + 246 + wifi_pwr_seq: pwrseq { 247 + pinctrl-names = "default"; 248 + pinctrl-0 = <&pinctrl_usdhc2_rst>; 249 + compatible = "mmc-pwrseq-simple"; 250 + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; 251 + }; 233 252 }; 234 253 235 254 &A53_0 { ··· 319 324 regulator-ramp-delay = <1250>; 320 325 rohm,dvs-run-voltage = <1000000>; 321 326 rohm,dvs-idle-voltage = <900000>; 327 + regulator-always-on; 322 328 }; 323 329 324 330 buck3_reg: BUCK3 { ··· 557 561 reg = <0x6a>; 558 562 vdd-supply = <&reg_3v3_p>; 559 563 vddio-supply = <&reg_3v3_p>; 560 - mount-matrix = "1", "0", "0", 561 - "0", "1", "0", 562 - "0", "0", "-1"; 564 + mount-matrix = "1", "0", "0", 565 + "0", "1", "0", 566 + "0", "0", "-1"; 563 567 }; 564 568 }; 565 569 ··· 803 807 >; 804 808 }; 805 809 806 - pinctrl_usdhc2_pwr: usdhc2pwrgrp { 810 + pinctrl_usdhc2_rst: usdhc2rstgrp { 807 811 fsl,pins = < 808 812 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 809 813 >; ··· 1026 1030 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 1027 1031 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1028 1032 bus-width = <4>; 1029 - vmmc-supply = <&reg_usdhc2_vmmc>; 1030 - power-supply = <&wifi_pwr_en>; 1033 + vmmc-supply = <&wifi_pwr_en>; 1034 + mmc-pwrseq = <&wifi_pwr_seq>; 1031 1035 broken-cd; 1032 1036 disable-wp; 1033 1037 cap-sdio-irq;

+3 -3

arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts

··· 13 13 }; 14 14 15 15 &accel_gyro { 16 - mount-matrix = "1", "0", "0", 17 - "0", "-1", "0", 18 - "0", "0", "1"; 16 + mount-matrix = "1", "0", "0", 17 + "0", "-1", "0", 18 + "0", "0", "1"; 19 19 }; 20 20 21 21 &bq25895 {

+6 -6

arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi

··· 16 16 }; 17 17 18 18 &accel_gyro { 19 - mount-matrix = "1", "0", "0", 20 - "0", "1", "0", 21 - "0", "0", "-1"; 19 + mount-matrix = "1", "0", "0", 20 + "0", "1", "0", 21 + "0", "0", "-1"; 22 22 }; 23 23 24 24 &bq25895 { ··· 39 39 }; 40 40 41 41 &magnetometer { 42 - mount-matrix = "1", "0", "0", 43 - "0", "-1", "0", 44 - "0", "0", "-1"; 42 + mount-matrix = "1", "0", "0", 43 + "0", "-1", "0", 44 + "0", "0", "-1"; 45 45 }; 46 46 47 47 &proximity {

+1 -1

arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts

··· 23 23 }; 24 24 25 25 &proximity { 26 - proximity-near-level = <5>; 26 + proximity-near-level = <7>; 27 27 };

+5 -2

arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi

··· 91 91 regulator-max-microvolt = <1800000>; 92 92 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 93 93 enable-active-high; 94 + regulator-always-on; 94 95 }; 95 96 96 97 reg_mic_2v4: regulator-mic-2v4 { ··· 796 795 interrupt-parent = <&gpio1>; 797 796 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 798 797 interrupt-names = "irq"; 798 + extcon = <&usb3_phy0>; 799 + wakeup-source; 799 800 800 801 connector { 801 802 compatible = "usb-c-connector"; ··· 1379 1376 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 1380 1377 bus-width = <8>; 1381 1378 vmmc-supply = <&reg_vdd_3v3>; 1382 - power-supply = <&reg_vdd_1v8>; 1379 + vqmmc-supply = <&reg_vdd_1v8>; 1383 1380 non-removable; 1384 1381 status = "okay"; 1385 1382 }; ··· 1394 1391 bus-width = <4>; 1395 1392 vmmc-supply = <&reg_wifi_3v3>; 1396 1393 mmc-pwrseq = <&usdhc2_pwrseq>; 1397 - post-power-on-delay-ms = <1000>; 1394 + post-power-on-delay-ms = <20>; 1398 1395 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 1399 1396 max-frequency = <100000000>; 1400 1397 disable-wp;

+1 -1

arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi

··· 133 133 }; 134 134 }; 135 135 136 - &pgc_gpu{ 136 + &pgc_gpu { 137 137 power-supply = <&sw1a_reg>; 138 138 }; 139 139

+1 -1

arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts

··· 24 24 compatible = "linux,extcon-usb-gpio"; 25 25 pinctrl-names = "default"; 26 26 pinctrl-0 = <&pinctrl_usbcon0>; 27 - id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 27 + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 28 28 }; 29 29 30 30 pcie0_refclk: pcie0-refclk {

+196 -4

arch/arm64/boot/dts/freescale/imx8mq.dtsi

··· 330 330 nvmem-cells = <&imx8mq_uid>; 331 331 nvmem-cell-names = "soc_unique_id"; 332 332 333 + etm0: etm@28440000 { 334 + compatible = "arm,coresight-etm4x", "arm,primecell"; 335 + reg = <0x28440000 0x1000>; 336 + cpu = <&A53_0>; 337 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 338 + clock-names = "apb_pclk"; 339 + 340 + out-ports { 341 + port { 342 + etm0_out_port: endpoint { 343 + remote-endpoint = <&ca_funnel_in_port0>; 344 + }; 345 + }; 346 + }; 347 + }; 348 + 349 + etm1: etm@28540000 { 350 + compatible = "arm,coresight-etm4x", "arm,primecell"; 351 + reg = <0x28540000 0x1000>; 352 + cpu = <&A53_1>; 353 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 354 + clock-names = "apb_pclk"; 355 + 356 + out-ports { 357 + port { 358 + etm1_out_port: endpoint { 359 + remote-endpoint = <&ca_funnel_in_port1>; 360 + }; 361 + }; 362 + }; 363 + }; 364 + 365 + etm2: etm@28640000 { 366 + compatible = "arm,coresight-etm4x", "arm,primecell"; 367 + reg = <0x28640000 0x1000>; 368 + cpu = <&A53_2>; 369 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 370 + clock-names = "apb_pclk"; 371 + 372 + out-ports { 373 + port { 374 + etm2_out_port: endpoint { 375 + remote-endpoint = <&ca_funnel_in_port2>; 376 + }; 377 + }; 378 + }; 379 + }; 380 + 381 + etm3: etm@28740000 { 382 + compatible = "arm,coresight-etm4x", "arm,primecell"; 383 + reg = <0x28740000 0x1000>; 384 + cpu = <&A53_3>; 385 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 386 + clock-names = "apb_pclk"; 387 + 388 + out-ports { 389 + port { 390 + etm3_out_port: endpoint { 391 + remote-endpoint = <&ca_funnel_in_port3>; 392 + }; 393 + }; 394 + }; 395 + }; 396 + 397 + funnel { 398 + /* 399 + * non-configurable funnel don't show up on the AMBA 400 + * bus. As such no need to add "arm,primecell". 401 + */ 402 + compatible = "arm,coresight-static-funnel"; 403 + 404 + in-ports { 405 + #address-cells = <1>; 406 + #size-cells = <0>; 407 + 408 + port@0 { 409 + reg = <0>; 410 + 411 + ca_funnel_in_port0: endpoint { 412 + remote-endpoint = <&etm0_out_port>; 413 + }; 414 + }; 415 + 416 + port@1 { 417 + reg = <1>; 418 + 419 + ca_funnel_in_port1: endpoint { 420 + remote-endpoint = <&etm1_out_port>; 421 + }; 422 + }; 423 + 424 + port@2 { 425 + reg = <2>; 426 + 427 + ca_funnel_in_port2: endpoint { 428 + remote-endpoint = <&etm2_out_port>; 429 + }; 430 + }; 431 + 432 + port@3 { 433 + reg = <3>; 434 + 435 + ca_funnel_in_port3: endpoint { 436 + remote-endpoint = <&etm3_out_port>; 437 + }; 438 + }; 439 + }; 440 + 441 + out-ports { 442 + port { 443 + ca_funnel_out_port0: endpoint { 444 + remote-endpoint = <&hugo_funnel_in_port0>; 445 + }; 446 + }; 447 + }; 448 + }; 449 + 450 + funnel@28c03000 { 451 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 452 + reg = <0x28c03000 0x1000>; 453 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 454 + clock-names = "apb_pclk"; 455 + 456 + in-ports { 457 + #address-cells = <1>; 458 + #size-cells = <0>; 459 + 460 + port@0 { 461 + reg = <0>; 462 + 463 + hugo_funnel_in_port0: endpoint { 464 + remote-endpoint = <&ca_funnel_out_port0>; 465 + }; 466 + }; 467 + 468 + port@1 { 469 + reg = <1>; 470 + 471 + hugo_funnel_in_port1: endpoint { 472 + /* M4 input */ 473 + }; 474 + }; 475 + /* the other input ports are not connect to anything */ 476 + }; 477 + 478 + out-ports { 479 + port { 480 + hugo_funnel_out_port0: endpoint { 481 + remote-endpoint = <&etf_in_port>; 482 + }; 483 + }; 484 + }; 485 + }; 486 + 487 + etf@28c04000 { 488 + compatible = "arm,coresight-tmc", "arm,primecell"; 489 + reg = <0x28c04000 0x1000>; 490 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 491 + clock-names = "apb_pclk"; 492 + 493 + in-ports { 494 + port { 495 + etf_in_port: endpoint { 496 + remote-endpoint = <&hugo_funnel_out_port0>; 497 + }; 498 + }; 499 + }; 500 + 501 + out-ports { 502 + port { 503 + etf_out_port: endpoint { 504 + remote-endpoint = <&etr_in_port>; 505 + }; 506 + }; 507 + }; 508 + }; 509 + 510 + etr@28c06000 { 511 + compatible = "arm,coresight-tmc", "arm,primecell"; 512 + reg = <0x28c06000 0x1000>; 513 + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 514 + clock-names = "apb_pclk"; 515 + 516 + in-ports { 517 + port { 518 + etr_in_port: endpoint { 519 + remote-endpoint = <&etf_out_port>; 520 + }; 521 + }; 522 + }; 523 + }; 524 + 333 525 aips1: bus@30000000 { /* AIPS1 */ 334 526 compatible = "fsl,aips-bus", "simple-bus"; 335 527 reg = <0x30000000 0x400000>; ··· 823 631 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 824 632 reg = <0x30370000 0x10000>; 825 633 826 - snvs_rtc: snvs-rtc-lp{ 634 + snvs_rtc: snvs-rtc-lp { 827 635 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 828 - regmap =<&snvs>; 636 + regmap = <&snvs>; 829 637 offset = <0x34>; 830 638 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 831 639 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; ··· 1774 1582 #size-cells = <2>; 1775 1583 device_type = "pci"; 1776 1584 bus-range = <0x00 0xff>; 1777 - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1778 - <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1585 + ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1586 + <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1779 1587 num-lanes = <1>; 1780 1588 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1781 1589 interrupt-names = "msi";

+4

arch/arm64/boot/dts/freescale/imx8qm-mek.dts

··· 22 22 /delete-node/ cpu@101; 23 23 }; 24 24 25 + thermal-zones { 26 + /delete-node/ cpu1-thermal; 27 + }; 28 + 25 29 memory@80000000 { 26 30 device_type = "memory"; 27 31 reg = <0x00000000 0x80000000 0 0x40000000>;

+209 -3

arch/arm64/boot/dts/freescale/imx8qm.dtsi

··· 9 9 #include <dt-bindings/gpio/gpio.h> 10 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 12 + #include <dt-bindings/thermal/thermal.h> 12 13 13 14 / { 14 15 interrupt-parent = <&gic>; ··· 24 23 serial1 = &lpuart1; 25 24 serial2 = &lpuart2; 26 25 serial3 = &lpuart3; 27 - vpu_core0 = &vpu_core0; 28 - vpu_core1 = &vpu_core1; 29 - vpu_core2 = &vpu_core2; 26 + vpu-core0 = &vpu_core0; 27 + vpu-core1 = &vpu_core1; 28 + vpu-core2 = &vpu_core2; 30 29 }; 31 30 32 31 cpus { ··· 63 62 device_type = "cpu"; 64 63 compatible = "arm,cortex-a53"; 65 64 reg = <0x0 0x0>; 65 + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 66 66 enable-method = "psci"; 67 67 i-cache-size = <0x8000>; 68 68 i-cache-line-size = <64>; ··· 72 70 d-cache-line-size = <64>; 73 71 d-cache-sets = <128>; 74 72 next-level-cache = <&A53_L2>; 73 + operating-points-v2 = <&a53_opp_table>; 74 + #cooling-cells = <2>; 75 75 }; 76 76 77 77 A53_1: cpu@1 { 78 78 device_type = "cpu"; 79 79 compatible = "arm,cortex-a53"; 80 80 reg = <0x0 0x1>; 81 + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 81 82 enable-method = "psci"; 82 83 i-cache-size = <0x8000>; 83 84 i-cache-line-size = <64>; ··· 89 84 d-cache-line-size = <64>; 90 85 d-cache-sets = <128>; 91 86 next-level-cache = <&A53_L2>; 87 + operating-points-v2 = <&a53_opp_table>; 88 + #cooling-cells = <2>; 92 89 }; 93 90 94 91 A53_2: cpu@2 { 95 92 device_type = "cpu"; 96 93 compatible = "arm,cortex-a53"; 97 94 reg = <0x0 0x2>; 95 + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 98 96 enable-method = "psci"; 99 97 i-cache-size = <0x8000>; 100 98 i-cache-line-size = <64>; ··· 106 98 d-cache-line-size = <64>; 107 99 d-cache-sets = <128>; 108 100 next-level-cache = <&A53_L2>; 101 + operating-points-v2 = <&a53_opp_table>; 102 + #cooling-cells = <2>; 109 103 }; 110 104 111 105 A53_3: cpu@3 { 112 106 device_type = "cpu"; 113 107 compatible = "arm,cortex-a53"; 114 108 reg = <0x0 0x3>; 109 + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 115 110 enable-method = "psci"; 116 111 i-cache-size = <0x8000>; 117 112 i-cache-line-size = <64>; ··· 123 112 d-cache-line-size = <64>; 124 113 d-cache-sets = <128>; 125 114 next-level-cache = <&A53_L2>; 115 + operating-points-v2 = <&a53_opp_table>; 116 + #cooling-cells = <2>; 126 117 }; 127 118 128 119 A72_0: cpu@100 { 129 120 device_type = "cpu"; 130 121 compatible = "arm,cortex-a72"; 131 122 reg = <0x0 0x100>; 123 + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 132 124 enable-method = "psci"; 133 125 i-cache-size = <0xC000>; 134 126 i-cache-line-size = <64>; ··· 140 126 d-cache-line-size = <64>; 141 127 d-cache-sets = <256>; 142 128 next-level-cache = <&A72_L2>; 129 + operating-points-v2 = <&a72_opp_table>; 130 + #cooling-cells = <2>; 143 131 }; 144 132 145 133 A72_1: cpu@101 { 146 134 device_type = "cpu"; 147 135 compatible = "arm,cortex-a72"; 148 136 reg = <0x0 0x101>; 137 + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 149 138 enable-method = "psci"; 150 139 next-level-cache = <&A72_L2>; 140 + operating-points-v2 = <&a72_opp_table>; 141 + #cooling-cells = <2>; 151 142 }; 152 143 153 144 A53_L2: l2-cache0 { ··· 171 152 cache-size = <0x100000>; 172 153 cache-line-size = <64>; 173 154 cache-sets = <1024>; 155 + }; 156 + }; 157 + 158 + a53_opp_table: opp-table-0 { 159 + compatible = "operating-points-v2"; 160 + opp-shared; 161 + 162 + opp-600000000 { 163 + opp-hz = /bits/ 64 <600000000>; 164 + opp-microvolt = <900000>; 165 + clock-latency-ns = <150000>; 166 + }; 167 + 168 + opp-896000000 { 169 + opp-hz = /bits/ 64 <896000000>; 170 + opp-microvolt = <1000000>; 171 + clock-latency-ns = <150000>; 172 + }; 173 + 174 + opp-1104000000 { 175 + opp-hz = /bits/ 64 <1104000000>; 176 + opp-microvolt = <1100000>; 177 + clock-latency-ns = <150000>; 178 + }; 179 + 180 + opp-1200000000 { 181 + opp-hz = /bits/ 64 <1200000000>; 182 + opp-microvolt = <1100000>; 183 + clock-latency-ns = <150000>; 184 + opp-suspend; 185 + }; 186 + }; 187 + 188 + a72_opp_table: opp-table-1 { 189 + compatible = "operating-points-v2"; 190 + opp-shared; 191 + 192 + opp-600000000 { 193 + opp-hz = /bits/ 64 <600000000>; 194 + opp-microvolt = <1000000>; 195 + clock-latency-ns = <150000>; 196 + }; 197 + 198 + opp-1056000000 { 199 + opp-hz = /bits/ 64 <1056000000>; 200 + opp-microvolt = <1000000>; 201 + clock-latency-ns = <150000>; 202 + }; 203 + 204 + opp-1296000000 { 205 + opp-hz = /bits/ 64 <1296000000>; 206 + opp-microvolt = <1100000>; 207 + clock-latency-ns = <150000>; 208 + }; 209 + 210 + opp-1596000000 { 211 + opp-hz = /bits/ 64 <1596000000>; 212 + opp-microvolt = <1100000>; 213 + clock-latency-ns = <150000>; 214 + opp-suspend; 174 215 }; 175 216 }; 176 217 ··· 290 211 291 212 rtc: rtc { 292 213 compatible = "fsl,imx8qxp-sc-rtc"; 214 + }; 215 + 216 + tsens: thermal-sensor { 217 + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 218 + #thermal-sensor-cells = <1>; 219 + }; 220 + }; 221 + 222 + thermal-zones { 223 + cpu0-thermal { 224 + polling-delay-passive = <250>; 225 + polling-delay = <2000>; 226 + thermal-sensors = <&tsens IMX_SC_R_A53>; 227 + 228 + trips { 229 + cpu_alert0: trip0 { 230 + temperature = <107000>; 231 + hysteresis = <2000>; 232 + type = "passive"; 233 + }; 234 + 235 + cpu_crit0: trip1 { 236 + temperature = <127000>; 237 + hysteresis = <2000>; 238 + type = "critical"; 239 + }; 240 + }; 241 + 242 + cooling-maps { 243 + map0 { 244 + trip = <&cpu_alert0>; 245 + cooling-device = 246 + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 247 + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 248 + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 249 + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 250 + }; 251 + }; 252 + }; 253 + 254 + cpu1-thermal { 255 + polling-delay-passive = <250>; 256 + polling-delay = <2000>; 257 + thermal-sensors = <&tsens IMX_SC_R_A72>; 258 + 259 + trips { 260 + cpu_alert1: trip0 { 261 + temperature = <107000>; 262 + hysteresis = <2000>; 263 + type = "passive"; 264 + }; 265 + 266 + cpu_crit1: trip1 { 267 + temperature = <127000>; 268 + hysteresis = <2000>; 269 + type = "critical"; 270 + }; 271 + }; 272 + 273 + cooling-maps { 274 + map0 { 275 + trip = <&cpu_alert1>; 276 + cooling-device = 277 + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 278 + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 279 + }; 280 + }; 281 + }; 282 + 283 + gpu0-thermal { 284 + polling-delay-passive = <250>; 285 + polling-delay = <2000>; 286 + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; 287 + 288 + trips { 289 + gpu_alert0: trip0 { 290 + temperature = <107000>; 291 + hysteresis = <2000>; 292 + type = "passive"; 293 + }; 294 + 295 + gpu_crit0: trip1 { 296 + temperature = <127000>; 297 + hysteresis = <2000>; 298 + type = "critical"; 299 + }; 300 + }; 301 + }; 302 + 303 + gpu1-thermal { 304 + polling-delay-passive = <250>; 305 + polling-delay = <2000>; 306 + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; 307 + 308 + trips { 309 + gpu_alert1: trip0 { 310 + temperature = <107000>; 311 + hysteresis = <2000>; 312 + type = "passive"; 313 + }; 314 + 315 + gpu_crit1: trip1 { 316 + temperature = <127000>; 317 + hysteresis = <2000>; 318 + type = "critical"; 319 + }; 320 + }; 321 + }; 322 + 323 + drc0-thermal { 324 + polling-delay-passive = <250>; 325 + polling-delay = <2000>; 326 + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; 327 + 328 + trips { 329 + drc_alert0: trip0 { 330 + temperature = <107000>; 331 + hysteresis = <2000>; 332 + type = "passive"; 333 + }; 334 + 335 + drc_crit0: trip1 { 336 + temperature = <127000>; 337 + hysteresis = <2000>; 338 + type = "critical"; 339 + }; 340 + }; 293 341 }; 294 342 }; 295 343

+1 -1

arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts

··· 180 180 >; 181 181 }; 182 182 183 - pinctrl_leds: ledsgrp{ 183 + pinctrl_leds: ledsgrp { 184 184 fsl,pins = < 185 185 IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021 186 186 IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021

+3 -3

arch/arm64/boot/dts/freescale/imx8qxp.dtsi

··· 46 46 serial1 = &lpuart1; 47 47 serial2 = &lpuart2; 48 48 serial3 = &lpuart3; 49 - vpu_core0 = &vpu_core0; 50 - vpu_core1 = &vpu_core1; 51 - vpu_core2 = &vpu_core2; 49 + vpu-core0 = &vpu_core0; 50 + vpu-core1 = &vpu_core1; 51 + vpu-core2 = &vpu_core2; 52 52 }; 53 53 54 54 cpus {

+133 -12

arch/arm64/boot/dts/freescale/imx8ulp-evk.dts

··· 20 20 reg = <0x0 0x80000000 0 0x80000000>; 21 21 }; 22 22 23 + reserved-memory { 24 + #address-cells = <2>; 25 + #size-cells = <2>; 26 + ranges; 27 + 28 + linux,cma { 29 + compatible = "shared-dma-pool"; 30 + reusable; 31 + size = <0 0x28000000>; 32 + linux,cma-default; 33 + }; 34 + 35 + m33_reserved: noncacheable-section@a8600000 { 36 + reg = <0 0xa8600000 0 0x1000000>; 37 + no-map; 38 + }; 39 + 40 + rsc_table: rsc-table@1fff8000{ 41 + reg = <0 0x1fff8000 0 0x1000>; 42 + no-map; 43 + }; 44 + 45 + vdev0vring0: vdev0vring0@aff00000 { 46 + reg = <0 0xaff00000 0 0x8000>; 47 + no-map; 48 + }; 49 + 50 + vdev0vring1: vdev0vring1@aff08000 { 51 + reg = <0 0xaff08000 0 0x8000>; 52 + no-map; 53 + }; 54 + 55 + vdev1vring0: vdev1vring0@aff10000 { 56 + reg = <0 0xaff10000 0 0x8000>; 57 + no-map; 58 + }; 59 + 60 + vdev1vring1: vdev1vring1@aff18000 { 61 + reg = <0 0xaff18000 0 0x8000>; 62 + no-map; 63 + }; 64 + 65 + vdevbuffer: vdevbuffer@a8400000 { 66 + compatible = "shared-dma-pool"; 67 + reg = <0 0xa8400000 0 0x100000>; 68 + no-map; 69 + }; 70 + }; 71 + 23 72 clock_ext_rmii: clock-ext-rmii { 24 73 compatible = "fixed-clock"; 25 74 clock-frequency = <50000000>; ··· 85 36 }; 86 37 }; 87 38 39 + &cm33 { 40 + mbox-names = "tx", "rx", "rxdb"; 41 + mboxes = <&mu 0 1>, 42 + <&mu 1 1>, 43 + <&mu 3 1>; 44 + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 45 + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 46 + status = "okay"; 47 + }; 48 + 49 + &flexspi2 { 50 + pinctrl-names = "default", "sleep"; 51 + pinctrl-0 = <&pinctrl_flexspi2_ptd>; 52 + pinctrl-1 = <&pinctrl_flexspi2_ptd>; 53 + status = "okay"; 54 + 55 + mx25uw51345gxdi00: flash@0 { 56 + compatible = "jedec,spi-nor"; 57 + reg = <0>; 58 + spi-max-frequency = <200000000>; 59 + spi-tx-bus-width = <8>; 60 + spi-rx-bus-width = <8>; 61 + }; 62 + }; 63 + 88 64 &lpuart5 { 89 65 /* console */ 90 66 pinctrl-names = "default", "sleep"; ··· 118 44 status = "okay"; 119 45 }; 120 46 121 - &usdhc0 { 47 + &lpi2c7 { 48 + #address-cells = <1>; 49 + #size-cells = <0>; 50 + clock-frequency = <400000>; 122 51 pinctrl-names = "default", "sleep"; 52 + pinctrl-0 = <&pinctrl_lpi2c7>; 53 + pinctrl-1 = <&pinctrl_lpi2c7>; 54 + status = "okay"; 55 + 56 + pcal6408: gpio@21 { 57 + compatible = "nxp,pcal9554b"; 58 + reg = <0x21>; 59 + gpio-controller; 60 + #gpio-cells = <2>; 61 + }; 62 + }; 63 + 64 + &usdhc0 { 65 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 123 66 pinctrl-0 = <&pinctrl_usdhc0>; 124 67 pinctrl-1 = <&pinctrl_usdhc0>; 68 + pinctrl-2 = <&pinctrl_usdhc0>; 69 + pinctrl-3 = <&pinctrl_usdhc0>; 125 70 non-removable; 126 71 bus-width = <8>; 127 72 status = "okay"; ··· 172 79 }; 173 80 }; 174 81 82 + &mu { 83 + status = "okay"; 84 + }; 85 + 175 86 &iomuxc1 { 176 87 pinctrl_enet: enetgrp { 177 88 fsl,pins = < ··· 193 96 >; 194 97 }; 195 98 99 + pinctrl_flexspi2_ptd: flexspi2ptdgrp { 100 + fsl,pins = < 101 + 102 + MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 103 + MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 104 + MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 105 + MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 106 + MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 107 + MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 108 + MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 109 + MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 110 + MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 111 + MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 112 + MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 113 + >; 114 + }; 115 + 196 116 pinctrl_lpuart5: lpuart5grp { 197 117 fsl,pins = < 198 118 MX8ULP_PAD_PTF14__LPUART5_TX 0x3 ··· 217 103 >; 218 104 }; 219 105 106 + pinctrl_lpi2c7: lpi2c7grp { 107 + fsl,pins = < 108 + MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 109 + MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 110 + >; 111 + }; 112 + 220 113 pinctrl_usdhc0: usdhc0grp { 221 114 fsl,pins = < 222 - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 223 - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 224 - MX8ULP_PAD_PTD10__SDHC0_D0 0x43 225 - MX8ULP_PAD_PTD9__SDHC0_D1 0x43 226 - MX8ULP_PAD_PTD8__SDHC0_D2 0x43 227 - MX8ULP_PAD_PTD7__SDHC0_D3 0x43 228 - MX8ULP_PAD_PTD6__SDHC0_D4 0x43 229 - MX8ULP_PAD_PTD5__SDHC0_D5 0x43 230 - MX8ULP_PAD_PTD4__SDHC0_D6 0x43 231 - MX8ULP_PAD_PTD3__SDHC0_D7 0x43 232 - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 115 + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 116 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 117 + MX8ULP_PAD_PTD10__SDHC0_D0 0x3 118 + MX8ULP_PAD_PTD9__SDHC0_D1 0x3 119 + MX8ULP_PAD_PTD8__SDHC0_D2 0x3 120 + MX8ULP_PAD_PTD7__SDHC0_D3 0x3 121 + MX8ULP_PAD_PTD6__SDHC0_D4 0x3 122 + MX8ULP_PAD_PTD5__SDHC0_D5 0x3 123 + MX8ULP_PAD_PTD4__SDHC0_D6 0x3 124 + MX8ULP_PAD_PTD3__SDHC0_D7 0x3 125 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 233 126 >; 234 127 }; 235 128 };

+72 -1

arch/arm64/boot/dts/freescale/imx8ulp.dtsi

··· 7 7 #include <dt-bindings/gpio/gpio.h> 8 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 9 #include <dt-bindings/power/imx8ulp-power.h> 10 + #include <dt-bindings/thermal/thermal.h> 10 11 11 12 #include "imx8ulp-pinfunc.h" 12 13 ··· 40 39 reg = <0x0 0x0>; 41 40 enable-method = "psci"; 42 41 next-level-cache = <&A35_L2>; 42 + cpu-idle-states = <&cpu_sleep>; 43 43 }; 44 44 45 45 A35_1: cpu@1 { ··· 49 47 reg = <0x0 0x1>; 50 48 enable-method = "psci"; 51 49 next-level-cache = <&A35_L2>; 50 + cpu-idle-states = <&cpu_sleep>; 52 51 }; 53 52 54 53 A35_L2: l2-cache0 { 55 54 compatible = "cache"; 56 55 cache-level = <2>; 57 56 cache-unified; 57 + }; 58 + 59 + idle-states { 60 + entry-method = "psci"; 61 + 62 + cpu_sleep: cpu-sleep { 63 + compatible = "arm,idle-state"; 64 + arm,psci-suspend-param = <0x0>; 65 + local-timer-stop; 66 + entry-latency-us = <1000>; 67 + exit-latency-us = <700>; 68 + min-residency-us = <2700>; 69 + }; 58 70 }; 59 71 }; 60 72 ··· 92 76 psci { 93 77 compatible = "arm,psci-1.0"; 94 78 method = "smc"; 79 + }; 80 + 81 + thermal-zones { 82 + cpu-thermal { 83 + polling-delay-passive = <250>; 84 + polling-delay = <2000>; 85 + thermal-sensors = <&scmi_sensor 0>; 86 + 87 + trips { 88 + cpu_alert0: trip0 { 89 + temperature = <85000>; 90 + hysteresis = <2000>; 91 + type = "passive"; 92 + }; 93 + 94 + cpu_crit0: trip1 { 95 + temperature = <95000>; 96 + hysteresis = <2000>; 97 + type = "critical"; 98 + }; 99 + }; 100 + }; 95 101 }; 96 102 97 103 timer { ··· 186 148 }; 187 149 }; 188 150 151 + cm33: remoteproc-cm33 { 152 + compatible = "fsl,imx8ulp-cm33"; 153 + status = "disabled"; 154 + }; 155 + 189 156 soc: soc@0 { 190 157 compatible = "simple-bus"; 191 158 #address-cells = <1>; 192 159 #size-cells = <1>; 193 - ranges = <0x0 0x0 0x0 0x40000000>; 160 + ranges = <0x0 0x0 0x0 0x40000000>, 161 + <0x60000000 0x0 0x60000000 0x1000000>; 194 162 195 163 s4muap: mailbox@27020000 { 196 164 compatible = "fsl,imx8ulp-mu-s4"; ··· 351 307 #reset-cells = <1>; 352 308 }; 353 309 310 + flexspi2: spi@29810000 { 311 + compatible = "nxp,imx8mm-fspi"; 312 + reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; 313 + reg-names = "fspi_base", "fspi_mmap"; 314 + #address-cells = <1>; 315 + #size-cells = <0>; 316 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 317 + clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, 318 + <&pcc4 IMX8ULP_CLK_FLEXSPI2>; 319 + clock-names = "fspi", "fspi_en"; 320 + assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>; 321 + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 322 + status = "disabled"; 323 + }; 324 + 354 325 lpi2c6: i2c@29840000 { 355 326 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 356 327 reg = <0x29840000 0x10000>; ··· 424 365 <&pcc4 IMX8ULP_CLK_USDHC0>; 425 366 clock-names = "ipg", "ahb", "per"; 426 367 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 368 + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, 369 + <&pcc4 IMX8ULP_CLK_USDHC0>; 370 + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; 371 + assigned-clock-rates = <389283840>, <389283840>; 427 372 fsl,tuning-start-tap = <20>; 428 373 fsl,tuning-step = <2>; 429 374 bus-width = <4>; ··· 443 380 <&pcc4 IMX8ULP_CLK_USDHC1>; 444 381 clock-names = "ipg", "ahb", "per"; 445 382 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 383 + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 384 + <&pcc4 IMX8ULP_CLK_USDHC1>; 385 + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 386 + assigned-clock-rates = <194641920>, <194641920>; 446 387 fsl,tuning-start-tap = <20>; 447 388 fsl,tuning-step = <2>; 448 389 bus-width = <4>; ··· 462 395 <&pcc4 IMX8ULP_CLK_USDHC2>; 463 396 clock-names = "ipg", "ahb", "per"; 464 397 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 398 + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 399 + <&pcc4 IMX8ULP_CLK_USDHC2>; 400 + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 401 + assigned-clock-rates = <194641920>, <194641920>; 465 402 fsl,tuning-start-tap = <20>; 466 403 fsl,tuning-step = <2>; 467 404 bus-width = <4>;

+1 -1

arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi

··· 35 35 36 36 /* Colibri UART_A */ 37 37 &lpuart3 { 38 - status= "okay"; 38 + status = "okay"; 39 39 }; 40 40 41 41 /* Colibri SDCard */

+1 -1

arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi

··· 77 77 78 78 /* Colibri UART_A */ 79 79 &lpuart3 { 80 - status= "okay"; 80 + status = "okay"; 81 81 }; 82 82 83 83 &lsio_gpio3 {

+56

arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts

··· 15 15 stdout-path = &lpuart1; 16 16 }; 17 17 18 + reserved-memory { 19 + #address-cells = <2>; 20 + #size-cells = <2>; 21 + ranges; 22 + 23 + linux,cma { 24 + compatible = "shared-dma-pool"; 25 + reusable; 26 + alloc-ranges = <0 0x80000000 0 0x40000000>; 27 + size = <0 0x10000000>; 28 + linux,cma-default; 29 + }; 30 + 31 + vdev0vring0: vdev0vring0@a4000000 { 32 + reg = <0 0xa4000000 0 0x8000>; 33 + no-map; 34 + }; 35 + 36 + vdev0vring1: vdev0vring1@a4008000 { 37 + reg = <0 0xa4008000 0 0x8000>; 38 + no-map; 39 + }; 40 + 41 + vdev1vring0: vdev1vring0@a4000000 { 42 + reg = <0 0xa4010000 0 0x8000>; 43 + no-map; 44 + }; 45 + 46 + vdev1vring1: vdev1vring1@a4018000 { 47 + reg = <0 0xa4018000 0 0x8000>; 48 + no-map; 49 + }; 50 + 51 + rsc_table: rsc-table@2021f000 { 52 + reg = <0 0x2021f000 0 0x1000>; 53 + no-map; 54 + }; 55 + 56 + vdevbuffer: vdevbuffer@a4020000 { 57 + compatible = "shared-dma-pool"; 58 + reg = <0 0xa4020000 0 0x100000>; 59 + no-map; 60 + }; 61 + 62 + }; 63 + 18 64 reg_vref_1v8: regulator-adc-vref { 19 65 compatible = "regulator-fixed"; 20 66 regulator-name = "vref_1v8"; ··· 82 36 83 37 &adc1 { 84 38 vref-supply = <&reg_vref_1v8>; 39 + status = "okay"; 40 + }; 41 + 42 + &cm33 { 43 + mbox-names = "tx", "rx", "rxdb"; 44 + mboxes = <&mu1 0 1>, 45 + <&mu1 1 1>, 46 + <&mu1 3 1>; 47 + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 48 + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 85 49 status = "okay"; 86 50 }; 87 51

+641

arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2 + /* 3 + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 + * D-82229 Seefeld, Germany. 5 + * Author: Markus Niebel 6 + * Author: Alexander Stein 7 + */ 8 + /dts-v1/; 9 + 10 + #include <dt-bindings/input/input.h> 11 + #include <dt-bindings/leds/common.h> 12 + #include <dt-bindings/net/ti-dp83867.h> 13 + #include <dt-bindings/pwm/pwm.h> 14 + #include <dt-bindings/usb/pd.h> 15 + #include "imx93-tqma9352.dtsi" 16 + 17 + /{ 18 + model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC"; 19 + compatible = "tq,imx93-tqma9352-mba93xxla", 20 + "tq,imx93-tqma9352", "fsl,imx93"; 21 + 22 + chosen { 23 + stdout-path = &lpuart1; 24 + }; 25 + 26 + aliases { 27 + eeprom0 = &eeprom0; 28 + rtc0 = &pcf85063; 29 + rtc1 = &bbnsm_rtc; 30 + }; 31 + 32 + backlight_lvds: backlight { 33 + compatible = "pwm-backlight"; 34 + pwms = <&tpm5 0 5000000 0>; 35 + brightness-levels = <0 4 8 16 32 64 128 255>; 36 + default-brightness-level = <7>; 37 + power-supply = <&reg_12v0>; 38 + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; 39 + status = "disabled"; 40 + }; 41 + 42 + clk_dp: clk-dp { 43 + compatible = "fixed-clock"; 44 + #clock-cells = <0>; 45 + clock-frequency = <26000000>; 46 + }; 47 + 48 + gpio-keys { 49 + compatible = "gpio-keys"; 50 + autorepeat; 51 + 52 + switch-a { 53 + label = "switcha"; 54 + linux,code = <BTN_0>; 55 + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; 56 + wakeup-source; 57 + }; 58 + 59 + switch-b { 60 + label = "switchb"; 61 + linux,code = <BTN_1>; 62 + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; 63 + wakeup-source; 64 + }; 65 + }; 66 + 67 + gpio-leds { 68 + compatible = "gpio-leds"; 69 + 70 + led-1 { 71 + color = <LED_COLOR_ID_GREEN>; 72 + function = LED_FUNCTION_STATUS; 73 + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; 74 + linux,default-trigger = "default-on"; 75 + }; 76 + 77 + led-2 { 78 + color = <LED_COLOR_ID_AMBER>; 79 + function = LED_FUNCTION_HEARTBEAT; 80 + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; 81 + linux,default-trigger = "heartbeat"; 82 + }; 83 + }; 84 + 85 + iio-hwmon { 86 + compatible = "iio-hwmon"; 87 + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; 88 + }; 89 + 90 + reg_3v3: regulator-3v3 { 91 + compatible = "regulator-fixed"; 92 + regulator-name = "V_3V3_MB"; 93 + regulator-min-microvolt = <3300000>; 94 + regulator-max-microvolt = <3300000>; 95 + }; 96 + 97 + reg_3v8: regulator-3v8 { 98 + compatible = "regulator-fixed"; 99 + regulator-name = "V_3V8"; 100 + regulator-min-microvolt = <3800000>; 101 + regulator-max-microvolt = <3800000>; 102 + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 103 + enable-active-high; 104 + /* TODO: this is supply for IOT module */ 105 + regulator-always-on; 106 + }; 107 + 108 + reg_5v0: regulator-5v0 { 109 + compatible = "regulator-fixed"; 110 + regulator-name = "V_5V0_MB"; 111 + regulator-min-microvolt = <5000000>; 112 + regulator-max-microvolt = <5000000>; 113 + }; 114 + 115 + reg_12v0: regulator-12v0 { 116 + compatible = "regulator-fixed"; 117 + regulator-name = "V_12V"; 118 + regulator-min-microvolt = <12000000>; 119 + regulator-max-microvolt = <12000000>; 120 + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; 121 + enable-active-high; 122 + }; 123 + }; 124 + 125 + &adc1 { 126 + status = "okay"; 127 + }; 128 + 129 + &eqos { 130 + pinctrl-names = "default"; 131 + pinctrl-0 = <&pinctrl_eqos>; 132 + phy-mode = "rgmii-id"; 133 + phy-handle = <&ethphy_eqos>; 134 + status = "okay"; 135 + 136 + mdio { 137 + compatible = "snps,dwmac-mdio"; 138 + #address-cells = <1>; 139 + #size-cells = <0>; 140 + 141 + ethphy_eqos: ethernet-phy@0 { 142 + compatible = "ethernet-phy-ieee802.3-c22"; 143 + reg = <0>; 144 + pinctrl-names = "default"; 145 + pinctrl-0 = <&pinctrl_eqos_phy>; 146 + interrupt-parent = <&gpio3>; 147 + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 148 + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; 149 + reset-assert-us = <500000>; 150 + reset-deassert-us = <50000>; 151 + enet-phy-lane-no-swap; 152 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 153 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 154 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 155 + ti,dp83867-rxctrl-strap-quirk; 156 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 157 + }; 158 + }; 159 + }; 160 + 161 + &fec { 162 + pinctrl-names = "default"; 163 + pinctrl-0 = <&pinctrl_fec>; 164 + phy-mode = "rgmii-id"; 165 + phy-handle = <&ethphy_fec>; 166 + fsl,magic-packet; 167 + status = "okay"; 168 + 169 + mdio { 170 + #address-cells = <1>; 171 + #size-cells = <0>; 172 + clock-frequency = <5000000>; 173 + 174 + ethphy_fec: ethernet-phy@0 { 175 + compatible = "ethernet-phy-ieee802.3-c22"; 176 + reg = <0>; 177 + pinctrl-names = "default"; 178 + pinctrl-0 = <&pinctrl_fec_phy>; 179 + interrupt-parent = <&gpio3>; 180 + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 181 + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; 182 + reset-assert-us = <500000>; 183 + reset-deassert-us = <50000>; 184 + enet-phy-lane-no-swap; 185 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 186 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 187 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 188 + ti,dp83867-rxctrl-strap-quirk; 189 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 190 + }; 191 + }; 192 + }; 193 + 194 + &flexcan1 { 195 + pinctrl-names = "default"; 196 + pinctrl-0 = <&pinctrl_flexcan1>; 197 + xceiver-supply = <&reg_3v3>; 198 + status = "okay"; 199 + }; 200 + 201 + &flexcan2 { 202 + pinctrl-names = "default"; 203 + pinctrl-0 = <&pinctrl_flexcan2>; 204 + xceiver-supply = <&reg_3v3>; 205 + status = "okay"; 206 + }; 207 + 208 + &gpio1 { 209 + expander-irq-hog { 210 + gpio-hog; 211 + gpios = <12 GPIO_ACTIVE_LOW>; 212 + input; 213 + line-name = "PEX_INT#"; 214 + }; 215 + 216 + rtc-irq-hog { 217 + gpio-hog; 218 + gpios = <14 GPIO_ACTIVE_LOW>; 219 + input; 220 + line-name = "RTC_EVENT#"; 221 + }; 222 + }; 223 + 224 + &gpio3 { 225 + ethphy-eqos-irq-hog { 226 + gpio-hog; 227 + gpios = <26 GPIO_ACTIVE_LOW>; 228 + input; 229 + line-name = "ENET0_IRQ#"; 230 + }; 231 + 232 + ethphy-fec-irq-hog { 233 + gpio-hog; 234 + gpios = <27 GPIO_ACTIVE_LOW>; 235 + input; 236 + line-name = "ENET1_IRQ#"; 237 + }; 238 + }; 239 + 240 + &lpi2c3 { 241 + #address-cells = <1>; 242 + #size-cells = <0>; 243 + clock-frequency = <400000>; 244 + pinctrl-names = "default", "sleep"; 245 + pinctrl-0 = <&pinctrl_lpi2c3>; 246 + pinctrl-1 = <&pinctrl_lpi2c3>; 247 + status = "okay"; 248 + 249 + temperature-sensor@1c { 250 + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 251 + reg = <0x1c>; 252 + }; 253 + 254 + eeprom2: eeprom@54 { 255 + compatible = "nxp,se97b", "atmel,24c02"; 256 + reg = <0x54>; 257 + pagesize = <16>; 258 + vcc-supply = <&reg_3v3>; 259 + }; 260 + 261 + expander0: gpio@70 { 262 + compatible = "nxp,pca9538"; 263 + reg = <0x70>; 264 + pinctrl-names = "default"; 265 + pinctrl-0 = <&pinctrl_pexp_irq>; 266 + gpio-controller; 267 + #gpio-cells = <2>; 268 + interrupt-controller; 269 + #interrupt-cells = <2>; 270 + interrupt-parent = <&gpio1>; 271 + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 272 + vcc-supply = <&reg_3v3>; 273 + gpio-line-names = "3V8_EN", "", 274 + "", "IOT_PWRKEY", 275 + "IOT_RESET", "IOT_W_DISABLE", 276 + "BUTTON_A#", "BUTTON_B#"; 277 + 278 + /* 279 + * Controls the IOT W_DISABLE pin which is low active 280 + * as disable signal but inverted as seen from the CPU. 281 + * The output-low states, the signal is 282 + * inactive, e.g. not disabled 283 + */ 284 + iot_wdisable_hog: iot-wdisable-hog { 285 + gpio-hog; 286 + gpios = <5 GPIO_ACTIVE_HIGH>; 287 + output-low; 288 + line-name = "IOT_W_DISABLE"; 289 + }; 290 + }; 291 + 292 + expander1: gpio@71 { 293 + compatible = "nxp,pca9538"; 294 + reg = <0x71>; 295 + gpio-controller; 296 + #gpio-cells = <2>; 297 + vcc-supply = <&reg_3v3>; 298 + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", 299 + "USB_RESET#", "", 300 + "WLAN_PD#", "WLAN_W_DISABLE#", 301 + "WLAN_PERST#", "12V_EN"; 302 + 303 + /* 304 + * Controls the WiFi card PD pin which is low active 305 + * as power down signal. The output-low states, the signal 306 + * is inactive, e.g. not power down 307 + */ 308 + wlan-pd-hog { 309 + gpio-hog; 310 + gpios = <4 GPIO_ACTIVE_LOW>; 311 + output-low; 312 + line-name = "WLAN_PD#"; 313 + }; 314 + 315 + /* 316 + * Controls the WiFi card disable pin which is low active 317 + * as disable signal. The output-low states, the signal 318 + * is inactive, e.g. not disabled 319 + */ 320 + wlan-wdisable-hog { 321 + gpio-hog; 322 + gpios = <5 GPIO_ACTIVE_LOW>; 323 + output-low; 324 + line-name = "WLAN_W_DISABLE#"; 325 + }; 326 + 327 + /* 328 + * Controls the WiFi card reset pin which is low active 329 + * as reset signal. The output-low states, the signal 330 + * is inactive, e.g. not in reset 331 + */ 332 + wlan-perst-hog { 333 + gpio-hog; 334 + gpios = <6 GPIO_ACTIVE_LOW>; 335 + output-low; 336 + line-name = "WLAN_PERST#"; 337 + }; 338 + }; 339 + 340 + expander2: gpio@72 { 341 + compatible = "nxp,pca9538"; 342 + reg = <0x72>; 343 + gpio-controller; 344 + #gpio-cells = <2>; 345 + vcc-supply = <&reg_3v3>; 346 + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", 347 + "LCD_BL_EN", "DP_EN", 348 + "MIPI_CSI_EN", "MIPI_CSI_RST#", 349 + "USER_LED1", "USER_LED2"; 350 + }; 351 + }; 352 + 353 + &lpi2c5 { 354 + #address-cells = <1>; 355 + #size-cells = <0>; 356 + clock-frequency = <400000>; 357 + pinctrl-names = "default", "sleep"; 358 + pinctrl-0 = <&pinctrl_lpi2c5>; 359 + pinctrl-1 = <&pinctrl_lpi2c5>; 360 + status = "okay"; 361 + 362 + dp_bridge: dp-bridge@f { 363 + compatible = "toshiba,tc9595", "toshiba,tc358767"; 364 + reg = <0x0f>; 365 + pinctrl-names = "default"; 366 + pinctrl-0 = <&pinctrl_tc9595>; 367 + clock-names = "ref"; 368 + clocks = <&clk_dp>; 369 + reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; 370 + interrupt-parent = <&gpio4>; 371 + interrupts = <29 IRQ_TYPE_EDGE_RISING>; 372 + toshiba,hpd-pin = <0>; 373 + status = "disabled"; 374 + 375 + ports { 376 + #address-cells = <1>; 377 + #size-cells = <0>; 378 + 379 + port@0 { 380 + reg = <0>; 381 + 382 + dp_dsi_in: endpoint { 383 + data-lanes = <1 2 3 4>; 384 + }; 385 + }; 386 + }; 387 + }; 388 + }; 389 + 390 + &lpuart1 { 391 + pinctrl-names = "default"; 392 + pinctrl-0 = <&pinctrl_uart1>; 393 + status = "okay"; 394 + }; 395 + 396 + &lpuart2 { 397 + pinctrl-names = "default"; 398 + pinctrl-0 = <&pinctrl_uart2>; 399 + linux,rs485-enabled-at-boot-time; 400 + status = "okay"; 401 + }; 402 + 403 + /* disabled per default, console for M33 */ 404 + &lpuart3 { 405 + pinctrl-names = "default"; 406 + pinctrl-0 = <&pinctrl_uart3>; 407 + status = "disabled"; 408 + }; 409 + 410 + &lpuart6 { 411 + pinctrl-names = "default"; 412 + pinctrl-0 = <&pinctrl_uart6>; 413 + status = "okay"; 414 + }; 415 + 416 + &lpuart8 { 417 + pinctrl-names = "default"; 418 + pinctrl-0 = <&pinctrl_uart8>; 419 + status = "okay"; 420 + }; 421 + 422 + &pcf85063 { 423 + /* RTC_EVENT# is connected on MBa93xxLA */ 424 + pinctrl-names = "default"; 425 + pinctrl-0 = <&pinctrl_pcf85063>; 426 + interrupt-parent = <&gpio1>; 427 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 428 + }; 429 + 430 + &tpm5 { 431 + pinctrl-names = "default"; 432 + pinctrl-0 = <&pinctrl_tpm5>; 433 + }; 434 + 435 + &usdhc2 { 436 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 437 + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; 438 + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 439 + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 440 + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 441 + vmmc-supply = <&reg_usdhc2_vmmc>; 442 + bus-width = <4>; 443 + no-sdio; 444 + no-mmc; 445 + disable-wp; 446 + status = "okay"; 447 + }; 448 + 449 + &iomuxc { 450 + pinctrl_eqos: eqosgrp { 451 + fsl,pins = < 452 + /* PD | FSEL_2 | DSE X4 */ 453 + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e 454 + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e 455 + /* PD | FSEL_2 | DSE X6 */ 456 + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 457 + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 458 + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 459 + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 460 + /* PD | FSEL_3 | DSE X6 */ 461 + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 462 + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 463 + /* PD | FSEL_2 | DSE X4 */ 464 + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e 465 + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e 466 + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e 467 + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e 468 + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e 469 + /* PD | FSEL_3 | DSE X3 */ 470 + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 471 + >; 472 + }; 473 + 474 + pinctrl_eqos_phy: eqosphygrp { 475 + fsl,pins = < 476 + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306 477 + >; 478 + }; 479 + 480 + pinctrl_fec: fecgrp { 481 + fsl,pins = < 482 + /* PD | FSEL_2 | DSE X4 */ 483 + MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e 484 + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e 485 + /* PD | FSEL_2 | DSE X6 */ 486 + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 487 + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 488 + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 489 + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 490 + /* PD | FSEL_3 | DSE X6 */ 491 + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 492 + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 493 + /* PD | FSEL_2 | DSE X4 */ 494 + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e 495 + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e 496 + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e 497 + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e 498 + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e 499 + /* PD | FSEL_3 | DSE X3 */ 500 + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 501 + >; 502 + }; 503 + 504 + pinctrl_fec_phy: fecphygrp { 505 + fsl,pins = < 506 + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306 507 + >; 508 + }; 509 + 510 + pinctrl_flexcan1: flexcan1grp { 511 + fsl,pins = < 512 + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 513 + MX93_PAD_PDM_CLK__CAN1_TX 0x139e 514 + >; 515 + }; 516 + 517 + pinctrl_flexcan2: flexcan2grp { 518 + fsl,pins = < 519 + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 520 + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 521 + >; 522 + }; 523 + 524 + pinctrl_lpi2c3: lpi2c3grp { 525 + fsl,pins = < 526 + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 527 + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 528 + >; 529 + }; 530 + 531 + pinctrl_lpi2c5: lpi2c5grp { 532 + fsl,pins = < 533 + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 534 + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 535 + >; 536 + }; 537 + 538 + pinctrl_pcf85063: pcf85063grp { 539 + fsl,pins = < 540 + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1306 541 + >; 542 + }; 543 + 544 + pinctrl_pexp_irq: pexpirqgrp { 545 + fsl,pins = < 546 + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306 547 + >; 548 + }; 549 + 550 + pinctrl_tc9595: tc9595-grp { 551 + fsl,pins = < 552 + /* DP_IRQ */ 553 + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1306 554 + >; 555 + }; 556 + 557 + pinctrl_tpm5: tpm5grp { 558 + fsl,pins = < 559 + MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e 560 + >; 561 + }; 562 + 563 + pinctrl_typec: typecgrp { 564 + fsl,pins = < 565 + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306 566 + >; 567 + }; 568 + 569 + pinctrl_uart1: uart1grp { 570 + fsl,pins = < 571 + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 572 + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 573 + >; 574 + }; 575 + 576 + pinctrl_uart2: uart2grp { 577 + fsl,pins = < 578 + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e 579 + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e 580 + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x31e 581 + >; 582 + }; 583 + 584 + pinctrl_uart3: uart3grp { 585 + fsl,pins = < 586 + MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e 587 + MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e 588 + >; 589 + }; 590 + 591 + pinctrl_uart6: uart6grp { 592 + fsl,pins = < 593 + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e 594 + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e 595 + >; 596 + }; 597 + 598 + pinctrl_uart8: uart8grp { 599 + fsl,pins = < 600 + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e 601 + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e 602 + >; 603 + }; 604 + 605 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 606 + fsl,pins = < 607 + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 608 + >; 609 + }; 610 + 611 + pinctrl_usdhc2_hs: usdhc2hsgrp { 612 + fsl,pins = < 613 + /* HYS | PD | PU | FSEL_3 | DSE X5 */ 614 + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be 615 + /* HYS | PD | PU | FSEL_3 | DSE X4 */ 616 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 617 + /* HYS | PD | PU | FSEL_3 | DSE X3 */ 618 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 619 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 620 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 621 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 622 + /* PD | PU | FSEL_2 | DSE X3 */ 623 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e 624 + >; 625 + }; 626 + 627 + pinctrl_usdhc2_uhs: usdhc2uhsgrp { 628 + fsl,pins = < 629 + /* HYS | PD | PU | FSEL_3 | DSE X6 */ 630 + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe 631 + /* HYS | PD | PU | FSEL_3 | DSE X4 */ 632 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 633 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e 634 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e 635 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 636 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 637 + /* PD | PU | FSEL_2 | DSE X3 */ 638 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e 639 + >; 640 + }; 641 + };

+213

arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2 + /* 3 + * Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 + * D-82229 Seefeld, Germany. 5 + * Author: Markus Niebel 6 + */ 7 + 8 + #include "imx93.dtsi" 9 + 10 + /{ 11 + model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM"; 12 + compatible = "tq,imx93-tqma9352", "fsl,imx93"; 13 + 14 + reserved-memory { 15 + #address-cells = <2>; 16 + #size-cells = <2>; 17 + ranges; 18 + 19 + linux,cma { 20 + compatible = "shared-dma-pool"; 21 + reusable; 22 + alloc-ranges = <0 0x60000000 0 0x40000000>; 23 + size = <0 0x10000000>; 24 + linux,cma-default; 25 + }; 26 + }; 27 + 28 + reg_v1v8: regulator-v1v8 { 29 + compatible = "regulator-fixed"; 30 + regulator-name = "V_1V8"; 31 + regulator-min-microvolt = <1800000>; 32 + regulator-max-microvolt = <1800000>; 33 + }; 34 + 35 + reg_v3v3: regulator-v3v3 { 36 + compatible = "regulator-fixed"; 37 + regulator-name = "V_3V3"; 38 + regulator-min-microvolt = <3300000>; 39 + regulator-max-microvolt = <3300000>; 40 + }; 41 + 42 + /* SD2 RST# via PMIC SW_EN */ 43 + reg_usdhc2_vmmc: regulator-usdhc2 { 44 + compatible = "regulator-fixed"; 45 + pinctrl-names = "default"; 46 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 47 + regulator-name = "VSD_3V3"; 48 + regulator-min-microvolt = <3300000>; 49 + regulator-max-microvolt = <3300000>; 50 + vin-supply = <&reg_v3v3>; 51 + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 52 + enable-active-high; 53 + }; 54 + }; 55 + 56 + &adc1 { 57 + vref-supply = <&reg_v1v8>; 58 + }; 59 + 60 + &flexspi1 { 61 + pinctrl-names = "default"; 62 + pinctrl-0 = <&pinctrl_flexspi1>; 63 + status = "okay"; 64 + 65 + flash0: flash@0 { 66 + compatible = "jedec,spi-nor"; 67 + reg = <0>; 68 + /* 69 + * no DQS, RXCLKSRC internal loop back, max 66 MHz 70 + * clk framework uses CLK_DIVIDER_ROUND_CLOSEST 71 + * selected value together with root from 72 + * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to 73 + * respect the maximum value. 74 + */ 75 + spi-max-frequency = <62000000>; 76 + spi-tx-bus-width = <4>; 77 + spi-rx-bus-width = <4>; 78 + }; 79 + }; 80 + 81 + &gpio1 { 82 + pmic-irq-hog { 83 + gpio-hog; 84 + gpios = <2 GPIO_ACTIVE_LOW>; 85 + input; 86 + line-name = "PMIC_IRQ#"; 87 + }; 88 + }; 89 + 90 + &lpi2c1 { 91 + clock-frequency = <400000>; 92 + pinctrl-names = "default", "sleep"; 93 + pinctrl-0 = <&pinctrl_lpi2c1>; 94 + pinctrl-1 = <&pinctrl_lpi2c1>; 95 + status = "okay"; 96 + 97 + se97_som: temperature-sensor@1b { 98 + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 99 + reg = <0x1b>; 100 + }; 101 + 102 + pcf85063: rtc@51 { 103 + compatible = "nxp,pcf85063a"; 104 + reg = <0x51>; 105 + quartz-load-femtofarads = <7000>; 106 + }; 107 + 108 + eeprom0: eeprom@53 { 109 + compatible = "nxp,se97b", "atmel,24c02"; 110 + reg = <0x53>; 111 + pagesize = <16>; 112 + read-only; 113 + vcc-supply = <&reg_v3v3>; 114 + }; 115 + 116 + eeprom1: eeprom@57 { 117 + compatible = "atmel,24c64"; 118 + reg = <0x57>; 119 + pagesize = <32>; 120 + vcc-supply = <&reg_v3v3>; 121 + }; 122 + 123 + /* protectable identification memory (part of M24C64-D @57) */ 124 + eeprom@5f { 125 + compatible = "st,24c64", "atmel,24c64"; 126 + reg = <0x5f>; 127 + size = <32>; 128 + pagesize = <32>; 129 + vcc-supply = <&reg_v3v3>; 130 + }; 131 + 132 + imu@6a { 133 + compatible = "st,ism330dhcx"; 134 + reg = <0x6a>; 135 + vdd-supply = <&reg_v3v3>; 136 + vddio-supply = <&reg_v3v3>; 137 + }; 138 + }; 139 + 140 + &usdhc1 { 141 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 142 + pinctrl-0 = <&pinctrl_usdhc1>; 143 + pinctrl-1 = <&pinctrl_usdhc1>; 144 + pinctrl-2 = <&pinctrl_usdhc1>; 145 + bus-width = <8>; 146 + non-removable; 147 + no-sdio; 148 + no-sd; 149 + status = "okay"; 150 + }; 151 + 152 + &wdog3 { 153 + pinctrl-names = "default"; 154 + pinctrl-0 = <&pinctrl_wdog>; 155 + status = "okay"; 156 + }; 157 + 158 + &iomuxc { 159 + pinctrl_flexspi1: flexspi1grp { 160 + fsl,pins = < 161 + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe 162 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe 163 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe 164 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe 165 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe 166 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe 167 + >; 168 + }; 169 + 170 + pinctrl_lpi2c1: lpi2c1grp { 171 + fsl,pins = < 172 + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 173 + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 174 + >; 175 + }; 176 + 177 + pinctrl_pca9451: pca9451grp { 178 + fsl,pins = < 179 + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1306 180 + >; 181 + }; 182 + 183 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 184 + fsl,pins = < 185 + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x1306 186 + >; 187 + }; 188 + 189 + pinctrl_usdhc1: usdhc1grp { 190 + fsl,pins = < 191 + /* HYS | PU | PD | FSEL_3 | X5 */ 192 + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 193 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17be 194 + /* HYS | PU | FSEL_3 | X5 */ 195 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13be 196 + /* HYS | PU | FSEL_3 | X4 */ 197 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x139e 198 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x139e 199 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x139e 200 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x139e 201 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x139e 202 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x139e 203 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x139e 204 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x139e 205 + >; 206 + }; 207 + 208 + pinctrl_wdog: wdoggrp { 209 + fsl,pins = < 210 + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 211 + >; 212 + }; 213 + };

+70 -11

arch/arm64/boot/dts/freescale/imx93.dtsi

··· 8 8 #include <dt-bindings/input/input.h> 9 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 10 #include <dt-bindings/power/fsl,imx93-power.h> 11 + #include <dt-bindings/thermal/thermal.h> 11 12 12 13 #include "imx93-pinfunc.h" 13 14 ··· 133 132 interrupt-parent = <&gic>; 134 133 }; 135 134 135 + thermal-zones { 136 + cpu-thermal { 137 + polling-delay-passive = <250>; 138 + polling-delay = <2000>; 139 + 140 + thermal-sensors = <&tmu 0>; 141 + 142 + trips { 143 + cpu_alert: cpu-alert { 144 + temperature = <80000>; 145 + hysteresis = <2000>; 146 + type = "passive"; 147 + }; 148 + 149 + cpu_crit: cpu-crit { 150 + temperature = <90000>; 151 + hysteresis = <2000>; 152 + type = "critical"; 153 + }; 154 + }; 155 + 156 + cooling-maps { 157 + map0 { 158 + trip = <&cpu_alert>; 159 + cooling-device = 160 + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161 + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 162 + }; 163 + }; 164 + }; 165 + }; 166 + 167 + cm33: remoteproc-cm33 { 168 + compatible = "fsl,imx93-cm33"; 169 + clocks = <&clk IMX93_CLK_CM33_GATE>; 170 + status = "disabled"; 171 + }; 172 + 136 173 soc@0 { 137 174 compatible = "simple-bus"; 138 175 #address-cells = <1>; ··· 291 252 }; 292 253 293 254 lpuart1: serial@44380000 { 294 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 255 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 295 256 reg = <0x44380000 0x1000>; 296 257 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 297 258 clocks = <&clk IMX93_CLK_LPUART1_GATE>; ··· 300 261 }; 301 262 302 263 lpuart2: serial@44390000 { 303 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 264 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 304 265 reg = <0x44390000 0x1000>; 305 266 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 306 267 clocks = <&clk IMX93_CLK_LPUART2_GATE>; ··· 381 342 compatible = "fsl,imx93-anatop", "syscon"; 382 343 reg = <0x44480000 0x10000>; 383 344 }; 345 + 346 + tmu: tmu@44482000 { 347 + compatible = "fsl,qoriq-tmu"; 348 + reg = <0x44482000 0x1000>; 349 + clocks = <&clk IMX93_CLK_TMC_GATE>; 350 + little-endian; 351 + fsl,tmu-range = <0x800000da 0x800000e9 352 + 0x80000102 0x8000012a 353 + 0x80000166 0x800001a7 354 + 0x800001b6>; 355 + fsl,tmu-calibration = <0x00000000 0x0000000e 356 + 0x00000001 0x00000029 357 + 0x00000002 0x00000056 358 + 0x00000003 0x000000a2 359 + 0x00000004 0x00000116 360 + 0x00000005 0x00000195 361 + 0x00000006 0x000001b2>; 362 + #thermal-sensor-cells = <1>; 363 + }; 364 + 384 365 385 366 adc1: adc@44530000 { 386 367 compatible = "nxp,imx93-adc"; ··· 545 486 }; 546 487 547 488 lpuart3: serial@42570000 { 548 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 489 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 549 490 reg = <0x42570000 0x1000>; 550 491 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 551 492 clocks = <&clk IMX93_CLK_LPUART3_GATE>; ··· 554 495 }; 555 496 556 497 lpuart4: serial@42580000 { 557 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 498 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 558 499 reg = <0x42580000 0x1000>; 559 500 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 560 501 clocks = <&clk IMX93_CLK_LPUART4_GATE>; ··· 563 504 }; 564 505 565 506 lpuart5: serial@42590000 { 566 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 507 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 567 508 reg = <0x42590000 0x1000>; 568 509 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 569 510 clocks = <&clk IMX93_CLK_LPUART5_GATE>; ··· 572 513 }; 573 514 574 515 lpuart6: serial@425a0000 { 575 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 516 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 576 517 reg = <0x425a0000 0x1000>; 577 518 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 578 519 clocks = <&clk IMX93_CLK_LPUART6_GATE>; ··· 610 551 }; 611 552 612 553 lpuart7: serial@42690000 { 613 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 554 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 614 555 reg = <0x42690000 0x1000>; 615 556 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 616 557 clocks = <&clk IMX93_CLK_LPUART7_GATE>; ··· 619 560 }; 620 561 621 562 lpuart8: serial@426a0000 { 622 - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 563 + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 623 564 reg = <0x426a0000 0x1000>; 624 565 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 625 566 clocks = <&clk IMX93_CLK_LPUART8_GATE>; ··· 742 683 clock-names = "ipg", "ahb", "per"; 743 684 bus-width = <8>; 744 685 fsl,tuning-start-tap = <20>; 745 - fsl,tuning-step= <2>; 686 + fsl,tuning-step = <2>; 746 687 status = "disabled"; 747 688 }; 748 689 ··· 756 697 clock-names = "ipg", "ahb", "per"; 757 698 bus-width = <4>; 758 699 fsl,tuning-start-tap = <20>; 759 - fsl,tuning-step= <2>; 700 + fsl,tuning-step = <2>; 760 701 status = "disabled"; 761 702 }; 762 703 ··· 819 760 clock-names = "ipg", "ahb", "per"; 820 761 bus-width = <4>; 821 762 fsl,tuning-start-tap = <20>; 822 - fsl,tuning-step= <2>; 763 + fsl,tuning-step = <2>; 823 764 status = "disabled"; 824 765 }; 825 766 };

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