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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Some minor fixes from Intel and a radeon fix.

I have the nouveau fix for the i2c regression queued for next week,
its mostly a revert and seems to work on the system it was originally
introduced for thanks to some i2c core changes."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon: clarify and extend wb setup on APUs and NI+ asics
drm/i915: enable dip before writing data on gen4
fixing dmi match for hp t5745 and hp st5747 thin client
drm/i915: Only enable IPS polling for gen5
drm/i915: Do not read non-existent DPLL registers on PCH hardware

+23 -14
+3
drivers/gpu/drm/i915/i915_debugfs.c
··· 1224 1224 unsigned long temp, chipset, gfx; 1225 1225 int ret; 1226 1226 1227 + if (!IS_GEN5(dev)) 1228 + return -ENODEV; 1229 + 1227 1230 ret = mutex_lock_interruptible(&dev->struct_mutex); 1228 1231 if (ret) 1229 1232 return ret;
+10 -5
drivers/gpu/drm/i915/i915_dma.c
··· 1701 1701 unsigned long diffms; 1702 1702 u32 count; 1703 1703 1704 + if (dev_priv->info->gen != 5) 1705 + return; 1706 + 1704 1707 getrawmonotonic(&now); 1705 1708 diff1 = timespec_sub(now, dev_priv->last_time2); 1706 1709 ··· 2124 2121 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, 2125 2122 (unsigned long) dev); 2126 2123 2127 - spin_lock(&mchdev_lock); 2128 - i915_mch_dev = dev_priv; 2129 - dev_priv->mchdev_lock = &mchdev_lock; 2130 - spin_unlock(&mchdev_lock); 2124 + if (IS_GEN5(dev)) { 2125 + spin_lock(&mchdev_lock); 2126 + i915_mch_dev = dev_priv; 2127 + dev_priv->mchdev_lock = &mchdev_lock; 2128 + spin_unlock(&mchdev_lock); 2131 2129 2132 - ips_ping_for_i915_load(); 2130 + ips_ping_for_i915_load(); 2131 + } 2133 2132 2134 2133 return 0; 2135 2134
+5 -4
drivers/gpu/drm/i915/intel_display.c
··· 7072 7072 struct drm_device *dev = crtc->dev; 7073 7073 drm_i915_private_t *dev_priv = dev->dev_private; 7074 7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7075 - int pipe = intel_crtc->pipe; 7076 - int dpll_reg = DPLL(pipe); 7077 - int dpll = I915_READ(dpll_reg); 7078 7075 7079 7076 if (HAS_PCH_SPLIT(dev)) 7080 7077 return; ··· 7084 7087 * the manual case. 7085 7088 */ 7086 7089 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 7090 + int pipe = intel_crtc->pipe; 7091 + int dpll_reg = DPLL(pipe); 7092 + u32 dpll; 7093 + 7087 7094 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 7088 7095 7089 7096 assert_panel_unlocked(dev_priv, pipe); 7090 7097 7098 + dpll = I915_READ(dpll_reg); 7091 7099 dpll |= DISPLAY_RATE_SELECT_FPA1; 7092 7100 I915_WRITE(dpll_reg, dpll); 7093 7101 intel_wait_for_vblank(dev, pipe); ··· 7100 7098 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 7101 7099 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 7102 7100 } 7103 - 7104 7101 } 7105 7102 7106 7103 /**
+1 -1
drivers/gpu/drm/i915/intel_hdmi.c
··· 136 136 137 137 val &= ~VIDEO_DIP_SELECT_MASK; 138 138 139 - I915_WRITE(VIDEO_DIP_CTL, val | port | flags); 139 + I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 140 140 141 141 for (i = 0; i < len; i += 4) { 142 142 I915_WRITE(VIDEO_DIP_DATA, *data);
+2 -2
drivers/gpu/drm/i915/intel_lvds.c
··· 750 750 .ident = "Hewlett-Packard t5745", 751 751 .matches = { 752 752 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 753 - DMI_MATCH(DMI_BOARD_NAME, "hp t5745"), 753 + DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 754 754 }, 755 755 }, 756 756 { ··· 758 758 .ident = "Hewlett-Packard st5747", 759 759 .matches = { 760 760 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 761 - DMI_MATCH(DMI_BOARD_NAME, "hp st5747"), 761 + DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 762 762 }, 763 763 }, 764 764 {
+2 -2
drivers/gpu/drm/radeon/radeon_device.c
··· 241 241 rdev->wb.use_event = true; 242 242 } 243 243 } 244 - /* always use writeback/events on NI */ 245 - if (ASIC_IS_DCE5(rdev)) { 244 + /* always use writeback/events on NI, APUs */ 245 + if (rdev->family >= CHIP_PALM) { 246 246 rdev->wb.enabled = true; 247 247 rdev->wb.use_event = true; 248 248 }