Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'mlx5_ipoib_qpn' into rdma.git for-next
Michael Guralnik says:
====================
This series handles IPoIB child interface creation with setting
interface's HW address.
In current implementation, lladdr requested by user is ignored and
overwritten. Child interface gets the same GID as the parent interface and
a QP number which is assigned by the underlying drivers.
In this series we fix this behavior so that user's requested address is
assigned to the newly created interface.
As specific QP number request is not supported for all vendors, QP number
requested by user will still be overwritten when this is not supported.
Behavior of creation of child interfaces through the sysfs mechanism or
without specifying a requested address, stays the same.
====================
Based on the mlx5-next branch at
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
due to dependencies.
* branch 'mlx5_ipoib_qpn':
RDMA/ipoib: Handle user-supplied address when creating child
net/mlx5: Enable QP number request when creating IPoIB underlay QP
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+59
-29
+9
-2
drivers/infiniband/ulp/ipoib/ipoib_main.c
+9
-2
drivers/infiniband/ulp/ipoib/ipoib_main.c
···
1892
1892
1893
1893
priv->max_ib_mtu = ppriv->max_ib_mtu;
1894
1894
set_bit(IPOIB_FLAG_SUBINTERFACE, &priv->flags);
1895
-
memcpy(priv->dev->dev_addr, ppriv->dev->dev_addr, INFINIBAND_ALEN);
1896
-
memcpy(&priv->local_gid, &ppriv->local_gid, sizeof(priv->local_gid));
1895
+
if (memchr_inv(priv->dev->dev_addr, 0, INFINIBAND_ALEN))
1896
+
memcpy(&priv->local_gid, priv->dev->dev_addr + 4,
1897
+
sizeof(priv->local_gid));
1898
+
else {
1899
+
memcpy(priv->dev->dev_addr, ppriv->dev->dev_addr,
1900
+
INFINIBAND_ALEN);
1901
+
memcpy(&priv->local_gid, &ppriv->local_gid,
1902
+
sizeof(priv->local_gid));
1903
+
}
1897
1904
}
1898
1905
1899
1906
static int ipoib_ndo_init(struct net_device *ndev)
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h
···
19
19
20
20
#define MLX5E_KTLS_PROGRESS_WQE_SZ \
21
21
(offsetof(struct mlx5e_tx_wqe, tls_progress_params_ctx) + \
22
-
MLX5_ST_SZ_BYTES(tls_progress_params))
22
+
sizeof(struct mlx5_wqe_tls_progress_params_seg))
23
23
#define MLX5E_KTLS_PROGRESS_WQEBBS \
24
24
(DIV_ROUND_UP(MLX5E_KTLS_PROGRESS_WQE_SZ, MLX5_SEND_WQE_BB))
25
25
+9
-5
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c
+9
-5
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c
···
64
64
cseg->qpn_ds = cpu_to_be32((sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
65
65
STATIC_PARAMS_DS_CNT);
66
66
cseg->fm_ce_se = fence ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;
67
-
cseg->tisn = cpu_to_be32(priv_tx->tisn << 8);
67
+
cseg->tis_tir_num = cpu_to_be32(priv_tx->tisn << 8);
68
68
69
69
ucseg->flags = MLX5_UMR_INLINE;
70
70
ucseg->bsf_octowords = cpu_to_be16(MLX5_ST_SZ_BYTES(tls_static_params) / 16);
···
75
75
static void
76
76
fill_progress_params_ctx(void *ctx, struct mlx5e_ktls_offload_context_tx *priv_tx)
77
77
{
78
-
MLX5_SET(tls_progress_params, ctx, tisn, priv_tx->tisn);
79
-
MLX5_SET(tls_progress_params, ctx, record_tracker_state,
78
+
struct mlx5_wqe_tls_progress_params_seg *params;
79
+
80
+
params = ctx;
81
+
82
+
params->tis_tir_num = cpu_to_be32(priv_tx->tisn);
83
+
MLX5_SET(tls_progress_params, params->ctx, record_tracker_state,
80
84
MLX5E_TLS_PROGRESS_PARAMS_RECORD_TRACKER_STATE_START);
81
-
MLX5_SET(tls_progress_params, ctx, auth_state,
85
+
MLX5_SET(tls_progress_params, params->ctx, auth_state,
82
86
MLX5E_TLS_PROGRESS_PARAMS_AUTH_STATE_NO_OFFLOAD);
83
87
}
84
88
···
288
284
289
285
cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_DUMP);
290
286
cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
291
-
cseg->tisn = cpu_to_be32(tisn << 8);
287
+
cseg->tis_tir_num = cpu_to_be32(tisn << 8);
292
288
cseg->fm_ce_se = first ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;
293
289
294
290
fsz = skb_frag_size(frag);
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c
···
305
305
void mlx5e_tls_handle_tx_wqe(struct mlx5e_txqsq *sq, struct mlx5_wqe_ctrl_seg *cseg,
306
306
struct mlx5e_accel_tx_tls_state *state)
307
307
{
308
-
cseg->tisn = cpu_to_be32(state->tls_tisn << 8);
308
+
cseg->tis_tir_num = cpu_to_be32(state->tls_tisn << 8);
309
309
}
310
310
311
311
static int tls_update_resync_sn(struct net_device *netdev,
-10
drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
-10
drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
···
44
44
#include "lib/mpfs.h"
45
45
#include "en/tc_ct.h"
46
46
47
-
#define FDB_TC_MAX_CHAIN 3
48
-
#define FDB_FT_CHAIN (FDB_TC_MAX_CHAIN + 1)
49
-
#define FDB_TC_SLOW_PATH_CHAIN (FDB_FT_CHAIN + 1)
50
-
51
-
/* The index of the last real chain (FT) + 1 as chain zero is valid as well */
52
-
#define FDB_NUM_CHAINS (FDB_FT_CHAIN + 1)
53
-
54
-
#define FDB_TC_MAX_PRIO 16
55
-
#define FDB_TC_LEVELS_PER_PRIO 2
56
-
57
47
#ifdef CONFIG_MLX5_ESWITCH
58
48
59
49
#define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15
-1
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
-1
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
+10
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
+10
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
···
39
39
#include <linux/llist.h>
40
40
#include <steering/fs_dr.h>
41
41
42
+
#define FDB_TC_MAX_CHAIN 3
43
+
#define FDB_FT_CHAIN (FDB_TC_MAX_CHAIN + 1)
44
+
#define FDB_TC_SLOW_PATH_CHAIN (FDB_FT_CHAIN + 1)
45
+
46
+
/* The index of the last real chain (FT) + 1 as chain zero is valid as well */
47
+
#define FDB_NUM_CHAINS (FDB_FT_CHAIN + 1)
48
+
49
+
#define FDB_TC_MAX_PRIO 16
50
+
#define FDB_TC_LEVELS_PER_PRIO 2
51
+
42
52
struct mlx5_modify_hdr {
43
53
enum mlx5_flow_namespace_type ns_type;
44
54
union {
+7
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
+7
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
···
226
226
227
227
int mlx5i_create_underlay_qp(struct mlx5e_priv *priv)
228
228
{
229
+
unsigned char *dev_addr = priv->netdev->dev_addr;
229
230
u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
230
231
u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {};
231
232
struct mlx5i_priv *ipriv = priv->ppriv;
232
233
void *addr_path;
234
+
int qpn = 0;
233
235
int ret = 0;
234
236
void *qpc;
237
+
238
+
if (MLX5_CAP_GEN(priv->mdev, mkey_by_name)) {
239
+
qpn = (dev_addr[1] << 16) + (dev_addr[2] << 8) + dev_addr[3];
240
+
MLX5_SET(create_qp_in, in, input_qpn, qpn);
241
+
}
235
242
236
243
qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
237
244
MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD);
+3
drivers/net/ethernet/mellanox/mlx5/core/main.c
+3
drivers/net/ethernet/mellanox/mlx5/core/main.c
···
557
557
if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
558
558
MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
559
559
560
+
if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
561
+
MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
562
+
560
563
return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
561
564
}
562
565
-1
include/linux/mlx5/cq.h
-1
include/linux/mlx5/cq.h
+9
include/linux/mlx5/device.h
+9
include/linux/mlx5/device.h
···
458
458
MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
459
459
};
460
460
461
+
struct mlx5_wqe_tls_static_params_seg {
462
+
u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
463
+
};
464
+
465
+
struct mlx5_wqe_tls_progress_params_seg {
466
+
__be32 tis_tir_num;
467
+
u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
468
+
};
469
+
461
470
enum {
462
471
MLX5_SET_PORT_RESET_QKEY = 0,
463
472
MLX5_SET_PORT_GUID0 = 16,
+8
-6
include/linux/mlx5/mlx5_ifc.h
+8
-6
include/linux/mlx5/mlx5_ifc.h
···
1392
1392
u8 bf[0x1];
1393
1393
u8 driver_version[0x1];
1394
1394
u8 pad_tx_eth_packet[0x1];
1395
-
u8 reserved_at_263[0x8];
1395
+
u8 reserved_at_263[0x3];
1396
+
u8 mkey_by_name[0x1];
1397
+
u8 reserved_at_267[0x4];
1398
+
1396
1399
u8 log_bf_reg_size[0x5];
1397
1400
1398
1401
u8 reserved_at_270[0x8];
···
7715
7712
u8 reserved_at_20[0x10];
7716
7713
u8 op_mod[0x10];
7717
7714
7718
-
u8 reserved_at_40[0x40];
7715
+
u8 reserved_at_40[0x8];
7716
+
u8 input_qpn[0x18];
7719
7717
7718
+
u8 reserved_at_60[0x20];
7720
7719
u8 opt_param_mask[0x20];
7721
7720
7722
7721
u8 ece[0x20];
···
10643
10638
};
10644
10639
10645
10640
struct mlx5_ifc_tls_progress_params_bits {
10646
-
u8 reserved_at_0[0x8];
10647
-
u8 tisn[0x18];
10648
-
10649
10641
u8 next_record_tcp_sn[0x20];
10650
10642
10651
10643
u8 hw_resync_tcp_sn[0x20];
10652
10644
10653
10645
u8 record_tracker_state[0x2];
10654
10646
u8 auth_state[0x2];
10655
-
u8 reserved_at_64[0x4];
10647
+
u8 reserved_at_44[0x4];
10656
10648
u8 hw_offset_record_number[0x18];
10657
10649
};
10658
10650