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drm/msm/dsi: Print dual-DSI-adjusted pclk instead of original mode pclk

When dual-DSI (bonded DSI) was added in commit ed9976a09b48
("drm/msm/dsi: adjust dsi timing for dual dsi mode") some DBG() prints
were not updated, leading to print the original mode->clock rather
than the adjusted (typically the mode clock divided by two, though more
recently also adjusted for DSC compression) msm_host->pixel_clk_rate
which is passed to clk_set_rate() just below. Fix that by printing the
actual pixel_clk_rate that is being set.

Fixes: ed9976a09b48 ("drm/msm/dsi: adjust dsi timing for dual dsi mode")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/589896/
Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-1-78ae3ee9a697@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Marijn Suijten and committed by
Dmitry Baryshkov f12e0e12 87d322e9

+5 -5
+5 -5
drivers/gpu/drm/msm/dsi/dsi_host.c
··· 356 356 { 357 357 int ret; 358 358 359 - DBG("Set clk rates: pclk=%d, byteclk=%lu", 360 - msm_host->mode->clock, msm_host->byte_clk_rate); 359 + DBG("Set clk rates: pclk=%lu, byteclk=%lu", 360 + msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 361 361 362 362 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 363 363 msm_host->byte_clk_rate); ··· 430 430 { 431 431 int ret; 432 432 433 - DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 434 - msm_host->mode->clock, msm_host->byte_clk_rate, 435 - msm_host->esc_clk_rate, msm_host->src_clk_rate); 433 + DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 434 + msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 435 + msm_host->esc_clk_rate, msm_host->src_clk_rate); 436 436 437 437 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 438 438 if (ret) {