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Merge patch series "Add support for Allwinner D1 CAN controllers"
John Watts <contact@jookia.org> says:
This patch series adds support for the Allwinner D1 CAN controllers.
It requires adding a new device tree compatible and driver support to
work around some hardware quirks.
This has been tested on the Mango Pi MQ Dual running a T113 and a
Lichee Panel 86 running a D1.
Changes in v2:
- Re-ordered patches to work with bisecting
- Fixed device tree label underscores
- Fixed email headers
- Link to v1: https://lore.kernel.org/all/20230715112523.2533742-1-contact@jookia.org
Link: https://lore.kernel.org/all/20230721221552.1973203-2-contact@jookia.org
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+55
-7
+4
-2
Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml
+4
-2
Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml
···
21
21
- const: allwinner,sun4i-a10-can
22
22
- const: allwinner,sun4i-a10-can
23
23
- const: allwinner,sun8i-r40-can
24
+
- const: allwinner,sun20i-d1-can
24
25
25
26
reg:
26
27
maxItems: 1
···
38
37
if:
39
38
properties:
40
39
compatible:
41
-
contains:
42
-
const: allwinner,sun8i-r40-can
40
+
enum:
41
+
- allwinner,sun8i-r40-can
42
+
- allwinner,sun20i-d1-can
43
43
44
44
then:
45
45
required:
+30
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+30
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
···
131
131
pins = "PB6", "PB7";
132
132
function = "uart3";
133
133
};
134
+
135
+
/omit-if-no-ref/
136
+
can0_pins: can0-pins {
137
+
pins = "PB2", "PB3";
138
+
function = "can0";
139
+
};
140
+
141
+
/omit-if-no-ref/
142
+
can1_pins: can1-pins {
143
+
pins = "PB4", "PB5";
144
+
function = "can1";
145
+
};
134
146
};
135
147
136
148
ccu: clock-controller@2001000 {
···
890
878
<&r_ccu CLK_R_AHB>;
891
879
clock-names = "bus", "hosc", "ahb";
892
880
#clock-cells = <1>;
881
+
};
882
+
883
+
can0: can@2504000 {
884
+
compatible = "allwinner,sun20i-d1-can";
885
+
reg = <0x02504000 0x400>;
886
+
interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
887
+
clocks = <&ccu CLK_BUS_CAN0>;
888
+
resets = <&ccu RST_BUS_CAN0>;
889
+
status = "disabled";
890
+
};
891
+
892
+
can1: can@2504400 {
893
+
compatible = "allwinner,sun20i-d1-can";
894
+
reg = <0x02504400 0x400>;
895
+
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
896
+
clocks = <&ccu CLK_BUS_CAN1>;
897
+
resets = <&ccu RST_BUS_CAN1>;
898
+
status = "disabled";
893
899
};
894
900
};
895
901
};
+2
-2
drivers/net/can/Kconfig
+2
-2
drivers/net/can/Kconfig
···
190
190
191
191
config CAN_SUN4I
192
192
tristate "Allwinner A10 CAN controller"
193
-
depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
193
+
depends on MACH_SUN4I || MACH_SUN7I || RISCV || COMPILE_TEST
194
194
help
195
195
Say Y here if you want to use CAN controller found on Allwinner
196
-
A10/A20 SoCs.
196
+
A10/A20/D1 SoCs.
197
197
198
198
To compile this driver as a module, choose M here: the module will
199
199
be called sun4i_can.
+19
-3
drivers/net/can/sun4i_can.c
+19
-3
drivers/net/can/sun4i_can.c
···
91
91
#define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */
92
92
#define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */
93
93
#define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */
94
+
#define SUN4I_REG_ACPC_ADDR_D1 0x0028 /* CAN Acceptance Code 0 on the D1 */
95
+
#define SUN4I_REG_ACPM_ADDR_D1 0x002C /* CAN Acceptance Mask 0 on the D1 */
94
96
#define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */
95
97
#define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */
96
98
···
207
205
* struct sun4ican_quirks - Differences between SoC variants.
208
206
*
209
207
* @has_reset: SoC needs reset deasserted.
208
+
* @acp_offset: Offset of ACPC and ACPM registers
210
209
*/
211
210
struct sun4ican_quirks {
212
211
bool has_reset;
212
+
int acp_offset;
213
213
};
214
214
215
215
struct sun4ican_priv {
···
220
216
struct clk *clk;
221
217
struct reset_control *reset;
222
218
spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */
219
+
int acp_offset;
223
220
};
224
221
225
222
static const struct can_bittiming_const sun4ican_bittiming_const = {
···
343
338
}
344
339
345
340
/* set filters - we accept all */
346
-
writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
347
-
writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
341
+
writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv->acp_offset);
342
+
writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv->acp_offset);
348
343
349
344
/* clear error counters and error code capture */
350
345
writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
···
773
768
774
769
static const struct sun4ican_quirks sun4ican_quirks_a10 = {
775
770
.has_reset = false,
771
+
.acp_offset = 0,
776
772
};
777
773
778
774
static const struct sun4ican_quirks sun4ican_quirks_r40 = {
779
775
.has_reset = true,
776
+
.acp_offset = 0,
777
+
};
778
+
779
+
static const struct sun4ican_quirks sun4ican_quirks_d1 = {
780
+
.has_reset = true,
781
+
.acp_offset = (SUN4I_REG_ACPC_ADDR_D1 - SUN4I_REG_ACPC_ADDR),
780
782
};
781
783
782
784
static const struct of_device_id sun4ican_of_match[] = {
···
796
784
}, {
797
785
.compatible = "allwinner,sun8i-r40-can",
798
786
.data = &sun4ican_quirks_r40
787
+
}, {
788
+
.compatible = "allwinner,sun20i-d1-can",
789
+
.data = &sun4ican_quirks_d1
799
790
}, {
800
791
/* sentinel */
801
792
},
···
885
870
priv->base = addr;
886
871
priv->clk = clk;
887
872
priv->reset = reset;
873
+
priv->acp_offset = quirks->acp_offset;
888
874
spin_lock_init(&priv->cmdreg_lock);
889
875
890
876
platform_set_drvdata(pdev, dev);
···
923
907
MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
924
908
MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
925
909
MODULE_LICENSE("Dual BSD/GPL");
926
-
MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");
910
+
MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20/D1)");