Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
[MIPS] SNI: MIPS_CPU_IRQ_BASE cleanup
Use MIPS_CPU_IRQ_BASE instead of own define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Thomas Bogendoerfer
and committed by
Ralf Baechle
f13cc01d
3dac2561
+13
-14
+2
-2
arch/mips/sni/pcimt.c
+2
-2
arch/mips/sni/pcimt.c
···
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u32 pending = (read_c0_cause() & read_c0_status());
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if (pending & C_IRQ5)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 7);
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else if (pending & C_IRQ4)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 6);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 6);
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else if (pending & C_IRQ3)
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pcimt_hwint3();
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else if (pending & C_IRQ1)
+6
-6
arch/mips/sni/pcit.c
+6
-6
arch/mips/sni/pcit.c
···
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if (pending & C_IRQ1)
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pcit_hwint1();
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else if (pending & C_IRQ2)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 4);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 4);
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else if (pending & C_IRQ3)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 5);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 5);
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else if (pending & C_IRQ5)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);
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do_IRQ (MIPS_CPU_IRQ_BASE + 7);
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}
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static void sni_pcit_hwint_cplus(void)
···
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if (pending & C_IRQ0)
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pcit_hwint0();
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else if (pending & C_IRQ2)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 4);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 4);
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else if (pending & C_IRQ3)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 5);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 5);
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else if (pending & C_IRQ5)
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-
do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);
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+
do_IRQ (MIPS_CPU_IRQ_BASE + 7);
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}
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void __init sni_pcit_irq_init(void)
+1
-1
arch/mips/sni/rm200.c
+1
-1
arch/mips/sni/rm200.c
+4
-5
include/asm-mips/sni.h
+4
-5
include/asm-mips/sni.h
···
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#define A20R_PT_TIM0_ACK 0xbc050000
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#define A20R_PT_TIM1_ACK 0xbc060000
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-
#define SNI_MIPS_IRQ_CPU_BASE 16
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#define SNI_MIPS_IRQ_CPU_TIMER (SNI_MIPS_IRQ_CPU_BASE+7)
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#define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
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-
#define SNI_A20R_IRQ_BASE SNI_MIPS_IRQ_CPU_BASE
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#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
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#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
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#define SNI_DS1216_A20R_BASE 0xbc081ffc
···
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#define SNI_PCIT_INT_START 24
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#define SNI_PCIT_INT_END 30
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-
#define PCIT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE + 5)
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+
#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
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#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
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#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
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#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
···
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#define PCIMT_IRQ_EISA 29
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#define PCIMT_IRQ_SCSI 30
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-
#define PCIMT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE+6)
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#define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
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#if 0
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#define PCIMT_IRQ_TEMPERATURE 24