tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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crypto: qat - update firmware api

Update the firmware API to have partial decomp as an argument.
Modify the firmware descriptor to support auto-select best and partial
decompress.
Define the maximal auto-select best value.
Define the mask and bit position for the partial decompress field in the
firmware descriptor.

Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Suman Kumar Chakraborty and committed by
Herbert Xu f14a2de5 0fdc836a

+22 -4
+2 -1
drivers/crypto/intel/qat/qat_common/adf_dc.c
··· 46 46 ICP_QAT_FW_COMP_NO_XXHASH_ACC, 47 47 ICP_QAT_FW_COMP_CNV_ERROR_NONE, 48 48 ICP_QAT_FW_COMP_NO_APPEND_CRC, 49 - ICP_QAT_FW_COMP_NO_DROP_DATA); 49 + ICP_QAT_FW_COMP_NO_DROP_DATA, 50 + ICP_QAT_FW_COMP_NO_PARTIAL_DECOMPRESS); 50 51 ICP_QAT_FW_COMN_NEXT_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR); 51 52 ICP_QAT_FW_COMN_CURR_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_COMP); 52 53
+20 -3
drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.h
··· 44 44 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1 45 45 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7 46 46 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1 47 + #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MAX_VALUE 0xFFFFFFFF 47 48 48 49 #define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \ 49 50 ret_uncomp, secure_ram) \ ··· 118 117 #define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \ 119 118 cnvdfx, crc, xxhash_acc, \ 120 119 cnv_error_type, append_crc, \ 121 - drop_data) \ 120 + drop_data, partial_decomp) \ 122 121 ((((sop) & ICP_QAT_FW_COMP_SOP_MASK) << \ 123 122 ICP_QAT_FW_COMP_SOP_BITPOS) | \ 124 123 (((eop) & ICP_QAT_FW_COMP_EOP_MASK) << \ ··· 140 139 (((append_crc) & ICP_QAT_FW_COMP_APPEND_CRC_MASK) \ 141 140 << ICP_QAT_FW_COMP_APPEND_CRC_BITPOS) | \ 142 141 (((drop_data) & ICP_QAT_FW_COMP_DROP_DATA_MASK) \ 143 - << ICP_QAT_FW_COMP_DROP_DATA_BITPOS)) 142 + << ICP_QAT_FW_COMP_DROP_DATA_BITPOS) | \ 143 + (((partial_decomp) & ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK) \ 144 + << ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS)) 144 145 145 146 #define ICP_QAT_FW_COMP_NOT_SOP 0 146 147 #define ICP_QAT_FW_COMP_SOP 1 ··· 164 161 #define ICP_QAT_FW_COMP_NO_APPEND_CRC 0 165 162 #define ICP_QAT_FW_COMP_DROP_DATA 1 166 163 #define ICP_QAT_FW_COMP_NO_DROP_DATA 0 164 + #define ICP_QAT_FW_COMP_PARTIAL_DECOMPRESS 1 165 + #define ICP_QAT_FW_COMP_NO_PARTIAL_DECOMPRESS 0 167 166 #define ICP_QAT_FW_COMP_SOP_BITPOS 0 168 167 #define ICP_QAT_FW_COMP_SOP_MASK 0x1 169 168 #define ICP_QAT_FW_COMP_EOP_BITPOS 1 ··· 194 189 #define ICP_QAT_FW_COMP_APPEND_CRC_MASK 0x1 195 190 #define ICP_QAT_FW_COMP_DROP_DATA_BITPOS 25 196 191 #define ICP_QAT_FW_COMP_DROP_DATA_MASK 0x1 192 + #define ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS 27 193 + #define ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK 0x1 197 194 198 195 #define ICP_QAT_FW_COMP_SOP_GET(flags) \ 199 196 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SOP_BITPOS, \ ··· 288 281 union { 289 282 struct icp_qat_fw_xlt_req_params xlt_pars; 290 283 __u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2]; 284 + struct { 285 + __u32 partial_decompress_length; 286 + __u32 partial_decompress_offset; 287 + } partial_decompress; 291 288 } u1; 292 - __u32 resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2]; 289 + union { 290 + __u32 resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2]; 291 + struct { 292 + __u32 asb_value; 293 + __u32 reserved; 294 + } asb_threshold; 295 + } u3; 293 296 struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl; 294 297 union { 295 298 struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;