Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/vga: Clean up VGA registers even if VGA plane is disabled
Turns out at least some systems (eg. HSW Lenovo ThinkCentre E73)
configure the VGA registers even when booting in UEFI mode. So
in order to avoid any issues with the MSR register we should
clean up the VGA registers anyway.
For now this mostly avoids the potential for unclaimed register
accesses due to the power well vs. MDA/CGA selection. But this
will become more important soon as we'll start to rely on the
MSR register to control VGA memory decode as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251208182637.334-7-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
+25
-11
+25
-11
drivers/gpu/drm/i915/display/intel_vga.c
+25
-11
drivers/gpu/drm/i915/display/intel_vga.c
···
63
63
{
64
64
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
65
65
i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
66
-
enum pipe pipe;
67
66
u8 msr, sr1;
68
67
u32 tmp;
69
68
···
78
79
}
79
80
80
81
tmp = intel_de_read(display, vga_reg);
81
-
if (tmp & VGA_DISP_DISABLE)
82
-
return;
83
82
84
-
if (display->platform.cherryview)
85
-
pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp);
86
-
else if (has_vga_pipe_sel(display))
87
-
pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp);
88
-
else
89
-
pipe = PIPE_A;
83
+
if ((tmp & VGA_DISP_DISABLE) == 0) {
84
+
enum pipe pipe;
90
85
91
-
drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n",
92
-
pipe_name(pipe));
86
+
if (display->platform.cherryview)
87
+
pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp);
88
+
else if (has_vga_pipe_sel(display))
89
+
pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp);
90
+
else
91
+
pipe = PIPE_A;
92
+
93
+
drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n",
94
+
pipe_name(pipe));
95
+
} else {
96
+
drm_dbg_kms(display->drm, "VGA plane is disabled\n");
97
+
98
+
/*
99
+
* Unfortunately at least some BIOSes (eg. HSW Lenovo
100
+
* ThinkCentre E73) set up the VGA registers even when
101
+
* in UEFI mode with the VGA plane disabled. So we need to
102
+
* always clean up the mess for iGPUs. For discrete GPUs we
103
+
* don't really care about the state of the VGA registers
104
+
* since all VGA accesses can be blocked via the bridge.
105
+
*/
106
+
if (display->platform.dgfx)
107
+
goto reset_vgacntr;
108
+
}
93
109
94
110
/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
95
111
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);