Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C2440: fix section mismatch on mini2440
ARM: S3C24XX: drop return codes in void function of dma.c
ARM: S3C24XX: don't use uninitialized variable in dma.c
ARM: EXYNOS4: Set appropriate I2C device variant
ARM: S5PC100: Fix for compilation error
spi/s3c64xx: Bug fix for SPI with different FIFO level
ARM: SAMSUNG: Add tx_st_done variable
ARM: EXYNOS4: Address a section mismatch w/ suspend issue.
ARM: S5P: Fix bug on init of PWMTimers for HRTimer
ARM: SAMSUNG: header file revised to prevent declaring duplicated
ARM: EXYNOS4: fix improper gpio configuration
ARM: EXYNOS4: Fix card detection for sdhci 0 and 2
+37
-23
+6
arch/arm/mach-exynos4/cpu.c
+6
arch/arm/mach-exynos4/cpu.c
···
23
23
#include <plat/sdhci.h>
24
24
#include <plat/devs.h>
25
25
#include <plat/fimc-core.h>
26
+
#include <plat/iic-core.h>
26
27
27
28
#include <mach/regs-irq.h>
28
29
···
133
132
s3c_fimc_setname(1, "exynos4-fimc");
134
133
s3c_fimc_setname(2, "exynos4-fimc");
135
134
s3c_fimc_setname(3, "exynos4-fimc");
135
+
136
+
/* The I2C bus controllers are directly compatible with s3c2440 */
137
+
s3c_i2c0_setname("s3c2440-i2c");
138
+
s3c_i2c1_setname("s3c2440-i2c");
139
+
s3c_i2c2_setname("s3c2440-i2c");
136
140
}
137
141
138
142
void __init exynos4_init_clocks(int xtal)
+1
-1
arch/arm/mach-exynos4/dev-audio.c
+1
-1
arch/arm/mach-exynos4/dev-audio.c
+1
-1
arch/arm/mach-exynos4/headsmp.S
+1
-1
arch/arm/mach-exynos4/headsmp.S
+2
-6
arch/arm/mach-exynos4/mach-smdkv310.c
+2
-6
arch/arm/mach-exynos4/mach-smdkv310.c
···
78
78
};
79
79
80
80
static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
81
-
.cd_type = S3C_SDHCI_CD_GPIO,
82
-
.ext_cd_gpio = EXYNOS4_GPK0(2),
83
-
.ext_cd_gpio_invert = 1,
81
+
.cd_type = S3C_SDHCI_CD_INTERNAL,
84
82
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
85
83
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
86
84
.max_width = 8,
···
94
96
};
95
97
96
98
static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
97
-
.cd_type = S3C_SDHCI_CD_GPIO,
98
-
.ext_cd_gpio = EXYNOS4_GPK2(2),
99
-
.ext_cd_gpio_invert = 1,
99
+
.cd_type = S3C_SDHCI_CD_INTERNAL,
100
100
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101
101
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102
102
.max_width = 8,
+1
-1
arch/arm/mach-s3c2440/mach-mini2440.c
+1
-1
arch/arm/mach-s3c2440/mach-mini2440.c
+2
arch/arm/mach-s3c64xx/dev-spi.c
+2
arch/arm/mach-s3c64xx/dev-spi.c
···
88
88
.cfg_gpio = s3c64xx_spi_cfg_gpio,
89
89
.fifo_lvl_mask = 0x7f,
90
90
.rx_lvl_offset = 13,
91
+
.tx_st_done = 21,
91
92
};
92
93
93
94
static u64 spi_dmamask = DMA_BIT_MASK(32);
···
133
132
.cfg_gpio = s3c64xx_spi_cfg_gpio,
134
133
.fifo_lvl_mask = 0x7f,
135
134
.rx_lvl_offset = 13,
135
+
.tx_st_done = 21,
136
136
};
137
137
138
138
struct platform_device s3c64xx_device_spi1 = {
+4
arch/arm/mach-s5p64x0/dev-spi.c
+4
arch/arm/mach-s5p64x0/dev-spi.c
···
112
112
.cfg_gpio = s5p6440_spi_cfg_gpio,
113
113
.fifo_lvl_mask = 0x1ff,
114
114
.rx_lvl_offset = 15,
115
+
.tx_st_done = 25,
115
116
};
116
117
117
118
static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
118
119
.cfg_gpio = s5p6450_spi_cfg_gpio,
119
120
.fifo_lvl_mask = 0x1ff,
120
121
.rx_lvl_offset = 15,
122
+
.tx_st_done = 25,
121
123
};
122
124
123
125
static u64 spi_dmamask = DMA_BIT_MASK(32);
···
162
160
.cfg_gpio = s5p6440_spi_cfg_gpio,
163
161
.fifo_lvl_mask = 0x7f,
164
162
.rx_lvl_offset = 15,
163
+
.tx_st_done = 25,
165
164
};
166
165
167
166
static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
168
167
.cfg_gpio = s5p6450_spi_cfg_gpio,
169
168
.fifo_lvl_mask = 0x7f,
170
169
.rx_lvl_offset = 15,
170
+
.tx_st_done = 25,
171
171
};
172
172
173
173
struct platform_device s5p64x0_device_spi1 = {
+4
arch/arm/mach-s5pc100/dev-spi.c
+4
arch/arm/mach-s5pc100/dev-spi.c
···
15
15
#include <mach/dma.h>
16
16
#include <mach/map.h>
17
17
#include <mach/spi-clocks.h>
18
+
#include <mach/irqs.h>
18
19
19
20
#include <plat/s3c64xx-spi.h>
20
21
#include <plat/gpio-cfg.h>
···
91
90
.fifo_lvl_mask = 0x7f,
92
91
.rx_lvl_offset = 13,
93
92
.high_speed = 1,
93
+
.tx_st_done = 21,
94
94
};
95
95
96
96
static u64 spi_dmamask = DMA_BIT_MASK(32);
···
136
134
.fifo_lvl_mask = 0x7f,
137
135
.rx_lvl_offset = 13,
138
136
.high_speed = 1,
137
+
.tx_st_done = 21,
139
138
};
140
139
141
140
struct platform_device s5pc100_device_spi1 = {
···
179
176
.fifo_lvl_mask = 0x7f,
180
177
.rx_lvl_offset = 13,
181
178
.high_speed = 1,
179
+
.tx_st_done = 21,
182
180
};
183
181
184
182
struct platform_device s5pc100_device_spi2 = {
+2
arch/arm/mach-s5pv210/dev-spi.c
+2
arch/arm/mach-s5pv210/dev-spi.c
···
85
85
.fifo_lvl_mask = 0x1ff,
86
86
.rx_lvl_offset = 15,
87
87
.high_speed = 1,
88
+
.tx_st_done = 25,
88
89
};
89
90
90
91
static u64 spi_dmamask = DMA_BIT_MASK(32);
···
130
129
.fifo_lvl_mask = 0x7f,
131
130
.rx_lvl_offset = 15,
132
131
.high_speed = 1,
132
+
.tx_st_done = 25,
133
133
};
134
134
135
135
struct platform_device s5pv210_device_spi1 = {
+3
-9
arch/arm/plat-s3c24xx/dma.c
+3
-9
arch/arm/plat-s3c24xx/dma.c
···
1027
1027
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1028
1028
unsigned int dcon;
1029
1029
1030
-
pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1031
-
__func__, channel, xferunit, dcon);
1030
+
pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
1032
1031
1033
1032
if (chan == NULL)
1034
1033
return -EINVAL;
1035
1034
1036
-
pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1037
-
1038
1035
dcon = chan->dcon & dma_sel.dcon_mask;
1039
-
1040
-
pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1036
+
pr_debug("%s: dcon is %08x\n", __func__, dcon);
1041
1037
1042
1038
switch (chan->req_ch) {
1043
1039
case DMACH_I2S_IN:
···
1231
1235
/* restore channel's hardware configuration */
1232
1236
1233
1237
if (!cp->in_use)
1234
-
return 0;
1238
+
return;
1235
1239
1236
1240
printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1237
1241
···
1242
1246
1243
1247
if (cp->map != NULL)
1244
1248
dma_sel.select(cp, cp->map);
1245
-
1246
-
return 0;
1247
1249
}
1248
1250
1249
1251
static void s3c2410_dma_resume(void)
+2
-2
arch/arm/plat-s5p/s5p-time.c
+2
-2
arch/arm/plat-s5p/s5p-time.c
···
370
370
371
371
clock_rate = clk_get_rate(tin_source);
372
372
373
-
init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
374
-
375
373
s5p_time_setup(timer_source.source_id, TCNT_MAX);
376
374
s5p_time_start(timer_source.source_id, PERIODIC);
375
+
376
+
init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
377
377
378
378
if (clocksource_register_hz(&time_clocksource, clock_rate))
379
379
panic("%s: can't register clocksource\n", time_clocksource.name);
+6
arch/arm/plat-samsung/include/plat/devs.h
+6
arch/arm/plat-samsung/include/plat/devs.h
···
12
12
* it under the terms of the GNU General Public License version 2 as
13
13
* published by the Free Software Foundation.
14
14
*/
15
+
16
+
#ifndef __PLAT_DEVS_H
17
+
#define __PLAT_DEVS_H __FILE__
18
+
15
19
#include <linux/platform_device.h>
16
20
17
21
struct s3c24xx_uart_resources {
···
163
159
*/
164
160
extern void *s3c_set_platdata(void *pd, size_t pdsize,
165
161
struct platform_device *pdev);
162
+
163
+
#endif /* __PLAT_DEVS_H */
+2
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+2
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
···
39
39
* @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
40
40
* @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
41
41
* @high_speed: If the controller supports HIGH_SPEED_EN bit
42
+
* @tx_st_done: Depends on tx fifo_lvl field
42
43
*/
43
44
struct s3c64xx_spi_info {
44
45
int src_clk_nr;
···
54
53
int fifo_lvl_mask;
55
54
int rx_lvl_offset;
56
55
int high_speed;
56
+
int tx_st_done;
57
57
};
58
58
59
59
/**
+1
-3
drivers/spi/spi_s3c64xx.c
+1
-3
drivers/spi/spi_s3c64xx.c
···
116
116
(((i)->fifo_lvl_mask + 1))) \
117
117
? 1 : 0)
118
118
119
-
#define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \
120
-
(((i)->fifo_lvl_mask + 1) << 1)) \
121
-
? 1 : 0)
119
+
#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
122
120
#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
123
121
#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
124
122