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Merge tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes

mvebu fixes for 6.17 (part 1)

Fix SATA ports on various boards: Macchiatobin, CN913x-solidrun.
Fix audio on Armada 370 DB and OpenRD.
Disable eMMC high-speed modes on the CN9132 CEX-7 module.
Disable runtime reconfiguration for PCIe lanes on the CN9132 CEX-7 module.

* tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes
arm64: dts: marvell: cn913x-solidrun: fix sata ports status
ARM: dts: kirkwood: Fix sound DAI cells for OpenRD clients
ARM64: dts: mcbin: fix SATA ports on Macchiatobin
ARM: dts: armada-370-db: Fix stereo audio input routing on Armada 370

Link: https://lore.kernel.org/r/87ikhnn1pl.fsf@BLaptop.bootlin.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann f1a43af7 875691ce

+36 -13
+1 -1
arch/arm/boot/dts/marvell/armada-370-db.dts
··· 119 119 "Out Jack", "HPL", 120 120 "Out Jack", "HPR", 121 121 "AIN1L", "In Jack", 122 - "AIN1L", "In Jack"; 122 + "AIN1R", "In Jack"; 123 123 status = "okay"; 124 124 125 125 simple-audio-card,dai-link@0 {
+1 -1
arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts
··· 38 38 simple-audio-card,mclk-fs = <256>; 39 39 40 40 simple-audio-card,cpu { 41 - sound-dai = <&audio0 0>; 41 + sound-dai = <&audio0>; 42 42 }; 43 43 44 44 simple-audio-card,codec {
+2
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
··· 345 345 /* CPS Lane 1 - U32 */ 346 346 sata-port@0 { 347 347 phys = <&cp1_comphy1 0>; 348 + status = "okay"; 348 349 }; 349 350 350 351 /* CPS Lane 3 - U31 */ 351 352 sata-port@1 { 352 353 phys = <&cp1_comphy3 1>; 354 + status = "okay"; 353 355 }; 354 356 }; 355 357
+4 -3
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
··· 152 152 153 153 /* SRDS #0 - SATA on M.2 connector */ 154 154 &cp0_sata0 { 155 - phys = <&cp0_comphy0 1>; 156 155 status = "okay"; 157 156 158 - /* only port 1 is available */ 159 - /delete-node/ sata-port@0; 157 + sata-port@1 { 158 + phys = <&cp0_comphy0 1>; 159 + status = "okay"; 160 + }; 160 161 }; 161 162 162 163 /* microSD */
+4 -2
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
··· 563 563 564 564 /* SRDS #1 - SATA on M.2 (J44) */ 565 565 &cp1_sata0 { 566 - phys = <&cp1_comphy1 0>; 567 566 status = "okay"; 568 567 569 568 /* only port 0 is available */ 570 - /delete-node/ sata-port@1; 569 + sata-port@0 { 570 + phys = <&cp1_comphy1 0>; 571 + status = "okay"; 572 + }; 571 573 }; 572 574 573 575 &cp1_syscon0 {
+16 -6
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
··· 413 413 /* SRDS #0,#1,#2,#3 - PCIe */ 414 414 &cp0_pcie0 { 415 415 num-lanes = <4>; 416 - phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; 416 + /* 417 + * The mvebu-comphy driver does not currently know how to pass correct 418 + * lane-count to ATF while configuring the serdes lanes. 419 + * Rely on bootloader configuration only. 420 + * 421 + * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; 422 + */ 417 423 status = "okay"; 418 424 }; 419 425 ··· 481 475 /* SRDS #0,#1 - PCIe */ 482 476 &cp1_pcie0 { 483 477 num-lanes = <2>; 484 - phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; 478 + /* 479 + * The mvebu-comphy driver does not currently know how to pass correct 480 + * lane-count to ATF while configuring the serdes lanes. 481 + * Rely on bootloader configuration only. 482 + * 483 + * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; 484 + */ 485 485 status = "okay"; 486 486 }; 487 487 ··· 524 512 status = "okay"; 525 513 526 514 /* only port 1 is available */ 527 - /delete-node/ sata-port@0; 528 - 529 515 sata-port@1 { 530 516 phys = <&cp1_comphy3 1>; 517 + status = "okay"; 531 518 }; 532 519 }; 533 520 ··· 642 631 status = "okay"; 643 632 644 633 /* only port 1 is available */ 645 - /delete-node/ sata-port@0; 646 - 647 634 sata-port@1 { 635 + status = "okay"; 648 636 phys = <&cp2_comphy3 1>; 649 637 }; 650 638 };
+8
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
··· 137 137 pinctrl-0 = <&ap_mmc0_pins>; 138 138 pinctrl-names = "default"; 139 139 vqmmc-supply = <&v_1_8>; 140 + /* 141 + * Not stable in HS modes - phy needs "more calibration", so disable 142 + * UHS (by preventing voltage switch), SDR104, SDR50 and DDR50 modes. 143 + */ 144 + no-1-8-v; 145 + no-sd; 146 + no-sdio; 147 + non-removable; 140 148 status = "okay"; 141 149 }; 142 150