Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue
Tony Nguyen says:
====================
Intel Wired LAN Driver Updates 2023-11-27 (i40e, iavf)
This series contains updates to i40e and iavf drivers.
Ivan Vecera performs more cleanups on i40e and iavf drivers; removing
unused fields, defines, and unneeded fields.
Petr Oros utilizes iavf_schedule_aq_request() helper to replace open
coded equivalents.
* '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
iavf: use iavf_schedule_aq_request() helper
iavf: Remove queue tracking fields from iavf_adminq_ring
i40e: Remove queue tracking fields from i40e_adminq_ring
i40e: Remove AQ register definitions for VF types
i40e: Delete unused and useless i40e_pf fields
====================
Link: https://lore.kernel.org/r/20231127211037.1135403-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+90
-200
-16
drivers/net/ethernet/intel/i40e/i40e.h
-16
drivers/net/ethernet/intel/i40e/i40e.h
···
468
468
struct i40e_hw hw;
469
469
DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
470
470
struct msix_entry *msix_entries;
471
-
bool fc_autoneg_status;
472
471
473
-
u16 eeprom_version;
474
472
u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
475
473
u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
476
474
u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
···
484
486
u16 rss_size_max; /* HW defined max RSS queues */
485
487
u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
486
488
u16 num_alloc_vsi; /* num VSIs this driver supports */
487
-
u8 atr_sample_rate;
488
489
bool wol_en;
489
490
490
491
struct hlist_head fdir_filter_list;
···
521
524
struct hlist_head cloud_filter_list;
522
525
u16 num_cloud_filters;
523
526
524
-
enum i40e_interrupt_policy int_policy;
525
527
u16 rx_itr_default;
526
528
u16 tx_itr_default;
527
529
u32 msg_enable;
528
530
char int_name[I40E_INT_NAME_STR_LEN];
529
-
u16 adminq_work_limit; /* num of admin receive queue desc to process */
530
531
unsigned long service_timer_period;
531
532
unsigned long service_timer_previous;
532
533
struct timer_list service_timer;
···
538
543
u32 tx_timeout_count;
539
544
u32 tx_timeout_recovery_level;
540
545
unsigned long tx_timeout_last_recovery;
541
-
u32 tx_sluggish_count;
542
546
u32 hw_csum_rx_error;
543
547
u32 led_status;
544
548
u16 corer_count; /* Core reset count */
···
559
565
struct i40e_lump_tracking *irq_pile;
560
566
561
567
/* switch config info */
562
-
u16 pf_seid;
563
568
u16 main_vsi_seid;
564
569
u16 mac_seid;
565
-
struct kobject *switch_kobj;
566
570
#ifdef CONFIG_DEBUG_FS
567
571
struct dentry *i40e_dbg_pf;
568
572
#endif /* CONFIG_DEBUG_FS */
569
573
bool cur_promisc;
570
-
571
-
u16 instance; /* A unique number per i40e_pf instance in the system */
572
574
573
575
/* sr-iov config info */
574
576
struct i40e_vf *vf;
···
659
669
unsigned long ptp_tx_start;
660
670
struct hwtstamp_config tstamp_config;
661
671
struct timespec64 ptp_prev_hw_time;
662
-
struct work_struct ptp_pps_work;
663
672
struct work_struct ptp_extts0_work;
664
-
struct work_struct ptp_extts1_work;
665
673
ktime_t ptp_reset_start;
666
674
struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
667
675
u32 ptp_adj_mult;
···
667
679
u32 tx_hwtstamp_skipped;
668
680
u32 rx_hwtstamp_cleared;
669
681
u32 latch_event_flags;
670
-
u64 ptp_pps_start;
671
-
u32 pps_delay;
672
682
spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
673
-
struct ptp_pin_desc ptp_pin[3];
674
683
unsigned long latch_events[4];
675
684
bool ptp_tx;
676
685
bool ptp_rx;
···
680
695
u32 fd_inv;
681
696
u16 phy_led_val;
682
697
683
-
u16 override_q_count;
684
698
u16 last_sw_conf_flags;
685
699
u16 last_sw_conf_valid_flags;
686
700
/* List to keep previous DDP profiles to be rolled back in the future */
+31
-55
drivers/net/ethernet/intel/i40e/i40e_adminq.c
+31
-55
drivers/net/ethernet/intel/i40e/i40e_adminq.c
···
9
9
static void i40e_resume_aq(struct i40e_hw *hw);
10
10
11
11
/**
12
-
* i40e_adminq_init_regs - Initialize AdminQ registers
13
-
* @hw: pointer to the hardware structure
14
-
*
15
-
* This assumes the alloc_asq and alloc_arq functions have already been called
16
-
**/
17
-
static void i40e_adminq_init_regs(struct i40e_hw *hw)
18
-
{
19
-
/* set head and tail registers in our local struct */
20
-
hw->aq.asq.tail = I40E_PF_ATQT;
21
-
hw->aq.asq.head = I40E_PF_ATQH;
22
-
hw->aq.asq.len = I40E_PF_ATQLEN;
23
-
hw->aq.asq.bal = I40E_PF_ATQBAL;
24
-
hw->aq.asq.bah = I40E_PF_ATQBAH;
25
-
hw->aq.arq.tail = I40E_PF_ARQT;
26
-
hw->aq.arq.head = I40E_PF_ARQH;
27
-
hw->aq.arq.len = I40E_PF_ARQLEN;
28
-
hw->aq.arq.bal = I40E_PF_ARQBAL;
29
-
hw->aq.arq.bah = I40E_PF_ARQBAH;
30
-
}
31
-
32
-
/**
33
12
* i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
34
13
* @hw: pointer to the hardware structure
35
14
**/
···
233
254
u32 reg = 0;
234
255
235
256
/* Clear Head and Tail */
236
-
wr32(hw, hw->aq.asq.head, 0);
237
-
wr32(hw, hw->aq.asq.tail, 0);
257
+
wr32(hw, I40E_PF_ATQH, 0);
258
+
wr32(hw, I40E_PF_ATQT, 0);
238
259
239
260
/* set starting point */
240
-
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
261
+
wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
241
262
I40E_PF_ATQLEN_ATQENABLE_MASK));
242
-
wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
243
-
wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
263
+
wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw->aq.asq.desc_buf.pa));
264
+
wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw->aq.asq.desc_buf.pa));
244
265
245
266
/* Check one register to verify that config was applied */
246
-
reg = rd32(hw, hw->aq.asq.bal);
267
+
reg = rd32(hw, I40E_PF_ATQBAL);
247
268
if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
248
269
ret_code = -EIO;
249
270
···
262
283
u32 reg = 0;
263
284
264
285
/* Clear Head and Tail */
265
-
wr32(hw, hw->aq.arq.head, 0);
266
-
wr32(hw, hw->aq.arq.tail, 0);
286
+
wr32(hw, I40E_PF_ARQH, 0);
287
+
wr32(hw, I40E_PF_ARQT, 0);
267
288
268
289
/* set starting point */
269
-
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
290
+
wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
270
291
I40E_PF_ARQLEN_ARQENABLE_MASK));
271
-
wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
272
-
wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
292
+
wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw->aq.arq.desc_buf.pa));
293
+
wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw->aq.arq.desc_buf.pa));
273
294
274
295
/* Update tail in the HW to post pre-allocated buffers */
275
-
wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
296
+
wr32(hw, I40E_PF_ARQT, hw->aq.num_arq_entries - 1);
276
297
277
298
/* Check one register to verify that config was applied */
278
-
reg = rd32(hw, hw->aq.arq.bal);
299
+
reg = rd32(hw, I40E_PF_ARQBAL);
279
300
if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
280
301
ret_code = -EIO;
281
302
···
418
439
}
419
440
420
441
/* Stop firmware AdminQ processing */
421
-
wr32(hw, hw->aq.asq.head, 0);
422
-
wr32(hw, hw->aq.asq.tail, 0);
423
-
wr32(hw, hw->aq.asq.len, 0);
424
-
wr32(hw, hw->aq.asq.bal, 0);
425
-
wr32(hw, hw->aq.asq.bah, 0);
442
+
wr32(hw, I40E_PF_ATQH, 0);
443
+
wr32(hw, I40E_PF_ATQT, 0);
444
+
wr32(hw, I40E_PF_ATQLEN, 0);
445
+
wr32(hw, I40E_PF_ATQBAL, 0);
446
+
wr32(hw, I40E_PF_ATQBAH, 0);
426
447
427
448
hw->aq.asq.count = 0; /* to indicate uninitialized queue */
428
449
···
452
473
}
453
474
454
475
/* Stop firmware AdminQ processing */
455
-
wr32(hw, hw->aq.arq.head, 0);
456
-
wr32(hw, hw->aq.arq.tail, 0);
457
-
wr32(hw, hw->aq.arq.len, 0);
458
-
wr32(hw, hw->aq.arq.bal, 0);
459
-
wr32(hw, hw->aq.arq.bah, 0);
476
+
wr32(hw, I40E_PF_ARQH, 0);
477
+
wr32(hw, I40E_PF_ARQT, 0);
478
+
wr32(hw, I40E_PF_ARQLEN, 0);
479
+
wr32(hw, I40E_PF_ARQBAL, 0);
480
+
wr32(hw, I40E_PF_ARQBAH, 0);
460
481
461
482
hw->aq.arq.count = 0; /* to indicate uninitialized queue */
462
483
···
587
608
goto init_adminq_exit;
588
609
}
589
610
590
-
/* Set up register offsets */
591
-
i40e_adminq_init_regs(hw);
592
-
593
611
/* setup ASQ command write back timeout */
594
612
hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
595
613
···
696
720
697
721
desc = I40E_ADMINQ_DESC(*asq, ntc);
698
722
details = I40E_ADMINQ_DETAILS(*asq, ntc);
699
-
while (rd32(hw, hw->aq.asq.head) != ntc) {
723
+
while (rd32(hw, I40E_PF_ATQH) != ntc) {
700
724
i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
701
-
"ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
725
+
"ntc %d head %d.\n", ntc, rd32(hw, I40E_PF_ATQH));
702
726
703
727
if (details->callback) {
704
728
I40E_ADMINQ_CALLBACK cb_func =
···
732
756
/* AQ designers suggest use of head for better
733
757
* timing reliability than DD bit
734
758
*/
735
-
return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
759
+
return rd32(hw, I40E_PF_ATQH) == hw->aq.asq.next_to_use;
736
760
737
761
}
738
762
···
773
797
774
798
hw->aq.asq_last_status = I40E_AQ_RC_OK;
775
799
776
-
val = rd32(hw, hw->aq.asq.head);
800
+
val = rd32(hw, I40E_PF_ATQH);
777
801
if (val >= hw->aq.num_asq_entries) {
778
802
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
779
803
"AQTX: head overrun at %d\n", val);
···
865
889
if (hw->aq.asq.next_to_use == hw->aq.asq.count)
866
890
hw->aq.asq.next_to_use = 0;
867
891
if (!details->postpone)
868
-
wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
892
+
wr32(hw, I40E_PF_ATQT, hw->aq.asq.next_to_use);
869
893
870
894
/* if cmd_details are not defined or async flag is not set,
871
895
* we need to wait for desc write back
···
925
949
/* update the error if time out occurred */
926
950
if ((!cmd_completed) &&
927
951
(!details->async && !details->postpone)) {
928
-
if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
952
+
if (rd32(hw, I40E_PF_ATQLEN) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
929
953
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
930
954
"AQTX: AQ Critical error.\n");
931
955
status = -EIO;
···
1079
1103
}
1080
1104
1081
1105
/* set next_to_use to head */
1082
-
ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1106
+
ntu = rd32(hw, I40E_PF_ARQH) & I40E_PF_ARQH_ARQH_MASK;
1083
1107
if (ntu == ntc) {
1084
1108
/* nothing to do - shouldn't need to update ring's values */
1085
1109
ret_code = -EALREADY;
···
1127
1151
desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
1128
1152
1129
1153
/* set tail = the last cleaned desc index. */
1130
-
wr32(hw, hw->aq.arq.tail, ntc);
1154
+
wr32(hw, I40E_PF_ARQT, ntc);
1131
1155
/* ntc is updated to tail + 1 */
1132
1156
ntc++;
1133
1157
if (ntc == hw->aq.num_arq_entries)
-7
drivers/net/ethernet/intel/i40e/i40e_adminq.h
-7
drivers/net/ethernet/intel/i40e/i40e_adminq.h
+4
-4
drivers/net/ethernet/intel/i40e/i40e_common.c
+4
-4
drivers/net/ethernet/intel/i40e/i40e_common.c
···
195
195
**/
196
196
bool i40e_check_asq_alive(struct i40e_hw *hw)
197
197
{
198
-
if (hw->aq.asq.len)
199
-
return !!(rd32(hw, hw->aq.asq.len) &
200
-
I40E_PF_ATQLEN_ATQENABLE_MASK);
201
-
else
198
+
/* Check if the queue is initialized */
199
+
if (!hw->aq.asq.count)
202
200
return false;
201
+
202
+
return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK);
203
203
}
204
204
205
205
/**
-3
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
-3
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
···
1028
1028
"emp reset count: %d\n", pf->empr_count);
1029
1029
dev_info(&pf->pdev->dev,
1030
1030
"pf reset count: %d\n", pf->pfr_count);
1031
-
dev_info(&pf->pdev->dev,
1032
-
"pf tx sluggish count: %d\n",
1033
-
pf->tx_sluggish_count);
1034
1031
} else if (strncmp(&cmd_buf[5], "port", 4) == 0) {
1035
1032
struct i40e_aqc_query_port_ets_config_resp *bw_data;
1036
1033
struct i40e_dcbx_config *cfg =
+8
-18
drivers/net/ethernet/intel/i40e/i40e_main.c
+8
-18
drivers/net/ethernet/intel/i40e/i40e_main.c
···
3465
3465
3466
3466
/* some ATR related tx ring init */
3467
3467
if (test_bit(I40E_FLAG_FD_ATR_ENA, vsi->back->flags)) {
3468
-
ring->atr_sample_rate = vsi->back->atr_sample_rate;
3468
+
ring->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
3469
3469
ring->atr_count = 0;
3470
3470
} else {
3471
3471
ring->atr_sample_rate = 0;
···
10127
10127
return;
10128
10128
10129
10129
/* check for error indications */
10130
-
val = rd32(&pf->hw, pf->hw.aq.arq.len);
10130
+
val = rd32(&pf->hw, I40E_PF_ARQLEN);
10131
10131
oldval = val;
10132
10132
if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
10133
10133
if (hw->debug_mask & I40E_DEBUG_AQ)
···
10146
10146
val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
10147
10147
}
10148
10148
if (oldval != val)
10149
-
wr32(&pf->hw, pf->hw.aq.arq.len, val);
10149
+
wr32(&pf->hw, I40E_PF_ARQLEN, val);
10150
10150
10151
-
val = rd32(&pf->hw, pf->hw.aq.asq.len);
10151
+
val = rd32(&pf->hw, I40E_PF_ATQLEN);
10152
10152
oldval = val;
10153
10153
if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
10154
10154
if (pf->hw.debug_mask & I40E_DEBUG_AQ)
···
10166
10166
val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
10167
10167
}
10168
10168
if (oldval != val)
10169
-
wr32(&pf->hw, pf->hw.aq.asq.len, val);
10169
+
wr32(&pf->hw, I40E_PF_ATQLEN, val);
10170
10170
10171
10171
event.buf_len = I40E_MAX_AQ_BUF_SIZE;
10172
10172
event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
···
10226
10226
opcode);
10227
10227
break;
10228
10228
}
10229
-
} while (i++ < pf->adminq_work_limit);
10229
+
} while (i++ < I40E_AQ_WORK_LIMIT);
10230
10230
10231
-
if (i < pf->adminq_work_limit)
10231
+
if (i < I40E_AQ_WORK_LIMIT)
10232
10232
clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state);
10233
10233
10234
10234
/* re-enable Admin queue interrupt cause */
···
12769
12769
if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
12770
12770
(pf->hw.func_caps.fd_filters_best_effort > 0)) {
12771
12771
set_bit(I40E_FLAG_FD_ATR_ENA, pf->flags);
12772
-
pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
12773
12772
if (test_bit(I40E_FLAG_MFP_ENA, pf->flags) &&
12774
12773
pf->hw.num_partitions > 1)
12775
12774
dev_info(&pf->pdev->dev,
···
12814
12815
I40E_MAX_VF_COUNT);
12815
12816
}
12816
12817
#endif /* CONFIG_PCI_IOV */
12817
-
pf->eeprom_version = 0xDEAD;
12818
12818
pf->lan_veb = I40E_NO_VEB;
12819
12819
pf->lan_vsi = I40E_NO_VSI;
12820
12820
···
14974
14976
* the PF's VSI
14975
14977
*/
14976
14978
pf->mac_seid = uplink_seid;
14977
-
pf->pf_seid = downlink_seid;
14978
14979
pf->main_vsi_seid = seid;
14979
14980
if (printconfig)
14980
14981
dev_info(&pf->pdev->dev,
14981
14982
"pf_seid=%d main_vsi_seid=%d\n",
14982
-
pf->pf_seid, pf->main_vsi_seid);
14983
+
downlink_seid, pf->main_vsi_seid);
14983
14984
break;
14984
14985
case I40E_SWITCH_ELEMENT_TYPE_PF:
14985
14986
case I40E_SWITCH_ELEMENT_TYPE_VF:
···
15156
15159
15157
15160
/* fill in link information and enable LSE reporting */
15158
15161
i40e_link_event(pf);
15159
-
15160
-
/* Initialize user-specific link properties */
15161
-
pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
15162
-
I40E_AQ_AN_COMPLETED) ? true : false);
15163
15162
15164
15163
i40e_ptp_init(pf);
15165
15164
···
15630
15637
#endif /* CONFIG_I40E_DCB */
15631
15638
struct i40e_pf *pf;
15632
15639
struct i40e_hw *hw;
15633
-
static u16 pfs_found;
15634
15640
u16 wol_nvm_bits;
15635
15641
char nvm_ver[32];
15636
15642
u16 link_status;
···
15707
15715
hw->bus.device = PCI_SLOT(pdev->devfn);
15708
15716
hw->bus.func = PCI_FUNC(pdev->devfn);
15709
15717
hw->bus.bus_id = pdev->bus->number;
15710
-
pf->instance = pfs_found;
15711
15718
15712
15719
/* Select something other than the 802.1ad ethertype for the
15713
15720
* switch to use internally and drop on ingress.
···
15768
15777
}
15769
15778
hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
15770
15779
hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
15771
-
pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
15772
15780
15773
15781
snprintf(pf->int_name, sizeof(pf->int_name) - 1,
15774
15782
"%s-%s:misc",
-10
drivers/net/ethernet/intel/i40e/i40e_register.h
-10
drivers/net/ethernet/intel/i40e/i40e_register.h
···
863
863
#define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */
864
864
#define I40E_PFPM_WUFC_MAG_SHIFT 1
865
865
#define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)
866
-
#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
867
-
#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
868
-
#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
869
-
#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
870
-
#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
871
-
#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
872
-
#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
873
-
#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
874
-
#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
875
-
#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
876
866
#define I40E_VFQF_HLUT_MAX_INDEX 15
877
867
878
868
+31
-55
drivers/net/ethernet/intel/iavf/iavf_adminq.c
+31
-55
drivers/net/ethernet/intel/iavf/iavf_adminq.c
···
8
8
#include "iavf_prototype.h"
9
9
10
10
/**
11
-
* iavf_adminq_init_regs - Initialize AdminQ registers
12
-
* @hw: pointer to the hardware structure
13
-
*
14
-
* This assumes the alloc_asq and alloc_arq functions have already been called
15
-
**/
16
-
static void iavf_adminq_init_regs(struct iavf_hw *hw)
17
-
{
18
-
/* set head and tail registers in our local struct */
19
-
hw->aq.asq.tail = IAVF_VF_ATQT1;
20
-
hw->aq.asq.head = IAVF_VF_ATQH1;
21
-
hw->aq.asq.len = IAVF_VF_ATQLEN1;
22
-
hw->aq.asq.bal = IAVF_VF_ATQBAL1;
23
-
hw->aq.asq.bah = IAVF_VF_ATQBAH1;
24
-
hw->aq.arq.tail = IAVF_VF_ARQT1;
25
-
hw->aq.arq.head = IAVF_VF_ARQH1;
26
-
hw->aq.arq.len = IAVF_VF_ARQLEN1;
27
-
hw->aq.arq.bal = IAVF_VF_ARQBAL1;
28
-
hw->aq.arq.bah = IAVF_VF_ARQBAH1;
29
-
}
30
-
31
-
/**
32
11
* iavf_alloc_adminq_asq_ring - Allocate Admin Queue send rings
33
12
* @hw: pointer to the hardware structure
34
13
**/
···
238
259
u32 reg = 0;
239
260
240
261
/* Clear Head and Tail */
241
-
wr32(hw, hw->aq.asq.head, 0);
242
-
wr32(hw, hw->aq.asq.tail, 0);
262
+
wr32(hw, IAVF_VF_ATQH1, 0);
263
+
wr32(hw, IAVF_VF_ATQT1, 0);
243
264
244
265
/* set starting point */
245
-
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
266
+
wr32(hw, IAVF_VF_ATQLEN1, (hw->aq.num_asq_entries |
246
267
IAVF_VF_ATQLEN1_ATQENABLE_MASK));
247
-
wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
248
-
wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
268
+
wr32(hw, IAVF_VF_ATQBAL1, lower_32_bits(hw->aq.asq.desc_buf.pa));
269
+
wr32(hw, IAVF_VF_ATQBAH1, upper_32_bits(hw->aq.asq.desc_buf.pa));
249
270
250
271
/* Check one register to verify that config was applied */
251
-
reg = rd32(hw, hw->aq.asq.bal);
272
+
reg = rd32(hw, IAVF_VF_ATQBAL1);
252
273
if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
253
274
ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
254
275
···
267
288
u32 reg = 0;
268
289
269
290
/* Clear Head and Tail */
270
-
wr32(hw, hw->aq.arq.head, 0);
271
-
wr32(hw, hw->aq.arq.tail, 0);
291
+
wr32(hw, IAVF_VF_ARQH1, 0);
292
+
wr32(hw, IAVF_VF_ARQT1, 0);
272
293
273
294
/* set starting point */
274
-
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
295
+
wr32(hw, IAVF_VF_ARQLEN1, (hw->aq.num_arq_entries |
275
296
IAVF_VF_ARQLEN1_ARQENABLE_MASK));
276
-
wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
277
-
wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
297
+
wr32(hw, IAVF_VF_ARQBAL1, lower_32_bits(hw->aq.arq.desc_buf.pa));
298
+
wr32(hw, IAVF_VF_ARQBAH1, upper_32_bits(hw->aq.arq.desc_buf.pa));
278
299
279
300
/* Update tail in the HW to post pre-allocated buffers */
280
-
wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
301
+
wr32(hw, IAVF_VF_ARQT1, hw->aq.num_arq_entries - 1);
281
302
282
303
/* Check one register to verify that config was applied */
283
-
reg = rd32(hw, hw->aq.arq.bal);
304
+
reg = rd32(hw, IAVF_VF_ARQBAL1);
284
305
if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
285
306
ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
286
307
···
434
455
}
435
456
436
457
/* Stop firmware AdminQ processing */
437
-
wr32(hw, hw->aq.asq.head, 0);
438
-
wr32(hw, hw->aq.asq.tail, 0);
439
-
wr32(hw, hw->aq.asq.len, 0);
440
-
wr32(hw, hw->aq.asq.bal, 0);
441
-
wr32(hw, hw->aq.asq.bah, 0);
458
+
wr32(hw, IAVF_VF_ATQH1, 0);
459
+
wr32(hw, IAVF_VF_ATQT1, 0);
460
+
wr32(hw, IAVF_VF_ATQLEN1, 0);
461
+
wr32(hw, IAVF_VF_ATQBAL1, 0);
462
+
wr32(hw, IAVF_VF_ATQBAH1, 0);
442
463
443
464
hw->aq.asq.count = 0; /* to indicate uninitialized queue */
444
465
···
468
489
}
469
490
470
491
/* Stop firmware AdminQ processing */
471
-
wr32(hw, hw->aq.arq.head, 0);
472
-
wr32(hw, hw->aq.arq.tail, 0);
473
-
wr32(hw, hw->aq.arq.len, 0);
474
-
wr32(hw, hw->aq.arq.bal, 0);
475
-
wr32(hw, hw->aq.arq.bah, 0);
492
+
wr32(hw, IAVF_VF_ARQH1, 0);
493
+
wr32(hw, IAVF_VF_ARQT1, 0);
494
+
wr32(hw, IAVF_VF_ARQLEN1, 0);
495
+
wr32(hw, IAVF_VF_ARQBAL1, 0);
496
+
wr32(hw, IAVF_VF_ARQBAH1, 0);
476
497
477
498
hw->aq.arq.count = 0; /* to indicate uninitialized queue */
478
499
···
507
528
ret_code = IAVF_ERR_CONFIG;
508
529
goto init_adminq_exit;
509
530
}
510
-
511
-
/* Set up register offsets */
512
-
iavf_adminq_init_regs(hw);
513
531
514
532
/* setup ASQ command write back timeout */
515
533
hw->aq.asq_cmd_timeout = IAVF_ASQ_CMD_TIMEOUT;
···
563
587
564
588
desc = IAVF_ADMINQ_DESC(*asq, ntc);
565
589
details = IAVF_ADMINQ_DETAILS(*asq, ntc);
566
-
while (rd32(hw, hw->aq.asq.head) != ntc) {
590
+
while (rd32(hw, IAVF_VF_ATQH1) != ntc) {
567
591
iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
568
-
"ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
592
+
"ntc %d head %d.\n", ntc, rd32(hw, IAVF_VF_ATQH1));
569
593
570
594
if (details->callback) {
571
595
IAVF_ADMINQ_CALLBACK cb_func =
···
600
624
/* AQ designers suggest use of head for better
601
625
* timing reliability than DD bit
602
626
*/
603
-
return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
627
+
return rd32(hw, IAVF_VF_ATQH1) == hw->aq.asq.next_to_use;
604
628
}
605
629
606
630
/**
···
639
663
640
664
hw->aq.asq_last_status = IAVF_AQ_RC_OK;
641
665
642
-
val = rd32(hw, hw->aq.asq.head);
666
+
val = rd32(hw, IAVF_VF_ATQH1);
643
667
if (val >= hw->aq.num_asq_entries) {
644
668
iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
645
669
"AQTX: head overrun at %d\n", val);
···
731
755
if (hw->aq.asq.next_to_use == hw->aq.asq.count)
732
756
hw->aq.asq.next_to_use = 0;
733
757
if (!details->postpone)
734
-
wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
758
+
wr32(hw, IAVF_VF_ATQT1, hw->aq.asq.next_to_use);
735
759
736
760
/* if cmd_details are not defined or async flag is not set,
737
761
* we need to wait for desc write back
···
786
810
/* update the error if time out occurred */
787
811
if ((!cmd_completed) &&
788
812
(!details->async && !details->postpone)) {
789
-
if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
813
+
if (rd32(hw, IAVF_VF_ATQLEN1) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
790
814
iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
791
815
"AQTX: AQ Critical error.\n");
792
816
status = IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
···
854
878
}
855
879
856
880
/* set next_to_use to head */
857
-
ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
881
+
ntu = rd32(hw, IAVF_VF_ARQH1) & IAVF_VF_ARQH1_ARQH_MASK;
858
882
if (ntu == ntc) {
859
883
/* nothing to do - shouldn't need to update ring's values */
860
884
ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;
···
902
926
desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
903
927
904
928
/* set tail = the last cleaned desc index. */
905
-
wr32(hw, hw->aq.arq.tail, ntc);
929
+
wr32(hw, IAVF_VF_ARQT1, ntc);
906
930
/* ntc is updated to tail + 1 */
907
931
ntc++;
908
932
if (ntc == hw->aq.num_arq_entries)
-7
drivers/net/ethernet/intel/iavf/iavf_adminq.h
-7
drivers/net/ethernet/intel/iavf/iavf_adminq.h
+4
-4
drivers/net/ethernet/intel/iavf/iavf_common.c
+4
-4
drivers/net/ethernet/intel/iavf/iavf_common.c
···
279
279
**/
280
280
bool iavf_check_asq_alive(struct iavf_hw *hw)
281
281
{
282
-
if (hw->aq.asq.len)
283
-
return !!(rd32(hw, hw->aq.asq.len) &
284
-
IAVF_VF_ATQLEN1_ATQENABLE_MASK);
285
-
else
282
+
/* Check if the queue is initialized */
283
+
if (!hw->aq.asq.count)
286
284
return false;
285
+
286
+
return !!(rd32(hw, IAVF_VF_ATQLEN1) & IAVF_VF_ATQLEN1_ATQENABLE_MASK);
287
287
}
288
288
289
289
/**
+3
-7
drivers/net/ethernet/intel/iavf/iavf_ethtool.c
+3
-7
drivers/net/ethernet/intel/iavf/iavf_ethtool.c
···
1445
1445
iavf_fdir_list_add_fltr(adapter, fltr);
1446
1446
adapter->fdir_active_fltr++;
1447
1447
fltr->state = IAVF_FDIR_FLTR_ADD_REQUEST;
1448
-
adapter->aq_required |= IAVF_FLAG_AQ_ADD_FDIR_FILTER;
1449
1448
spin_unlock_bh(&adapter->fdir_fltr_lock);
1450
1449
1451
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
1450
+
iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_FDIR_FILTER);
1452
1451
1453
1452
ret:
1454
1453
if (err && fltr)
···
1478
1479
if (fltr) {
1479
1480
if (fltr->state == IAVF_FDIR_FLTR_ACTIVE) {
1480
1481
fltr->state = IAVF_FDIR_FLTR_DEL_REQUEST;
1481
-
adapter->aq_required |= IAVF_FLAG_AQ_DEL_FDIR_FILTER;
1482
1482
} else {
1483
1483
err = -EBUSY;
1484
1484
}
···
1487
1489
spin_unlock_bh(&adapter->fdir_fltr_lock);
1488
1490
1489
1491
if (fltr && fltr->state == IAVF_FDIR_FLTR_DEL_REQUEST)
1490
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
1492
+
iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_DEL_FDIR_FILTER);
1491
1493
1492
1494
return err;
1493
1495
}
···
1656
1658
rss_old->hash_flds = hash_flds;
1657
1659
memcpy(&rss_old->cfg_msg, &rss_new->cfg_msg,
1658
1660
sizeof(rss_new->cfg_msg));
1659
-
adapter->aq_required |= IAVF_FLAG_AQ_ADD_ADV_RSS_CFG;
1660
1661
} else {
1661
1662
err = -EEXIST;
1662
1663
}
···
1665
1668
rss_new->packet_hdrs = hdrs;
1666
1669
rss_new->hash_flds = hash_flds;
1667
1670
list_add_tail(&rss_new->list, &adapter->adv_rss_list_head);
1668
-
adapter->aq_required |= IAVF_FLAG_AQ_ADD_ADV_RSS_CFG;
1669
1671
}
1670
1672
spin_unlock_bh(&adapter->adv_rss_lock);
1671
1673
1672
1674
if (!err)
1673
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
1675
+
iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_ADV_RSS_CFG);
1674
1676
1675
1677
mutex_unlock(&adapter->crit_lock);
1676
1678
+9
-14
drivers/net/ethernet/intel/iavf/iavf_main.c
+9
-14
drivers/net/ethernet/intel/iavf/iavf_main.c
···
1059
1059
*/
1060
1060
new_f->is_primary = true;
1061
1061
new_f->add = true;
1062
-
adapter->aq_required |= IAVF_FLAG_AQ_ADD_MAC_FILTER;
1063
1062
ether_addr_copy(hw->mac.addr, new_mac);
1064
1063
1065
1064
spin_unlock_bh(&adapter->mac_vlan_list_lock);
1066
1065
1067
1066
/* schedule the watchdog task to immediately process the request */
1068
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
1067
+
iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_MAC_FILTER);
1069
1068
return 0;
1070
1069
}
1071
1070
···
1283
1284
1284
1285
iavf_napi_enable_all(adapter);
1285
1286
1286
-
adapter->aq_required |= IAVF_FLAG_AQ_ENABLE_QUEUES;
1287
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
1287
+
iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ENABLE_QUEUES);
1288
1288
}
1289
1289
1290
1290
/**
···
1437
1439
adapter->aq_required |= IAVF_FLAG_AQ_DEL_ADV_RSS_CFG;
1438
1440
}
1439
1441
1440
-
adapter->aq_required |= IAVF_FLAG_AQ_DISABLE_QUEUES;
1441
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
1442
+
iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_DISABLE_QUEUES);
1442
1443
}
1443
1444
1444
1445
/**
···
2334
2337
}
2335
2338
}
2336
2339
2337
-
if (aq_required) {
2338
-
adapter->aq_required |= aq_required;
2339
-
mod_delayed_work(adapter->wq, &adapter->watchdog_task, 0);
2340
-
}
2340
+
if (aq_required)
2341
+
iavf_schedule_aq_request(adapter, aq_required);
2341
2342
}
2342
2343
2343
2344
/**
···
3248
3253
goto freedom;
3249
3254
3250
3255
/* check for error indications */
3251
-
val = rd32(hw, hw->aq.arq.len);
3256
+
val = rd32(hw, IAVF_VF_ARQLEN1);
3252
3257
if (val == 0xdeadbeef || val == 0xffffffff) /* device in reset */
3253
3258
goto freedom;
3254
3259
oldval = val;
···
3265
3270
val &= ~IAVF_VF_ARQLEN1_ARQCRIT_MASK;
3266
3271
}
3267
3272
if (oldval != val)
3268
-
wr32(hw, hw->aq.arq.len, val);
3273
+
wr32(hw, IAVF_VF_ARQLEN1, val);
3269
3274
3270
-
val = rd32(hw, hw->aq.asq.len);
3275
+
val = rd32(hw, IAVF_VF_ATQLEN1);
3271
3276
oldval = val;
3272
3277
if (val & IAVF_VF_ATQLEN1_ATQVFE_MASK) {
3273
3278
dev_info(&adapter->pdev->dev, "ASQ VF Error detected\n");
···
3282
3287
val &= ~IAVF_VF_ATQLEN1_ATQCRIT_MASK;
3283
3288
}
3284
3289
if (oldval != val)
3285
-
wr32(hw, hw->aq.asq.len, val);
3290
+
wr32(hw, IAVF_VF_ATQLEN1, val);
3286
3291
3287
3292
freedom:
3288
3293
kfree(event.msg_buf);