Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410
ARM: S3C64XX: Fix coding style errors on mach-real6410
ARM: S3C64XX: Prototype SPI devices
ARM: S3C64XX: Fix dev-spi build
ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr
ARM: SAMSUNG: Fix on drive strength value
ARM: S5PV210: Add FIMC clocks
ARM: S5PV210: Reduce the iodesc length of systimer
ARM: S5PV210: Update I2C-1 Clock Register Property.
ARM: S5P: Decrease IO Registers memory region size on FIMC
ARM: S5P: Fix DMA coherent mask for FIMC
+107
-66
+2
-1
arch/arm/mach-s3c64xx/dev-spi.c
+2
-1
arch/arm/mach-s3c64xx/dev-spi.c
···
18
18
#include <mach/map.h>
19
19
#include <mach/gpio-bank-c.h>
20
20
#include <mach/spi-clocks.h>
21
+
#include <mach/irqs.h>
21
22
22
23
#include <plat/s3c64xx-spi.h>
23
24
#include <plat/gpio-cfg.h>
24
-
#include <plat/irqs.h>
25
+
#include <plat/devs.h>
25
26
26
27
static char *spi_src_clks[] = {
27
28
[S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
+52
-52
arch/arm/mach-s3c64xx/mach-real6410.c
+52
-52
arch/arm/mach-s3c64xx/mach-real6410.c
···
30
30
#include <plat/devs.h>
31
31
#include <plat/regs-serial.h>
32
32
33
-
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
34
-
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
35
-
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
33
+
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
34
+
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
35
+
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
36
36
37
37
static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
38
38
[0] = {
39
-
.hwport = 0,
40
-
.flags = 0,
41
-
.ucon = UCON,
42
-
.ulcon = ULCON,
43
-
.ufcon = UFCON,
39
+
.hwport = 0,
40
+
.flags = 0,
41
+
.ucon = UCON,
42
+
.ulcon = ULCON,
43
+
.ufcon = UFCON,
44
44
},
45
45
[1] = {
46
-
.hwport = 1,
47
-
.flags = 0,
48
-
.ucon = UCON,
49
-
.ulcon = ULCON,
50
-
.ufcon = UFCON,
46
+
.hwport = 1,
47
+
.flags = 0,
48
+
.ucon = UCON,
49
+
.ulcon = ULCON,
50
+
.ufcon = UFCON,
51
51
},
52
52
[2] = {
53
-
.hwport = 2,
54
-
.flags = 0,
55
-
.ucon = UCON,
56
-
.ulcon = ULCON,
57
-
.ufcon = UFCON,
53
+
.hwport = 2,
54
+
.flags = 0,
55
+
.ucon = UCON,
56
+
.ulcon = ULCON,
57
+
.ufcon = UFCON,
58
58
},
59
59
[3] = {
60
-
.hwport = 3,
61
-
.flags = 0,
62
-
.ucon = UCON,
63
-
.ulcon = ULCON,
64
-
.ufcon = UFCON,
60
+
.hwport = 3,
61
+
.flags = 0,
62
+
.ucon = UCON,
63
+
.ulcon = ULCON,
64
+
.ufcon = UFCON,
65
65
},
66
66
};
67
67
68
68
/* DM9000AEP 10/100 ethernet controller */
69
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static struct resource real6410_dm9k_resource[] = {
71
-
[0] = {
72
-
.start = S3C64XX_PA_XM0CSN1,
73
-
.end = S3C64XX_PA_XM0CSN1 + 1,
74
-
.flags = IORESOURCE_MEM
75
-
},
76
-
[1] = {
77
-
.start = S3C64XX_PA_XM0CSN1 + 4,
78
-
.end = S3C64XX_PA_XM0CSN1 + 5,
79
-
.flags = IORESOURCE_MEM
80
-
},
81
-
[2] = {
82
-
.start = S3C_EINT(7),
83
-
.end = S3C_EINT(7),
84
-
.flags = IORESOURCE_IRQ,
85
-
}
71
+
[0] = {
72
+
.start = S3C64XX_PA_XM0CSN1,
73
+
.end = S3C64XX_PA_XM0CSN1 + 1,
74
+
.flags = IORESOURCE_MEM
75
+
},
76
+
[1] = {
77
+
.start = S3C64XX_PA_XM0CSN1 + 4,
78
+
.end = S3C64XX_PA_XM0CSN1 + 5,
79
+
.flags = IORESOURCE_MEM
80
+
},
81
+
[2] = {
82
+
.start = S3C_EINT(7),
83
+
.end = S3C_EINT(7),
84
+
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
85
+
}
86
86
};
87
87
88
88
static struct dm9000_plat_data real6410_dm9k_pdata = {
89
-
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
89
+
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
90
90
};
91
91
92
92
static struct platform_device real6410_device_eth = {
93
-
.name = "dm9000",
94
-
.id = -1,
95
-
.num_resources = ARRAY_SIZE(real6410_dm9k_resource),
96
-
.resource = real6410_dm9k_resource,
97
-
.dev = {
98
-
.platform_data = &real6410_dm9k_pdata,
99
-
},
93
+
.name = "dm9000",
94
+
.id = -1,
95
+
.num_resources = ARRAY_SIZE(real6410_dm9k_resource),
96
+
.resource = real6410_dm9k_resource,
97
+
.dev = {
98
+
.platform_data = &real6410_dm9k_pdata,
99
+
},
100
100
};
101
101
102
102
static struct platform_device *real6410_devices[] __initdata = {
···
129
129
/* set timing for nCS1 suitable for ethernet chip */
130
130
131
131
__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
132
-
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
133
-
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
134
-
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
135
-
(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
136
-
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
137
-
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
132
+
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
133
+
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
134
+
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
135
+
(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
136
+
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
137
+
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
138
138
139
139
platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
140
140
}
+19
-1
arch/arm/mach-s5pv210/clock.c
+19
-1
arch/arm/mach-s5pv210/clock.c
···
281
281
.enable = s5pv210_clk_ip0_ctrl,
282
282
.ctrlbit = (1<<29),
283
283
}, {
284
+
.name = "fimc",
285
+
.id = 0,
286
+
.parent = &clk_hclk_dsys.clk,
287
+
.enable = s5pv210_clk_ip0_ctrl,
288
+
.ctrlbit = (1 << 24),
289
+
}, {
290
+
.name = "fimc",
291
+
.id = 1,
292
+
.parent = &clk_hclk_dsys.clk,
293
+
.enable = s5pv210_clk_ip0_ctrl,
294
+
.ctrlbit = (1 << 25),
295
+
}, {
296
+
.name = "fimc",
297
+
.id = 2,
298
+
.parent = &clk_hclk_dsys.clk,
299
+
.enable = s5pv210_clk_ip0_ctrl,
300
+
.ctrlbit = (1 << 26),
301
+
}, {
284
302
.name = "otg",
285
303
.id = -1,
286
304
.parent = &clk_hclk_psys.clk,
···
375
357
.id = 1,
376
358
.parent = &clk_pclk_psys.clk,
377
359
.enable = s5pv210_clk_ip3_ctrl,
378
-
.ctrlbit = (1<<8),
360
+
.ctrlbit = (1 << 10),
379
361
}, {
380
362
.name = "i2c",
381
363
.id = 2,
+1
-1
arch/arm/mach-s5pv210/cpu.c
+1
-1
arch/arm/mach-s5pv210/cpu.c
+8
-1
arch/arm/plat-s5p/dev-fimc0.c
+8
-1
arch/arm/plat-s5p/dev-fimc0.c
···
10
10
*/
11
11
12
12
#include <linux/kernel.h>
13
+
#include <linux/dma-mapping.h>
13
14
#include <linux/platform_device.h>
14
15
#include <linux/interrupt.h>
15
16
#include <linux/ioport.h>
···
19
18
static struct resource s5p_fimc0_resource[] = {
20
19
[0] = {
21
20
.start = S5P_PA_FIMC0,
22
-
.end = S5P_PA_FIMC0 + SZ_1M - 1,
21
+
.end = S5P_PA_FIMC0 + SZ_4K - 1,
23
22
.flags = IORESOURCE_MEM,
24
23
},
25
24
[1] = {
···
29
28
},
30
29
};
31
30
31
+
static u64 s5p_fimc0_dma_mask = DMA_BIT_MASK(32);
32
+
32
33
struct platform_device s5p_device_fimc0 = {
33
34
.name = "s5p-fimc",
34
35
.id = 0,
35
36
.num_resources = ARRAY_SIZE(s5p_fimc0_resource),
36
37
.resource = s5p_fimc0_resource,
38
+
.dev = {
39
+
.dma_mask = &s5p_fimc0_dma_mask,
40
+
.coherent_dma_mask = DMA_BIT_MASK(32),
41
+
},
37
42
};
+8
-1
arch/arm/plat-s5p/dev-fimc1.c
+8
-1
arch/arm/plat-s5p/dev-fimc1.c
···
10
10
*/
11
11
12
12
#include <linux/kernel.h>
13
+
#include <linux/dma-mapping.h>
13
14
#include <linux/platform_device.h>
14
15
#include <linux/interrupt.h>
15
16
#include <linux/ioport.h>
···
19
18
static struct resource s5p_fimc1_resource[] = {
20
19
[0] = {
21
20
.start = S5P_PA_FIMC1,
22
-
.end = S5P_PA_FIMC1 + SZ_1M - 1,
21
+
.end = S5P_PA_FIMC1 + SZ_4K - 1,
23
22
.flags = IORESOURCE_MEM,
24
23
},
25
24
[1] = {
···
29
28
},
30
29
};
31
30
31
+
static u64 s5p_fimc1_dma_mask = DMA_BIT_MASK(32);
32
+
32
33
struct platform_device s5p_device_fimc1 = {
33
34
.name = "s5p-fimc",
34
35
.id = 1,
35
36
.num_resources = ARRAY_SIZE(s5p_fimc1_resource),
36
37
.resource = s5p_fimc1_resource,
38
+
.dev = {
39
+
.dma_mask = &s5p_fimc1_dma_mask,
40
+
.coherent_dma_mask = DMA_BIT_MASK(32),
41
+
},
37
42
};
+8
-1
arch/arm/plat-s5p/dev-fimc2.c
+8
-1
arch/arm/plat-s5p/dev-fimc2.c
···
10
10
*/
11
11
12
12
#include <linux/kernel.h>
13
+
#include <linux/dma-mapping.h>
13
14
#include <linux/platform_device.h>
14
15
#include <linux/interrupt.h>
15
16
#include <linux/ioport.h>
···
19
18
static struct resource s5p_fimc2_resource[] = {
20
19
[0] = {
21
20
.start = S5P_PA_FIMC2,
22
-
.end = S5P_PA_FIMC2 + SZ_1M - 1,
21
+
.end = S5P_PA_FIMC2 + SZ_4K - 1,
23
22
.flags = IORESOURCE_MEM,
24
23
},
25
24
[1] = {
···
29
28
},
30
29
};
31
30
31
+
static u64 s5p_fimc2_dma_mask = DMA_BIT_MASK(32);
32
+
32
33
struct platform_device s5p_device_fimc2 = {
33
34
.name = "s5p-fimc",
34
35
.id = 2,
35
36
.num_resources = ARRAY_SIZE(s5p_fimc2_resource),
36
37
.resource = s5p_fimc2_resource,
38
+
.dev = {
39
+
.dma_mask = &s5p_fimc2_dma_mask,
40
+
.coherent_dma_mask = DMA_BIT_MASK(32),
41
+
},
37
42
};
+4
-3
arch/arm/plat-samsung/gpio-config.c
+4
-3
arch/arm/plat-samsung/gpio-config.c
···
273
273
if (!chip)
274
274
return -EINVAL;
275
275
276
-
off = chip->chip.base - pin;
276
+
off = pin - chip->chip.base;
277
277
shift = off * 2;
278
278
reg = chip->base + 0x0C;
279
279
280
280
drvstr = __raw_readl(reg);
281
-
drvstr = 0xffff & (0x3 << shift);
282
281
drvstr = drvstr >> shift;
282
+
drvstr &= 0x3;
283
283
284
284
return (__force s5p_gpio_drvstr_t)drvstr;
285
285
}
···
296
296
if (!chip)
297
297
return -EINVAL;
298
298
299
-
off = chip->chip.base - pin;
299
+
off = pin - chip->chip.base;
300
300
shift = off * 2;
301
301
reg = chip->base + 0x0C;
302
302
303
303
tmp = __raw_readl(reg);
304
+
tmp &= ~(0x3 << shift);
304
305
tmp |= drvstr << shift;
305
306
306
307
__raw_writel(tmp, reg);
+5
-5
arch/arm/plat-samsung/include/plat/gpio-cfg.h
+5
-5
arch/arm/plat-samsung/include/plat/gpio-cfg.h
···
143
143
/* Define values for the drvstr available for each gpio pin.
144
144
*
145
145
* These values control the value of the output signal driver strength,
146
-
* configurable on most pins on the S5C series.
146
+
* configurable on most pins on the S5P series.
147
147
*/
148
-
#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x00)
149
-
#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x01)
150
-
#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x10)
151
-
#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x11)
148
+
#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
149
+
#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
150
+
#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
151
+
#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
152
152
153
153
/**
154
154
* s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin