Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/mes12_1: fix the failure access to MID1 registers
Correct the mid die id and mid1 register relative offset
for mes fw to access to mid1 registers.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Jack Xiao
and committed by
Alex Deucher
f1d7a876
189208d3
+52
-38
+17
-38
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+17
-38
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
···
494
494
}
495
495
static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset)
496
496
{
497
-
/* Check xcc reg offset range */
498
-
uint32_t xcc = (reg_offset & XCC_MID_MASK) ? 4 : 0;
499
-
/* Each XCC has two register ranges.
500
-
* These are represented in reg_offset[17:16]
501
-
*/
502
-
return ((reg_offset >> 16) & 0x3) + xcc;
497
+
return ((reg_offset >> 16) & 0x7);
503
498
}
504
499
505
500
static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id,
506
-
struct RRMT_OPTION *rrmt_opt)
501
+
struct RRMT_OPTION *rrmt_opt,
502
+
uint32_t *out_reg)
507
503
{
508
504
uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
509
505
···
509
513
MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD;
510
514
} else {
511
515
rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID;
516
+
if (soc_v1_0_mid1_reg_range(reg))
517
+
rrmt_opt->mid_die_id = 1;
512
518
}
519
+
520
+
*out_reg = soc_v1_0_normalize_reg_offset(reg);
513
521
}
514
522
515
523
static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
···
537
537
switch (input->op) {
538
538
case MES_MISC_OP_READ_REG:
539
539
misc_pkt.opcode = MESAPI_MISC__READ_REG;
540
-
misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
541
540
misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
542
541
mes_v12_1_get_rrmt(input->read_reg.reg_offset,
543
542
GET_INST(GC, input->xcc_id),
544
-
&misc_pkt.read_reg.rrmt_opt);
545
-
if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
546
-
misc_pkt.read_reg.reg_offset =
547
-
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset);
548
-
}
543
+
&misc_pkt.read_reg.rrmt_opt,
544
+
&misc_pkt.read_reg.reg_offset);
549
545
break;
550
546
case MES_MISC_OP_WRITE_REG:
551
547
misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
552
-
misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
553
548
misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
554
549
mes_v12_1_get_rrmt(input->write_reg.reg_offset,
555
550
GET_INST(GC, input->xcc_id),
556
-
&misc_pkt.write_reg.rrmt_opt);
557
-
if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
558
-
misc_pkt.write_reg.reg_offset =
559
-
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset);
560
-
}
551
+
&misc_pkt.write_reg.rrmt_opt,
552
+
&misc_pkt.write_reg.reg_offset);
561
553
break;
562
554
case MES_MISC_OP_WRM_REG_WAIT:
563
555
misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
564
556
misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
565
557
misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
566
558
misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
567
-
misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
568
559
misc_pkt.wait_reg_mem.reg_offset2 = 0;
569
560
mes_v12_1_get_rrmt(input->wrm_reg.reg0,
570
561
GET_INST(GC, input->xcc_id),
571
-
&misc_pkt.wait_reg_mem.rrmt_opt1);
572
-
if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
573
-
misc_pkt.wait_reg_mem.reg_offset1 =
574
-
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
575
-
}
562
+
&misc_pkt.wait_reg_mem.rrmt_opt1,
563
+
&misc_pkt.wait_reg_mem.reg_offset1);
576
564
break;
577
565
case MES_MISC_OP_WRM_REG_WR_WAIT:
578
566
misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
579
567
misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
580
568
misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
581
569
misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
582
-
misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
583
-
misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
584
570
mes_v12_1_get_rrmt(input->wrm_reg.reg0,
585
571
GET_INST(GC, input->xcc_id),
586
-
&misc_pkt.wait_reg_mem.rrmt_opt1);
572
+
&misc_pkt.wait_reg_mem.rrmt_opt1,
573
+
&misc_pkt.wait_reg_mem.reg_offset1);
587
574
mes_v12_1_get_rrmt(input->wrm_reg.reg1,
588
575
GET_INST(GC, input->xcc_id),
589
-
&misc_pkt.wait_reg_mem.rrmt_opt2);
590
-
591
-
if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
592
-
misc_pkt.wait_reg_mem.reg_offset1 =
593
-
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
594
-
}
595
-
if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) {
596
-
misc_pkt.wait_reg_mem.reg_offset2 =
597
-
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2);
598
-
}
576
+
&misc_pkt.wait_reg_mem.rrmt_opt2,
577
+
&misc_pkt.wait_reg_mem.reg_offset2);
599
578
break;
600
579
case MES_MISC_OP_SET_SHADER_DEBUGGER:
601
580
pipe = AMDGPU_MES_SCHED_PIPE;
+33
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+33
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
···
41
41
#define NORMALIZE_XCC_REG_OFFSET(offset) \
42
42
(offset & 0xFFFF)
43
43
44
+
#define MID1_REG_RANGE_0_LOW 0x40000
45
+
#define MID1_REG_RANGE_0_HIGH 0x80000
46
+
#define NORMALIZE_MID_REG_OFFSET(offset) \
47
+
(offset & 0x3FFFF)
48
+
44
49
/* Initialized doorbells for amdgpu including multimedia
45
50
* KFD can use all the rest in 2M doorbell bar */
46
51
static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev)
···
875
870
else
876
871
return reg;
877
872
}
873
+
874
+
bool soc_v1_0_mid1_reg_range(uint32_t reg)
875
+
{
876
+
uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
877
+
878
+
if (soc_v1_0_normalize_xcc_reg_range(normalized_reg))
879
+
return false;
880
+
881
+
if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH))
882
+
return true;
883
+
else
884
+
return false;
885
+
}
886
+
887
+
uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg)
888
+
{
889
+
uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
890
+
891
+
if (soc_v1_0_normalize_xcc_reg_range(normalized_reg))
892
+
return soc_v1_0_normalize_xcc_reg_offset(reg);
893
+
894
+
/* check if the reg offset is inside MID1. */
895
+
if (soc_v1_0_mid1_reg_range(reg))
896
+
return NORMALIZE_MID_REG_OFFSET(reg);
897
+
898
+
return reg;
899
+
}
900
+
+2
drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
+2
drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
···
31
31
int xcc_id);
32
32
int soc_v1_0_init_soc_config(struct amdgpu_device *adev);
33
33
bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg);
34
+
bool soc_v1_0_mid1_reg_range(uint32_t reg);
34
35
uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg);
36
+
uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg);
35
37
u64 soc_v1_0_encode_ext_smn_addressing(int ext_id);
36
38
37
39
#endif