Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'tpmdd-next-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd
Pull tpm updates from Jarkko Sakkinen:
"Mostly TPM and also few keyring fixes"
* tag 'tpmdd-next-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd:
tpm: Add check for Failure mode for TPM2 modules
tpm: eventlog: Fix section mismatch for DEBUG_SECTION_MISMATCH
tpm: fix platform_no_drv_owner.cocci warning
KEYS: asymmetric: enforce SM2 signature use pkey algo
pkcs7: support EC-RDSA/streebog in SignerInfo
pkcs7: parser support SM2 and SM3 algorithms combination
sign-file: Fix confusing error messages
X.509: Support parsing certificate using SM2 algorithm
tpm: Add tpm_tis_i2c backend for tpm_tis_core
tpm: Add tpm_tis_verify_crc to the tpm_tis_phy_ops protocol layer
dt-bindings: trivial-devices: Add Infineon SLB9673 TPM
tpm: Add upgrade/reduced mode support for TPM1.2 modules
+470
-5
+2
Documentation/devicetree/bindings/trivial-devices.yaml
+2
Documentation/devicetree/bindings/trivial-devices.yaml
···
141
141
- infineon,slb9635tt
142
142
# Infineon SLB9645 I2C TPM (new protocol, max 400khz)
143
143
- infineon,slb9645tt
144
+
# Infineon SLB9673 I2C TPM 2.0
145
+
- infineon,slb9673
144
146
# Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
145
147
- infineon,tlv493d-a1b6
146
148
# Infineon Multi-phase Digital VR Controller xdpe11280
+18
crypto/asymmetric_keys/pkcs7_parser.c
+18
crypto/asymmetric_keys/pkcs7_parser.c
···
248
248
case OID_sha224:
249
249
ctx->sinfo->sig->hash_algo = "sha224";
250
250
break;
251
+
case OID_sm3:
252
+
ctx->sinfo->sig->hash_algo = "sm3";
253
+
break;
254
+
case OID_gost2012Digest256:
255
+
ctx->sinfo->sig->hash_algo = "streebog256";
256
+
break;
257
+
case OID_gost2012Digest512:
258
+
ctx->sinfo->sig->hash_algo = "streebog512";
259
+
break;
251
260
default:
252
261
printk("Unsupported digest algo: %u\n", ctx->last_oid);
253
262
return -ENOPKG;
···
285
276
case OID_id_ecdsa_with_sha512:
286
277
ctx->sinfo->sig->pkey_algo = "ecdsa";
287
278
ctx->sinfo->sig->encoding = "x962";
279
+
break;
280
+
case OID_SM2_with_SM3:
281
+
ctx->sinfo->sig->pkey_algo = "sm2";
282
+
ctx->sinfo->sig->encoding = "raw";
283
+
break;
284
+
case OID_gost2012PKey256:
285
+
case OID_gost2012PKey512:
286
+
ctx->sinfo->sig->pkey_algo = "ecrdsa";
287
+
ctx->sinfo->sig->encoding = "raw";
288
288
break;
289
289
default:
290
290
printk("Unsupported pkey algo: %u\n", ctx->last_oid);
+5
-2
crypto/asymmetric_keys/public_key.c
+5
-2
crypto/asymmetric_keys/public_key.c
···
304
304
305
305
BUG_ON(!sig->data);
306
306
307
+
/* SM2 signatures always use the SM3 hash algorithm */
308
+
if (!sig->hash_algo || strcmp(sig->hash_algo, "sm3") != 0)
309
+
return -EINVAL;
310
+
307
311
ret = sm2_compute_z_digest(tfm_pkey, SM2_DEFAULT_USERID,
308
312
SM2_DEFAULT_USERID_LEN, dgst);
309
313
if (ret)
···
418
414
if (ret)
419
415
goto error_free_key;
420
416
421
-
if (sig->pkey_algo && strcmp(sig->pkey_algo, "sm2") == 0 &&
422
-
sig->data_size) {
417
+
if (strcmp(pkey->pkey_algo, "sm2") == 0 && sig->data_size) {
423
418
ret = cert_sig_digest_update(sig, tfm);
424
419
if (ret)
425
420
goto error_free_key;
+3
crypto/asymmetric_keys/x509_cert_parser.c
+3
crypto/asymmetric_keys/x509_cert_parser.c
+12
drivers/char/tpm/Kconfig
+12
drivers/char/tpm/Kconfig
···
74
74
If you have a H1 secure module running Cr50 firmware on SPI bus,
75
75
say Yes and it will be accessible from within Linux.
76
76
77
+
config TCG_TIS_I2C
78
+
tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (I2C - generic)"
79
+
depends on I2C
80
+
select CRC_CCITT
81
+
select TCG_TIS_CORE
82
+
help
83
+
If you have a TPM security chip, compliant with the TCG TPM PTP
84
+
(I2C interface) specification and connected to an I2C bus master,
85
+
say Yes and it will be accessible from within Linux.
86
+
To compile this driver as a module, choose M here;
87
+
the module will be called tpm_tis_i2c.
88
+
77
89
config TCG_TIS_SYNQUACER
78
90
tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
79
91
depends on ARCH_SYNQUACER || COMPILE_TEST
+1
drivers/char/tpm/Makefile
+1
drivers/char/tpm/Makefile
···
29
29
30
30
obj-$(CONFIG_TCG_TIS_I2C_CR50) += tpm_tis_i2c_cr50.o
31
31
32
+
obj-$(CONFIG_TCG_TIS_I2C) += tpm_tis_i2c.o
32
33
obj-$(CONFIG_TCG_TIS_I2C_ATMEL) += tpm_i2c_atmel.o
33
34
obj-$(CONFIG_TCG_TIS_I2C_INFINEON) += tpm_i2c_infineon.o
34
35
obj-$(CONFIG_TCG_TIS_I2C_NUVOTON) += tpm_i2c_nuvoton.o
+1
drivers/char/tpm/tpm.h
+1
drivers/char/tpm/tpm.h
+6
-1
drivers/char/tpm/tpm1-cmd.c
+6
-1
drivers/char/tpm/tpm1-cmd.c
···
709
709
if (rc)
710
710
goto out;
711
711
rc = tpm1_do_selftest(chip);
712
-
if (rc) {
712
+
if (rc == TPM_ERR_FAILEDSELFTEST) {
713
+
dev_warn(&chip->dev, "TPM self test failed, switching to the firmware upgrade mode\n");
714
+
/* A TPM in this state possibly allows or needs a firmware upgrade */
715
+
chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
716
+
return 0;
717
+
} else if (rc) {
713
718
dev_err(&chip->dev, "TPM self test failed\n");
714
719
goto out;
715
720
}
+6
drivers/char/tpm/tpm2-cmd.c
+6
drivers/char/tpm/tpm2-cmd.c
···
752
752
}
753
753
754
754
rc = tpm2_get_cc_attrs_tbl(chip);
755
+
if (rc == TPM2_RC_FAILURE || (rc < 0 && rc != -ENOMEM)) {
756
+
dev_info(&chip->dev,
757
+
"TPM in field failure mode, requires firmware upgrade\n");
758
+
chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
759
+
rc = 0;
760
+
}
755
761
756
762
out:
757
763
/*
+14
drivers/char/tpm/tpm_tis_core.c
+14
drivers/char/tpm/tpm_tis_core.c
···
289
289
int size = 0;
290
290
int status;
291
291
u32 expected;
292
+
int rc;
292
293
293
294
if (count < TPM_HEADER_SIZE) {
294
295
size = -EIO;
···
326
325
if (status & TPM_STS_DATA_AVAIL) { /* retry? */
327
326
dev_err(&chip->dev, "Error left over data\n");
328
327
size = -EIO;
328
+
goto out;
329
+
}
330
+
331
+
rc = tpm_tis_verify_crc(priv, (size_t)size, buf);
332
+
if (rc < 0) {
333
+
dev_err(&chip->dev, "CRC mismatch for response.\n");
334
+
size = rc;
329
335
goto out;
330
336
}
331
337
···
450
442
rc = tpm_tis_send_data(chip, buf, len);
451
443
if (rc < 0)
452
444
return rc;
445
+
446
+
rc = tpm_tis_verify_crc(priv, len, buf);
447
+
if (rc < 0) {
448
+
dev_err(&chip->dev, "CRC mismatch for command.\n");
449
+
return rc;
450
+
}
453
451
454
452
/* go and do it */
455
453
rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO);
+10
drivers/char/tpm/tpm_tis_core.h
+10
drivers/char/tpm/tpm_tis_core.h
···
121
121
u8 *result, enum tpm_tis_io_mode mode);
122
122
int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
123
123
const u8 *value, enum tpm_tis_io_mode mode);
124
+
int (*verify_crc)(struct tpm_tis_data *data, size_t len,
125
+
const u8 *value);
124
126
};
125
127
126
128
static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
···
188
186
rc = data->phy_ops->write_bytes(data, addr, sizeof(u32),
189
187
(u8 *)&value_le, TPM_TIS_PHYS_32);
190
188
return rc;
189
+
}
190
+
191
+
static inline int tpm_tis_verify_crc(struct tpm_tis_data *data, size_t len,
192
+
const u8 *value)
193
+
{
194
+
if (!data->phy_ops->verify_crc)
195
+
return 0;
196
+
return data->phy_ops->verify_crc(data, len, value);
191
197
}
192
198
193
199
static inline bool is_bsw(void)
+390
drivers/char/tpm/tpm_tis_i2c.c
+390
drivers/char/tpm/tpm_tis_i2c.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2014-2021 Nuvoton Technology corporation
4
+
* Copyright (C) 2019-2022 Infineon Technologies AG
5
+
*
6
+
* This device driver implements the TPM interface as defined in the TCG PC
7
+
* Client Platform TPM Profile (PTP) Specification for TPM 2.0 v1.04
8
+
* Revision 14.
9
+
*
10
+
* It is based on the tpm_tis_spi device driver.
11
+
*/
12
+
13
+
#include <linux/i2c.h>
14
+
#include <linux/crc-ccitt.h>
15
+
#include "tpm_tis_core.h"
16
+
17
+
/* TPM registers */
18
+
#define TPM_I2C_LOC_SEL 0x00
19
+
#define TPM_I2C_ACCESS 0x04
20
+
#define TPM_I2C_INTERFACE_CAPABILITY 0x30
21
+
#define TPM_I2C_DEVICE_ADDRESS 0x38
22
+
#define TPM_I2C_DATA_CSUM_ENABLE 0x40
23
+
#define TPM_DATA_CSUM 0x44
24
+
#define TPM_I2C_DID_VID 0x48
25
+
#define TPM_I2C_RID 0x4C
26
+
27
+
/* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
28
+
#define TPM_LOC_SEL 0x0FFF
29
+
30
+
/* Mask to extract the I2C register from TIS register addresses */
31
+
#define TPM_TIS_REGISTER_MASK 0x0FFF
32
+
33
+
/* Default Guard Time of 250µs until interface capability register is read */
34
+
#define GUARD_TIME_DEFAULT_MIN 250
35
+
#define GUARD_TIME_DEFAULT_MAX 300
36
+
37
+
/* Guard Time of 250µs after I2C slave NACK */
38
+
#define GUARD_TIME_ERR_MIN 250
39
+
#define GUARD_TIME_ERR_MAX 300
40
+
41
+
/* Guard Time bit masks; SR is repeated start, RW is read then write, etc. */
42
+
#define TPM_GUARD_TIME_SR_MASK 0x40000000
43
+
#define TPM_GUARD_TIME_RR_MASK 0x00100000
44
+
#define TPM_GUARD_TIME_RW_MASK 0x00080000
45
+
#define TPM_GUARD_TIME_WR_MASK 0x00040000
46
+
#define TPM_GUARD_TIME_WW_MASK 0x00020000
47
+
#define TPM_GUARD_TIME_MIN_MASK 0x0001FE00
48
+
#define TPM_GUARD_TIME_MIN_SHIFT 9
49
+
50
+
/* Masks with bits that must be read zero */
51
+
#define TPM_ACCESS_READ_ZERO 0x48
52
+
#define TPM_INT_ENABLE_ZERO 0x7FFFFF6
53
+
#define TPM_STS_READ_ZERO 0x23
54
+
#define TPM_INTF_CAPABILITY_ZERO 0x0FFFF000
55
+
#define TPM_I2C_INTERFACE_CAPABILITY_ZERO 0x80000000
56
+
57
+
struct tpm_tis_i2c_phy {
58
+
struct tpm_tis_data priv;
59
+
struct i2c_client *i2c_client;
60
+
bool guard_time_read;
61
+
bool guard_time_write;
62
+
u16 guard_time_min;
63
+
u16 guard_time_max;
64
+
u8 *io_buf;
65
+
};
66
+
67
+
static inline struct tpm_tis_i2c_phy *
68
+
to_tpm_tis_i2c_phy(struct tpm_tis_data *data)
69
+
{
70
+
return container_of(data, struct tpm_tis_i2c_phy, priv);
71
+
}
72
+
73
+
/*
74
+
* tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
75
+
* of Register Space for FIFO TPM Access" of the TCG PC Client PTP
76
+
* Specification. In order for this code to work together with tpm_tis_core,
77
+
* those addresses need to mapped to the registers defined for I2C TPMs in
78
+
* Table 51 "I2C-TPM Register Overview".
79
+
*
80
+
* For most addresses this can be done by simply stripping off the locality
81
+
* information from the address. A few addresses need to be mapped explicitly,
82
+
* since the corresponding I2C registers have been moved around. TPM_LOC_SEL is
83
+
* only defined for I2C TPMs and is also mapped explicitly here to distinguish
84
+
* it from TPM_ACCESS(0).
85
+
*
86
+
* Locality information is ignored, since this driver assumes exclusive access
87
+
* to the TPM and always uses locality 0.
88
+
*/
89
+
static u8 tpm_tis_i2c_address_to_register(u32 addr)
90
+
{
91
+
addr &= TPM_TIS_REGISTER_MASK;
92
+
93
+
switch (addr) {
94
+
case TPM_ACCESS(0):
95
+
return TPM_I2C_ACCESS;
96
+
case TPM_LOC_SEL:
97
+
return TPM_I2C_LOC_SEL;
98
+
case TPM_DID_VID(0):
99
+
return TPM_I2C_DID_VID;
100
+
case TPM_RID(0):
101
+
return TPM_I2C_RID;
102
+
default:
103
+
return addr;
104
+
}
105
+
}
106
+
107
+
static int tpm_tis_i2c_retry_transfer_until_ack(struct tpm_tis_data *data,
108
+
struct i2c_msg *msg)
109
+
{
110
+
struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
111
+
bool guard_time;
112
+
int i = 0;
113
+
int ret;
114
+
115
+
if (msg->flags & I2C_M_RD)
116
+
guard_time = phy->guard_time_read;
117
+
else
118
+
guard_time = phy->guard_time_write;
119
+
120
+
do {
121
+
ret = i2c_transfer(phy->i2c_client->adapter, msg, 1);
122
+
if (ret < 0)
123
+
usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
124
+
else if (guard_time)
125
+
usleep_range(phy->guard_time_min, phy->guard_time_max);
126
+
/* retry on TPM NACK */
127
+
} while (ret < 0 && i++ < TPM_RETRY);
128
+
129
+
return ret;
130
+
}
131
+
132
+
/* Check that bits which must be read zero are not set */
133
+
static int tpm_tis_i2c_sanity_check_read(u8 reg, u16 len, u8 *buf)
134
+
{
135
+
u32 zero_mask;
136
+
u32 value;
137
+
138
+
switch (len) {
139
+
case sizeof(u8):
140
+
value = buf[0];
141
+
break;
142
+
case sizeof(u16):
143
+
value = le16_to_cpup((__le16 *)buf);
144
+
break;
145
+
case sizeof(u32):
146
+
value = le32_to_cpup((__le32 *)buf);
147
+
break;
148
+
default:
149
+
/* unknown length, skip check */
150
+
return 0;
151
+
}
152
+
153
+
switch (reg) {
154
+
case TPM_I2C_ACCESS:
155
+
zero_mask = TPM_ACCESS_READ_ZERO;
156
+
break;
157
+
case TPM_INT_ENABLE(0) & TPM_TIS_REGISTER_MASK:
158
+
zero_mask = TPM_INT_ENABLE_ZERO;
159
+
break;
160
+
case TPM_STS(0) & TPM_TIS_REGISTER_MASK:
161
+
zero_mask = TPM_STS_READ_ZERO;
162
+
break;
163
+
case TPM_INTF_CAPS(0) & TPM_TIS_REGISTER_MASK:
164
+
zero_mask = TPM_INTF_CAPABILITY_ZERO;
165
+
break;
166
+
case TPM_I2C_INTERFACE_CAPABILITY:
167
+
zero_mask = TPM_I2C_INTERFACE_CAPABILITY_ZERO;
168
+
break;
169
+
default:
170
+
/* unknown register, skip check */
171
+
return 0;
172
+
}
173
+
174
+
if (unlikely((value & zero_mask) != 0x00)) {
175
+
pr_debug("TPM I2C read of register 0x%02x failed sanity check: 0x%x\n", reg, value);
176
+
return -EIO;
177
+
}
178
+
179
+
return 0;
180
+
}
181
+
182
+
static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
183
+
u8 *result, enum tpm_tis_io_mode io_mode)
184
+
{
185
+
struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
186
+
struct i2c_msg msg = { .addr = phy->i2c_client->addr };
187
+
u8 reg = tpm_tis_i2c_address_to_register(addr);
188
+
int i;
189
+
int ret;
190
+
191
+
for (i = 0; i < TPM_RETRY; i++) {
192
+
/* write register */
193
+
msg.len = sizeof(reg);
194
+
msg.buf = ®
195
+
msg.flags = 0;
196
+
ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
197
+
if (ret < 0)
198
+
return ret;
199
+
200
+
/* read data */
201
+
msg.buf = result;
202
+
msg.len = len;
203
+
msg.flags = I2C_M_RD;
204
+
ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
205
+
if (ret < 0)
206
+
return ret;
207
+
208
+
ret = tpm_tis_i2c_sanity_check_read(reg, len, result);
209
+
if (ret == 0)
210
+
return 0;
211
+
212
+
usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
213
+
}
214
+
215
+
return ret;
216
+
}
217
+
218
+
static int tpm_tis_i2c_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
219
+
const u8 *value,
220
+
enum tpm_tis_io_mode io_mode)
221
+
{
222
+
struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
223
+
struct i2c_msg msg = { .addr = phy->i2c_client->addr };
224
+
u8 reg = tpm_tis_i2c_address_to_register(addr);
225
+
int ret;
226
+
227
+
if (len > TPM_BUFSIZE - 1)
228
+
return -EIO;
229
+
230
+
/* write register and data in one go */
231
+
phy->io_buf[0] = reg;
232
+
memcpy(phy->io_buf + sizeof(reg), value, len);
233
+
234
+
msg.len = sizeof(reg) + len;
235
+
msg.buf = phy->io_buf;
236
+
ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
237
+
if (ret < 0)
238
+
return ret;
239
+
240
+
return 0;
241
+
}
242
+
243
+
static int tpm_tis_i2c_verify_crc(struct tpm_tis_data *data, size_t len,
244
+
const u8 *value)
245
+
{
246
+
u16 crc_tpm, crc_host;
247
+
int rc;
248
+
249
+
rc = tpm_tis_read16(data, TPM_DATA_CSUM, &crc_tpm);
250
+
if (rc < 0)
251
+
return rc;
252
+
253
+
/* reflect crc result, regardless of host endianness */
254
+
crc_host = swab16(crc_ccitt(0, value, len));
255
+
if (crc_tpm != crc_host)
256
+
return -EIO;
257
+
258
+
return 0;
259
+
}
260
+
261
+
/*
262
+
* Guard Time:
263
+
* After each I2C operation, the TPM might require the master to wait.
264
+
* The time period is vendor-specific and must be read from the
265
+
* TPM_I2C_INTERFACE_CAPABILITY register.
266
+
*
267
+
* Before the Guard Time is read (or after the TPM failed to send an I2C NACK),
268
+
* a Guard Time of 250µs applies.
269
+
*
270
+
* Various flags in the same register indicate if a guard time is needed:
271
+
* - SR: <I2C read with repeated start> <guard time> <I2C read>
272
+
* - RR: <I2C read> <guard time> <I2C read>
273
+
* - RW: <I2C read> <guard time> <I2C write>
274
+
* - WR: <I2C write> <guard time> <I2C read>
275
+
* - WW: <I2C write> <guard time> <I2C write>
276
+
*
277
+
* See TCG PC Client PTP Specification v1.04, 8.1.10 GUARD_TIME
278
+
*/
279
+
static int tpm_tis_i2c_init_guard_time(struct tpm_tis_i2c_phy *phy)
280
+
{
281
+
u32 i2c_caps;
282
+
int ret;
283
+
284
+
phy->guard_time_read = true;
285
+
phy->guard_time_write = true;
286
+
phy->guard_time_min = GUARD_TIME_DEFAULT_MIN;
287
+
phy->guard_time_max = GUARD_TIME_DEFAULT_MAX;
288
+
289
+
ret = tpm_tis_i2c_read_bytes(&phy->priv, TPM_I2C_INTERFACE_CAPABILITY,
290
+
sizeof(i2c_caps), (u8 *)&i2c_caps,
291
+
TPM_TIS_PHYS_32);
292
+
if (ret)
293
+
return ret;
294
+
295
+
phy->guard_time_read = (i2c_caps & TPM_GUARD_TIME_RR_MASK) ||
296
+
(i2c_caps & TPM_GUARD_TIME_RW_MASK);
297
+
phy->guard_time_write = (i2c_caps & TPM_GUARD_TIME_WR_MASK) ||
298
+
(i2c_caps & TPM_GUARD_TIME_WW_MASK);
299
+
phy->guard_time_min = (i2c_caps & TPM_GUARD_TIME_MIN_MASK) >>
300
+
TPM_GUARD_TIME_MIN_SHIFT;
301
+
/* guard_time_max = guard_time_min * 1.2 */
302
+
phy->guard_time_max = phy->guard_time_min + phy->guard_time_min / 5;
303
+
304
+
return 0;
305
+
}
306
+
307
+
static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
308
+
309
+
static const struct tpm_tis_phy_ops tpm_i2c_phy_ops = {
310
+
.read_bytes = tpm_tis_i2c_read_bytes,
311
+
.write_bytes = tpm_tis_i2c_write_bytes,
312
+
.verify_crc = tpm_tis_i2c_verify_crc,
313
+
};
314
+
315
+
static int tpm_tis_i2c_probe(struct i2c_client *dev,
316
+
const struct i2c_device_id *id)
317
+
{
318
+
struct tpm_tis_i2c_phy *phy;
319
+
const u8 crc_enable = 1;
320
+
const u8 locality = 0;
321
+
int ret;
322
+
323
+
phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_i2c_phy),
324
+
GFP_KERNEL);
325
+
if (!phy)
326
+
return -ENOMEM;
327
+
328
+
phy->io_buf = devm_kzalloc(&dev->dev, TPM_BUFSIZE, GFP_KERNEL);
329
+
if (!phy->io_buf)
330
+
return -ENOMEM;
331
+
332
+
phy->i2c_client = dev;
333
+
334
+
/* must precede all communication with the tpm */
335
+
ret = tpm_tis_i2c_init_guard_time(phy);
336
+
if (ret)
337
+
return ret;
338
+
339
+
ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_LOC_SEL, sizeof(locality),
340
+
&locality, TPM_TIS_PHYS_8);
341
+
if (ret)
342
+
return ret;
343
+
344
+
ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_I2C_DATA_CSUM_ENABLE,
345
+
sizeof(crc_enable), &crc_enable,
346
+
TPM_TIS_PHYS_8);
347
+
if (ret)
348
+
return ret;
349
+
350
+
return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_i2c_phy_ops,
351
+
NULL);
352
+
}
353
+
354
+
static int tpm_tis_i2c_remove(struct i2c_client *client)
355
+
{
356
+
struct tpm_chip *chip = i2c_get_clientdata(client);
357
+
358
+
tpm_chip_unregister(chip);
359
+
tpm_tis_remove(chip);
360
+
return 0;
361
+
}
362
+
363
+
static const struct i2c_device_id tpm_tis_i2c_id[] = {
364
+
{ "tpm_tis_i2c", 0 },
365
+
{}
366
+
};
367
+
MODULE_DEVICE_TABLE(i2c, tpm_tis_i2c_id);
368
+
369
+
#ifdef CONFIG_OF
370
+
static const struct of_device_id of_tis_i2c_match[] = {
371
+
{ .compatible = "infineon,slb9673", },
372
+
{}
373
+
};
374
+
MODULE_DEVICE_TABLE(of, of_tis_i2c_match);
375
+
#endif
376
+
377
+
static struct i2c_driver tpm_tis_i2c_driver = {
378
+
.driver = {
379
+
.name = "tpm_tis_i2c",
380
+
.pm = &tpm_tis_pm,
381
+
.of_match_table = of_match_ptr(of_tis_i2c_match),
382
+
},
383
+
.probe = tpm_tis_i2c_probe,
384
+
.remove = tpm_tis_i2c_remove,
385
+
.id_table = tpm_tis_i2c_id,
386
+
};
387
+
module_i2c_driver(tpm_tis_i2c_driver);
388
+
389
+
MODULE_DESCRIPTION("TPM Driver for native I2C access");
390
+
MODULE_LICENSE("GPL");
+1
-1
include/linux/tpm_eventlog.h
+1
-1
include/linux/tpm_eventlog.h
···
157
157
* Return: size of the event on success, 0 on failure
158
158
*/
159
159
160
-
static inline int __calc_tpm2_event_size(struct tcg_pcr_event2_head *event,
160
+
static __always_inline int __calc_tpm2_event_size(struct tcg_pcr_event2_head *event,
161
161
struct tcg_pcr_event *event_header,
162
162
bool do_mapping)
163
163
{