tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Another week of fixes, nothing too crazy, but a few all over the
place.

Two locking fixes in the core/ttm area, a couple of small driver fixes
(radeon, sun4i, mcde, vc4). Then msm and amdgpu have a set of fixes
each, mostly for smaller things, though the msm has a DSI fix for a
black screen.

I haven't seen any intel fixes this week so they may have a few that
may or may not wait for next week.

drm:
- auth locking fix

ttm:
- locking fix

amdgpu:
- Use kvzmalloc in amdgu_bo_create
- Use drm_dbg_kms for reporting failure to get a GEM FB
- Fix some register offsets for Sienna Cichlid
- Fix fall-through warning

radeon:
- memcpy_to/from_io fixes

msm:
- NULL ptr deref fix
- CP_PROTECT reg programming fix
- incorrect register shift fix
- DSI blank screen fix

sun4i:
- hdmi output probing fix

mcde:
- DSI pipeline calc fix

vc4:
- out of bounds fix"

* tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm:
drm/msm/dsi: Stash away calculated vco frequency on recalc
drm: Lock pointer access in drm_master_release()
drm/mcde: Fix off by 10^3 in calculation
drm/msm/a6xx: avoid shadow NULL reference in failure path
drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650
drm/msm/a6xx: update/fix CP_PROTECT initialization
radeon: use memcpy_to/fromio for UVD fw upload
drm/amd/pm: Fix fall-through warning for Clang
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FB
drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create
drm/msm: Init mm_list before accessing it for use_vram path
drm: Fix use-after-free read in drm_getunique()
drm/vc4: fix vc4_atomic_commit_tail() logic
drm/ttm: fix deref of bo->ttm without holding the lock v2
drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device

Linus Torvalds f21b807c 929d931f

+232 -79
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 1057 1057 1058 1058 return 0; 1059 1059 err: 1060 - drm_err(dev, "Failed to init gem fb: %d\n", ret); 1060 + drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); 1061 1061 rfb->base.obj[0] = NULL; 1062 1062 return ret; 1063 1063 } ··· 1094 1094 1095 1095 return 0; 1096 1096 err: 1097 - drm_err(dev, "Failed to verify and init gem fb: %d\n", ret); 1097 + drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); 1098 1098 rfb->base.obj[0] = NULL; 1099 1099 return ret; 1100 1100 }
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 100 100 kfree(ubo->metadata); 101 101 } 102 102 103 - kfree(bo); 103 + kvfree(bo); 104 104 } 105 105 106 106 /** ··· 552 552 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 553 553 554 554 *bo_ptr = NULL; 555 - bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL); 555 + bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 556 556 if (bo == NULL) 557 557 return -ENOMEM; 558 558 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
+21 -5
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 173 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 174 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 175 175 176 + #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 177 + #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 178 + 176 179 #define GFX_RLCG_GC_WRITE_OLD (0x8 << 28) 177 180 #define GFX_RLCG_GC_WRITE (0x0 << 28) 178 181 #define GFX_RLCG_GC_READ (0x1 << 28) ··· 1483 1480 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; 1484 1481 scratch_reg3 = adev->rmmio + 1485 1482 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; 1486 - spare_int = adev->rmmio + 1487 - (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; 1483 + 1484 + if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 1485 + spare_int = adev->rmmio + 1486 + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX] 1487 + + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4; 1488 + } else { 1489 + spare_int = adev->rmmio + 1490 + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; 1491 + } 1488 1492 1489 1493 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1490 1494 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; ··· 7359 7349 if (amdgpu_sriov_vf(adev)) { 7360 7350 gfx_v10_0_cp_gfx_enable(adev, false); 7361 7351 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7362 - tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7363 - tmp &= 0xffffff00; 7364 - WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7352 + if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 7353 + tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 7354 + tmp &= 0xffffff00; 7355 + WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 7356 + } else { 7357 + tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7358 + tmp &= 0xffffff00; 7359 + WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7360 + } 7365 7361 7366 7362 return 0; 7367 7363 }
+1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
··· 810 810 break; 811 811 case AMD_DPM_FORCED_LEVEL_MANUAL: 812 812 data->fine_grain_enabled = 1; 813 + break; 813 814 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 814 815 default: 815 816 break;
+2 -1
drivers/gpu/drm/drm_auth.c
··· 314 314 void drm_master_release(struct drm_file *file_priv) 315 315 { 316 316 struct drm_device *dev = file_priv->minor->dev; 317 - struct drm_master *master = file_priv->master; 317 + struct drm_master *master; 318 318 319 319 mutex_lock(&dev->master_mutex); 320 + master = file_priv->master; 320 321 if (file_priv->magic) 321 322 idr_remove(&file_priv->master->magic_map, file_priv->magic); 322 323
+5 -4
drivers/gpu/drm/drm_ioctl.c
··· 118 118 struct drm_file *file_priv) 119 119 { 120 120 struct drm_unique *u = data; 121 - struct drm_master *master = file_priv->master; 121 + struct drm_master *master; 122 122 123 - mutex_lock(&master->dev->master_mutex); 123 + mutex_lock(&dev->master_mutex); 124 + master = file_priv->master; 124 125 if (u->unique_len >= master->unique_len) { 125 126 if (copy_to_user(u->unique, master->unique, master->unique_len)) { 126 - mutex_unlock(&master->dev->master_mutex); 127 + mutex_unlock(&dev->master_mutex); 127 128 return -EFAULT; 128 129 } 129 130 } 130 131 u->unique_len = master->unique_len; 131 - mutex_unlock(&master->dev->master_mutex); 132 + mutex_unlock(&dev->master_mutex); 132 133 133 134 return 0; 134 135 }
+1 -1
drivers/gpu/drm/mcde/mcde_dsi.c
··· 577 577 * porches and sync. 578 578 */ 579 579 /* (ps/s) / (pixels/s) = ps/pixels */ 580 - pclk = DIV_ROUND_UP_ULL(1000000000000, mode->clock); 580 + pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000)); 581 581 dev_dbg(d->dev, "picoseconds between two pixels: %llu\n", 582 582 pclk); 583 583
+114 -41
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 157 157 * GPU registers so we need to add 0x1a800 to the register value on A630 158 158 * to get the right value from PM4. 159 159 */ 160 - get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 160 + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 161 161 rbmemptr_stats(ring, index, alwayson_start)); 162 162 163 163 /* Invalidate CCU depth and color */ ··· 187 187 188 188 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 189 189 rbmemptr_stats(ring, index, cpcycles_end)); 190 - get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 190 + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 191 191 rbmemptr_stats(ring, index, alwayson_end)); 192 192 193 193 /* Write the fence to the scratch register */ ··· 206 206 OUT_RING(ring, submit->seqno); 207 207 208 208 trace_msm_gpu_submit_flush(submit, 209 - gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L, 210 - REG_A6XX_GMU_ALWAYS_ON_COUNTER_H)); 209 + gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 210 + REG_A6XX_CP_ALWAYS_ON_COUNTER_HI)); 211 211 212 212 a6xx_flush(gpu, ring); 213 213 } ··· 462 462 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 463 463 } 464 464 465 + /* For a615, a616, a618, A619, a630, a640 and a680 */ 466 + static const u32 a6xx_protect[] = { 467 + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 468 + A6XX_PROTECT_RDONLY(0x00501, 0x0005), 469 + A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 470 + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 471 + A6XX_PROTECT_NORDWR(0x00510, 0x0000), 472 + A6XX_PROTECT_NORDWR(0x00534, 0x0000), 473 + A6XX_PROTECT_NORDWR(0x00800, 0x0082), 474 + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 475 + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 476 + A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 477 + A6XX_PROTECT_NORDWR(0x00900, 0x004d), 478 + A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 479 + A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 480 + A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 481 + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 482 + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 483 + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 484 + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 485 + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 486 + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 487 + A6XX_PROTECT_NORDWR(0x09624, 0x01db), 488 + A6XX_PROTECT_NORDWR(0x09e70, 0x0001), 489 + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 490 + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 491 + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 492 + A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 493 + A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 494 + A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 495 + A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 496 + A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 497 + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 498 + A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ 499 + }; 500 + 501 + /* These are for a620 and a650 */ 502 + static const u32 a650_protect[] = { 503 + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 504 + A6XX_PROTECT_RDONLY(0x00501, 0x0005), 505 + A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 506 + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 507 + A6XX_PROTECT_NORDWR(0x00510, 0x0000), 508 + A6XX_PROTECT_NORDWR(0x00534, 0x0000), 509 + A6XX_PROTECT_NORDWR(0x00800, 0x0082), 510 + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 511 + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 512 + A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 513 + A6XX_PROTECT_NORDWR(0x00900, 0x004d), 514 + A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 515 + A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 516 + A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 517 + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 518 + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 519 + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 520 + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 521 + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 522 + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 523 + A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 524 + A6XX_PROTECT_NORDWR(0x09624, 0x01db), 525 + A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 526 + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 527 + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 528 + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 529 + A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 530 + A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 531 + A6XX_PROTECT_NORDWR(0x0b608, 0x0007), 532 + A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 533 + A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 534 + A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 535 + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 536 + A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 537 + A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), 538 + A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 539 + A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 540 + A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 541 + A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 542 + }; 543 + 544 + static void a6xx_set_cp_protect(struct msm_gpu *gpu) 545 + { 546 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 547 + const u32 *regs = a6xx_protect; 548 + unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32; 549 + 550 + BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32); 551 + BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48); 552 + 553 + if (adreno_is_a650(adreno_gpu)) { 554 + regs = a650_protect; 555 + count = ARRAY_SIZE(a650_protect); 556 + count_max = 48; 557 + } 558 + 559 + /* 560 + * Enable access protection to privileged registers, fault on an access 561 + * protect violation and select the last span to protect from the start 562 + * address all the way to the end of the register address space 563 + */ 564 + gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); 565 + 566 + for (i = 0; i < count - 1; i++) 567 + gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); 568 + /* last CP_PROTECT to have "infinite" length on the last entry */ 569 + gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); 570 + } 571 + 465 572 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 466 573 { 467 574 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); ··· 596 489 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); 597 490 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); 598 491 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 599 - uavflagprd_inv >> 4 | lower_bit << 1); 492 + uavflagprd_inv << 4 | lower_bit << 1); 600 493 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); 601 494 } 602 495 ··· 883 776 } 884 777 885 778 /* Protect registers from the CP */ 886 - gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); 887 - 888 - gpu_write(gpu, REG_A6XX_CP_PROTECT(0), 889 - A6XX_PROTECT_RDONLY(0x600, 0x51)); 890 - gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); 891 - gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); 892 - gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); 893 - gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); 894 - gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); 895 - gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); 896 - gpu_write(gpu, REG_A6XX_CP_PROTECT(7), 897 - A6XX_PROTECT_RDONLY(0xfc00, 0x3)); 898 - gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); 899 - gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); 900 - gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); 901 - gpu_write(gpu, REG_A6XX_CP_PROTECT(11), 902 - A6XX_PROTECT_RDONLY(0x0, 0x4f9)); 903 - gpu_write(gpu, REG_A6XX_CP_PROTECT(12), 904 - A6XX_PROTECT_RDONLY(0x501, 0xa)); 905 - gpu_write(gpu, REG_A6XX_CP_PROTECT(13), 906 - A6XX_PROTECT_RDONLY(0x511, 0x44)); 907 - gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); 908 - gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); 909 - gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); 910 - gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); 911 - gpu_write(gpu, REG_A6XX_CP_PROTECT(18), 912 - A6XX_PROTECT_RW(0xbe20, 0x11f3)); 913 - gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); 914 - gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); 915 - gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); 916 - gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); 917 - gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); 918 - gpu_write(gpu, REG_A6XX_CP_PROTECT(24), 919 - A6XX_PROTECT_RDONLY(0x980, 0x4)); 920 - gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); 779 + a6xx_set_cp_protect(gpu); 921 780 922 781 /* Enable expanded apriv for targets that support it */ 923 782 if (gpu->hw_apriv) { ··· 1284 1211 if (ret) 1285 1212 return ret; 1286 1213 1287 - if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1214 + if (a6xx_gpu->shadow_bo) 1288 1215 for (i = 0; i < gpu->nr_rings; i++) 1289 1216 a6xx_gpu->shadow[i] = 0; 1290 1217
+1 -1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
··· 44 44 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 45 45 * registers starting at _reg. 46 46 */ 47 - #define A6XX_PROTECT_RW(_reg, _len) \ 47 + #define A6XX_PROTECT_NORDWR(_reg, _len) \ 48 48 ((1 << 31) | \ 49 49 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 50 50
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
··· 432 432 pll_freq += div_u64(tmp64, multiplier); 433 433 434 434 vco_rate = pll_freq; 435 + pll_10nm->vco_current_rate = vco_rate; 435 436 436 437 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", 437 438 pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
··· 460 460 pll_freq += div_u64(tmp64, multiplier); 461 461 462 462 vco_rate = pll_freq; 463 + pll_7nm->vco_current_rate = vco_rate; 463 464 464 465 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", 465 466 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
+7
drivers/gpu/drm/msm/msm_gem.c
··· 1241 1241 1242 1242 to_msm_bo(obj)->vram_node = &vma->node; 1243 1243 1244 + /* Call chain get_pages() -> update_inactive() tries to 1245 + * access msm_obj->mm_list, but it is not initialized yet. 1246 + * To avoid NULL pointer dereference error, initialize 1247 + * mm_list to be empty. 1248 + */ 1249 + INIT_LIST_HEAD(&msm_obj->mm_list); 1250 + 1244 1251 msm_gem_lock(obj); 1245 1252 pages = get_pages(obj); 1246 1253 msm_gem_unlock(obj);
+2 -2
drivers/gpu/drm/radeon/radeon_uvd.c
··· 286 286 if (rdev->uvd.vcpu_bo == NULL) 287 287 return -EINVAL; 288 288 289 - memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 289 + memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 290 290 291 291 size = radeon_bo_size(rdev->uvd.vcpu_bo); 292 292 size -= rdev->uvd_fw->size; ··· 294 294 ptr = rdev->uvd.cpu_addr; 295 295 ptr += rdev->uvd_fw->size; 296 296 297 - memset(ptr, 0, size); 297 + memset_io((void __iomem *)ptr, 0, size); 298 298 299 299 return 0; 300 300 }
+27 -4
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
··· 209 209 goto err_disable_clk_tmds; 210 210 } 211 211 212 - ret = sun8i_hdmi_phy_probe(hdmi, phy_node); 212 + ret = sun8i_hdmi_phy_get(hdmi, phy_node); 213 213 of_node_put(phy_node); 214 214 if (ret) { 215 215 dev_err(dev, "Couldn't get the HDMI PHY\n"); ··· 242 242 243 243 cleanup_encoder: 244 244 drm_encoder_cleanup(encoder); 245 - sun8i_hdmi_phy_remove(hdmi); 246 245 err_disable_clk_tmds: 247 246 clk_disable_unprepare(hdmi->clk_tmds); 248 247 err_assert_ctrl_reset: ··· 262 263 struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev); 263 264 264 265 dw_hdmi_unbind(hdmi->hdmi); 265 - sun8i_hdmi_phy_remove(hdmi); 266 266 clk_disable_unprepare(hdmi->clk_tmds); 267 267 reset_control_assert(hdmi->rst_ctrl); 268 268 gpiod_set_value(hdmi->ddc_en, 0); ··· 318 320 .of_match_table = sun8i_dw_hdmi_dt_ids, 319 321 }, 320 322 }; 321 - module_platform_driver(sun8i_dw_hdmi_pltfm_driver); 323 + 324 + static int __init sun8i_dw_hdmi_init(void) 325 + { 326 + int ret; 327 + 328 + ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver); 329 + if (ret) 330 + return ret; 331 + 332 + ret = platform_driver_register(&sun8i_hdmi_phy_driver); 333 + if (ret) { 334 + platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver); 335 + return ret; 336 + } 337 + 338 + return ret; 339 + } 340 + 341 + static void __exit sun8i_dw_hdmi_exit(void) 342 + { 343 + platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver); 344 + platform_driver_unregister(&sun8i_hdmi_phy_driver); 345 + } 346 + 347 + module_init(sun8i_dw_hdmi_init); 348 + module_exit(sun8i_dw_hdmi_exit); 322 349 323 350 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>"); 324 351 MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
+3 -2
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
··· 195 195 struct gpio_desc *ddc_en; 196 196 }; 197 197 198 + extern struct platform_driver sun8i_hdmi_phy_driver; 199 + 198 200 static inline struct sun8i_dw_hdmi * 199 201 encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder) 200 202 { 201 203 return container_of(encoder, struct sun8i_dw_hdmi, encoder); 202 204 } 203 205 204 - int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node); 205 - void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi); 206 + int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node); 206 207 207 208 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy); 208 209 void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
+36 -5
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
··· 5 5 6 6 #include <linux/delay.h> 7 7 #include <linux/of_address.h> 8 + #include <linux/of_platform.h> 8 9 9 10 #include "sun8i_dw_hdmi.h" 10 11 ··· 598 597 { /* sentinel */ } 599 598 }; 600 599 601 - int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 600 + int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 601 + { 602 + struct platform_device *pdev = of_find_device_by_node(node); 603 + struct sun8i_hdmi_phy *phy; 604 + 605 + if (!pdev) 606 + return -EPROBE_DEFER; 607 + 608 + phy = platform_get_drvdata(pdev); 609 + if (!phy) 610 + return -EPROBE_DEFER; 611 + 612 + hdmi->phy = phy; 613 + 614 + put_device(&pdev->dev); 615 + 616 + return 0; 617 + } 618 + 619 + static int sun8i_hdmi_phy_probe(struct platform_device *pdev) 602 620 { 603 621 const struct of_device_id *match; 604 - struct device *dev = hdmi->dev; 622 + struct device *dev = &pdev->dev; 623 + struct device_node *node = dev->of_node; 605 624 struct sun8i_hdmi_phy *phy; 606 625 struct resource res; 607 626 void __iomem *regs; ··· 725 704 clk_prepare_enable(phy->clk_phy); 726 705 } 727 706 728 - hdmi->phy = phy; 707 + platform_set_drvdata(pdev, phy); 729 708 730 709 return 0; 731 710 ··· 749 728 return ret; 750 729 } 751 730 752 - void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) 731 + static int sun8i_hdmi_phy_remove(struct platform_device *pdev) 753 732 { 754 - struct sun8i_hdmi_phy *phy = hdmi->phy; 733 + struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev); 755 734 756 735 clk_disable_unprepare(phy->clk_mod); 757 736 clk_disable_unprepare(phy->clk_bus); ··· 765 744 clk_put(phy->clk_pll1); 766 745 clk_put(phy->clk_mod); 767 746 clk_put(phy->clk_bus); 747 + return 0; 768 748 } 749 + 750 + struct platform_driver sun8i_hdmi_phy_driver = { 751 + .probe = sun8i_hdmi_phy_probe, 752 + .remove = sun8i_hdmi_phy_remove, 753 + .driver = { 754 + .name = "sun8i-hdmi-phy", 755 + .of_match_table = sun8i_hdmi_phy_of_table, 756 + }, 757 + };
+4 -1
drivers/gpu/drm/ttm/ttm_bo.c
··· 1172 1172 if (!ttm_bo_evict_swapout_allowable(bo, ctx, &locked, NULL)) 1173 1173 return -EBUSY; 1174 1174 1175 - if (!ttm_bo_get_unless_zero(bo)) { 1175 + if (!bo->ttm || !ttm_tt_is_populated(bo->ttm) || 1176 + bo->ttm->page_flags & TTM_PAGE_FLAG_SG || 1177 + bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED || 1178 + !ttm_bo_get_unless_zero(bo)) { 1176 1179 if (locked) 1177 1180 dma_resv_unlock(bo->base.resv); 1178 1181 return -EBUSY;
+1 -7
drivers/gpu/drm/ttm/ttm_device.c
··· 143 143 144 144 for (j = 0; j < TTM_MAX_BO_PRIORITY; ++j) { 145 145 list_for_each_entry(bo, &man->lru[j], lru) { 146 - uint32_t num_pages; 146 + uint32_t num_pages = PFN_UP(bo->base.size); 147 147 148 - if (!bo->ttm || !ttm_tt_is_populated(bo->ttm) || 149 - bo->ttm->page_flags & TTM_PAGE_FLAG_SG || 150 - bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED) 151 - continue; 152 - 153 - num_pages = bo->ttm->num_pages; 154 148 ret = ttm_bo_swapout(bo, ctx, gfp_flags); 155 149 /* ttm_bo_swapout has dropped the lru_lock */ 156 150 if (!ret)
+1 -1
drivers/gpu/drm/vc4/vc4_kms.c
··· 372 372 if (!old_hvs_state->fifo_state[channel].in_use) 373 373 continue; 374 374 375 - ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[i].pending_commit); 375 + ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[channel].pending_commit); 376 376 if (ret) 377 377 drm_err(dev, "Timed out waiting for commit\n"); 378 378 }