Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (42 commits)
drm/radeon/kms/pm: switch to dynamically allocating clock mode array
drm/radeon/kms: optimize r600_pm_profile_init
drm/radeon/kms/pm: add a proper pm profile init function for fusion
drm/radeon/kms: remove extraneous calls to radeon_pm_compute_clocks()
drm/exynos: added padding to be 64-bit align.
drm: fix kconfig unmet dependency warning
drm: add some comments to drm_wait_vblank and drm_queue_vblank_event
drm/radeon/benchmark: signedness bug in radeon_benchmark_move()
drm: do not sleep on vblank while holding a mutex
MAINTAINERS: exynos: Add EXYNOS DRM maintainer entry
drm: try to restore previous CRTC config if mode set fails
drm/radeon/kms: make an aux failure debug only
drm: drop select of SLOW_WORK
drm: serialize access to list of debugfs files
drm/radeon/kms: fix use of vram scratch page on evergreen/ni
drm/radeon: Make sure CS mutex is held across GPU reset.
drm: Ensure string is null terminated.
vmwgfx: Only allow 64x64 cursors
vmwgfx: Initialize clip rect loop correctly in surface dirty
vmwgfx: Close screen object system
...
+441
-234
+7
MAINTAINERS
+7
MAINTAINERS
···
2342
2342
F: drivers/gpu/drm/i915
2343
2343
F: include/drm/i915*
2344
2344
2345
+
DRM DRIVERS FOR EXYNOS
2346
+
M: Inki Dae <inki.dae@samsung.com>
2347
+
L: dri-devel@lists.freedesktop.org
2348
+
S: Supported
2349
+
F: drivers/gpu/drm/exynos
2350
+
F: include/drm/exynos*
2351
+
2345
2352
DSCC4 DRIVER
2346
2353
M: Francois Romieu <romieu@fr.zoreil.com>
2347
2354
L: netdev@vger.kernel.org
+4
-3
drivers/char/agp/intel-gtt.c
+4
-3
drivers/char/agp/intel-gtt.c
···
1186
1186
/* Certain Gen5 chipsets require require idling the GPU before
1187
1187
* unmapping anything from the GTT when VT-d is enabled.
1188
1188
*/
1189
-
extern int intel_iommu_gfx_mapped;
1190
1189
static inline int needs_idle_maps(void)
1191
1190
{
1191
+
#ifdef CONFIG_INTEL_IOMMU
1192
1192
const unsigned short gpu_devid = intel_private.pcidev->device;
1193
+
extern int intel_iommu_gfx_mapped;
1193
1194
1194
1195
/* Query intel_iommu to see if we need the workaround. Presumably that
1195
1196
* was loaded first.
···
1199
1198
gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1200
1199
intel_iommu_gfx_mapped)
1201
1200
return 1;
1202
-
1201
+
#endif
1203
1202
return 0;
1204
1203
}
1205
1204
···
1237
1236
intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1238
1237
}
1239
1238
1240
-
if (needs_idle_maps());
1239
+
if (needs_idle_maps())
1241
1240
intel_private.base.do_idle_maps = 1;
1242
1241
1243
1242
intel_i9xx_setup_flush();
+1
-1
drivers/gpu/drm/Kconfig
+1
-1
drivers/gpu/drm/Kconfig
···
9
9
depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU
10
10
select I2C
11
11
select I2C_ALGOBIT
12
-
select SLOW_WORK
13
12
help
14
13
Kernel-level support for the Direct Rendering Infrastructure (DRI)
15
14
introduced in XFree86 4.0. If you say Y here, you need to select
···
95
96
select FB_CFB_IMAGEBLIT
96
97
# i915 depends on ACPI_VIDEO when ACPI is enabled
97
98
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
99
+
select BACKLIGHT_LCD_SUPPORT if ACPI
98
100
select BACKLIGHT_CLASS_DEVICE if ACPI
99
101
select VIDEO_OUTPUT_CONTROL if ACPI
100
102
select INPUT if ACPI
+3
-1
drivers/gpu/drm/drm_crtc.c
+3
-1
drivers/gpu/drm/drm_crtc.c
···
2118
2118
property->num_values = num_values;
2119
2119
INIT_LIST_HEAD(&property->enum_blob_list);
2120
2120
2121
-
if (name)
2121
+
if (name) {
2122
2122
strncpy(property->name, name, DRM_PROP_NAME_LEN);
2123
+
property->name[DRM_PROP_NAME_LEN-1] = '\0';
2124
+
}
2123
2125
2124
2126
list_add_tail(&property->head, &dev->mode_config.property_list);
2125
2127
return property;
+13
drivers/gpu/drm/drm_crtc_helper.c
+13
drivers/gpu/drm/drm_crtc_helper.c
···
484
484
struct drm_connector *save_connectors, *connector;
485
485
int count = 0, ro, fail = 0;
486
486
struct drm_crtc_helper_funcs *crtc_funcs;
487
+
struct drm_mode_set save_set;
487
488
int ret = 0;
488
489
int i;
489
490
···
556
555
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
557
556
save_connectors[count++] = *connector;
558
557
}
558
+
559
+
save_set.crtc = set->crtc;
560
+
save_set.mode = &set->crtc->mode;
561
+
save_set.x = set->crtc->x;
562
+
save_set.y = set->crtc->y;
563
+
save_set.fb = set->crtc->fb;
559
564
560
565
/* We should be able to check here if the fb has the same properties
561
566
* and then just flip_or_move it */
···
727
720
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
728
721
*connector = save_connectors[count++];
729
722
}
723
+
724
+
/* Try to restore the config */
725
+
if (mode_changed &&
726
+
!drm_crtc_helper_set_mode(save_set.crtc, save_set.mode, save_set.x,
727
+
save_set.y, save_set.fb))
728
+
DRM_ERROR("failed to restore config after modeset failure\n");
730
729
731
730
kfree(save_connectors);
732
731
kfree(save_encoders);
+9
-3
drivers/gpu/drm/drm_debugfs.c
+9
-3
drivers/gpu/drm/drm_debugfs.c
···
118
118
tmp->minor = minor;
119
119
tmp->dent = ent;
120
120
tmp->info_ent = &files[i];
121
-
list_add(&(tmp->list), &(minor->debugfs_nodes.list));
121
+
122
+
mutex_lock(&minor->debugfs_lock);
123
+
list_add(&tmp->list, &minor->debugfs_list);
124
+
mutex_unlock(&minor->debugfs_lock);
122
125
}
123
126
return 0;
124
127
···
149
146
char name[64];
150
147
int ret;
151
148
152
-
INIT_LIST_HEAD(&minor->debugfs_nodes.list);
149
+
INIT_LIST_HEAD(&minor->debugfs_list);
150
+
mutex_init(&minor->debugfs_lock);
153
151
sprintf(name, "%d", minor_id);
154
152
minor->debugfs_root = debugfs_create_dir(name, root);
155
153
if (!minor->debugfs_root) {
···
196
192
struct drm_info_node *tmp;
197
193
int i;
198
194
195
+
mutex_lock(&minor->debugfs_lock);
199
196
for (i = 0; i < count; i++) {
200
-
list_for_each_safe(pos, q, &minor->debugfs_nodes.list) {
197
+
list_for_each_safe(pos, q, &minor->debugfs_list) {
201
198
tmp = list_entry(pos, struct drm_info_node, list);
202
199
if (tmp->info_ent == &files[i]) {
203
200
debugfs_remove(tmp->dent);
···
207
202
}
208
203
}
209
204
}
205
+
mutex_unlock(&minor->debugfs_lock);
210
206
return 0;
211
207
}
212
208
EXPORT_SYMBOL(drm_debugfs_remove_files);
+1
-1
drivers/gpu/drm/drm_drv.c
+1
-1
drivers/gpu/drm/drm_drv.c
···
125
125
DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_sg_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
126
126
DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_sg_free, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
127
127
128
-
DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, 0),
128
+
DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
129
129
130
130
DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
131
131
+15
-7
drivers/gpu/drm/drm_irq.c
+15
-7
drivers/gpu/drm/drm_irq.c
···
407
407
/*
408
408
* Wake up any waiters so they don't hang.
409
409
*/
410
-
spin_lock_irqsave(&dev->vbl_lock, irqflags);
411
-
for (i = 0; i < dev->num_crtcs; i++) {
412
-
DRM_WAKEUP(&dev->vbl_queue[i]);
413
-
dev->vblank_enabled[i] = 0;
414
-
dev->last_vblank[i] = dev->driver->get_vblank_counter(dev, i);
410
+
if (dev->num_crtcs) {
411
+
spin_lock_irqsave(&dev->vbl_lock, irqflags);
412
+
for (i = 0; i < dev->num_crtcs; i++) {
413
+
DRM_WAKEUP(&dev->vbl_queue[i]);
414
+
dev->vblank_enabled[i] = 0;
415
+
dev->last_vblank[i] =
416
+
dev->driver->get_vblank_counter(dev, i);
417
+
}
418
+
spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
415
419
}
416
-
spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
417
420
418
421
if (!irq_enabled)
419
422
return -EINVAL;
···
1128
1125
trace_drm_vblank_event_delivered(current->pid, pipe,
1129
1126
vblwait->request.sequence);
1130
1127
} else {
1128
+
/* drm_handle_vblank_events will call drm_vblank_put */
1131
1129
list_add_tail(&e->base.link, &dev->vblank_event_list);
1132
1130
vblwait->reply.sequence = vblwait->request.sequence;
1133
1131
}
···
1209
1205
goto done;
1210
1206
}
1211
1207
1212
-
if (flags & _DRM_VBLANK_EVENT)
1208
+
if (flags & _DRM_VBLANK_EVENT) {
1209
+
/* must hold on to the vblank ref until the event fires
1210
+
* drm_vblank_put will be called asynchronously
1211
+
*/
1213
1212
return drm_queue_vblank_event(dev, crtc, vblwait, file_priv);
1213
+
}
1214
1214
1215
1215
if ((flags & _DRM_VBLANK_NEXTONMISS) &&
1216
1216
(seq - vblwait->request.sequence) <= (1<<23)) {
+4
-1
drivers/gpu/drm/i915/i915_debugfs.c
+4
-1
drivers/gpu/drm/i915/i915_debugfs.c
···
1506
1506
node->minor = minor;
1507
1507
node->dent = ent;
1508
1508
node->info_ent = (void *) key;
1509
-
list_add(&node->list, &minor->debugfs_nodes.list);
1509
+
1510
+
mutex_lock(&minor->debugfs_lock);
1511
+
list_add(&node->list, &minor->debugfs_list);
1512
+
mutex_unlock(&minor->debugfs_lock);
1510
1513
1511
1514
return 0;
1512
1515
}
+1
-1
drivers/gpu/drm/i915/i915_gem.c
+1
-1
drivers/gpu/drm/i915/i915_gem.c
+13
-9
drivers/gpu/drm/nouveau/nouveau_bios.c
+13
-9
drivers/gpu/drm/nouveau/nouveau_bios.c
···
640
640
nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
641
641
{
642
642
struct drm_nouveau_private *dev_priv = dev->dev_private;
643
-
uint32_t reg0 = nv_rd32(dev, reg + 0);
644
-
uint32_t reg1 = nv_rd32(dev, reg + 4);
645
643
struct nouveau_pll_vals pll;
646
644
struct pll_lims pll_limits;
645
+
u32 ctrl, mask, coef;
647
646
int ret;
648
647
649
648
ret = get_pll_limits(dev, reg, &pll_limits);
···
653
654
if (!clk)
654
655
return -ERANGE;
655
656
656
-
reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
657
-
reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
658
-
659
-
if (dev_priv->vbios.execute) {
660
-
still_alive();
661
-
nv_wr32(dev, reg + 4, reg1);
662
-
nv_wr32(dev, reg + 0, reg0);
657
+
coef = pll.N1 << 8 | pll.M1;
658
+
ctrl = pll.log2P << 16;
659
+
mask = 0x00070000;
660
+
if (reg == 0x004008) {
661
+
mask |= 0x01f80000;
662
+
ctrl |= (pll_limits.log2p_bias << 19);
663
+
ctrl |= (pll.log2P << 22);
663
664
}
664
665
666
+
if (!dev_priv->vbios.execute)
667
+
return 0;
668
+
669
+
nv_mask(dev, reg + 0, mask, ctrl);
670
+
nv_wr32(dev, reg + 4, coef);
665
671
return 0;
666
672
}
667
673
+1
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
···
148
148
149
149
if (dev_priv->card_type == NV_10 &&
150
150
nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
151
-
nvbo->bo.mem.num_pages < vram_pages / 2) {
151
+
nvbo->bo.mem.num_pages < vram_pages / 4) {
152
152
/*
153
153
* Make sure that the color and depth buffers are handled
154
154
* by independent memory controller units. Up to a 9x
+1
drivers/gpu/drm/nouveau/nouveau_channel.c
+1
drivers/gpu/drm/nouveau/nouveau_channel.c
···
158
158
INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
159
159
INIT_LIST_HEAD(&chan->nvsw.flip);
160
160
INIT_LIST_HEAD(&chan->fence.pending);
161
+
spin_lock_init(&chan->fence.lock);
161
162
162
163
/* setup channel's memory and vm */
163
164
ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
+1
-1
drivers/gpu/drm/nouveau/nouveau_connector.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_connector.c
+10
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.c
+10
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.c
···
487
487
{
488
488
struct drm_nouveau_private *dev_priv = dev->dev_private;
489
489
struct nouveau_fbdev *nfbdev;
490
+
int preferred_bpp;
490
491
int ret;
491
492
492
493
nfbdev = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);
···
506
505
}
507
506
508
507
drm_fb_helper_single_add_all_connectors(&nfbdev->helper);
509
-
drm_fb_helper_initial_config(&nfbdev->helper, 32);
508
+
509
+
if (dev_priv->vram_size <= 32 * 1024 * 1024)
510
+
preferred_bpp = 8;
511
+
else if (dev_priv->vram_size <= 64 * 1024 * 1024)
512
+
preferred_bpp = 16;
513
+
else
514
+
preferred_bpp = 32;
515
+
516
+
drm_fb_helper_initial_config(&nfbdev->helper, preferred_bpp);
510
517
return 0;
511
518
}
512
519
-2
drivers/gpu/drm/nouveau/nouveau_fence.c
-2
drivers/gpu/drm/nouveau/nouveau_fence.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_i2c.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_i2c.c
···
333
333
334
334
NV_DEBUG(dev, "Probing %ss on I2C bus: %d\n", what, index);
335
335
336
-
for (i = 0; info[i].addr; i++) {
336
+
for (i = 0; i2c && info[i].addr; i++) {
337
337
if (nouveau_probe_i2c_addr(i2c, info[i].addr) &&
338
338
(!match || match(i2c, &info[i]))) {
339
339
NV_INFO(dev, "Detected %s: %s\n", what, info[i].type);
+1
-1
drivers/gpu/drm/nouveau/nouveau_perf.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_perf.c
+11
-2
drivers/gpu/drm/nouveau/nouveau_state.c
+11
-2
drivers/gpu/drm/nouveau/nouveau_state.c
···
579
579
if (ret)
580
580
goto out_display_early;
581
581
582
+
/* workaround an odd issue on nvc1 by disabling the device's
583
+
* nosnoop capability. hopefully won't cause issues until a
584
+
* better fix is found - assuming there is one...
585
+
*/
586
+
if (dev_priv->chipset == 0xc1) {
587
+
nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
588
+
}
589
+
582
590
nouveau_pm_init(dev);
583
591
584
592
ret = engine->vram.init(dev);
···
1110
1102
dev_priv->noaccel = !!nouveau_noaccel;
1111
1103
if (nouveau_noaccel == -1) {
1112
1104
switch (dev_priv->chipset) {
1113
-
case 0xc1: /* known broken */
1114
-
case 0xc8: /* never tested */
1105
+
#if 0
1106
+
case 0xXX: /* known broken */
1115
1107
NV_INFO(dev, "acceleration disabled by default, pass "
1116
1108
"noaccel=0 to force enable\n");
1117
1109
dev_priv->noaccel = true;
1118
1110
break;
1111
+
#endif
1119
1112
default:
1120
1113
dev_priv->noaccel = false;
1121
1114
break;
+15
-5
drivers/gpu/drm/nouveau/nv40_pm.c
+15
-5
drivers/gpu/drm/nouveau/nv40_pm.c
···
57
57
int P = (ctrl & 0x00070000) >> 16;
58
58
u32 ref = 27000, clk = 0;
59
59
60
-
if (ctrl & 0x80000000)
60
+
if ((ctrl & 0x80000000) && M1) {
61
61
clk = ref * N1 / M1;
62
-
63
-
if (!(ctrl & 0x00000100)) {
64
-
if (ctrl & 0x40000000)
65
-
clk = clk * N2 / M2;
62
+
if ((ctrl & 0x40000100) == 0x40000000) {
63
+
if (M2)
64
+
clk = clk * N2 / M2;
65
+
else
66
+
clk = 0;
67
+
}
66
68
}
67
69
68
70
return clk >> P;
···
179
177
}
180
178
181
179
/* memory clock */
180
+
if (!perflvl->memory) {
181
+
info->mpll_ctrl = 0x00000000;
182
+
goto out;
183
+
}
184
+
182
185
ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
183
186
&N1, &M1, &N2, &M2, &log2P);
184
187
if (ret < 0)
···
270
263
nv_mask(dev, 0x004008, 0xc007ffff, info->spll);
271
264
mdelay(5);
272
265
nv_mask(dev, 0x00c040, 0x00000333, info->ctrl);
266
+
267
+
if (!info->mpll_ctrl)
268
+
goto resume;
273
269
274
270
/* wait for vblank start on active crtcs, disable memory access */
275
271
for (i = 0; i < 2; i++) {
+2
-2
drivers/gpu/drm/nouveau/nv50_graph.c
+2
-2
drivers/gpu/drm/nouveau/nv50_graph.c
···
131
131
NV_DEBUG(dev, "\n");
132
132
133
133
/* master reset */
134
-
nv_mask(dev, 0x000200, 0x00200100, 0x00000000);
135
-
nv_mask(dev, 0x000200, 0x00200100, 0x00200100);
134
+
nv_mask(dev, 0x000200, 0x00201000, 0x00000000);
135
+
nv_mask(dev, 0x000200, 0x00201000, 0x00201000);
136
136
nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
137
137
138
138
/* reset/enable traps and interrupts */
+1
-1
drivers/gpu/drm/nouveau/nv50_grctx.c
+1
-1
drivers/gpu/drm/nouveau/nv50_grctx.c
+1
-1
drivers/gpu/drm/nouveau/nv50_vram.c
+1
-1
drivers/gpu/drm/nouveau/nv50_vram.c
···
160
160
colbits = (r4 & 0x0000f000) >> 12;
161
161
rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
162
162
rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
163
-
banks = ((r4 & 0x01000000) ? 8 : 4);
163
+
banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
164
164
165
165
rowsize = parts * banks * (1 << colbits) * 8;
166
166
predicted = rowsize << rowbitsa;
+32
-9
drivers/gpu/drm/nouveau/nvc0_graph.c
+32
-9
drivers/gpu/drm/nouveau/nvc0_graph.c
···
157
157
struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
158
158
struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
159
159
struct drm_device *dev = chan->dev;
160
+
struct drm_nouveau_private *dev_priv = dev->dev_private;
160
161
int i = 0, gpc, tp, ret;
161
-
u32 magic;
162
162
163
163
ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
164
164
&grch->unk408004);
···
207
207
nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
208
208
nv_wo32(grch->mmio, i++ * 4, 0x80000018);
209
209
210
-
magic = 0x02180000;
211
-
nv_wo32(grch->mmio, i++ * 4, 0x00405830);
212
-
nv_wo32(grch->mmio, i++ * 4, magic);
213
-
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
214
-
for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) {
215
-
u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
216
-
nv_wo32(grch->mmio, i++ * 4, reg);
217
-
nv_wo32(grch->mmio, i++ * 4, magic);
210
+
if (dev_priv->chipset != 0xc1) {
211
+
u32 magic = 0x02180000;
212
+
nv_wo32(grch->mmio, i++ * 4, 0x00405830);
213
+
nv_wo32(grch->mmio, i++ * 4, magic);
214
+
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
215
+
for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
216
+
u32 reg = TP_UNIT(gpc, tp, 0x520);
217
+
nv_wo32(grch->mmio, i++ * 4, reg);
218
+
nv_wo32(grch->mmio, i++ * 4, magic);
219
+
magic += 0x0324;
220
+
}
221
+
}
222
+
} else {
223
+
u32 magic = 0x02180000;
224
+
nv_wo32(grch->mmio, i++ * 4, 0x00405830);
225
+
nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218);
226
+
nv_wo32(grch->mmio, i++ * 4, 0x004064c4);
227
+
nv_wo32(grch->mmio, i++ * 4, 0x0086ffff);
228
+
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
229
+
for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
230
+
u32 reg = TP_UNIT(gpc, tp, 0x520);
231
+
nv_wo32(grch->mmio, i++ * 4, reg);
232
+
nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic);
233
+
magic += 0x0324;
234
+
}
235
+
for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
236
+
u32 reg = TP_UNIT(gpc, tp, 0x544);
237
+
nv_wo32(grch->mmio, i++ * 4, reg);
238
+
nv_wo32(grch->mmio, i++ * 4, magic);
239
+
magic += 0x0324;
240
+
}
218
241
}
219
242
}
220
243
+14
-17
drivers/gpu/drm/nouveau/nvc0_grctx.c
+14
-17
drivers/gpu/drm/nouveau/nvc0_grctx.c
···
1812
1812
/* calculate first set of magics */
1813
1813
memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
1814
1814
1815
+
gpc = -1;
1815
1816
for (tp = 0; tp < priv->tp_total; tp++) {
1816
1817
do {
1817
1818
gpc = (gpc + 1) % priv->gpc_nr;
···
1862
1861
1863
1862
if (1) {
1864
1863
u32 tp_mask = 0, tp_set = 0;
1865
-
u8 tpnr[GPC_MAX];
1864
+
u8 tpnr[GPC_MAX], a, b;
1866
1865
1867
1866
memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
1868
1867
for (gpc = 0; gpc < priv->gpc_nr; gpc++)
1869
1868
tp_mask |= ((1 << priv->tp_nr[gpc]) - 1) << (gpc * 8);
1870
1869
1871
-
gpc = -1;
1872
-
for (i = 0, gpc = -1; i < 32; i++) {
1873
-
int ltp = i * (priv->tp_total - 1) / 32;
1870
+
for (i = 0, gpc = -1, b = -1; i < 32; i++) {
1871
+
a = (i * (priv->tp_total - 1)) / 32;
1872
+
if (a != b) {
1873
+
b = a;
1874
+
do {
1875
+
gpc = (gpc + 1) % priv->gpc_nr;
1876
+
} while (!tpnr[gpc]);
1877
+
tp = priv->tp_nr[gpc] - tpnr[gpc]--;
1874
1878
1875
-
do {
1876
-
gpc = (gpc + 1) % priv->gpc_nr;
1877
-
} while (!tpnr[gpc]);
1878
-
tp = priv->tp_nr[gpc] - tpnr[gpc]--;
1879
+
tp_set |= 1 << ((gpc * 8) + tp);
1880
+
}
1879
1881
1880
-
tp_set |= 1 << ((gpc * 8) + tp);
1881
-
1882
-
do {
1883
-
nv_wr32(dev, 0x406800 + (i * 0x20), tp_set);
1884
-
tp_set ^= tp_mask;
1885
-
nv_wr32(dev, 0x406c00 + (i * 0x20), tp_set);
1886
-
tp_set ^= tp_mask;
1887
-
} while (ltp == (++i * (priv->tp_total - 1) / 32));
1888
-
i--;
1882
+
nv_wr32(dev, 0x406800 + (i * 0x20), tp_set);
1883
+
nv_wr32(dev, 0x406c00 + (i * 0x20), tp_set ^ tp_mask);
1889
1884
}
1890
1885
}
1891
1886
+10
-6
drivers/gpu/drm/nouveau/nvc0_vram.c
+10
-6
drivers/gpu/drm/nouveau/nvc0_vram.c
···
43
43
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
44
44
0, 0, 0, 3, 3, 3, 3, 1, 1, 1, 1, 0, 0, 0, 0, 0,
45
45
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3,
46
-
3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3,
46
+
3, 3, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3,
47
47
3, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 3, 0, 3, 0, 3,
48
48
3, 0, 3, 3, 3, 3, 3, 0, 0, 3, 0, 3, 0, 3, 3, 0,
49
49
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 1, 1, 0
···
110
110
u32 bsize = nv_rd32(dev, 0x10f20c);
111
111
u32 offset, length;
112
112
bool uniform = true;
113
-
int ret, i;
113
+
int ret, part;
114
114
115
115
NV_DEBUG(dev, "0x100800: 0x%08x\n", nv_rd32(dev, 0x100800));
116
116
NV_DEBUG(dev, "parts 0x%08x bcast_mem_amount 0x%08x\n", parts, bsize);
117
117
118
118
/* read amount of vram attached to each memory controller */
119
-
for (i = 0; i < parts; i++) {
120
-
u32 psize = nv_rd32(dev, 0x11020c + (i * 0x1000));
119
+
part = 0;
120
+
while (parts) {
121
+
u32 psize = nv_rd32(dev, 0x11020c + (part++ * 0x1000));
122
+
if (psize == 0)
123
+
continue;
124
+
parts--;
125
+
121
126
if (psize != bsize) {
122
127
if (psize < bsize)
123
128
bsize = psize;
124
129
uniform = false;
125
130
}
126
131
127
-
NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", i, psize);
128
-
132
+
NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize);
129
133
dev_priv->vram_size += (u64)psize << 20;
130
134
}
131
135
-6
drivers/gpu/drm/radeon/atombios_crtc.c
-6
drivers/gpu/drm/radeon/atombios_crtc.c
···
1522
1522
struct drm_display_mode *mode,
1523
1523
struct drm_display_mode *adjusted_mode)
1524
1524
{
1525
-
struct drm_device *dev = crtc->dev;
1526
-
struct radeon_device *rdev = dev->dev_private;
1527
-
1528
-
/* adjust pm to upcoming mode change */
1529
-
radeon_pm_compute_clocks(rdev);
1530
-
1531
1525
if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1532
1526
return false;
1533
1527
return true;
+1
-1
drivers/gpu/drm/radeon/atombios_dp.c
+1
-1
drivers/gpu/drm/radeon/atombios_dp.c
+52
-1
drivers/gpu/drm/radeon/evergreen.c
+52
-1
drivers/gpu/drm/radeon/evergreen.c
···
157
157
return actual_temp * 1000;
158
158
}
159
159
160
+
void sumo_pm_init_profile(struct radeon_device *rdev)
161
+
{
162
+
int idx;
163
+
164
+
/* default */
165
+
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
166
+
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
167
+
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
168
+
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
169
+
170
+
/* low,mid sh/mh */
171
+
if (rdev->flags & RADEON_IS_MOBILITY)
172
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
173
+
else
174
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
175
+
176
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
177
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
178
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
179
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
180
+
181
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
182
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
183
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
184
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
185
+
186
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
187
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
188
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
189
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
190
+
191
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
192
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
193
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
194
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
195
+
196
+
/* high sh/mh */
197
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
198
+
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
199
+
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
200
+
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
201
+
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
202
+
rdev->pm.power_state[idx].num_clock_modes - 1;
203
+
204
+
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
205
+
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
206
+
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
207
+
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
208
+
rdev->pm.power_state[idx].num_clock_modes - 1;
209
+
}
210
+
160
211
void evergreen_pm_misc(struct radeon_device *rdev)
161
212
{
162
213
int req_ps_idx = rdev->pm.requested_power_state_index;
···
1270
1219
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1271
1220
rdev->mc.vram_end >> 12);
1272
1221
}
1273
-
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1222
+
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1274
1223
if (rdev->flags & RADEON_IS_IGP) {
1275
1224
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1276
1225
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
+32
-86
drivers/gpu/drm/radeon/r600.c
+32
-86
drivers/gpu/drm/radeon/r600.c
···
288
288
pcie_lanes);
289
289
}
290
290
291
-
static int r600_pm_get_type_index(struct radeon_device *rdev,
292
-
enum radeon_pm_state_type ps_type,
293
-
int instance)
294
-
{
295
-
int i;
296
-
int found_instance = -1;
297
-
298
-
for (i = 0; i < rdev->pm.num_power_states; i++) {
299
-
if (rdev->pm.power_state[i].type == ps_type) {
300
-
found_instance++;
301
-
if (found_instance == instance)
302
-
return i;
303
-
}
304
-
}
305
-
/* return default if no match */
306
-
return rdev->pm.default_power_state_index;
307
-
}
308
-
309
291
void rs780_pm_init_profile(struct radeon_device *rdev)
310
292
{
311
293
if (rdev->pm.num_power_states == 2) {
···
403
421
404
422
void r600_pm_init_profile(struct radeon_device *rdev)
405
423
{
424
+
int idx;
425
+
406
426
if (rdev->family == CHIP_R600) {
407
427
/* XXX */
408
428
/* default */
···
486
502
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
487
503
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
488
504
/* low sh */
489
-
if (rdev->flags & RADEON_IS_MOBILITY) {
490
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
491
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
493
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
494
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
495
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
496
-
} else {
497
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
498
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
499
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
500
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
501
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
502
-
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
503
-
}
505
+
if (rdev->flags & RADEON_IS_MOBILITY)
506
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
507
+
else
508
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
509
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
510
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
511
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
512
+
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
504
513
/* mid sh */
505
-
if (rdev->flags & RADEON_IS_MOBILITY) {
506
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
507
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
508
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
509
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
510
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
511
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
512
-
} else {
513
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
514
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
515
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
516
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
517
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
518
-
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
519
-
}
514
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
515
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
516
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
517
+
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
520
518
/* high sh */
521
-
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
522
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
523
-
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
524
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
519
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
520
+
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
521
+
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
525
522
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
526
523
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
527
524
/* low mh */
528
-
if (rdev->flags & RADEON_IS_MOBILITY) {
529
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
530
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
531
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
532
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
533
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
534
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
535
-
} else {
536
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
537
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
538
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
539
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
540
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
541
-
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
542
-
}
525
+
if (rdev->flags & RADEON_IS_MOBILITY)
526
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
527
+
else
528
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
529
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
530
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
531
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
532
+
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
543
533
/* mid mh */
544
-
if (rdev->flags & RADEON_IS_MOBILITY) {
545
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
546
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
547
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
548
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
549
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
550
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
551
-
} else {
552
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
553
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
554
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
555
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
556
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
557
-
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
558
-
}
534
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
535
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
536
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
537
+
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
559
538
/* high mh */
560
-
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
561
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
562
-
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
563
-
r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
539
+
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
540
+
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
541
+
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
564
542
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
565
543
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
566
544
}
+47
-3
drivers/gpu/drm/radeon/radeon.h
+47
-3
drivers/gpu/drm/radeon/radeon.h
···
784
784
785
785
struct radeon_power_state {
786
786
enum radeon_pm_state_type type;
787
-
/* XXX: use a define for num clock modes */
788
-
struct radeon_pm_clock_info clock_info[8];
787
+
struct radeon_pm_clock_info *clock_info;
789
788
/* number of valid clock modes in this power state */
790
789
int num_clock_modes;
791
790
struct radeon_pm_clock_info *default_clock_mode;
···
854
855
struct device *int_hwmon_dev;
855
856
};
856
857
858
+
int radeon_pm_get_type_index(struct radeon_device *rdev,
859
+
enum radeon_pm_state_type ps_type,
860
+
int instance);
857
861
858
862
/*
859
863
* Benchmarking
···
1144
1142
u64 gpu_addr;
1145
1143
};
1146
1144
1145
+
1146
+
/*
1147
+
* Mutex which allows recursive locking from the same process.
1148
+
*/
1149
+
struct radeon_mutex {
1150
+
struct mutex mutex;
1151
+
struct task_struct *owner;
1152
+
int level;
1153
+
};
1154
+
1155
+
static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1156
+
{
1157
+
mutex_init(&mutex->mutex);
1158
+
mutex->owner = NULL;
1159
+
mutex->level = 0;
1160
+
}
1161
+
1162
+
static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1163
+
{
1164
+
if (mutex_trylock(&mutex->mutex)) {
1165
+
/* The mutex was unlocked before, so it's ours now */
1166
+
mutex->owner = current;
1167
+
} else if (mutex->owner != current) {
1168
+
/* Another process locked the mutex, take it */
1169
+
mutex_lock(&mutex->mutex);
1170
+
mutex->owner = current;
1171
+
}
1172
+
/* Otherwise the mutex was already locked by this process */
1173
+
1174
+
mutex->level++;
1175
+
}
1176
+
1177
+
static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1178
+
{
1179
+
if (--mutex->level > 0)
1180
+
return;
1181
+
1182
+
mutex->owner = NULL;
1183
+
mutex_unlock(&mutex->mutex);
1184
+
}
1185
+
1186
+
1147
1187
/*
1148
1188
* Core structure, functions and helpers.
1149
1189
*/
···
1241
1197
struct radeon_gem gem;
1242
1198
struct radeon_pm pm;
1243
1199
uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1244
-
struct mutex cs_mutex;
1200
+
struct radeon_mutex cs_mutex;
1245
1201
struct radeon_wb wb;
1246
1202
struct radeon_dummy_page dummy_page;
1247
1203
bool gpu_lockup;
+1
-1
drivers/gpu/drm/radeon/radeon_asic.c
+1
-1
drivers/gpu/drm/radeon/radeon_asic.c
···
834
834
.pm_misc = &evergreen_pm_misc,
835
835
.pm_prepare = &evergreen_pm_prepare,
836
836
.pm_finish = &evergreen_pm_finish,
837
-
.pm_init_profile = &rs780_pm_init_profile,
837
+
.pm_init_profile = &sumo_pm_init_profile,
838
838
.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
839
839
.pre_page_flip = &evergreen_pre_page_flip,
840
840
.page_flip = &evergreen_page_flip,
+1
drivers/gpu/drm/radeon/radeon_asic.h
+1
drivers/gpu/drm/radeon/radeon_asic.h
···
413
413
extern void evergreen_pm_misc(struct radeon_device *rdev);
414
414
extern void evergreen_pm_prepare(struct radeon_device *rdev);
415
415
extern void evergreen_pm_finish(struct radeon_device *rdev);
416
+
extern void sumo_pm_init_profile(struct radeon_device *rdev);
416
417
extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
417
418
extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
418
419
extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
+81
-37
drivers/gpu/drm/radeon/radeon_atombios.c
+81
-37
drivers/gpu/drm/radeon/radeon_atombios.c
···
1999
1999
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2000
2000
switch (frev) {
2001
2001
case 1:
2002
+
rdev->pm.power_state[state_index].clock_info =
2003
+
kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2004
+
if (!rdev->pm.power_state[state_index].clock_info)
2005
+
return state_index;
2002
2006
rdev->pm.power_state[state_index].num_clock_modes = 1;
2003
2007
rdev->pm.power_state[state_index].clock_info[0].mclk =
2004
2008
le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
···
2039
2035
state_index++;
2040
2036
break;
2041
2037
case 2:
2038
+
rdev->pm.power_state[state_index].clock_info =
2039
+
kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2040
+
if (!rdev->pm.power_state[state_index].clock_info)
2041
+
return state_index;
2042
2042
rdev->pm.power_state[state_index].num_clock_modes = 1;
2043
2043
rdev->pm.power_state[state_index].clock_info[0].mclk =
2044
2044
le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
···
2080
2072
state_index++;
2081
2073
break;
2082
2074
case 3:
2075
+
rdev->pm.power_state[state_index].clock_info =
2076
+
kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2077
+
if (!rdev->pm.power_state[state_index].clock_info)
2078
+
return state_index;
2083
2079
rdev->pm.power_state[state_index].num_clock_modes = 1;
2084
2080
rdev->pm.power_state[state_index].clock_info[0].mclk =
2085
2081
le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
···
2269
2257
rdev->pm.default_power_state_index = state_index;
2270
2258
rdev->pm.power_state[state_index].default_clock_mode =
2271
2259
&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2272
-
if (ASIC_IS_DCE5(rdev)) {
2260
+
if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2273
2261
/* NI chips post without MC ucode, so default clocks are strobe mode only */
2274
2262
rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2275
2263
rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
···
2389
2377
le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2390
2378
(power_state->v1.ucNonClockStateIndex *
2391
2379
power_info->pplib.ucNonClockSize));
2392
-
for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2393
-
clock_info = (union pplib_clock_info *)
2394
-
(mode_info->atom_context->bios + data_offset +
2395
-
le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2396
-
(power_state->v1.ucClockStateIndices[j] *
2397
-
power_info->pplib.ucClockInfoSize));
2398
-
valid = radeon_atombios_parse_pplib_clock_info(rdev,
2399
-
state_index, mode_index,
2400
-
clock_info);
2401
-
if (valid)
2402
-
mode_index++;
2380
+
rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2381
+
((power_info->pplib.ucStateEntrySize - 1) ?
2382
+
(power_info->pplib.ucStateEntrySize - 1) : 1),
2383
+
GFP_KERNEL);
2384
+
if (!rdev->pm.power_state[i].clock_info)
2385
+
return state_index;
2386
+
if (power_info->pplib.ucStateEntrySize - 1) {
2387
+
for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2388
+
clock_info = (union pplib_clock_info *)
2389
+
(mode_info->atom_context->bios + data_offset +
2390
+
le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2391
+
(power_state->v1.ucClockStateIndices[j] *
2392
+
power_info->pplib.ucClockInfoSize));
2393
+
valid = radeon_atombios_parse_pplib_clock_info(rdev,
2394
+
state_index, mode_index,
2395
+
clock_info);
2396
+
if (valid)
2397
+
mode_index++;
2398
+
}
2399
+
} else {
2400
+
rdev->pm.power_state[state_index].clock_info[0].mclk =
2401
+
rdev->clock.default_mclk;
2402
+
rdev->pm.power_state[state_index].clock_info[0].sclk =
2403
+
rdev->clock.default_sclk;
2404
+
mode_index++;
2403
2405
}
2404
2406
rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2405
2407
if (mode_index) {
···
2482
2456
non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2483
2457
non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2484
2458
&non_clock_info_array->nonClockInfo[non_clock_array_index];
2485
-
for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2486
-
clock_array_index = power_state->v2.clockInfoIndex[j];
2487
-
/* XXX this might be an inagua bug... */
2488
-
if (clock_array_index >= clock_info_array->ucNumEntries)
2489
-
continue;
2490
-
clock_info = (union pplib_clock_info *)
2491
-
&clock_info_array->clockInfo[clock_array_index];
2492
-
valid = radeon_atombios_parse_pplib_clock_info(rdev,
2493
-
state_index, mode_index,
2494
-
clock_info);
2495
-
if (valid)
2496
-
mode_index++;
2459
+
rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2460
+
(power_state->v2.ucNumDPMLevels ?
2461
+
power_state->v2.ucNumDPMLevels : 1),
2462
+
GFP_KERNEL);
2463
+
if (!rdev->pm.power_state[i].clock_info)
2464
+
return state_index;
2465
+
if (power_state->v2.ucNumDPMLevels) {
2466
+
for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2467
+
clock_array_index = power_state->v2.clockInfoIndex[j];
2468
+
/* XXX this might be an inagua bug... */
2469
+
if (clock_array_index >= clock_info_array->ucNumEntries)
2470
+
continue;
2471
+
clock_info = (union pplib_clock_info *)
2472
+
&clock_info_array->clockInfo[clock_array_index];
2473
+
valid = radeon_atombios_parse_pplib_clock_info(rdev,
2474
+
state_index, mode_index,
2475
+
clock_info);
2476
+
if (valid)
2477
+
mode_index++;
2478
+
}
2479
+
} else {
2480
+
rdev->pm.power_state[state_index].clock_info[0].mclk =
2481
+
rdev->clock.default_mclk;
2482
+
rdev->pm.power_state[state_index].clock_info[0].sclk =
2483
+
rdev->clock.default_sclk;
2484
+
mode_index++;
2497
2485
}
2498
2486
rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2499
2487
if (mode_index) {
···
2564
2524
} else {
2565
2525
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2566
2526
if (rdev->pm.power_state) {
2567
-
/* add the default mode */
2568
-
rdev->pm.power_state[state_index].type =
2569
-
POWER_STATE_TYPE_DEFAULT;
2570
-
rdev->pm.power_state[state_index].num_clock_modes = 1;
2571
-
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2572
-
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2573
-
rdev->pm.power_state[state_index].default_clock_mode =
2574
-
&rdev->pm.power_state[state_index].clock_info[0];
2575
-
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2576
-
rdev->pm.power_state[state_index].pcie_lanes = 16;
2577
-
rdev->pm.default_power_state_index = state_index;
2578
-
rdev->pm.power_state[state_index].flags = 0;
2579
-
state_index++;
2527
+
rdev->pm.power_state[0].clock_info =
2528
+
kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2529
+
if (rdev->pm.power_state[0].clock_info) {
2530
+
/* add the default mode */
2531
+
rdev->pm.power_state[state_index].type =
2532
+
POWER_STATE_TYPE_DEFAULT;
2533
+
rdev->pm.power_state[state_index].num_clock_modes = 1;
2534
+
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2535
+
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2536
+
rdev->pm.power_state[state_index].default_clock_mode =
2537
+
&rdev->pm.power_state[state_index].clock_info[0];
2538
+
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2539
+
rdev->pm.power_state[state_index].pcie_lanes = 16;
2540
+
rdev->pm.default_power_state_index = state_index;
2541
+
rdev->pm.power_state[state_index].flags = 0;
2542
+
state_index++;
2543
+
}
2580
2544
}
2581
2545
}
2582
2546
+1
-1
drivers/gpu/drm/radeon/radeon_benchmark.c
+1
-1
drivers/gpu/drm/radeon/radeon_benchmark.c
+7
-7
drivers/gpu/drm/radeon/radeon_cs.c
+7
-7
drivers/gpu/drm/radeon/radeon_cs.c
···
222
222
struct radeon_cs_chunk *ib_chunk;
223
223
int r;
224
224
225
-
mutex_lock(&rdev->cs_mutex);
225
+
radeon_mutex_lock(&rdev->cs_mutex);
226
226
/* initialize parser */
227
227
memset(&parser, 0, sizeof(struct radeon_cs_parser));
228
228
parser.filp = filp;
···
233
233
if (r) {
234
234
DRM_ERROR("Failed to initialize parser !\n");
235
235
radeon_cs_parser_fini(&parser, r);
236
-
mutex_unlock(&rdev->cs_mutex);
236
+
radeon_mutex_unlock(&rdev->cs_mutex);
237
237
return r;
238
238
}
239
239
r = radeon_ib_get(rdev, &parser.ib);
240
240
if (r) {
241
241
DRM_ERROR("Failed to get ib !\n");
242
242
radeon_cs_parser_fini(&parser, r);
243
-
mutex_unlock(&rdev->cs_mutex);
243
+
radeon_mutex_unlock(&rdev->cs_mutex);
244
244
return r;
245
245
}
246
246
r = radeon_cs_parser_relocs(&parser);
···
248
248
if (r != -ERESTARTSYS)
249
249
DRM_ERROR("Failed to parse relocation %d!\n", r);
250
250
radeon_cs_parser_fini(&parser, r);
251
-
mutex_unlock(&rdev->cs_mutex);
251
+
radeon_mutex_unlock(&rdev->cs_mutex);
252
252
return r;
253
253
}
254
254
/* Copy the packet into the IB, the parser will read from the
···
260
260
if (r || parser.parser_error) {
261
261
DRM_ERROR("Invalid command stream !\n");
262
262
radeon_cs_parser_fini(&parser, r);
263
-
mutex_unlock(&rdev->cs_mutex);
263
+
radeon_mutex_unlock(&rdev->cs_mutex);
264
264
return r;
265
265
}
266
266
r = radeon_cs_finish_pages(&parser);
267
267
if (r) {
268
268
DRM_ERROR("Invalid command stream !\n");
269
269
radeon_cs_parser_fini(&parser, r);
270
-
mutex_unlock(&rdev->cs_mutex);
270
+
radeon_mutex_unlock(&rdev->cs_mutex);
271
271
return r;
272
272
}
273
273
r = radeon_ib_schedule(rdev, parser.ib);
···
275
275
DRM_ERROR("Failed to schedule IB !\n");
276
276
}
277
277
radeon_cs_parser_fini(&parser, r);
278
-
mutex_unlock(&rdev->cs_mutex);
278
+
radeon_mutex_unlock(&rdev->cs_mutex);
279
279
return r;
280
280
}
281
281
+12
-4
drivers/gpu/drm/radeon/radeon_device.c
+12
-4
drivers/gpu/drm/radeon/radeon_device.c
···
716
716
717
717
/* mutex initialization are all done here so we
718
718
* can recall function without having locking issues */
719
-
mutex_init(&rdev->cs_mutex);
719
+
radeon_mutex_init(&rdev->cs_mutex);
720
720
mutex_init(&rdev->ib_pool.mutex);
721
721
mutex_init(&rdev->cp.mutex);
722
722
mutex_init(&rdev->dc_hw_i2c_mutex);
···
955
955
int r;
956
956
int resched;
957
957
958
+
/* Prevent CS ioctl from interfering */
959
+
radeon_mutex_lock(&rdev->cs_mutex);
960
+
958
961
radeon_save_bios_scratch_regs(rdev);
959
962
/* block TTM */
960
963
resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
···
970
967
radeon_restore_bios_scratch_regs(rdev);
971
968
drm_helper_resume_force_mode(rdev->ddev);
972
969
ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
973
-
return 0;
974
970
}
975
-
/* bad news, how to tell it to userspace ? */
976
-
dev_info(rdev->dev, "GPU reset failed\n");
971
+
972
+
radeon_mutex_unlock(&rdev->cs_mutex);
973
+
974
+
if (r) {
975
+
/* bad news, how to tell it to userspace ? */
976
+
dev_info(rdev->dev, "GPU reset failed\n");
977
+
}
978
+
977
979
return r;
978
980
}
979
981
-6
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
-6
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
···
991
991
struct drm_display_mode *mode,
992
992
struct drm_display_mode *adjusted_mode)
993
993
{
994
-
struct drm_device *dev = crtc->dev;
995
-
struct radeon_device *rdev = dev->dev_private;
996
-
997
-
/* adjust pm to upcoming mode change */
998
-
radeon_pm_compute_clocks(rdev);
999
-
1000
994
if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1001
995
return false;
1002
996
return true;
+18
drivers/gpu/drm/radeon/radeon_pm.c
+18
drivers/gpu/drm/radeon/radeon_pm.c
···
53
53
54
54
#define ACPI_AC_CLASS "ac_adapter"
55
55
56
+
int radeon_pm_get_type_index(struct radeon_device *rdev,
57
+
enum radeon_pm_state_type ps_type,
58
+
int instance)
59
+
{
60
+
int i;
61
+
int found_instance = -1;
62
+
63
+
for (i = 0; i < rdev->pm.num_power_states; i++) {
64
+
if (rdev->pm.power_state[i].type == ps_type) {
65
+
found_instance++;
66
+
if (found_instance == instance)
67
+
return i;
68
+
}
69
+
}
70
+
/* return default if no match */
71
+
return rdev->pm.default_power_state_index;
72
+
}
73
+
56
74
#ifdef CONFIG_ACPI
57
75
static int radeon_acpi_event(struct notifier_block *nb,
58
76
unsigned long val,
+11
-3
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+11
-3
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
105
105
struct vmw_dma_buffer *dmabuf = NULL;
106
106
int ret;
107
107
108
+
/* A lot of the code assumes this */
109
+
if (handle && (width != 64 || height != 64))
110
+
return -EINVAL;
111
+
108
112
if (handle) {
109
113
ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110
114
handle, &surface);
···
414
410
top = clips->y1;
415
411
bottom = clips->y2;
416
412
417
-
clips_ptr = clips;
418
-
for (i = 1; i < num_clips; i++, clips_ptr += inc) {
413
+
/* skip the first clip rect */
414
+
for (i = 1, clips_ptr = clips + inc;
415
+
i < num_clips; i++, clips_ptr += inc) {
419
416
left = min_t(int, left, (int)clips_ptr->x1);
420
417
right = max_t(int, right, (int)clips_ptr->x2);
421
418
top = min_t(int, top, (int)clips_ptr->y1);
···
1328
1323
* drm_encoder_cleanup which takes the lock we deadlock.
1329
1324
*/
1330
1325
drm_mode_config_cleanup(dev_priv->dev);
1331
-
vmw_kms_close_legacy_display_system(dev_priv);
1326
+
if (dev_priv->sou_priv)
1327
+
vmw_kms_close_screen_object_display(dev_priv);
1328
+
else
1329
+
vmw_kms_close_legacy_display_system(dev_priv);
1332
1330
return 0;
1333
1331
}
1334
1332
+3
-1
include/drm/drmP.h
+3
-1
include/drm/drmP.h
···
990
990
struct proc_dir_entry *proc_root; /**< proc directory entry */
991
991
struct drm_info_node proc_nodes;
992
992
struct dentry *debugfs_root;
993
-
struct drm_info_node debugfs_nodes;
993
+
994
+
struct list_head debugfs_list;
995
+
struct mutex debugfs_lock; /* Protects debugfs_list. */
994
996
995
997
struct drm_master *master; /* currently active master for this node */
996
998
struct list_head master_list;
+2
include/drm/exynos_drm.h
+2
include/drm/exynos_drm.h
···
36
36
* - this size value would be page-aligned internally.
37
37
* @flags: user request for setting memory type or cache attributes.
38
38
* @handle: returned handle for the object.
39
+
* @pad: just padding to be 64-bit aligned.
39
40
*/
40
41
struct drm_exynos_gem_create {
41
42
unsigned int size;
42
43
unsigned int flags;
43
44
unsigned int handle;
45
+
unsigned int pad;
44
46
};
45
47
46
48
/**