tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Remove volatile from ring manipulation

None of the pointer operations handled by the ring file requires
volatile, for this reason, this commit removes all occurrences of
volatile associated with rings.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rodrigo Siqueira and committed by
Alex Deucher f307cfb9 b8fc5410

+10 -10
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 545 545 * this value can be accessed directly by using the offset as an index. 546 546 * For the GPU address, it is necessary to use gpu_addr and the offset. 547 547 */ 548 - volatile uint32_t *wb; 548 + uint32_t *wb; 549 549 550 550 /** 551 551 * @gpu_addr:
+6 -6
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
··· 114 114 */ 115 115 struct amdgpu_fence_driver { 116 116 uint64_t gpu_addr; 117 - volatile uint32_t *cpu_addr; 117 + uint32_t *cpu_addr; 118 118 /* sync_seq is protected by ring emission lock */ 119 119 uint32_t sync_seq; 120 120 atomic_t last_seq; ··· 298 298 unsigned int ring_backup_entries_to_copy; 299 299 unsigned rptr_offs; 300 300 u64 rptr_gpu_addr; 301 - volatile u32 *rptr_cpu_addr; 301 + u32 *rptr_cpu_addr; 302 302 303 303 /** 304 304 * @wptr: ··· 378 378 * This is the CPU address pointer in the writeback slot. This is used 379 379 * to commit changes to the GPU. 380 380 */ 381 - volatile u32 *wptr_cpu_addr; 381 + u32 *wptr_cpu_addr; 382 382 unsigned fence_offs; 383 383 u64 fence_gpu_addr; 384 - volatile u32 *fence_cpu_addr; 384 + u32 *fence_cpu_addr; 385 385 uint64_t current_ctx; 386 386 char name[16]; 387 387 u32 trail_seq; 388 388 unsigned trail_fence_offs; 389 389 u64 trail_fence_gpu_addr; 390 - volatile u32 *trail_fence_cpu_addr; 390 + u32 *trail_fence_cpu_addr; 391 391 unsigned cond_exe_offs; 392 392 u64 cond_exe_gpu_addr; 393 - volatile u32 *cond_exe_cpu_addr; 393 + u32 *cond_exe_cpu_addr; 394 394 unsigned int set_q_mode_offs; 395 395 u32 *set_q_mode_ptr; 396 396 u64 set_q_mode_token;
+1 -1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 4075 4075 struct dma_fence *f = NULL; 4076 4076 unsigned int index; 4077 4077 uint64_t gpu_addr; 4078 - volatile uint32_t *cpu_ptr; 4078 + uint32_t *cpu_ptr; 4079 4079 long r; 4080 4080 4081 4081 memset(&ib, 0, sizeof(ib));
+1 -1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 603 603 struct dma_fence *f = NULL; 604 604 unsigned index; 605 605 uint64_t gpu_addr; 606 - volatile uint32_t *cpu_ptr; 606 + uint32_t *cpu_ptr; 607 607 long r; 608 608 609 609 /* MES KIQ fw hasn't indirect buffer support for now */
+1 -1
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 497 497 struct dma_fence *f = NULL; 498 498 unsigned index; 499 499 uint64_t gpu_addr; 500 - volatile uint32_t *cpu_ptr; 500 + uint32_t *cpu_ptr; 501 501 long r; 502 502 503 503 /* MES KIQ fw hasn't indirect buffer support for now */