tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2021-10-29' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Quiet but not too quiet, I blame Halloween.

The first set of amdgpu fixes missed last week, hence why this has a
few more of them, it's mostly display fixes for new GPUs and some
debugfs OOB stuff.

The i915 patches have one to remove a tracepoint possible issue before
it's a real problem, the others around cflush and display are cc'ed to
stable as well.

Otherwise it's just a few misc fixes.

Summary:

MAINTAINERS:
- Fix the path pattern

ttm:
- Fix fence leak in ttm_transfered_destroy.

core:
- Add GPD Win3 rotation quirk

i915:
- Remove unconditional clflushes
- Fix oops on boot due to sync state on disabled DP encoders
- Revert backend specific data added to tracepoints
- Remove useless and incorrect memory frequence calculation

panel:
- Add quirk for Aya Neo 2021

seltest:
- Reset property count for each drm damage selftest so full run will
work correctly.

amdgpu:
- Fix two potential out of bounds writes in debugfs
- Fix revision handling for Yellow Carp
- Display fixes for Yellow Carp
- Display fixes for DCN 3.1"

* tag 'drm-fixes-2021-10-29' of git://anongit.freedesktop.org/drm/drm: (21 commits)
MAINTAINERS: dri-devel is for all of drivers/gpu
drm/i915: Revert 'guc_id' from i915_request tracepoint
drm/amd/display: Fix deadlock when falling back to v2 from v3
drm/amd/display: Fallback to clocks which meet requested voltage on DCN31
drm/amdgpu: Fix even more out of bound writes from debugfs
drm: panel-orientation-quirks: Add quirk for GPD Win3
drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
drm/i915: Catch yet another unconditioal clflush
drm/i915: Convert unconditional clflush to drm_clflush_virt_range()
drm/i915/selftests: Properly reset mock object propers for each test
drm: panel-orientation-quirks: Add quirk for Aya Neo 2021
drm/ttm: fix memleak in ttm_transfered_destroy
drm/amdgpu: support B0&B1 external revision id for yellow carp
drm/amd/display: Moved dccg init to after bios golden init
drm/amd/display: Increase watermark latencies for DCN3.1
drm/amd/display: increase Z9 latency to workaround underflow in Z9
drm/amd/display: Require immediate flip support for DCN3.1 planes
drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
drm/amdgpu: fix out of bounds write
...

Linus Torvalds f31531e5 411a44c2

+72 -82
+1 -2
MAINTAINERS
··· 6160 6160 F: Documentation/devicetree/bindings/display/ 6161 6161 F: Documentation/devicetree/bindings/gpu/ 6162 6162 F: Documentation/gpu/ 6163 - F: drivers/gpu/drm/ 6164 - F: drivers/gpu/vga/ 6163 + F: drivers/gpu/ 6165 6164 F: include/drm/ 6166 6165 F: include/linux/vga* 6167 6166 F: include/uapi/drm/
+1 -1
drivers/gpu/drm/amd/amdgpu/nv.c
··· 1257 1257 AMD_PG_SUPPORT_VCN_DPG | 1258 1258 AMD_PG_SUPPORT_JPEG; 1259 1259 if (adev->pdev->device == 0x1681) 1260 - adev->external_rev_id = adev->rev_id + 0x19; 1260 + adev->external_rev_id = 0x20; 1261 1261 else 1262 1262 adev->external_rev_id = adev->rev_id + 0x01; 1263 1263 break;
+10 -10
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
··· 263 263 if (!wr_buf) 264 264 return -ENOSPC; 265 265 266 - if (parse_write_buffer_into_params(wr_buf, size, 266 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 267 267 (long *)param, buf, 268 268 max_param_num, 269 269 &param_nums)) { ··· 487 487 if (!wr_buf) 488 488 return -ENOSPC; 489 489 490 - if (parse_write_buffer_into_params(wr_buf, size, 490 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 491 491 (long *)param, buf, 492 492 max_param_num, 493 493 &param_nums)) { ··· 639 639 if (!wr_buf) 640 640 return -ENOSPC; 641 641 642 - if (parse_write_buffer_into_params(wr_buf, size, 642 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 643 643 (long *)param, buf, 644 644 max_param_num, 645 645 &param_nums)) { ··· 914 914 return -ENOSPC; 915 915 } 916 916 917 - if (parse_write_buffer_into_params(wr_buf, size, 917 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 918 918 &param, buf, 919 919 max_param_num, 920 920 &param_nums)) { ··· 1211 1211 return -ENOSPC; 1212 1212 } 1213 1213 1214 - if (parse_write_buffer_into_params(wr_buf, size, 1214 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1215 1215 (long *)param, buf, 1216 1216 max_param_num, 1217 1217 &param_nums)) { ··· 1396 1396 return -ENOSPC; 1397 1397 } 1398 1398 1399 - if (parse_write_buffer_into_params(wr_buf, size, 1399 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1400 1400 (long *)param, buf, 1401 1401 max_param_num, 1402 1402 &param_nums)) { ··· 1581 1581 return -ENOSPC; 1582 1582 } 1583 1583 1584 - if (parse_write_buffer_into_params(wr_buf, size, 1584 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1585 1585 (long *)param, buf, 1586 1586 max_param_num, 1587 1587 &param_nums)) { ··· 1766 1766 return -ENOSPC; 1767 1767 } 1768 1768 1769 - if (parse_write_buffer_into_params(wr_buf, size, 1769 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1770 1770 (long *)param, buf, 1771 1771 max_param_num, 1772 1772 &param_nums)) { ··· 1944 1944 return -ENOSPC; 1945 1945 } 1946 1946 1947 - if (parse_write_buffer_into_params(wr_buf, size, 1947 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1948 1948 (long *)param, buf, 1949 1949 max_param_num, 1950 1950 &param_nums)) { ··· 2382 2382 return -ENOSPC; 2383 2383 } 2384 2384 2385 - if (parse_write_buffer_into_params(wr_buf, size, 2385 + if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2386 2386 (long *)param, buf, 2387 2387 max_param_num, 2388 2388 &param_nums)) {
+18 -11
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
··· 366 366 .wm_inst = WM_A, 367 367 .wm_type = WM_TYPE_PSTATE_CHG, 368 368 .pstate_latency_us = 11.65333, 369 - .sr_exit_time_us = 5.32, 370 - .sr_enter_plus_exit_time_us = 6.38, 369 + .sr_exit_time_us = 11.5, 370 + .sr_enter_plus_exit_time_us = 14.5, 371 371 .valid = true, 372 372 }, 373 373 { 374 374 .wm_inst = WM_B, 375 375 .wm_type = WM_TYPE_PSTATE_CHG, 376 376 .pstate_latency_us = 11.65333, 377 - .sr_exit_time_us = 9.82, 378 - .sr_enter_plus_exit_time_us = 11.196, 377 + .sr_exit_time_us = 11.5, 378 + .sr_enter_plus_exit_time_us = 14.5, 379 379 .valid = true, 380 380 }, 381 381 { 382 382 .wm_inst = WM_C, 383 383 .wm_type = WM_TYPE_PSTATE_CHG, 384 384 .pstate_latency_us = 11.65333, 385 - .sr_exit_time_us = 9.89, 386 - .sr_enter_plus_exit_time_us = 11.24, 385 + .sr_exit_time_us = 11.5, 386 + .sr_enter_plus_exit_time_us = 14.5, 387 387 .valid = true, 388 388 }, 389 389 { 390 390 .wm_inst = WM_D, 391 391 .wm_type = WM_TYPE_PSTATE_CHG, 392 392 .pstate_latency_us = 11.65333, 393 - .sr_exit_time_us = 9.748, 394 - .sr_enter_plus_exit_time_us = 11.102, 393 + .sr_exit_time_us = 11.5, 394 + .sr_enter_plus_exit_time_us = 14.5, 395 395 .valid = true, 396 396 }, 397 397 } ··· 518 518 unsigned int voltage) 519 519 { 520 520 int i; 521 + int max_voltage = 0; 522 + int clock = 0; 521 523 522 524 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { 523 - if (clock_table->SocVoltage[i] == voltage) 525 + if (clock_table->SocVoltage[i] == voltage) { 524 526 return clocks[i]; 527 + } else if (clock_table->SocVoltage[i] >= max_voltage && 528 + clock_table->SocVoltage[i] < voltage) { 529 + max_voltage = clock_table->SocVoltage[i]; 530 + clock = clocks[i]; 531 + } 525 532 } 526 533 527 - ASSERT(0); 528 - return 0; 534 + ASSERT(clock); 535 + return clock; 529 536 } 530 537 531 538 void dcn31_clk_mgr_helper_populate_bw_params(
+3 -4
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
··· 76 76 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 77 77 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 78 78 79 - // Initialize the dccg 80 - if (res_pool->dccg->funcs->dccg_init) 81 - res_pool->dccg->funcs->dccg_init(res_pool->dccg); 82 - 83 79 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 84 80 85 81 REG_WRITE(REFCLK_CNTL, 0); ··· 102 106 hws->funcs.bios_golden_init(dc); 103 107 hws->funcs.disable_vga(dc->hwseq); 104 108 } 109 + // Initialize the dccg 110 + if (res_pool->dccg->funcs->dccg_init) 111 + res_pool->dccg->funcs->dccg_init(res_pool->dccg); 105 112 106 113 if (dc->debug.enable_mem_low_power.bits.dmcu) { 107 114 // Force ERAM to shutdown if DMCU is not enabled
+10 -3
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
··· 217 217 .num_states = 5, 218 218 .sr_exit_time_us = 9.0, 219 219 .sr_enter_plus_exit_time_us = 11.0, 220 - .sr_exit_z8_time_us = 402.0, 221 - .sr_enter_plus_exit_z8_time_us = 520.0, 220 + .sr_exit_z8_time_us = 442.0, 221 + .sr_enter_plus_exit_z8_time_us = 560.0, 222 222 .writeback_latency_us = 12.0, 223 223 .dram_channel_width_bytes = 4, 224 224 .round_trip_ping_latency_dcfclk_cycles = 106, ··· 928 928 .disable_dcc = DCC_ENABLE, 929 929 .vsr_support = true, 930 930 .performance_trace = false, 931 - .max_downscale_src_width = 3840,/*upto 4K*/ 931 + .max_downscale_src_width = 4096,/*upto true 4K*/ 932 932 .disable_pplib_wm_range = false, 933 933 .scl_reset_length10 = true, 934 934 .sanity_checks = false, ··· 1589 1589 continue; 1590 1590 pipe = &res_ctx->pipe_ctx[i]; 1591 1591 timing = &pipe->stream->timing; 1592 + 1593 + /* 1594 + * Immediate flip can be set dynamically after enabling the plane. 1595 + * We need to require support for immediate flip or underflow can be 1596 + * intermittently experienced depending on peak b/w requirements. 1597 + */ 1598 + pipes[pipe_cnt].pipe.src.immediate_flip = true; 1592 1599 1593 1600 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1594 1601 pipes[pipe_cnt].pipe.src.gpuvm = true;
+3 -3
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
··· 5398 5398 5399 5399 v->MaximumReadBandwidthWithPrefetch = 5400 5400 v->MaximumReadBandwidthWithPrefetch 5401 - + dml_max4( 5402 - v->VActivePixelBandwidth[i][j][k], 5403 - v->VActiveCursorBandwidth[i][j][k] 5401 + + dml_max3( 5402 + v->VActivePixelBandwidth[i][j][k] 5403 + + v->VActiveCursorBandwidth[i][j][k] 5404 5404 + v->NoOfDPP[i][j][k] 5405 5405 * (v->meta_row_bandwidth[i][j][k] 5406 5406 + v->dpte_row_bandwidth[i][j][k]),
+1 -1
drivers/gpu/drm/amd/display/include/dal_asic_id.h
··· 227 227 #define FAMILY_YELLOW_CARP 146 228 228 229 229 #define YELLOW_CARP_A0 0x01 230 - #define YELLOW_CARP_B0 0x1A 230 + #define YELLOW_CARP_B0 0x20 231 231 #define YELLOW_CARP_UNKNOWN 0xFF 232 232 233 233 #ifndef ASICREV_IS_YELLOW_CARP
+2 -4
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
··· 105 105 dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; 106 106 107 107 psp_dtm_invoke(psp, dtm_cmd->cmd_id); 108 + mutex_unlock(&psp->dtm_context.mutex); 108 109 109 110 if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { 110 111 status = remove_display_from_topology_v2(hdcp, index); ··· 115 114 display->state = MOD_HDCP_DISPLAY_ACTIVE; 116 115 HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index); 117 116 } 118 - 119 - mutex_unlock(&psp->dtm_context.mutex); 120 117 121 118 return status; 122 119 } ··· 204 205 dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational; 205 206 206 207 psp_dtm_invoke(psp, dtm_cmd->cmd_id); 208 + mutex_unlock(&psp->dtm_context.mutex); 207 209 208 210 if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { 209 211 status = add_display_to_topology_v2(hdcp, display); ··· 213 213 } else { 214 214 HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index); 215 215 } 216 - 217 - mutex_unlock(&psp->dtm_context.mutex); 218 216 219 217 return status; 220 218 }
+12
drivers/gpu/drm/drm_panel_orientation_quirks.c
··· 134 134 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "T103HAF"), 135 135 }, 136 136 .driver_data = (void *)&lcd800x1280_rightside_up, 137 + }, { /* AYA NEO 2021 */ 138 + .matches = { 139 + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AYADEVICE"), 140 + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "AYA NEO 2021"), 141 + }, 142 + .driver_data = (void *)&lcd800x1280_rightside_up, 137 143 }, { /* GPD MicroPC (generic strings, also match on bios date) */ 138 144 .matches = { 139 145 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"), ··· 191 185 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), 192 186 }, 193 187 .driver_data = (void *)&gpd_win2, 188 + }, { /* GPD Win 3 */ 189 + .matches = { 190 + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"), 191 + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "G1618-03") 192 + }, 193 + .driver_data = (void *)&lcd720x1280_rightside_up, 194 194 }, { /* I.T.Works TW891 */ 195 195 .matches = { 196 196 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "To be filled by O.E.M."),
+3
drivers/gpu/drm/i915/display/intel_dp.c
··· 1916 1916 { 1917 1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1918 1918 1919 + if (!crtc_state) 1920 + return; 1921 + 1919 1922 /* 1920 1923 * Don't clobber DPCD if it's been already read out during output 1921 1924 * setup (eDP) or detect.
+2 -2
drivers/gpu/drm/i915/gt/intel_timeline.c
··· 64 64 65 65 timeline->hwsp_map = vaddr; 66 66 timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES); 67 - clflush(vaddr + ofs); 67 + drm_clflush_virt_range(vaddr + ofs, TIMELINE_SEQNO_BYTES); 68 68 69 69 return 0; 70 70 } ··· 225 225 226 226 memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno)); 227 227 WRITE_ONCE(*hwsp_seqno, tl->seqno); 228 - clflush(hwsp_seqno); 228 + drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES); 229 229 } 230 230 231 231 void intel_timeline_enter(struct intel_timeline *tl)
-8
drivers/gpu/drm/i915/i915_reg.h
··· 11048 11048 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 11049 11049 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 11050 11050 11051 - #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) 11052 - #define BXT_REQ_DATA_MASK 0x3F 11053 - #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12 11054 - #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12) 11055 - #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333 11056 - 11057 11051 #define BXT_D_CR_DRP0_DUNIT8 0x1000 11058 11052 #define BXT_D_CR_DRP0_DUNIT9 0x1200 11059 11053 #define BXT_D_CR_DRP0_DUNIT_START 8 ··· 11078 11084 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) 11079 11085 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22) 11080 11086 11081 - #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666 11082 11087 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) 11083 - #define SKL_REQ_DATA_MASK (0xF << 0) 11084 11088 #define DG1_GEAR_TYPE REG_BIT(16) 11085 11089 11086 11090 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
+2 -5
drivers/gpu/drm/i915/i915_trace.h
··· 794 794 TP_STRUCT__entry( 795 795 __field(u32, dev) 796 796 __field(u64, ctx) 797 - __field(u32, guc_id) 798 797 __field(u16, class) 799 798 __field(u16, instance) 800 799 __field(u32, seqno) ··· 804 805 __entry->dev = rq->engine->i915->drm.primary->index; 805 806 __entry->class = rq->engine->uabi_class; 806 807 __entry->instance = rq->engine->uabi_instance; 807 - __entry->guc_id = rq->context->guc_id; 808 808 __entry->ctx = rq->fence.context; 809 809 __entry->seqno = rq->fence.seqno; 810 810 __entry->tail = rq->tail; 811 811 ), 812 812 813 - TP_printk("dev=%u, engine=%u:%u, guc_id=%u, ctx=%llu, seqno=%u, tail=%u", 813 + TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u, tail=%u", 814 814 __entry->dev, __entry->class, __entry->instance, 815 - __entry->guc_id, __entry->ctx, __entry->seqno, 816 - __entry->tail) 815 + __entry->ctx, __entry->seqno, __entry->tail) 817 816 ); 818 817 819 818 DEFINE_EVENT(i915_request, i915_request_add,
+2 -28
drivers/gpu/drm/i915/intel_dram.c
··· 244 244 skl_get_dram_info(struct drm_i915_private *i915) 245 245 { 246 246 struct dram_info *dram_info = &i915->dram_info; 247 - u32 mem_freq_khz, val; 248 247 int ret; 249 248 250 249 dram_info->type = skl_get_dram_type(i915); ··· 253 254 ret = skl_dram_get_channels_info(i915); 254 255 if (ret) 255 256 return ret; 256 - 257 - val = intel_uncore_read(&i915->uncore, 258 - SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); 259 - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) * 260 - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000); 261 - 262 - if (dram_info->num_channels * mem_freq_khz == 0) { 263 - drm_info(&i915->drm, 264 - "Couldn't get system memory bandwidth\n"); 265 - return -EINVAL; 266 - } 267 257 268 258 return 0; 269 259 } ··· 338 350 static int bxt_get_dram_info(struct drm_i915_private *i915) 339 351 { 340 352 struct dram_info *dram_info = &i915->dram_info; 341 - u32 dram_channels; 342 - u32 mem_freq_khz, val; 343 - u8 num_active_channels, valid_ranks = 0; 353 + u32 val; 354 + u8 valid_ranks = 0; 344 355 int i; 345 - 346 - val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0); 347 - mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) * 348 - BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000); 349 - 350 - dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK; 351 - num_active_channels = hweight32(dram_channels); 352 - 353 - if (mem_freq_khz * num_active_channels == 0) { 354 - drm_info(&i915->drm, 355 - "Couldn't get system memory bandwidth\n"); 356 - return -EINVAL; 357 - } 358 356 359 357 /* 360 358 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
+1
drivers/gpu/drm/selftests/test-drm_damage_helper.c
··· 30 30 mock_device.driver = &mock_driver; 31 31 mock_device.mode_config.prop_fb_damage_clips = &mock_prop; 32 32 mock_plane.dev = &mock_device; 33 + mock_obj_props.count = 0; 33 34 mock_plane.base.properties = &mock_obj_props; 34 35 mock_prop.base.id = 1; /* 0 is an invalid id */ 35 36 mock_prop.dev = &mock_device;
+1
drivers/gpu/drm/ttm/ttm_bo_util.c
··· 190 190 struct ttm_transfer_obj *fbo; 191 191 192 192 fbo = container_of(bo, struct ttm_transfer_obj, base); 193 + dma_resv_fini(&fbo->base.base._resv); 193 194 ttm_bo_put(fbo->bo); 194 195 kfree(fbo); 195 196 }