Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v4.8-rc6' of git://git.linaro.org/people/ulf.hansson/mmc
Pull MMC fixes from Ulf Hansson:
"MMC host:
- omap/omap_hsmmc: Initialize dma_slave_config to avoid random data
- sdhci-st: Handle interconnect clock"
* tag 'mmc-v4.8-rc6' of git://git.linaro.org/people/ulf.hansson/mmc:
mmc: omap: Initialize dma_slave_config to avoid random data in it's fields
mmc: omap_hsmmc: Initialize dma_slave_config to avoid random data
mmc: sdhci-st: Handle interconnect clock
dt-bindings: mmc: sdhci-st: Mention the discretionary "icn" clock
+33
-18
+1
-1
Documentation/devicetree/bindings/mmc/sdhci-st.txt
+1
-1
Documentation/devicetree/bindings/mmc/sdhci-st.txt
···
10
10
subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
11
11
family).
12
12
13
-
- clock-names: Should be "mmc".
13
+
- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14
14
See: Documentation/devicetree/bindings/resource-names.txt
15
15
- clocks: Phandle to the clock.
16
16
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+10
-8
drivers/mmc/host/omap.c
+10
-8
drivers/mmc/host/omap.c
···
1016
1016
1017
1017
/* Only reconfigure if we have a different burst size */
1018
1018
if (*bp != burst) {
1019
-
struct dma_slave_config cfg;
1020
-
1021
-
cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1022
-
cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023
-
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1024
-
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025
-
cfg.src_maxburst = burst;
1026
-
cfg.dst_maxburst = burst;
1019
+
struct dma_slave_config cfg = {
1020
+
.src_addr = host->phys_base +
1021
+
OMAP_MMC_REG(host, DATA),
1022
+
.dst_addr = host->phys_base +
1023
+
OMAP_MMC_REG(host, DATA),
1024
+
.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1025
+
.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1026
+
.src_maxburst = burst,
1027
+
.dst_maxburst = burst,
1028
+
};
1027
1029
1028
1030
if (dmaengine_slave_config(c, &cfg))
1029
1031
goto use_pio;
+8
-8
drivers/mmc/host/omap_hsmmc.c
+8
-8
drivers/mmc/host/omap_hsmmc.c
···
1409
1409
static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1410
1410
struct mmc_request *req)
1411
1411
{
1412
-
struct dma_slave_config cfg;
1413
1412
struct dma_async_tx_descriptor *tx;
1414
1413
int ret = 0, i;
1415
1414
struct mmc_data *data = req->data;
1416
1415
struct dma_chan *chan;
1416
+
struct dma_slave_config cfg = {
1417
+
.src_addr = host->mapbase + OMAP_HSMMC_DATA,
1418
+
.dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1419
+
.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1420
+
.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1421
+
.src_maxburst = data->blksz / 4,
1422
+
.dst_maxburst = data->blksz / 4,
1423
+
};
1417
1424
1418
1425
/* Sanity check: all the SG entries must be aligned by block size. */
1419
1426
for (i = 0; i < data->sg_len; i++) {
···
1439
1432
BUG_ON(host->dma_ch != -1);
1440
1433
1441
1434
chan = omap_hsmmc_get_dma_chan(host, data);
1442
-
1443
-
cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1444
-
cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1445
-
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1446
-
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1447
-
cfg.src_maxburst = data->blksz / 4;
1448
-
cfg.dst_maxburst = data->blksz / 4;
1449
1435
1450
1436
ret = dmaengine_slave_config(chan, &cfg);
1451
1437
if (ret)
+14
-1
drivers/mmc/host/sdhci-st.c
+14
-1
drivers/mmc/host/sdhci-st.c
···
28
28
29
29
struct st_mmc_platform_data {
30
30
struct reset_control *rstc;
31
+
struct clk *icnclk;
31
32
void __iomem *top_ioaddr;
32
33
};
33
34
···
354
353
struct sdhci_host *host;
355
354
struct st_mmc_platform_data *pdata;
356
355
struct sdhci_pltfm_host *pltfm_host;
357
-
struct clk *clk;
356
+
struct clk *clk, *icnclk;
358
357
int ret = 0;
359
358
u16 host_version;
360
359
struct resource *res;
···
365
364
dev_err(&pdev->dev, "Peripheral clk not found\n");
366
365
return PTR_ERR(clk);
367
366
}
367
+
368
+
/* ICN clock isn't compulsory, but use it if it's provided. */
369
+
icnclk = devm_clk_get(&pdev->dev, "icn");
370
+
if (IS_ERR(icnclk))
371
+
icnclk = NULL;
368
372
369
373
rstc = devm_reset_control_get(&pdev->dev, NULL);
370
374
if (IS_ERR(rstc))
···
395
389
}
396
390
397
391
clk_prepare_enable(clk);
392
+
clk_prepare_enable(icnclk);
398
393
399
394
/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
400
395
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
···
407
400
}
408
401
409
402
pltfm_host->clk = clk;
403
+
pdata->icnclk = icnclk;
410
404
411
405
/* Configure the Arasan HC inside the flashSS */
412
406
st_mmcss_cconfig(np, host);
···
430
422
return 0;
431
423
432
424
err_out:
425
+
clk_disable_unprepare(icnclk);
433
426
clk_disable_unprepare(clk);
434
427
err_of:
435
428
sdhci_pltfm_free(pdev);
···
450
441
int ret;
451
442
452
443
ret = sdhci_pltfm_unregister(pdev);
444
+
445
+
clk_disable_unprepare(pdata->icnclk);
453
446
454
447
if (rstc)
455
448
reset_control_assert(rstc);
···
473
462
if (pdata->rstc)
474
463
reset_control_assert(pdata->rstc);
475
464
465
+
clk_disable_unprepare(pdata->icnclk);
476
466
clk_disable_unprepare(pltfm_host->clk);
477
467
out:
478
468
return ret;
···
487
475
struct device_node *np = dev->of_node;
488
476
489
477
clk_prepare_enable(pltfm_host->clk);
478
+
clk_prepare_enable(pdata->icnclk);
490
479
491
480
if (pdata->rstc)
492
481
reset_control_deassert(pdata->rstc);