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drm/i915/cx0: Read out power-down state of both PHY lanes for reversed lanes

For a port used with lane reversal enabled the first two TX lanes will
be enabled in PHY lane#1 instead of PHY lane#0. At the moment the HW
readout will read out the power-down state for these two TX lanes from
PHY lane#0 incorrectly. The display HW lane reversal feature (vs. the
similar TCSS lane swap) is only used for TypeC legacy mode and for
non-TypeC PHYs. Since in both of these cases the display owns both PHY
lanes, both of these PHY lanes' state can be read out. Do that to fix
cases when lane reversal is used with 1 or 2 active TX lanes.

While at it add an assert to the PLL enable function about the above
assumption on when lane reversal can be used.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Fixes: 230d4c748113 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state")
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-5-imre.deak@intel.com

Imre Deak f32df9e9 dc5b3ef8

+22 -2
+22 -2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 2197 2197 { 2198 2198 struct intel_display *display = to_intel_display(encoder); 2199 2199 u8 enabled_tx_lane_count = 0; 2200 - int max_tx_lane_count; 2200 + int max_tx_lane_count = 4; 2201 + bool lane_reversal; 2201 2202 int tx_lane; 2203 + 2204 + lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) & 2205 + XELPDP_PORT_REVERSAL; 2202 2206 2203 2207 /* 2204 2208 * TODO: also check inactive TX lanes in all PHY lanes owned by the ··· 2210 2206 * based on the active TX lane count (i.e. 2211 2207 * 1,2 active TX lanes -> PHY lane#0 2212 2208 * 3,4 active TX lanes -> PHY lane#0 and PHY lane#1). 2209 + * 2210 + * In case of lane reversal for 1, 2 active TX lanes, only PHY 2211 + * lane#1 is used. This is only possible in TypeC legacy mode or if 2212 + * the port is connected to a non-TC PHY. In both of these cases both 2213 + * PHY lane#0 and #1 are owned by display, so check all 4 TX lanes in 2214 + * both PHY lanes in those cases. 2213 2215 */ 2214 - max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, DDI_BUF_CTL(encoder->port))); 2216 + if (!lane_reversal) 2217 + max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, 2218 + DDI_BUF_CTL(encoder->port))); 2219 + 2215 2220 if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0)) 2216 2221 max_tx_lane_count = round_up(max_tx_lane_count, 2); 2217 2222 ··· 3226 3213 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : 3227 3214 INTEL_CX0_LANE0; 3228 3215 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 3216 + 3217 + /* 3218 + * Lane reversal is never used in DP-alt mode, in that case the 3219 + * corresponding lane swapping (based on the TypeC cable flip state 3220 + * for instance) is handled automatically by the HW via a TCSS mux. 3221 + */ 3222 + drm_WARN_ON(display->drm, lane_reversal && intel_tc_port_in_dp_alt_mode(dig_port)); 3229 3223 3230 3224 /* 3231 3225 * 1. Program PORT_CLOCK_CTL REGISTER to configure