dt-bindings: i3c: Add adi-i3c-master

Add bindings doc for ADI I3C Controller IP core, a FPGA synthesizable IP
core that implements the MIPI I3C Basic controller specification.
The IP Core is versioned following Semantic Versioning 2.0.0 and
ADI's open-source HDL guidelines for devicetree bindings and drivers.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Link: https://lore.kernel.org/r/20250827-adi-i3c-master-v9-1-04413925abe1@analog.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

authored by

Jorge Marques and committed by

Alexandre Belloni 9 months ago f3317e8c 9395b3c4

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Documentation

devicetree

bindings

i3c

adi,i3c-master.yaml

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+72

Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Analog Devices I3C Controller 8 + 9 + description: 10 + FPGA-based I3C controller designed to interface with I3C and I2C peripherals, 11 + implementing a subset of the I3C-basic specification. The IP core is tested 12 + on arm, microblaze, and arm64 architectures. 13 + 14 + https://analogdevicesinc.github.io/hdl/library/i3c_controller 15 + 16 + maintainers: 17 + - Jorge Marques <jorge.marques@analog.com> 18 + 19 + properties: 20 + compatible: 21 + const: adi,i3c-master-v1 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + clocks: 27 + minItems: 1 28 + items: 29 + - description: The AXI interconnect clock, drives the register map. 30 + - description: 31 + The secondary clock, drives the internal logic asynchronously to the 32 + register map. The presence of this entry states that the IP Core was 33 + synthesized with a second clock input, and the absence of this entry 34 + indicates a topology where a single clock input drives all the 35 + internal logic. 36 + 37 + clock-names: 38 + minItems: 1 39 + items: 40 + - const: axi 41 + - const: i3c 42 + 43 + interrupts: 44 + maxItems: 1 45 + 46 + required: 47 + - compatible 48 + - reg 49 + - clocks 50 + - clock-names 51 + - interrupts 52 + 53 + allOf: 54 + - $ref: i3c.yaml# 55 + 56 + unevaluatedProperties: false 57 + 58 + examples: 59 + - | 60 + #include <dt-bindings/interrupt-controller/irq.h> 61 + 62 + i3c@44a00000 { 63 + compatible = "adi,i3c-master-v1"; 64 + reg = <0x44a00000 0x1000>; 65 + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 66 + clocks = <&clkc 15>, <&clkc 15>; 67 + clock-names = "axi", "i3c"; 68 + #address-cells = <3>; 69 + #size-cells = <0>; 70 + 71 + /* I3C and I2C devices */ 72 + };

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··· 11606 11606 F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml 11607 11607 F: drivers/i3c/master/ast2600-i3c-master.c 11608 11608 11609 + I3C DRIVER FOR ANALOG DEVICES I3C CONTROLLER IP 11610 + M: Jorge Marques <jorge.marques@analog.com> 11611 + S: Maintained 11612 + F: Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml 11613 + 11609 11614 I3C DRIVER FOR CADENCE I3C MASTER IP 11610 11615 M: Przemysław Gaj <pgaj@cadence.com> 11611 11616 S: Maintained

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