Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/swsmu: Move IP specific functions
Move SMU v15_0_0 specific functions to IP file
- smu_v15_0_0_set_default_dpm_tables and
- smu_v15_0_0_update_table
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Pratik Vishwakarma
and committed by
Alex Deucher
f38bb9b0
b18fc0ab
+67
-74
-7
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
-7
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
···
226
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int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu);
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-
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu);
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-
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int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu,
232
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void **table,
233
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uint32_t *size,
···
238
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int smu_v15_0_enable_thermal_alert(struct smu_context *smu);
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int smu_v15_0_disable_thermal_alert(struct smu_context *smu);
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-
242
-
int smu_v15_0_0_update_table(struct smu_context *smu,
243
-
enum smu_table_id table_index,
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-
int argument, void *table_data,
245
-
bool drv2smu);
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#endif
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#endif
-66
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
-66
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
···
1726
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return ret;
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}
1728
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1729
-
int smu_v15_0_0_update_table(struct smu_context *smu,
1730
-
enum smu_table_id table_index,
1731
-
int argument,
1732
-
void *table_data,
1733
-
bool drv2smu)
1734
-
{
1735
-
struct smu_table_context *smu_table = &smu->smu_table;
1736
-
struct amdgpu_device *adev = smu->adev;
1737
-
struct smu_table *table = &smu_table->driver_table;
1738
-
int table_id = smu_cmn_to_asic_specific_index(smu,
1739
-
CMN2ASIC_MAPPING_TABLE,
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-
table_index);
1741
-
uint64_t address;
1742
-
uint32_t table_size;
1743
-
int ret;
1744
-
struct smu_msg_ctl *ctl = &smu->msg_ctl;
1745
-
1746
-
if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
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-
return -EINVAL;
1748
-
1749
-
table_size = smu_table->tables[table_index].size;
1750
-
1751
-
if (drv2smu) {
1752
-
memcpy(table->cpu_addr, table_data, table_size);
1753
-
/*
1754
-
* Flush hdp cache: to guard the content seen by
1755
-
* GPU is consitent with CPU.
1756
-
*/
1757
-
amdgpu_hdp_flush(adev, NULL);
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-
}
1759
-
1760
-
address = table->mc_address;
1761
-
1762
-
struct smu_msg_args args = {
1763
-
.msg = drv2smu ?
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-
SMU_MSG_TransferTableDram2Smu :
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-
SMU_MSG_TransferTableSmu2Dram,
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-
.num_args = 3,
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-
.num_out_args = 0,
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-
};
1769
-
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-
args.args[0] = table_id;
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-
args.args[1] = (uint32_t)lower_32_bits(address);
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-
args.args[2] = (uint32_t)upper_32_bits(address);
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-
1774
-
ret = ctl->ops->send_msg(ctl, &args);
1775
-
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-
if (ret)
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-
return ret;
1778
-
1779
-
if (!drv2smu) {
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-
amdgpu_hdp_invalidate(adev, NULL);
1781
-
memcpy(table_data, table->cpu_addr, table_size);
1782
-
}
1783
-
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-
return 0;
1785
-
}
1786
-
1787
-
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu)
1788
-
{
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-
struct smu_table_context *smu_table = &smu->smu_table;
1790
-
1791
-
return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
1792
-
smu_table->clocks_table, false);
1793
-
}
1794
-
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int smu_v15_0_od_edit_dpm_table(struct smu_context *smu,
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1730
enum PP_OD_DPM_TABLE_COMMAND type,
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1731
long input[], uint32_t size)
+67
-1
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
+67
-1
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
···
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return ret;
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}
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+
static int smu_v15_0_0_update_table(struct smu_context *smu,
237
+
enum smu_table_id table_index,
238
+
int argument,
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+
void *table_data,
240
+
bool drv2smu)
241
+
{
242
+
struct smu_table_context *smu_table = &smu->smu_table;
243
+
struct amdgpu_device *adev = smu->adev;
244
+
struct smu_table *table = &smu_table->driver_table;
245
+
int table_id = smu_cmn_to_asic_specific_index(smu,
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+
CMN2ASIC_MAPPING_TABLE,
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+
table_index);
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+
uint64_t address;
249
+
uint32_t table_size;
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+
int ret;
251
+
struct smu_msg_ctl *ctl = &smu->msg_ctl;
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+
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+
if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
254
+
return -EINVAL;
255
+
256
+
table_size = smu_table->tables[table_index].size;
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+
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+
if (drv2smu) {
259
+
memcpy(table->cpu_addr, table_data, table_size);
260
+
/*
261
+
* Flush hdp cache: to guard the content seen by
262
+
* GPU is consitent with CPU.
263
+
*/
264
+
amdgpu_hdp_flush(adev, NULL);
265
+
}
266
+
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+
address = table->mc_address;
268
+
269
+
struct smu_msg_args args = {
270
+
.msg = drv2smu ?
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+
SMU_MSG_TransferTableDram2Smu :
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+
SMU_MSG_TransferTableSmu2Dram,
273
+
.num_args = 3,
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+
.num_out_args = 0,
275
+
};
276
+
277
+
args.args[0] = table_id;
278
+
args.args[1] = (uint32_t)lower_32_bits(address);
279
+
args.args[2] = (uint32_t)upper_32_bits(address);
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+
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+
ret = ctl->ops->send_msg(ctl, &args);
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+
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+
if (ret)
284
+
return ret;
285
+
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+
if (!drv2smu) {
287
+
amdgpu_hdp_invalidate(adev, NULL);
288
+
memcpy(table_data, table->cpu_addr, table_size);
289
+
}
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+
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+
return 0;
292
+
}
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+
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+
static int smu_v15_0_0_set_default_dpm_tables(struct smu_context *smu)
295
+
{
296
+
struct smu_table_context *smu_table = &smu->smu_table;
297
+
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+
return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
299
+
smu_table->clocks_table, false);
300
+
}
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+
236
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static int smu_v15_0_0_get_metrics_table(struct smu_context *smu,
237
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void *metrics_table,
238
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bool bypass_cache)
···
1423
1357
.system_features_control = smu_v15_0_0_system_features_control,
1424
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.dpm_set_vcn_enable = smu_v15_0_set_vcn_enable,
1425
1359
.dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable,
1426
-
.set_default_dpm_table = smu_v15_0_set_default_dpm_tables,
1360
+
.set_default_dpm_table = smu_v15_0_0_set_default_dpm_tables,
1427
1361
.read_sensor = smu_v15_0_0_read_sensor,
1428
1362
.is_dpm_running = smu_v15_0_0_is_dpm_running,
1429
1363
.set_watermarks_table = smu_v15_0_0_set_watermarks_table,