Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rproc-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull remoteproc updates from Bjorn Andersson:
- Support for PRU clients to acquire a control reference to the PRU
instances is introduced, and the PRU now allows specifying
firmware-name in Devicetree. sysfs is requested to be read-only when
the remoteproc instance is consumed by another kernel driver
- Support for the C7xv DSP on AM62A SoC is introduced
- The Devicetree binding for the Qualcomm PAS devices are split up in
multiple files, to better account for the differences in resources
between them. A number of missing Devicetree bindings are added, and
the Qualcomm WCNSS binding is converted to YAML
- A few cleanups are introduced for the Mediatek SCP driver. And a
sanity check of the firmware image is introduced in the Mediatek
driver
- For Qualcomm SC7280 ADSP support is added, MSM8953 gains ADSP and
modem support, SM6115 and SM8550 gains ADSP, CDSP and modem support,
and support for pronto v3 support (used on e.g. MSM8953) is added
- The Qualcomm modem remoteproc driver is modified to use a no-map
reserved-memory region for it's authentication metadata, in order to
avoid fatal security violations caused by accesses from Linux during
the authentication process
- Support for separate loading of a Devicetree blob is added to the PAS
driver, and support for the PAS driver to carve out DSM memory for
the modem is added as well
- The Qualcomm ADSP remoteproc driver gains support for mapping memory
into specific range using the IOMMU. The sysmon driver is
transitioned to strlcpy()
* tag 'rproc-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (69 commits)
dt-bindings: mailbox: qcom,apcs-kpss-global: drop mbox-names from example
dt-bindings: remoteproc: qcom,glink-edge: correct label description
dt-bindings: remoteproc: qcom,glink-rpm-edge: convert to DT schema
dt-bindings: remoteproc: qcom,sm8550-pas: correct power domains
remoteproc: qcom_q6v5_pas: enable sm8550 adsp & cdsp autoboot
dt-bindings: remoteproc: qcom: Add sm6115 pas yaml file
remoteproc: qcom: pas: Add sm6115 remoteprocs
remoteproc: qcom: pas: Adjust the phys addr wrt the mem region
remoteproc: qcom: fix sparse warnings
remoteproc: qcom: replace kstrdup with kstrndup
remoteproc: mediatek: Check the SCP image format
remoteproc: qcom_q6v5_mss: Use a carveout to authenticate modem headers
Revert "remoteproc: qcom_q6v5_mss: map/unmap metadata region before/after use"
dt-bindings: remoteproc: qcom,sc7280-mss-pil: Update memory-region
dt-bindings: remoteproc: qcom,sc7180-mss-pil: Update memory-region
dt-bindings: remoteproc: qcom,msm8996-mss-pil: Update memory region
dt-bindings: remoteproc: qcom,q6v5: Move MSM8996 to schema
remoteproc: qcom_q6v5_pas: add sm8550 adsp, cdsp & mpss compatible & data
remoteproc: qcom_q6v5_pas: add support for assigning memory to firmware
remoteproc: qcom_q6v5_pas: add support for dtb co-firmware loading
...
+3737
-911
-1
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
-1
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+11
-410
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+11
-410
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
···
17
17
compatible:
18
18
enum:
19
19
- qcom,msm8226-adsp-pil
20
+
- qcom,msm8953-adsp-pil
20
21
- qcom,msm8974-adsp-pil
21
22
- qcom,msm8996-adsp-pil
22
23
- qcom,msm8996-slpi-pil
23
24
- qcom,msm8998-adsp-pas
24
25
- qcom,msm8998-slpi-pas
25
-
- qcom,qcs404-adsp-pas
26
-
- qcom,qcs404-cdsp-pas
27
-
- qcom,qcs404-wcss-pas
28
-
- qcom,sc7180-mpss-pas
29
-
- qcom,sc7280-mpss-pas
30
-
- qcom,sc8180x-adsp-pas
31
-
- qcom,sc8180x-cdsp-pas
32
-
- qcom,sc8180x-mpss-pas
33
-
- qcom,sc8280xp-adsp-pas
34
-
- qcom,sc8280xp-nsp0-pas
35
-
- qcom,sc8280xp-nsp1-pas
36
26
- qcom,sdm660-adsp-pas
37
27
- qcom,sdm845-adsp-pas
38
28
- qcom,sdm845-cdsp-pas
39
-
- qcom,sdx55-mpss-pas
40
-
- qcom,sm6350-adsp-pas
41
-
- qcom,sm6350-cdsp-pas
42
-
- qcom,sm6350-mpss-pas
43
-
- qcom,sm8150-adsp-pas
44
-
- qcom,sm8150-cdsp-pas
45
-
- qcom,sm8150-mpss-pas
46
-
- qcom,sm8150-slpi-pas
47
-
- qcom,sm8250-adsp-pas
48
-
- qcom,sm8250-cdsp-pas
49
-
- qcom,sm8250-slpi-pas
50
-
- qcom,sm8350-adsp-pas
51
-
- qcom,sm8350-cdsp-pas
52
-
- qcom,sm8350-slpi-pas
53
-
- qcom,sm8350-mpss-pas
54
-
- qcom,sm8450-adsp-pas
55
-
- qcom,sm8450-cdsp-pas
56
-
- qcom,sm8450-mpss-pas
57
-
- qcom,sm8450-slpi-pas
58
29
59
30
reg:
60
31
maxItems: 1
61
-
62
-
clocks:
63
-
minItems: 1
64
-
maxItems: 8
65
-
66
-
clock-names:
67
-
minItems: 1
68
-
maxItems: 8
69
-
70
-
interconnects:
71
-
maxItems: 1
72
-
73
-
interrupts:
74
-
minItems: 5
75
-
items:
76
-
- description: Watchdog interrupt
77
-
- description: Fatal interrupt
78
-
- description: Ready interrupt
79
-
- description: Handover interrupt
80
-
- description: Stop acknowledge interrupt
81
-
- description: Shutdown acknowledge interrupt
82
-
83
-
interrupt-names:
84
-
minItems: 5
85
-
items:
86
-
- const: wdog
87
-
- const: fatal
88
-
- const: ready
89
-
- const: handover
90
-
- const: stop-ack
91
-
- const: shutdown-ack
92
-
93
-
resets:
94
-
minItems: 1
95
-
maxItems: 3
96
-
97
-
reset-names:
98
-
minItems: 1
99
-
maxItems: 3
100
32
101
33
cx-supply:
102
34
description: Phandle to the CX regulator
···
36
104
px-supply:
37
105
description: Phandle to the PX regulator
38
106
39
-
power-domains:
40
-
minItems: 1
41
-
maxItems: 3
42
-
43
-
power-domain-names:
44
-
minItems: 1
45
-
maxItems: 3
46
-
47
-
firmware-name:
48
-
$ref: /schemas/types.yaml#/definitions/string
49
-
description: Firmware name for the Hexagon core
107
+
qcom,qmp:
108
+
$ref: /schemas/types.yaml#/definitions/phandle
109
+
description: Reference to the AOSS side-channel message RAM.
50
110
51
111
memory-region:
52
112
maxItems: 1
53
113
description: Reference to the reserved-memory for the Hexagon core
54
114
55
-
qcom,qmp:
56
-
$ref: /schemas/types.yaml#/definitions/phandle
57
-
description: Reference to the AOSS side-channel message RAM.
58
-
59
-
qcom,smem-states:
60
-
$ref: /schemas/types.yaml#/definitions/phandle-array
61
-
description: States used by the AP to signal the Hexagon core
62
-
items:
63
-
- description: Stop the modem
64
-
65
-
qcom,smem-state-names:
66
-
description: The names of the state bits used for SMP2P output
67
-
items:
68
-
- const: stop
69
-
70
-
qcom,halt-regs:
71
-
$ref: /schemas/types.yaml#/definitions/phandle-array
72
-
items:
73
-
- items:
74
-
- description: Phandle reference to a syscon representing TCSR
75
-
- description: offsets within syscon for q6 halt registers
76
-
- description: offsets within syscon for modem halt registers
77
-
- description: offsets within syscon for nc halt registers
78
-
description:
79
-
Phandle reference to a syscon representing TCSR followed by the
80
-
three offsets within syscon for q6, modem and nc halt registers.
81
-
82
-
smd-edge:
83
-
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
84
-
description:
85
-
Qualcomm Shared Memory subnode which represents communication edge,
86
-
channels and devices related to the ADSP.
87
-
unevaluatedProperties: false
88
-
89
-
glink-edge:
90
-
$ref: /schemas/remoteproc/qcom,glink-edge.yaml#
91
-
description:
92
-
Qualcomm G-Link subnode which represents communication edge, channels
93
-
and devices related to the ADSP.
94
-
95
115
required:
96
116
- compatible
97
-
- clocks
98
-
- clock-names
99
-
- interrupts
100
-
- interrupt-names
101
-
- memory-region
102
-
- qcom,smem-states
103
-
- qcom,smem-state-names
104
117
105
-
additionalProperties: false
118
+
unevaluatedProperties: false
106
119
107
120
allOf:
121
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
108
122
- if:
109
123
properties:
110
124
compatible:
111
125
contains:
112
126
enum:
113
127
- qcom,msm8226-adsp-pil
128
+
- qcom,msm8953-adsp-pil
114
129
- qcom,msm8974-adsp-pil
115
130
- qcom,msm8996-adsp-pil
116
-
- qcom,msm8996-slpi-pil
117
131
- qcom,msm8998-adsp-pas
118
-
- qcom,qcs404-adsp-pas
119
-
- qcom,qcs404-wcss-pas
120
-
- qcom,sc7280-mpss-pas
121
-
- qcom,sc8180x-adsp-pas
122
-
- qcom,sc8180x-cdsp-pas
123
-
- qcom,sc8180x-mpss-pas
124
-
- qcom,sc8280xp-adsp-pas
125
-
- qcom,sc8280xp-nsp0-pas
126
-
- qcom,sc8280xp-nsp1-pas
127
132
- qcom,sdm845-adsp-pas
128
133
- qcom,sdm845-cdsp-pas
129
-
- qcom,sm6350-adsp-pas
130
-
- qcom,sm6350-cdsp-pas
131
-
- qcom,sm6350-mpss-pas
132
-
- qcom,sm8150-adsp-pas
133
-
- qcom,sm8150-cdsp-pas
134
-
- qcom,sm8150-mpss-pas
135
-
- qcom,sm8150-slpi-pas
136
-
- qcom,sm8250-adsp-pas
137
-
- qcom,sm8250-cdsp-pas
138
-
- qcom,sm8250-slpi-pas
139
-
- qcom,sm8350-adsp-pas
140
-
- qcom,sm8350-cdsp-pas
141
-
- qcom,sm8350-slpi-pas
142
-
- qcom,sm8350-mpss-pas
143
-
- qcom,sm8450-adsp-pas
144
-
- qcom,sm8450-cdsp-pas
145
-
- qcom,sm8450-slpi-pas
146
-
- qcom,sm8450-mpss-pas
147
134
then:
148
135
properties:
149
136
clocks:
···
77
226
compatible:
78
227
contains:
79
228
enum:
229
+
- qcom,msm8996-slpi-pil
80
230
- qcom,msm8998-slpi-pas
81
231
then:
82
232
properties:
···
95
243
compatible:
96
244
contains:
97
245
enum:
98
-
- qcom,qcs404-cdsp-pas
99
-
then:
100
-
properties:
101
-
clocks:
102
-
items:
103
-
- description: XO clock
104
-
- description: SWAY clock
105
-
- description: TBU clock
106
-
- description: BIMC clock
107
-
- description: AHB AON clock
108
-
- description: Q6SS SLAVE clock
109
-
- description: Q6SS MASTER clock
110
-
- description: Q6 AXIM clock
111
-
clock-names:
112
-
items:
113
-
- const: xo
114
-
- const: sway
115
-
- const: tbu
116
-
- const: bimc
117
-
- const: ahb_aon
118
-
- const: q6ss_slave
119
-
- const: q6ss_master
120
-
- const: q6_axim
121
-
122
-
- if:
123
-
properties:
124
-
compatible:
125
-
contains:
126
-
enum:
127
-
- qcom,sc7180-mpss-pas
128
-
then:
129
-
properties:
130
-
clocks:
131
-
items:
132
-
- description: XO clock
133
-
- description: IFACE clock
134
-
- description: BUS clock
135
-
- description: NAC clock
136
-
- description: SNOC AXI clock
137
-
- description: MNOC AXI clock
138
-
clock-names:
139
-
items:
140
-
- const: xo
141
-
- const: iface
142
-
- const: bus
143
-
- const: nav
144
-
- const: snoc_axi
145
-
- const: mnoc_axi
146
-
147
-
- if:
148
-
properties:
149
-
compatible:
150
-
contains:
151
-
enum:
152
246
- qcom,msm8226-adsp-pil
247
+
- qcom,msm8953-adsp-pil
153
248
- qcom,msm8974-adsp-pil
154
249
- qcom,msm8996-adsp-pil
155
250
- qcom,msm8996-slpi-pil
156
251
- qcom,msm8998-adsp-pas
157
252
- qcom,msm8998-slpi-pas
158
-
- qcom,qcs404-adsp-pas
159
-
- qcom,qcs404-cdsp-pas
160
-
- qcom,qcs404-wcss-pas
161
-
- qcom,sc8180x-adsp-pas
162
-
- qcom,sc8180x-cdsp-pas
163
-
- qcom,sc8280xp-adsp-pas
164
-
- qcom,sc8280xp-nsp0-pas
165
-
- qcom,sc8280xp-nsp1-pas
166
253
- qcom,sdm845-adsp-pas
167
254
- qcom,sdm845-cdsp-pas
168
-
- qcom,sm6350-adsp-pas
169
-
- qcom,sm6350-cdsp-pas
170
-
- qcom,sm8150-adsp-pas
171
-
- qcom,sm8150-cdsp-pas
172
-
- qcom,sm8150-slpi-pas
173
-
- qcom,sm8250-adsp-pas
174
-
- qcom,sm8250-cdsp-pas
175
-
- qcom,sm8250-slpi-pas
176
-
- qcom,sm8350-adsp-pas
177
-
- qcom,sm8350-cdsp-pas
178
-
- qcom,sm8350-slpi-pas
179
-
- qcom,sm8450-adsp-pas
180
-
- qcom,sm8450-cdsp-pas
181
-
- qcom,sm8450-slpi-pas
182
255
then:
183
256
properties:
184
257
interrupts:
185
258
maxItems: 5
186
259
interrupt-names:
187
260
maxItems: 5
188
-
189
-
- if:
190
-
properties:
191
-
compatible:
192
-
contains:
193
-
enum:
194
-
- qcom,sc7180-mpss-pas
195
-
- qcom,sc7280-mpss-pas
196
-
- qcom,sc8180x-mpss-pas
197
-
- qcom,sdx55-mpss-pas
198
-
- qcom,sm6350-mpss-pas
199
-
- qcom,sm8150-mpss-pas
200
-
- qcom,sm8350-mpss-pas
201
-
- qcom,sm8450-mpss-pas
202
-
then:
203
-
properties:
204
-
interrupts:
205
-
minItems: 6
206
-
interrupt-names:
207
-
minItems: 6
208
261
209
262
- if:
210
263
properties:
···
127
370
contains:
128
371
enum:
129
372
- qcom,msm8226-adsp-pil
373
+
- qcom,msm8953-adsp-pil
130
374
- qcom,msm8996-adsp-pil
131
375
- qcom,msm8998-adsp-pas
132
-
- qcom,sm8150-adsp-pas
133
-
- qcom,sm8150-cdsp-pas
134
376
then:
135
377
properties:
136
378
power-domains:
···
162
406
compatible:
163
407
contains:
164
408
enum:
165
-
- qcom,sc7180-mpss-pas
166
-
then:
167
-
properties:
168
-
power-domains:
169
-
items:
170
-
- description: CX power domain
171
-
- description: MX power domain
172
-
- description: MSS power domain
173
-
power-domain-names:
174
-
items:
175
-
- const: cx
176
-
- const: mx
177
-
- const: mss
178
-
179
-
- if:
180
-
properties:
181
-
compatible:
182
-
contains:
183
-
enum:
184
-
- qcom,sm6350-cdsp-pas
185
-
then:
186
-
properties:
187
-
power-domains:
188
-
items:
189
-
- description: CX power domain
190
-
- description: MX power domain
191
-
power-domain-names:
192
-
items:
193
-
- const: cx
194
-
- const: mx
195
-
196
-
- if:
197
-
properties:
198
-
compatible:
199
-
contains:
200
-
enum:
201
-
- qcom,sc7280-mpss-pas
202
-
- qcom,sdx55-mpss-pas
203
-
- qcom,sm6350-mpss-pas
204
-
- qcom,sm8150-mpss-pas
205
-
- qcom,sm8350-mpss-pas
206
-
- qcom,sm8450-mpss-pas
207
-
then:
208
-
properties:
209
-
power-domains:
210
-
items:
211
-
- description: CX power domain
212
-
- description: MSS power domain
213
-
power-domain-names:
214
-
items:
215
-
- const: cx
216
-
- const: mss
217
-
218
-
- if:
219
-
properties:
220
-
compatible:
221
-
contains:
222
-
enum:
223
-
- qcom,sc8180x-adsp-pas
224
-
- qcom,sc8180x-cdsp-pas
225
-
- qcom,sc8280xp-adsp-pas
226
-
- qcom,sm6350-adsp-pas
227
-
- qcom,sm8150-slpi-pas
228
-
- qcom,sm8250-adsp-pas
229
-
- qcom,sm8250-slpi-pas
230
-
- qcom,sm8350-adsp-pas
231
-
- qcom,sm8350-slpi-pas
232
-
- qcom,sm8450-adsp-pas
233
-
- qcom,sm8450-slpi-pas
234
-
then:
235
-
properties:
236
-
power-domains:
237
-
items:
238
-
- description: LCX power domain
239
-
- description: LMX power domain
240
-
power-domain-names:
241
-
items:
242
-
- const: lcx
243
-
- const: lmx
244
-
245
-
- if:
246
-
properties:
247
-
compatible:
248
-
contains:
249
-
enum:
250
-
- qcom,sm8350-cdsp-pas
251
-
- qcom,sm8450-cdsp-pas
252
-
then:
253
-
properties:
254
-
power-domains:
255
-
items:
256
-
- description: CX power domain
257
-
- description: MXC power domain
258
-
power-domain-names:
259
-
items:
260
-
- const: cx
261
-
- const: mxc
262
-
263
-
- if:
264
-
properties:
265
-
compatible:
266
-
contains:
267
-
enum:
268
-
- qcom,sc8280xp-nsp0-pas
269
-
- qcom,sc8280xp-nsp1-pas
270
-
then:
271
-
properties:
272
-
power-domains:
273
-
items:
274
-
- description: NSP power domain
275
-
power-domain-names:
276
-
items:
277
-
- const: nsp
278
-
279
-
- if:
280
-
properties:
281
-
compatible:
282
-
contains:
283
-
enum:
284
-
- qcom,qcs404-cdsp-pas
285
-
then:
286
-
properties:
287
-
resets:
288
-
items:
289
-
- description: CDSP restart
290
-
reset-names:
291
-
items:
292
-
- const: restart
293
-
294
-
- if:
295
-
properties:
296
-
compatible:
297
-
contains:
298
-
enum:
299
-
- qcom,sc7180-mpss-pas
300
-
- qcom,sc7280-mpss-pas
301
-
then:
302
-
properties:
303
-
resets:
304
-
items:
305
-
- description: MSS restart
306
-
- description: PDC reset
307
-
reset-names:
308
-
items:
309
-
- const: mss_restart
310
-
- const: pdc_reset
311
-
312
-
- if:
313
-
properties:
314
-
compatible:
315
-
contains:
316
-
enum:
317
409
- qcom,msm8226-adsp-pil
410
+
- qcom,msm8953-adsp-pil
318
411
- qcom,msm8974-adsp-pil
319
412
- qcom,msm8996-adsp-pil
320
413
- qcom,msm8996-slpi-pil
321
414
- qcom,msm8998-adsp-pas
322
415
- qcom,msm8998-slpi-pas
323
-
- qcom,qcs404-adsp-pas
324
-
- qcom,qcs404-cdsp-pas
325
-
- qcom,qcs404-wcss-pas
326
416
- qcom,sdm660-adsp-pas
327
-
- qcom,sdx55-mpss-pas
328
417
then:
329
418
properties:
330
419
qcom,qmp: false
+3
-1
Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml
+3
-1
Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml
+289
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
+289
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8916 MSS Peripheral Image Loader (and similar)
8
+
9
+
maintainers:
10
+
- Stephan Gerhold <stephan@gerhold.net>
11
+
12
+
description:
13
+
This document describes the hardware for a component that loads and boots
14
+
firmware on the Qualcomm MSM8916 Modem Hexagon Core (and similar).
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- qcom,msm8909-mss-pil
21
+
- qcom,msm8916-mss-pil
22
+
- qcom,msm8953-mss-pil
23
+
- qcom,msm8974-mss-pil
24
+
25
+
- const: qcom,q6v5-pil
26
+
description: Deprecated, prefer using qcom,msm8916-mss-pil
27
+
deprecated: true
28
+
29
+
reg:
30
+
items:
31
+
- description: MSS QDSP6 registers
32
+
- description: RMB registers
33
+
34
+
reg-names:
35
+
items:
36
+
- const: qdsp6
37
+
- const: rmb
38
+
39
+
interrupts:
40
+
items:
41
+
- description: Watchdog interrupt
42
+
- description: Fatal interrupt
43
+
- description: Ready interrupt
44
+
- description: Handover interrupt
45
+
- description: Stop acknowledge interrupt
46
+
47
+
interrupt-names:
48
+
items:
49
+
- const: wdog
50
+
- const: fatal
51
+
- const: ready
52
+
- const: handover
53
+
- const: stop-ack
54
+
55
+
clocks:
56
+
items:
57
+
- description: Configuration interface (AXI) clock
58
+
- description: Configuration bus (AHB) clock
59
+
- description: Boot ROM (AHB) clock
60
+
- description: XO proxy clock (control handed over after startup)
61
+
62
+
clock-names:
63
+
items:
64
+
- const: iface
65
+
- const: bus
66
+
- const: mem
67
+
- const: xo
68
+
69
+
power-domains:
70
+
items:
71
+
- description: CX proxy power domain (control handed over after startup)
72
+
- description: MX proxy power domain (control handed over after startup)
73
+
- description: MSS proxy power domain (control handed over after startup)
74
+
(only valid for qcom,msm8953-mss-pil)
75
+
minItems: 2
76
+
77
+
power-domain-names:
78
+
items:
79
+
- const: cx
80
+
- const: mx
81
+
- const: mss # only valid for qcom,msm8953-mss-pil
82
+
minItems: 2
83
+
84
+
pll-supply:
85
+
description: PLL proxy supply (control handed over after startup)
86
+
87
+
mss-supply:
88
+
description: MSS power domain supply (only valid for qcom,msm8974-mss-pil)
89
+
90
+
resets:
91
+
items:
92
+
- description: MSS restart control
93
+
94
+
reset-names:
95
+
items:
96
+
- const: mss_restart
97
+
98
+
qcom,smem-states:
99
+
$ref: /schemas/types.yaml#/definitions/phandle-array
100
+
description: States used by the AP to signal the Hexagon core
101
+
items:
102
+
- description: Stop modem
103
+
104
+
qcom,smem-state-names:
105
+
description: Names of the states used by the AP to signal the Hexagon core
106
+
items:
107
+
- const: stop
108
+
109
+
qcom,halt-regs:
110
+
$ref: /schemas/types.yaml#/definitions/phandle-array
111
+
description:
112
+
Halt registers are used to halt transactions of various sub-components
113
+
within MSS.
114
+
items:
115
+
- items:
116
+
- description: phandle to TCSR syscon region
117
+
- description: offset to the Q6 halt register
118
+
- description: offset to the modem halt register
119
+
- description: offset to the nc halt register
120
+
121
+
memory-region:
122
+
items:
123
+
- description: MBA reserved region
124
+
- description: MPSS reserved region
125
+
126
+
firmware-name:
127
+
$ref: /schemas/types.yaml#/definitions/string-array
128
+
items:
129
+
- description: Name of MBA firmware
130
+
- description: Name of modem firmware
131
+
132
+
bam-dmux:
133
+
$ref: /schemas/net/qcom,bam-dmux.yaml#
134
+
description:
135
+
Qualcomm BAM Data Multiplexer (provides network interface to the modem)
136
+
137
+
smd-edge:
138
+
$ref: qcom,smd-edge.yaml#
139
+
description:
140
+
Qualcomm SMD subnode which represents communication edge, channels
141
+
and devices related to the DSP.
142
+
properties:
143
+
label:
144
+
enum:
145
+
- modem
146
+
- hexagon
147
+
unevaluatedProperties: false
148
+
149
+
# Deprecated properties
150
+
cx-supply:
151
+
description: CX power domain regulator supply (prefer using power-domains)
152
+
deprecated: true
153
+
154
+
mx-supply:
155
+
description: MX power domain regulator supply (prefer using power-domains)
156
+
deprecated: true
157
+
158
+
mba:
159
+
type: object
160
+
description:
161
+
MBA reserved region (prefer using memory-region with two items)
162
+
properties:
163
+
memory-region: true
164
+
required:
165
+
- memory-region
166
+
deprecated: true
167
+
168
+
mpss:
169
+
type: object
170
+
description:
171
+
MPSS reserved region (prefer using memory-region with two items)
172
+
properties:
173
+
memory-region: true
174
+
required:
175
+
- memory-region
176
+
deprecated: true
177
+
178
+
required:
179
+
- compatible
180
+
- reg
181
+
- reg-names
182
+
- interrupts
183
+
- interrupt-names
184
+
- clocks
185
+
- clock-names
186
+
- pll-supply
187
+
- resets
188
+
- reset-names
189
+
- qcom,halt-regs
190
+
- qcom,smem-states
191
+
- qcom,smem-state-names
192
+
- smd-edge
193
+
194
+
allOf:
195
+
- if:
196
+
properties:
197
+
compatible:
198
+
const: qcom,msm8953-mss-pil
199
+
then:
200
+
properties:
201
+
power-domains:
202
+
minItems: 3
203
+
power-domain-names:
204
+
minItems: 3
205
+
required:
206
+
- power-domains
207
+
- power-domain-names
208
+
else:
209
+
properties:
210
+
power-domains:
211
+
maxItems: 2
212
+
power-domain-names:
213
+
maxItems: 2
214
+
215
+
- if:
216
+
properties:
217
+
compatible:
218
+
const: qcom,msm8974-mss-pil
219
+
then:
220
+
required:
221
+
- mss-supply
222
+
else:
223
+
properties:
224
+
mss-supply: false
225
+
226
+
# Fallbacks for deprecated properties
227
+
- oneOf:
228
+
- required:
229
+
- memory-region
230
+
- required:
231
+
- mba
232
+
- mpss
233
+
- oneOf:
234
+
- required:
235
+
- power-domains
236
+
- power-domain-names
237
+
- required:
238
+
- cx-supply
239
+
- mx-supply
240
+
241
+
additionalProperties: false
242
+
243
+
examples:
244
+
- |
245
+
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
246
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
247
+
#include <dt-bindings/power/qcom-rpmpd.h>
248
+
249
+
remoteproc_mpss: remoteproc@4080000 {
250
+
compatible = "qcom,msm8916-mss-pil";
251
+
reg = <0x04080000 0x100>, <0x04020000 0x40>;
252
+
reg-names = "qdsp6", "rmb";
253
+
254
+
interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
255
+
<&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
256
+
<&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
257
+
<&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
258
+
<&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
259
+
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
260
+
261
+
qcom,smem-states = <&hexagon_smp2p_out 0>;
262
+
qcom,smem-state-names = "stop";
263
+
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
264
+
265
+
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
266
+
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
267
+
<&gcc GCC_BOOT_ROM_AHB_CLK>,
268
+
<&xo_board>;
269
+
clock-names = "iface", "bus", "mem", "xo";
270
+
271
+
power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>;
272
+
power-domain-names = "cx", "mx";
273
+
pll-supply = <&pm8916_l7>;
274
+
275
+
resets = <&scm 0>;
276
+
reset-names = "mss_restart";
277
+
278
+
memory-region = <&mba_mem>, <&mpss_mem>;
279
+
280
+
smd-edge {
281
+
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
282
+
283
+
qcom,smd-edge = <0>;
284
+
qcom,ipc = <&apcs 8 12>;
285
+
qcom,remote-pid = <1>;
286
+
287
+
label = "hexagon";
288
+
};
289
+
};
+393
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
+393
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8996 MSS Peripheral Image Loader (and similar)
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Sibi Sankar <quic_sibis@quicinc.com>
12
+
13
+
description:
14
+
MSS Peripheral Image Loader loads and boots firmware on the
15
+
Qualcomm Technology Inc. MSM8996 Modem Hexagon Core (and similar).
16
+
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- qcom,msm8996-mss-pil
21
+
- qcom,msm8998-mss-pil
22
+
- qcom,sdm845-mss-pil
23
+
24
+
reg:
25
+
items:
26
+
- description: MSS QDSP6 registers
27
+
- description: RMB registers
28
+
29
+
reg-names:
30
+
items:
31
+
- const: qdsp6
32
+
- const: rmb
33
+
34
+
iommus:
35
+
items:
36
+
- description: MSA Stream 1
37
+
- description: MSA Stream 2
38
+
39
+
interrupts:
40
+
items:
41
+
- description: Watchdog interrupt
42
+
- description: Fatal interrupt
43
+
- description: Ready interrupt
44
+
- description: Handover interrupt
45
+
- description: Stop acknowledge interrupt
46
+
- description: Shutdown acknowledge interrupt
47
+
48
+
interrupt-names:
49
+
items:
50
+
- const: wdog
51
+
- const: fatal
52
+
- const: ready
53
+
- const: handover
54
+
- const: stop-ack
55
+
- const: shutdown-ack
56
+
57
+
clocks:
58
+
minItems: 8
59
+
maxItems: 9
60
+
61
+
clock-names:
62
+
minItems: 8
63
+
maxItems: 9
64
+
65
+
power-domains:
66
+
items:
67
+
- description: CX power domain
68
+
- description: MX power domain
69
+
- description: MSS power domain (only valid for qcom,sdm845-mss-pil)
70
+
minItems: 2
71
+
72
+
power-domain-names:
73
+
items:
74
+
- const: cx
75
+
- const: mx
76
+
- const: mss # only valid for qcom,sdm845-mss-pil
77
+
minItems: 2
78
+
79
+
pll-supply:
80
+
description: PLL supply
81
+
82
+
resets:
83
+
items:
84
+
- description: AOSS restart
85
+
- description: PDC reset (only valid for qcom,sdm845-mss-pil)
86
+
minItems: 1
87
+
88
+
reset-names:
89
+
items:
90
+
- const: mss_restart
91
+
- const: pdc_reset # only valid for qcom,sdm845-mss-pil
92
+
minItems: 1
93
+
94
+
qcom,qmp:
95
+
$ref: /schemas/types.yaml#/definitions/phandle
96
+
description: Reference to the AOSS side-channel message RAM.
97
+
98
+
qcom,smem-states:
99
+
$ref: /schemas/types.yaml#/definitions/phandle-array
100
+
description: States used by the AP to signal the Hexagon core
101
+
items:
102
+
- description: Stop modem
103
+
104
+
qcom,smem-state-names:
105
+
description: Names of the states used by the AP to signal the Hexagon core
106
+
items:
107
+
- const: stop
108
+
109
+
qcom,halt-regs:
110
+
$ref: /schemas/types.yaml#/definitions/phandle-array
111
+
description:
112
+
Halt registers are used to halt transactions of various sub-components
113
+
within MSS.
114
+
items:
115
+
- items:
116
+
- description: phandle to TCSR syscon region
117
+
- description: offset to the Q6 halt register
118
+
- description: offset to the modem halt register
119
+
- description: offset to the nc halt register
120
+
121
+
memory-region:
122
+
items:
123
+
- description: MBA reserved region
124
+
- description: Modem reserved region
125
+
- description: Metadata reserved region
126
+
127
+
firmware-name:
128
+
$ref: /schemas/types.yaml#/definitions/string-array
129
+
items:
130
+
- description: Name of MBA firmware
131
+
- description: Name of modem firmware
132
+
133
+
smd-edge:
134
+
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
135
+
description:
136
+
Qualcomm Shared Memory subnode which represents communication edge,
137
+
channels and devices related to the Modem.
138
+
unevaluatedProperties: false
139
+
140
+
glink-edge:
141
+
$ref: /schemas/remoteproc/qcom,glink-edge.yaml#
142
+
description:
143
+
Qualcomm G-Link subnode which represents communication edge, channels
144
+
and devices related to the Modem.
145
+
unevaluatedProperties: false
146
+
147
+
# Deprecated properties
148
+
mba:
149
+
type: object
150
+
description:
151
+
MBA reserved region
152
+
153
+
properties:
154
+
memory-region: true
155
+
156
+
required:
157
+
- memory-region
158
+
159
+
additionalProperties: false
160
+
deprecated: true
161
+
162
+
mpss:
163
+
type: object
164
+
description:
165
+
MPSS reserved region
166
+
167
+
properties:
168
+
memory-region: true
169
+
170
+
required:
171
+
- memory-region
172
+
173
+
additionalProperties: false
174
+
deprecated: true
175
+
176
+
metadata:
177
+
type: object
178
+
description:
179
+
Metadata reserved region
180
+
181
+
properties:
182
+
memory-region: true
183
+
184
+
required:
185
+
- memory-region
186
+
187
+
additionalProperties: false
188
+
deprecated: true
189
+
190
+
required:
191
+
- compatible
192
+
- reg
193
+
- reg-names
194
+
- interrupts
195
+
- interrupt-names
196
+
- clocks
197
+
- clock-names
198
+
- power-domains
199
+
- power-domain-names
200
+
- resets
201
+
- reset-names
202
+
- qcom,halt-regs
203
+
- qcom,smem-states
204
+
- qcom,smem-state-names
205
+
206
+
allOf:
207
+
- if:
208
+
properties:
209
+
compatible:
210
+
const: qcom,msm8996-mss-pil
211
+
then:
212
+
properties:
213
+
clocks:
214
+
items:
215
+
- description: GCC MSS IFACE clock
216
+
- description: GCC MSS BUS clock
217
+
- description: GCC MSS MEM clock
218
+
- description: RPMH XO clock
219
+
- description: GCC MSS GPLL0 clock
220
+
- description: GCC MSS SNOC_AXI clock
221
+
- description: GCC MSS MNOC_AXI clock
222
+
- description: RPMH PNOC clock
223
+
- description: GCC MSS PRNG clock
224
+
- description: RPMH QDSS clock
225
+
clock-names:
226
+
items:
227
+
- const: iface
228
+
- const: bus
229
+
- const: mem
230
+
- const: xo
231
+
- const: gpll0_mss
232
+
- const: snoc_axi
233
+
- const: mnoc_axi
234
+
- const: pnoc
235
+
- const: qdss
236
+
glink-edge: false
237
+
required:
238
+
- pll-supply
239
+
- smd-edge
240
+
else:
241
+
properties:
242
+
pll-supply: false
243
+
smd-edge: false
244
+
245
+
- if:
246
+
properties:
247
+
compatible:
248
+
const: qcom,msm8998-mss-pil
249
+
then:
250
+
properties:
251
+
clocks:
252
+
items:
253
+
- description: GCC MSS IFACE clock
254
+
- description: GCC MSS BUS clock
255
+
- description: GCC MSS MEM clock
256
+
- description: GCC MSS GPLL0 clock
257
+
- description: GCC MSS SNOC_AXI clock
258
+
- description: GCC MSS MNOC_AXI clock
259
+
- description: RPMH QDSS clock
260
+
- description: RPMH XO clock
261
+
clock-names:
262
+
items:
263
+
- const: iface
264
+
- const: bus
265
+
- const: mem
266
+
- const: gpll0_mss
267
+
- const: snoc_axi
268
+
- const: mnoc_axi
269
+
- const: qdss
270
+
- const: xo
271
+
required:
272
+
- glink-edge
273
+
274
+
- if:
275
+
properties:
276
+
compatible:
277
+
const: qcom,sdm845-mss-pil
278
+
then:
279
+
properties:
280
+
power-domains:
281
+
minItems: 3
282
+
power-domain-names:
283
+
minItems: 3
284
+
resets:
285
+
minItems: 2
286
+
reset-names:
287
+
minItems: 2
288
+
clocks:
289
+
items:
290
+
- description: GCC MSS IFACE clock
291
+
- description: GCC MSS BUS clock
292
+
- description: GCC MSS MEM clock
293
+
- description: GCC MSS GPLL0 clock
294
+
- description: GCC MSS SNOC_AXI clock
295
+
- description: GCC MSS MNOC_AXI clock
296
+
- description: GCC MSS PRNG clock
297
+
- description: RPMH XO clock
298
+
clock-names:
299
+
items:
300
+
- const: iface
301
+
- const: bus
302
+
- const: mem
303
+
- const: gpll0_mss
304
+
- const: snoc_axi
305
+
- const: mnoc_axi
306
+
- const: prng
307
+
- const: xo
308
+
required:
309
+
- qcom,qmp
310
+
- glink-edge
311
+
else:
312
+
properties:
313
+
iommus: false
314
+
power-domains:
315
+
maxItems: 2
316
+
power-domain-names:
317
+
maxItems: 2
318
+
resets:
319
+
maxItems: 1
320
+
reset-names:
321
+
maxItems: 1
322
+
qcom,qmp: false
323
+
324
+
# Fallbacks for deprecated properties
325
+
- oneOf:
326
+
- required:
327
+
- memory-region
328
+
- required:
329
+
- mba
330
+
- mpss
331
+
- metadata
332
+
333
+
additionalProperties: false
334
+
335
+
examples:
336
+
- |
337
+
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
338
+
#include <dt-bindings/clock/qcom,rpmh.h>
339
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
340
+
#include <dt-bindings/power/qcom-rpmpd.h>
341
+
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
342
+
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
343
+
344
+
remoteproc@4080000 {
345
+
compatible = "qcom,sdm845-mss-pil";
346
+
reg = <0x04080000 0x408>, <0x04180000 0x48>;
347
+
reg-names = "qdsp6", "rmb";
348
+
349
+
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
350
+
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
351
+
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
352
+
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
353
+
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
354
+
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
355
+
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack",
356
+
"shutdown-ack";
357
+
358
+
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
359
+
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
360
+
<&gcc GCC_BOOT_ROM_AHB_CLK>,
361
+
<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
362
+
<&gcc GCC_MSS_SNOC_AXI_CLK>,
363
+
<&gcc GCC_MSS_MFAB_AXIS_CLK>,
364
+
<&gcc GCC_PRNG_AHB_CLK>,
365
+
<&rpmhcc RPMH_CXO_CLK>;
366
+
clock-names = "iface", "bus", "mem", "gpll0_mss",
367
+
"snoc_axi", "mnoc_axi", "prng", "xo";
368
+
369
+
power-domains = <&rpmhpd SDM845_CX>,
370
+
<&rpmhpd SDM845_MX>,
371
+
<&rpmhpd SDM845_MSS>;
372
+
power-domain-names = "cx", "mx", "mss";
373
+
374
+
memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
375
+
376
+
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
377
+
<&pdc_reset PDC_MODEM_SYNC_RESET>;
378
+
reset-names = "mss_restart", "pdc_reset";
379
+
380
+
qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
381
+
382
+
qcom,qmp = <&aoss_qmp>;
383
+
384
+
qcom,smem-states = <&modem_smp2p_out 0>;
385
+
qcom,smem-state-names = "stop";
386
+
387
+
glink-edge {
388
+
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
389
+
label = "modem";
390
+
qcom,remote-pid = <1>;
391
+
mboxes = <&apss_shared 12>;
392
+
};
393
+
};
+89
Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml
+89
Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,pas-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Peripheral Authentication Service Common Properties
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Common properties of Qualcomm SoCs Peripheral Authentication Service.
14
+
15
+
properties:
16
+
clocks:
17
+
minItems: 1
18
+
maxItems: 2
19
+
20
+
clock-names:
21
+
minItems: 1
22
+
maxItems: 2
23
+
24
+
interconnects:
25
+
maxItems: 1
26
+
27
+
interrupts:
28
+
minItems: 5
29
+
items:
30
+
- description: Watchdog interrupt
31
+
- description: Fatal interrupt
32
+
- description: Ready interrupt
33
+
- description: Handover interrupt
34
+
- description: Stop acknowledge interrupt
35
+
- description: Shutdown acknowledge interrupt
36
+
37
+
interrupt-names:
38
+
minItems: 5
39
+
items:
40
+
- const: wdog
41
+
- const: fatal
42
+
- const: ready
43
+
- const: handover
44
+
- const: stop-ack
45
+
- const: shutdown-ack
46
+
47
+
power-domains:
48
+
minItems: 1
49
+
maxItems: 3
50
+
51
+
power-domain-names:
52
+
minItems: 1
53
+
maxItems: 3
54
+
55
+
qcom,smem-states:
56
+
$ref: /schemas/types.yaml#/definitions/phandle-array
57
+
description: States used by the AP to signal the Hexagon core
58
+
items:
59
+
- description: Stop the modem
60
+
61
+
qcom,smem-state-names:
62
+
description: The names of the state bits used for SMP2P output
63
+
items:
64
+
- const: stop
65
+
66
+
smd-edge:
67
+
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
68
+
description:
69
+
Qualcomm Shared Memory subnode which represents communication edge,
70
+
channels and devices related to the ADSP.
71
+
unevaluatedProperties: false
72
+
73
+
glink-edge:
74
+
$ref: /schemas/remoteproc/qcom,glink-edge.yaml#
75
+
description:
76
+
Qualcomm G-Link subnode which represents communication edge, channels
77
+
and devices related to the ADSP.
78
+
unevaluatedProperties: false
79
+
80
+
required:
81
+
- clocks
82
+
- clock-names
83
+
- interrupts
84
+
- interrupt-names
85
+
- memory-region
86
+
- qcom,smem-states
87
+
- qcom,smem-state-names
88
+
89
+
additionalProperties: true
+5
-167
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+5
-167
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
···
7
7
Usage: required
8
8
Value type: <string>
9
9
Definition: must be one of:
10
-
"qcom,q6v5-pil",
11
10
"qcom,ipq8074-wcss-pil"
12
11
"qcom,qcs404-wcss-pil"
13
-
"qcom,msm8916-mss-pil",
14
-
"qcom,msm8974-mss-pil"
15
-
"qcom,msm8996-mss-pil"
16
-
"qcom,msm8998-mss-pil"
17
-
"qcom,sdm845-mss-pil"
18
12
19
13
- reg:
20
14
Usage: required
···
29
35
- interrupt-names:
30
36
Usage: required
31
37
Value type: <stringlist>
32
-
Definition: The interrupts needed depends on the compatible
33
-
string:
34
-
qcom,q6v5-pil:
35
-
qcom,ipq8074-wcss-pil:
36
-
qcom,qcs404-wcss-pil:
37
-
qcom,msm8916-mss-pil:
38
-
qcom,msm8974-mss-pil:
39
-
must be "wdog", "fatal", "ready", "handover", "stop-ack"
40
-
qcom,msm8996-mss-pil:
41
-
qcom,msm8998-mss-pil:
42
-
qcom,sdm845-mss-pil:
43
-
must be "wdog", "fatal", "ready", "handover", "stop-ack",
44
-
"shutdown-ack"
45
-
46
-
- firmware-name:
47
-
Usage: optional
48
-
Value type: <stringlist>
49
-
Definition: must list the relative firmware image paths for mba and
50
-
modem. They are used for booting and authenticating the
51
-
Hexagon core.
38
+
Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
52
39
53
40
- clocks:
54
41
Usage: required
···
47
72
"gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc",
48
73
"lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc",
49
74
"lcc_axim_cbc", "lcc_bcr_sleep"
50
-
qcom,q6v5-pil:
51
-
qcom,msm8916-mss-pil:
52
-
qcom,msm8974-mss-pil:
53
-
must be "iface", "bus", "mem", "xo"
54
-
qcom,msm8996-mss-pil:
55
-
must be "iface", "bus", "mem", "xo", "gpll0_mss",
56
-
"snoc_axi", "mnoc_axi", "pnoc", "qdss"
57
-
qcom,msm8998-mss-pil:
58
-
must be "iface", "bus", "mem", "xo", "gpll0_mss",
59
-
"snoc_axi", "mnoc_axi", "qdss"
60
-
qcom,sdm845-mss-pil:
61
-
must be "iface", "bus", "mem", "xo", "gpll0_mss",
62
-
"snoc_axi", "mnoc_axi", "prng"
63
75
64
76
- resets:
65
77
Usage: required
66
78
Value type: <phandle>
67
-
Definition: reference to the reset-controller for the modem sub-system
68
-
reference to the list of 3 reset-controllers for the
79
+
Definition: reference to the list of 3 reset-controllers for the
69
80
wcss sub-system
70
-
reference to the list of 2 reset-controllers for the modem
71
-
sub-system on SDM845 SoCs
72
81
73
82
- reset-names:
74
83
Usage: required
75
84
Value type: <stringlist>
76
-
Definition: must be "mss_restart" for the modem sub-system
77
-
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
85
+
Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
78
86
for the wcss sub-system
79
-
must be "mss_restart", "pdc_reset" for the modem
80
-
sub-system on SDM845 SoCs
81
87
82
-
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
83
-
should be referenced as follows:
84
88
- memory-region:
85
89
Usage: required
86
90
Value type: <phandle>
87
-
Definition: reference to the reserved-memory for the mba region followed
88
-
by the mpss region
89
-
90
-
For the compatible strings below the following supplies are required:
91
-
"qcom,q6v5-pil"
92
-
"qcom,msm8916-mss-pil",
93
-
- cx-supply: (deprecated, use power domain instead)
94
-
- mx-supply: (deprecated, use power domain instead)
95
-
- pll-supply:
96
-
Usage: required
97
-
Value type: <phandle>
98
-
Definition: reference to the regulators to be held on behalf of the
99
-
booting of the Hexagon core
100
-
101
-
For the compatible string below the following supplies are required:
102
-
"qcom,msm8974-mss-pil"
103
-
- cx-supply: (deprecated, use power domain instead)
104
-
- mss-supply:
105
-
- mx-supply: (deprecated, use power domain instead)
106
-
- pll-supply:
107
-
Usage: required
108
-
Value type: <phandle>
109
-
Definition: reference to the regulators to be held on behalf of the
110
-
booting of the Hexagon core
91
+
Definition: reference to wcss reserved-memory region.
111
92
112
93
For the compatible string below the following supplies are required:
113
94
"qcom,qcs404-wcss-pil"
···
72
141
Value type: <phandle>
73
142
Definition: reference to the regulators to be held on behalf of the
74
143
booting of the Hexagon core
75
-
76
-
For the compatible string below the following supplies are required:
77
-
"qcom,msm8996-mss-pil"
78
-
- pll-supply:
79
-
Usage: required
80
-
Value type: <phandle>
81
-
Definition: reference to the regulators to be held on behalf of the
82
-
booting of the Hexagon core
83
-
84
-
- power-domains:
85
-
Usage: required
86
-
Value type: <phandle>
87
-
Definition: reference to power-domains that match power-domain-names
88
-
89
-
- power-domain-names:
90
-
Usage: required
91
-
Value type: <stringlist>
92
-
Definition: The power-domains needed depend on the compatible string:
93
-
qcom,ipq8074-wcss-pil:
94
-
no power-domain names required
95
-
qcom,q6v5-pil:
96
-
qcom,msm8916-mss-pil:
97
-
qcom,msm8974-mss-pil:
98
-
qcom,msm8996-mss-pil:
99
-
qcom,msm8998-mss-pil:
100
-
must be "cx", "mx"
101
-
qcom,sdm845-mss-pil:
102
-
must be "cx", "mx", "mss"
103
-
104
-
- qcom,qmp:
105
-
Usage: optional
106
-
Value type: <phandle>
107
-
Definition: reference to the AOSS side-channel message RAM.
108
144
109
145
- qcom,smem-states:
110
146
Usage: required
···
88
190
Usage: required
89
191
Value type: <prop-encoded-array>
90
192
Definition: a phandle reference to a syscon representing TCSR followed
91
-
by the three offsets within syscon for q6, modem and nc
193
+
by the three offsets within syscon for q6, wcss and nc
92
194
halt registers.
93
-
94
-
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
95
-
on platforms which do not have TrustZone.
96
-
97
-
= SUBNODES:
98
-
The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
99
-
the memory regions used by the Hexagon firmware. Each sub-node must contain:
100
195
101
196
- memory-region:
102
197
Usage: required
···
100
209
"glink-edge" that describes the communication edge, channels and devices
101
210
related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and
102
211
../soc/qcom/qcom,glink.txt for details on how to describe these.
103
-
104
-
= EXAMPLE
105
-
The following example describes the resources needed to boot control the
106
-
Hexagon, as it is found on MSM8974 boards.
107
-
108
-
remoteproc@fc880000 {
109
-
compatible = "qcom,msm8974-mss-pil";
110
-
reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
111
-
reg-names = "qdsp6", "rmb";
112
-
113
-
interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
114
-
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
115
-
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
116
-
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
117
-
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
118
-
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
119
-
120
-
clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
121
-
<&gcc GCC_MSS_CFG_AHB_CLK>,
122
-
<&gcc GCC_BOOT_ROM_AHB_CLK>,
123
-
<&xo_board>;
124
-
clock-names = "iface", "bus", "mem", "xo";
125
-
126
-
resets = <&gcc GCC_MSS_RESTART>;
127
-
reset-names = "mss_restart";
128
-
129
-
cx-supply = <&pm8841_s2>;
130
-
mss-supply = <&pm8841_s3>;
131
-
mx-supply = <&pm8841_s1>;
132
-
pll-supply = <&pm8941_l12>;
133
-
134
-
qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
135
-
136
-
qcom,smem-states = <&modem_smp2p_out 0>;
137
-
qcom,smem-state-names = "stop";
138
-
139
-
mba {
140
-
memory-region = <&mba_region>;
141
-
};
142
-
143
-
mpss {
144
-
memory-region = <&mpss_region>;
145
-
};
146
-
147
-
smd-edge {
148
-
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
149
-
150
-
qcom,ipc = <&apcs 8 12>;
151
-
qcom,smd-edge = <0>;
152
-
153
-
label = "modem";
154
-
};
155
-
};
+94
Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml
+94
Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm QCS404 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm QCS404 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,qcs404-adsp-pas
20
+
- qcom,qcs404-cdsp-pas
21
+
- qcom,qcs404-wcss-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
interrupts:
35
+
maxItems: 5
36
+
37
+
interrupt-names:
38
+
maxItems: 5
39
+
40
+
power-domains: false
41
+
power-domain-names: false
42
+
smd-edge: false
43
+
44
+
memory-region:
45
+
minItems: 1
46
+
description: Reference to the reserved-memory for the Hexagon core
47
+
48
+
firmware-name:
49
+
$ref: /schemas/types.yaml#/definitions/string
50
+
description: Firmware name for the Hexagon core
51
+
52
+
required:
53
+
- compatible
54
+
- reg
55
+
56
+
allOf:
57
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
58
+
59
+
unevaluatedProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
64
+
#include <dt-bindings/interrupt-controller/irq.h>
65
+
66
+
remoteproc@c700000 {
67
+
compatible = "qcom,qcs404-adsp-pas";
68
+
reg = <0x0c700000 0x4040>;
69
+
70
+
clocks = <&xo_board>;
71
+
clock-names = "xo";
72
+
73
+
interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
74
+
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
75
+
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
76
+
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
77
+
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
78
+
interrupt-names = "wdog", "fatal", "ready",
79
+
"handover", "stop-ack";
80
+
81
+
memory-region = <&adsp_fw_mem>;
82
+
83
+
qcom,smem-states = <&adsp_smp2p_out 0>;
84
+
qcom,smem-state-names = "stop";
85
+
86
+
glink-edge {
87
+
interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
88
+
89
+
qcom,remote-pid = <2>;
90
+
mboxes = <&apcs_glb 8>;
91
+
92
+
label = "adsp";
93
+
};
94
+
};
+2
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml
+2
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml
···
95
95
items:
96
96
- description: MBA reserved region
97
97
- description: modem reserved region
98
+
- description: metadata reserved region
98
99
99
100
firmware-name:
100
101
$ref: /schemas/types.yaml#/definitions/string-array
···
224
223
<&rpmhpd SC7180_MSS>;
225
224
power-domain-names = "cx", "mx", "mss";
226
225
227
-
memory-region = <&mba_mem>, <&mpss_mem>;
226
+
memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
228
227
229
228
qcom,qmp = <&aoss_qmp>;
230
229
+133
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml
+133
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SC7180/SC7280 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sc7180-mpss-pas
20
+
- qcom,sc7280-mpss-pas
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
clocks:
26
+
items:
27
+
- description: XO clock
28
+
29
+
clock-names:
30
+
items:
31
+
- const: xo
32
+
33
+
interrupts:
34
+
minItems: 6
35
+
36
+
interrupt-names:
37
+
minItems: 6
38
+
39
+
power-domains:
40
+
minItems: 2
41
+
items:
42
+
- description: CX power domain
43
+
- description: MX power domain
44
+
- description: MSS power domain
45
+
46
+
power-domain-names:
47
+
minItems: 2
48
+
items:
49
+
- const: cx
50
+
- const: mx
51
+
- const: mss
52
+
53
+
memory-region:
54
+
minItems: 1
55
+
description: Reference to the reserved-memory for the Hexagon core
56
+
57
+
qcom,qmp:
58
+
$ref: /schemas/types.yaml#/definitions/phandle
59
+
description: Reference to the AOSS side-channel message RAM.
60
+
61
+
smd-edge: false
62
+
63
+
firmware-name:
64
+
$ref: /schemas/types.yaml#/definitions/string
65
+
description: Firmware name for the Hexagon core
66
+
67
+
required:
68
+
- compatible
69
+
- reg
70
+
71
+
allOf:
72
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
enum:
77
+
- qcom,sc7180-mpss-pas
78
+
then:
79
+
properties:
80
+
power-domains:
81
+
minItems: 3
82
+
power-domain-names:
83
+
minItems: 3
84
+
else:
85
+
properties:
86
+
power-domains:
87
+
maxItems: 2
88
+
power-domain-names:
89
+
maxItems: 2
90
+
91
+
unevaluatedProperties: false
92
+
93
+
examples:
94
+
- |
95
+
#include <dt-bindings/clock/qcom,rpmh.h>
96
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
97
+
#include <dt-bindings/interrupt-controller/irq.h>
98
+
#include <dt-bindings/power/qcom-rpmpd.h>
99
+
100
+
remoteproc@4080000 {
101
+
compatible = "qcom,sc7180-mpss-pas";
102
+
reg = <0x04080000 0x4040>;
103
+
104
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
105
+
clock-names = "xo";
106
+
107
+
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
108
+
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
109
+
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
110
+
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
111
+
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
112
+
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
113
+
interrupt-names = "wdog", "fatal", "ready", "handover",
114
+
"stop-ack", "shutdown-ack";
115
+
116
+
memory-region = <&mpss_mem>;
117
+
118
+
power-domains = <&rpmhpd SC7180_CX>,
119
+
<&rpmhpd SC7180_MX>,
120
+
<&rpmhpd SC7180_MSS>;
121
+
power-domain-names = "cx", "mx", "mss";
122
+
123
+
qcom,qmp = <&aoss_qmp>;
124
+
qcom,smem-states = <&modem_smp2p_out 0>;
125
+
qcom,smem-state-names = "stop";
126
+
127
+
glink-edge {
128
+
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
129
+
label = "modem";
130
+
qcom,remote-pid = <1>;
131
+
mboxes = <&apss_shared 12>;
132
+
};
133
+
};
+195
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml
+195
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SC7280 ADSP Peripheral Image Loader
8
+
9
+
maintainers:
10
+
- Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
11
+
12
+
description:
13
+
This document describes the hardware for a component that loads and boots firmware
14
+
on the Qualcomm Technology Inc. ADSP.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sc7280-adsp-pil
20
+
21
+
reg:
22
+
items:
23
+
- description: qdsp6ss register
24
+
- description: efuse q6ss register
25
+
26
+
iommus:
27
+
items:
28
+
- description: Phandle to apps_smmu node with sid mask
29
+
30
+
interrupts:
31
+
items:
32
+
- description: Watchdog interrupt
33
+
- description: Fatal interrupt
34
+
- description: Ready interrupt
35
+
- description: Handover interrupt
36
+
- description: Stop acknowledge interrupt
37
+
- description: Shutdown acknowledge interrupt
38
+
39
+
interrupt-names:
40
+
items:
41
+
- const: wdog
42
+
- const: fatal
43
+
- const: ready
44
+
- const: handover
45
+
- const: stop-ack
46
+
- const: shutdown-ack
47
+
48
+
clocks:
49
+
items:
50
+
- description: XO clock
51
+
- description: GCC CFG NOC LPASS clock
52
+
53
+
clock-names:
54
+
items:
55
+
- const: xo
56
+
- const: gcc_cfg_noc_lpass
57
+
58
+
power-domains:
59
+
items:
60
+
- description: LCX power domain
61
+
62
+
resets:
63
+
items:
64
+
- description: PDC AUDIO SYNC RESET
65
+
- description: CC LPASS restart
66
+
67
+
reset-names:
68
+
items:
69
+
- const: pdc_sync
70
+
- const: cc_lpass
71
+
72
+
memory-region:
73
+
maxItems: 1
74
+
description: Reference to the reserved-memory for the Hexagon core
75
+
76
+
qcom,halt-regs:
77
+
$ref: /schemas/types.yaml#/definitions/phandle-array
78
+
description:
79
+
Phandle reference to a syscon representing TCSR followed by the
80
+
four offsets within syscon for q6, modem, nc and qv6 halt registers.
81
+
items:
82
+
- items:
83
+
- description: phandle to TCSR_MUTEX registers
84
+
- description: offset to the Q6 halt register
85
+
- description: offset to the modem halt register
86
+
- description: offset to the nc halt register
87
+
- description: offset to the vq6 halt register
88
+
89
+
qcom,smem-states:
90
+
$ref: /schemas/types.yaml#/definitions/phandle-array
91
+
description: States used by the AP to signal the Hexagon core
92
+
items:
93
+
- description: Stop the modem
94
+
95
+
qcom,smem-state-names:
96
+
description: The names of the state bits used for SMP2P output
97
+
const: stop
98
+
99
+
qcom,qmp:
100
+
$ref: /schemas/types.yaml#/definitions/phandle
101
+
description: Reference to the AOSS side-channel message RAM.
102
+
103
+
glink-edge:
104
+
$ref: qcom,glink-edge.yaml#
105
+
type: object
106
+
unevaluatedProperties: false
107
+
description: |
108
+
Qualcomm G-Link subnode which represents communication edge, channels
109
+
and devices related to the ADSP.
110
+
111
+
properties:
112
+
label:
113
+
const: lpass
114
+
115
+
gpr: true
116
+
apr: false
117
+
fastrpc: false
118
+
119
+
required:
120
+
- label
121
+
122
+
required:
123
+
- compatible
124
+
- reg
125
+
- interrupts
126
+
- interrupt-names
127
+
- clocks
128
+
- clock-names
129
+
- power-domains
130
+
- resets
131
+
- reset-names
132
+
- qcom,halt-regs
133
+
- memory-region
134
+
- qcom,smem-states
135
+
- qcom,smem-state-names
136
+
- qcom,qmp
137
+
138
+
additionalProperties: false
139
+
140
+
examples:
141
+
- |
142
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
143
+
#include <dt-bindings/clock/qcom,rpmh.h>
144
+
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
145
+
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
146
+
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
147
+
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
148
+
#include <dt-bindings/power/qcom-rpmpd.h>
149
+
#include <dt-bindings/mailbox/qcom-ipcc.h>
150
+
151
+
remoteproc@3000000 {
152
+
compatible = "qcom,sc7280-adsp-pil";
153
+
reg = <0x03000000 0x5000>,
154
+
<0x0355b000 0x10>;
155
+
156
+
interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>,
157
+
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
158
+
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
159
+
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
160
+
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
161
+
<&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
162
+
163
+
interrupt-names = "wdog", "fatal", "ready",
164
+
"handover", "stop-ack", "shutdown-ack";
165
+
166
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
167
+
<&gcc GCC_CFG_NOC_LPASS_CLK>;
168
+
clock-names = "xo", "gcc_cfg_noc_lpass";
169
+
170
+
power-domains = <&rpmhpd SC7280_LCX>;
171
+
172
+
resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
173
+
<&aoss_reset AOSS_CC_LPASS_RESTART>;
174
+
reset-names = "pdc_sync", "cc_lpass";
175
+
176
+
qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
177
+
178
+
memory-region = <&adsp_mem>;
179
+
180
+
qcom,smem-states = <&adsp_smp2p_out 0>;
181
+
qcom,smem-state-names = "stop";
182
+
183
+
qcom,qmp = <&aoss_qmp>;
184
+
185
+
glink-edge {
186
+
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
187
+
IPCC_MPROC_SIGNAL_GLINK_QMP
188
+
IRQ_TYPE_EDGE_RISING>;
189
+
mboxes = <&ipcc IPCC_CLIENT_LPASS
190
+
IPCC_MPROC_SIGNAL_GLINK_QMP>;
191
+
192
+
label = "lpass";
193
+
qcom,remote-pid = <2>;
194
+
};
195
+
};
+2
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
+2
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
···
95
95
items:
96
96
- description: MBA reserved region
97
97
- description: modem reserved region
98
+
- description: metadata reserved region
98
99
99
100
firmware-name:
100
101
$ref: /schemas/types.yaml#/definitions/string-array
···
241
240
<&rpmhpd SC7280_MSS>;
242
241
power-domain-names = "cx", "mss";
243
242
244
-
memory-region = <&mba_mem>, <&mpss_mem>;
243
+
memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
245
244
246
245
qcom,qmp = <&aoss_qmp>;
247
246
+95
Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml
+95
Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SC8180X Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sc8180x-adsp-pas
20
+
- qcom,sc8180x-cdsp-pas
21
+
- qcom,sc8180x-mpss-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
qcom,qmp:
35
+
$ref: /schemas/types.yaml#/definitions/phandle
36
+
description: Reference to the AOSS side-channel message RAM.
37
+
38
+
smd-edge: false
39
+
40
+
memory-region:
41
+
minItems: 1
42
+
description: Reference to the reserved-memory for the Hexagon core
43
+
44
+
firmware-name:
45
+
$ref: /schemas/types.yaml#/definitions/string
46
+
description: Firmware name for the Hexagon core
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
52
+
allOf:
53
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
54
+
- if:
55
+
properties:
56
+
compatible:
57
+
enum:
58
+
- qcom,sc8180x-adsp-pas
59
+
- qcom,sc8180x-cdsp-pas
60
+
then:
61
+
properties:
62
+
interrupts:
63
+
maxItems: 5
64
+
interrupt-names:
65
+
maxItems: 5
66
+
else:
67
+
properties:
68
+
interrupts:
69
+
minItems: 6
70
+
interrupt-names:
71
+
minItems: 6
72
+
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
enum:
77
+
- qcom,sc8180x-adsp-pas
78
+
- qcom,sc8180x-cdsp-pas
79
+
then:
80
+
properties:
81
+
power-domains:
82
+
items:
83
+
- description: LCX power domain
84
+
- description: LMX power domain
85
+
power-domain-names:
86
+
items:
87
+
- const: lcx
88
+
- const: lmx
89
+
else:
90
+
properties:
91
+
# TODO: incomplete
92
+
power-domains: false
93
+
power-domain-names: false
94
+
95
+
unevaluatedProperties: false
+147
Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml
+147
Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SC8280XP Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SC8280XP SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sc8280xp-adsp-pas
20
+
- qcom,sc8280xp-nsp0-pas
21
+
- qcom,sc8280xp-nsp1-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
qcom,qmp:
35
+
$ref: /schemas/types.yaml#/definitions/phandle
36
+
description: Reference to the AOSS side-channel message RAM.
37
+
38
+
smd-edge: false
39
+
40
+
memory-region:
41
+
minItems: 1
42
+
description: Reference to the reserved-memory for the Hexagon core
43
+
44
+
firmware-name:
45
+
$ref: /schemas/types.yaml#/definitions/string
46
+
description: Firmware name for the Hexagon core
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
52
+
allOf:
53
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
54
+
- if:
55
+
properties:
56
+
compatible:
57
+
enum:
58
+
- qcom,sc8280xp-nsp0-pas
59
+
- qcom,sc8280xp-nsp1-pas
60
+
then:
61
+
properties:
62
+
interrupts:
63
+
maxItems: 5
64
+
interrupt-names:
65
+
maxItems: 5
66
+
else:
67
+
properties:
68
+
interrupts:
69
+
minItems: 6
70
+
interrupt-names:
71
+
minItems: 6
72
+
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
enum:
77
+
- qcom,sc8280xp-adsp-pas
78
+
then:
79
+
properties:
80
+
power-domains:
81
+
items:
82
+
- description: LCX power domain
83
+
- description: LMX power domain
84
+
power-domain-names:
85
+
items:
86
+
- const: lcx
87
+
- const: lmx
88
+
else:
89
+
properties:
90
+
power-domains:
91
+
items:
92
+
- description: NSP power domain
93
+
power-domain-names:
94
+
items:
95
+
- const: nsp
96
+
97
+
unevaluatedProperties: false
98
+
99
+
examples:
100
+
- |
101
+
#include <dt-bindings/clock/qcom,rpmh.h>
102
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
103
+
#include <dt-bindings/interrupt-controller/irq.h>
104
+
#include <dt-bindings/mailbox/qcom-ipcc.h>
105
+
#include <dt-bindings/power/qcom-rpmpd.h>
106
+
107
+
remoteproc@3000000 {
108
+
compatible = "qcom,sc8280xp-adsp-pas";
109
+
reg = <0x03000000 0x100>;
110
+
111
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
112
+
clock-names = "xo";
113
+
114
+
firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
115
+
116
+
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
117
+
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
118
+
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
119
+
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
120
+
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
121
+
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
122
+
interrupt-names = "wdog", "fatal", "ready",
123
+
"handover", "stop-ack", "shutdown-ack";
124
+
125
+
memory-region = <&pil_adsp_mem>;
126
+
127
+
power-domains = <&rpmhpd SC8280XP_LCX>,
128
+
<&rpmhpd SC8280XP_LMX>;
129
+
power-domain-names = "lcx", "lmx";
130
+
131
+
qcom,qmp = <&aoss_qmp>;
132
+
qcom,smem-states = <&smp2p_adsp_out 0>;
133
+
qcom,smem-state-names = "stop";
134
+
135
+
glink-edge {
136
+
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
137
+
IPCC_MPROC_SIGNAL_GLINK_QMP
138
+
IRQ_TYPE_EDGE_RISING>;
139
+
mboxes = <&ipcc IPCC_CLIENT_LPASS
140
+
IPCC_MPROC_SIGNAL_GLINK_QMP>;
141
+
142
+
label = "lpass";
143
+
qcom,remote-pid = <2>;
144
+
145
+
/* ... */
146
+
};
147
+
};
+109
Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml
+109
Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sdx55-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDX55 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SDX55 SoC Peripheral Authentication Service loads and boots firmware
14
+
on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sdx55-mpss-pas
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
items:
26
+
- description: XO clock
27
+
28
+
clock-names:
29
+
items:
30
+
- const: xo
31
+
32
+
interrupts:
33
+
minItems: 6
34
+
35
+
interrupt-names:
36
+
minItems: 6
37
+
38
+
power-domains:
39
+
items:
40
+
- description: CX power domain
41
+
- description: MSS power domain
42
+
43
+
power-domain-names:
44
+
items:
45
+
- const: cx
46
+
- const: mss
47
+
48
+
memory-region:
49
+
minItems: 1
50
+
description: Reference to the reserved-memory for the Hexagon core
51
+
52
+
qcom,qmp:
53
+
$ref: /schemas/types.yaml#/definitions/phandle
54
+
description: Reference to the AOSS side-channel message RAM.
55
+
56
+
smd-edge: false
57
+
58
+
firmware-name:
59
+
$ref: /schemas/types.yaml#/definitions/string
60
+
description: Firmware name for the Hexagon core
61
+
62
+
required:
63
+
- compatible
64
+
- reg
65
+
66
+
allOf:
67
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
68
+
69
+
unevaluatedProperties: false
70
+
71
+
examples:
72
+
- |
73
+
#include <dt-bindings/clock/qcom,rpmh.h>
74
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
75
+
#include <dt-bindings/power/qcom-rpmpd.h>
76
+
77
+
remoteproc@4080000 {
78
+
compatible = "qcom,sdx55-mpss-pas";
79
+
reg = <0x04080000 0x4040>;
80
+
81
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
82
+
clock-names = "xo";
83
+
84
+
interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
85
+
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
86
+
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
87
+
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
88
+
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
89
+
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
90
+
interrupt-names = "wdog", "fatal", "ready", "handover",
91
+
"stop-ack", "shutdown-ack";
92
+
93
+
memory-region = <&mpss_adsp_mem>;
94
+
95
+
power-domains = <&rpmhpd SDX55_CX>, <&rpmhpd SDX55_MSS>;
96
+
power-domain-names = "cx", "mss";
97
+
98
+
qcom,smem-states = <&modem_smp2p_out 0>;
99
+
qcom,smem-state-names = "stop";
100
+
101
+
glink-edge {
102
+
interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
103
+
label = "mpss";
104
+
mboxes = <&apcs 15>;
105
+
qcom,remote-pid = <1>;
106
+
107
+
/* ... */
108
+
};
109
+
};
+143
Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml
+143
Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sm6115-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM6115 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sm6115-adsp-pas
20
+
- qcom,sm6115-cdsp-pas
21
+
- qcom,sm6115-mpss-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
memory-region:
35
+
minItems: 1
36
+
description: Reference to the reserved-memory for the Hexagon core
37
+
38
+
smd-edge: false
39
+
40
+
firmware-name:
41
+
$ref: /schemas/types.yaml#/definitions/string
42
+
description: Firmware name for the Hexagon core
43
+
44
+
required:
45
+
- compatible
46
+
- reg
47
+
48
+
allOf:
49
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
50
+
- if:
51
+
properties:
52
+
compatible:
53
+
enum:
54
+
- qcom,sm6115-adsp-pas
55
+
- qcom,sm6115-cdsp-pas
56
+
then:
57
+
properties:
58
+
interrupts:
59
+
maxItems: 5
60
+
interrupt-names:
61
+
maxItems: 5
62
+
else:
63
+
properties:
64
+
interrupts:
65
+
minItems: 6
66
+
interrupt-names:
67
+
minItems: 6
68
+
69
+
- if:
70
+
properties:
71
+
compatible:
72
+
enum:
73
+
- qcom,sm6115-cdsp-pas
74
+
- qcom,sm6115-mpss-pas
75
+
then:
76
+
properties:
77
+
power-domains:
78
+
items:
79
+
- description: CX power domain
80
+
power-domain-names:
81
+
items:
82
+
- const: cx
83
+
84
+
- if:
85
+
properties:
86
+
compatible:
87
+
enum:
88
+
- qcom,sm6115-adsp-pas
89
+
then:
90
+
properties:
91
+
power-domains:
92
+
items:
93
+
- description: LPI CX power domain
94
+
- description: LPI MX power domain
95
+
power-domain-names:
96
+
items:
97
+
- const: lcx
98
+
- const: lmx
99
+
100
+
unevaluatedProperties: false
101
+
102
+
examples:
103
+
- |
104
+
#include <dt-bindings/clock/qcom,rpmcc.h>
105
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
106
+
#include <dt-bindings/interrupt-controller/irq.h>
107
+
#include <dt-bindings/power/qcom-rpmpd.h>
108
+
109
+
remoteproc@ab00000 {
110
+
compatible = "qcom,sm6115-adsp-pas";
111
+
reg = <0x0ab00000 0x100>;
112
+
113
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
114
+
clock-names = "xo";
115
+
116
+
firmware-name = "qcom/sm6115/adsp.mdt";
117
+
118
+
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
119
+
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
120
+
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
121
+
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
122
+
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
123
+
interrupt-names = "wdog", "fatal", "ready",
124
+
"handover", "stop-ack";
125
+
126
+
memory-region = <&pil_adsp_mem>;
127
+
128
+
power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
129
+
<&rpmpd SM6115_VDD_LPI_MX>;
130
+
131
+
qcom,smem-states = <&adsp_smp2p_out 0>;
132
+
qcom,smem-state-names = "stop";
133
+
134
+
glink-edge {
135
+
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
136
+
label = "lpass";
137
+
qcom,remote-pid = <2>;
138
+
mboxes = <&apcs_glb 8>;
139
+
140
+
/* ... */
141
+
142
+
};
143
+
};
+167
Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml
+167
Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM6350 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SM6350 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sm6350-adsp-pas
20
+
- qcom,sm6350-cdsp-pas
21
+
- qcom,sm6350-mpss-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
qcom,qmp:
35
+
$ref: /schemas/types.yaml#/definitions/phandle
36
+
description: Reference to the AOSS side-channel message RAM.
37
+
38
+
memory-region:
39
+
minItems: 1
40
+
description: Reference to the reserved-memory for the Hexagon core
41
+
42
+
smd-edge: false
43
+
44
+
firmware-name:
45
+
$ref: /schemas/types.yaml#/definitions/string
46
+
description: Firmware name for the Hexagon core
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
52
+
allOf:
53
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
54
+
- if:
55
+
properties:
56
+
compatible:
57
+
enum:
58
+
- qcom,sm6350-adsp-pas
59
+
- qcom,sm6350-cdsp-pas
60
+
then:
61
+
properties:
62
+
interrupts:
63
+
maxItems: 5
64
+
interrupt-names:
65
+
maxItems: 5
66
+
else:
67
+
properties:
68
+
interrupts:
69
+
minItems: 6
70
+
interrupt-names:
71
+
minItems: 6
72
+
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
enum:
77
+
- qcom,sm6350-adsp-pas
78
+
then:
79
+
properties:
80
+
power-domains:
81
+
items:
82
+
- description: LCX power domain
83
+
- description: LMX power domain
84
+
power-domain-names:
85
+
items:
86
+
- const: lcx
87
+
- const: lmx
88
+
89
+
- if:
90
+
properties:
91
+
compatible:
92
+
enum:
93
+
- qcom,sm6350-cdsp-pas
94
+
then:
95
+
properties:
96
+
power-domains:
97
+
items:
98
+
- description: CX power domain
99
+
- description: MX power domain
100
+
power-domain-names:
101
+
items:
102
+
- const: cx
103
+
- const: mx
104
+
105
+
- if:
106
+
properties:
107
+
compatible:
108
+
enum:
109
+
- qcom,sm6350-mpss-pas
110
+
then:
111
+
properties:
112
+
power-domains:
113
+
items:
114
+
- description: CX power domain
115
+
- description: MSS power domain
116
+
power-domain-names:
117
+
items:
118
+
- const: cx
119
+
- const: mss
120
+
121
+
unevaluatedProperties: false
122
+
123
+
examples:
124
+
- |
125
+
#include <dt-bindings/clock/qcom,rpmh.h>
126
+
#include <dt-bindings/interrupt-controller/irq.h>
127
+
#include <dt-bindings/mailbox/qcom-ipcc.h>
128
+
#include <dt-bindings/power/qcom-rpmpd.h>
129
+
130
+
remoteproc@3000000 {
131
+
compatible = "qcom,sm6350-adsp-pas";
132
+
reg = <0x03000000 0x100>;
133
+
134
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
135
+
clock-names = "xo";
136
+
137
+
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
138
+
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
139
+
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
140
+
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
141
+
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
142
+
interrupt-names = "wdog", "fatal", "ready",
143
+
"handover", "stop-ack";
144
+
145
+
memory-region = <&pil_adsp_mem>;
146
+
147
+
power-domains = <&rpmhpd SM6350_LCX>,
148
+
<&rpmhpd SM6350_LMX>;
149
+
power-domain-names = "lcx", "lmx";
150
+
151
+
qcom,qmp = <&aoss_qmp>;
152
+
qcom,smem-states = <&smp2p_adsp_out 0>;
153
+
qcom,smem-state-names = "stop";
154
+
155
+
glink-edge {
156
+
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
157
+
IPCC_MPROC_SIGNAL_GLINK_QMP
158
+
IRQ_TYPE_EDGE_RISING>;
159
+
mboxes = <&ipcc IPCC_CLIENT_LPASS
160
+
IPCC_MPROC_SIGNAL_GLINK_QMP>;
161
+
162
+
label = "lpass";
163
+
qcom,remote-pid = <2>;
164
+
165
+
/* ... */
166
+
};
167
+
};
+174
Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml
+174
Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8150/SM8250 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SM8150/SM8250 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sm8150-adsp-pas
20
+
- qcom,sm8150-cdsp-pas
21
+
- qcom,sm8150-mpss-pas
22
+
- qcom,sm8150-slpi-pas
23
+
- qcom,sm8250-adsp-pas
24
+
- qcom,sm8250-cdsp-pas
25
+
- qcom,sm8250-slpi-pas
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
clocks:
31
+
items:
32
+
- description: XO clock
33
+
34
+
clock-names:
35
+
items:
36
+
- const: xo
37
+
38
+
qcom,qmp:
39
+
$ref: /schemas/types.yaml#/definitions/phandle
40
+
description: Reference to the AOSS side-channel message RAM.
41
+
42
+
memory-region:
43
+
minItems: 1
44
+
description: Reference to the reserved-memory for the Hexagon core
45
+
46
+
smd-edge: false
47
+
48
+
firmware-name:
49
+
$ref: /schemas/types.yaml#/definitions/string
50
+
description: Firmware name for the Hexagon core
51
+
52
+
required:
53
+
- compatible
54
+
- reg
55
+
56
+
allOf:
57
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
58
+
- if:
59
+
properties:
60
+
compatible:
61
+
enum:
62
+
- qcom,sm8150-adsp-pas
63
+
- qcom,sm8150-cdsp-pas
64
+
- qcom,sm8150-slpi-pas
65
+
- qcom,sm8250-adsp-pas
66
+
- qcom,sm8250-cdsp-pas
67
+
- qcom,sm8250-slpi-pas
68
+
then:
69
+
properties:
70
+
interrupts:
71
+
maxItems: 5
72
+
interrupt-names:
73
+
maxItems: 5
74
+
else:
75
+
properties:
76
+
interrupts:
77
+
minItems: 6
78
+
interrupt-names:
79
+
minItems: 6
80
+
81
+
- if:
82
+
properties:
83
+
compatible:
84
+
enum:
85
+
- qcom,sm8150-adsp-pas
86
+
- qcom,sm8150-cdsp-pas
87
+
- qcom,sm8250-cdsp-pas
88
+
then:
89
+
properties:
90
+
power-domains:
91
+
items:
92
+
- description: CX power domain
93
+
power-domain-names:
94
+
items:
95
+
- const: cx
96
+
97
+
- if:
98
+
properties:
99
+
compatible:
100
+
enum:
101
+
- qcom,sm8150-mpss-pas
102
+
then:
103
+
properties:
104
+
power-domains:
105
+
items:
106
+
- description: CX power domain
107
+
- description: MSS power domain
108
+
power-domain-names:
109
+
items:
110
+
- const: cx
111
+
- const: mss
112
+
113
+
- if:
114
+
properties:
115
+
compatible:
116
+
enum:
117
+
- qcom,sm8150-slpi-pas
118
+
- qcom,sm8250-adsp-pas
119
+
- qcom,sm8250-slpi-pas
120
+
then:
121
+
properties:
122
+
power-domains:
123
+
items:
124
+
- description: LCX power domain
125
+
- description: LMX power domain
126
+
power-domain-names:
127
+
items:
128
+
- const: lcx
129
+
- const: lmx
130
+
131
+
unevaluatedProperties: false
132
+
133
+
examples:
134
+
- |
135
+
#include <dt-bindings/clock/qcom,rpmh.h>
136
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
137
+
#include <dt-bindings/interrupt-controller/irq.h>
138
+
#include <dt-bindings/power/qcom-rpmpd.h>
139
+
140
+
remoteproc@17300000 {
141
+
compatible = "qcom,sm8150-adsp-pas";
142
+
reg = <0x17300000 0x4040>;
143
+
144
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
145
+
clock-names = "xo";
146
+
147
+
firmware-name = "qcom/sm8150/adsp.mbn";
148
+
149
+
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
150
+
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
151
+
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
152
+
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
153
+
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
154
+
interrupt-names = "wdog", "fatal", "ready",
155
+
"handover", "stop-ack";
156
+
157
+
memory-region = <&adsp_mem>;
158
+
159
+
power-domains = <&rpmhpd SM8150_CX>;
160
+
161
+
qcom,qmp = <&aoss_qmp>;
162
+
qcom,smem-states = <&adsp_smp2p_out 0>;
163
+
qcom,smem-state-names = "stop";
164
+
165
+
glink-edge {
166
+
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
167
+
label = "lpass";
168
+
qcom,remote-pid = <2>;
169
+
mboxes = <&apss_shared 8>;
170
+
171
+
/* ... */
172
+
173
+
};
174
+
};
+182
Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
+182
Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8350/SM8450 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sm8350-adsp-pas
20
+
- qcom,sm8350-cdsp-pas
21
+
- qcom,sm8350-slpi-pas
22
+
- qcom,sm8350-mpss-pas
23
+
- qcom,sm8450-adsp-pas
24
+
- qcom,sm8450-cdsp-pas
25
+
- qcom,sm8450-mpss-pas
26
+
- qcom,sm8450-slpi-pas
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
clocks:
32
+
items:
33
+
- description: XO clock
34
+
35
+
clock-names:
36
+
items:
37
+
- const: xo
38
+
39
+
qcom,qmp:
40
+
$ref: /schemas/types.yaml#/definitions/phandle
41
+
description: Reference to the AOSS side-channel message RAM.
42
+
43
+
smd-edge: false
44
+
45
+
memory-region:
46
+
minItems: 1
47
+
description: Reference to the reserved-memory for the Hexagon core
48
+
49
+
firmware-name:
50
+
$ref: /schemas/types.yaml#/definitions/string
51
+
description: Firmware name for the Hexagon core
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
57
+
allOf:
58
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
59
+
- if:
60
+
properties:
61
+
compatible:
62
+
enum:
63
+
- qcom,sm8350-adsp-pas
64
+
- qcom,sm8350-cdsp-pas
65
+
- qcom,sm8350-slpi-pas
66
+
- qcom,sm8450-adsp-pas
67
+
- qcom,sm8450-cdsp-pas
68
+
- qcom,sm8450-slpi-pas
69
+
then:
70
+
properties:
71
+
interrupts:
72
+
maxItems: 5
73
+
interrupt-names:
74
+
maxItems: 5
75
+
else:
76
+
properties:
77
+
interrupts:
78
+
minItems: 6
79
+
interrupt-names:
80
+
minItems: 6
81
+
82
+
- if:
83
+
properties:
84
+
compatible:
85
+
enum:
86
+
- qcom,sm8350-mpss-pas
87
+
- qcom,sm8450-mpss-pas
88
+
then:
89
+
properties:
90
+
power-domains:
91
+
items:
92
+
- description: CX power domain
93
+
- description: MSS power domain
94
+
power-domain-names:
95
+
items:
96
+
- const: cx
97
+
- const: mss
98
+
99
+
- if:
100
+
properties:
101
+
compatible:
102
+
enum:
103
+
- qcom,sm8350-adsp-pas
104
+
- qcom,sm8350-slpi-pas
105
+
- qcom,sm8450-adsp-pas
106
+
- qcom,sm8450-slpi-pas
107
+
then:
108
+
properties:
109
+
power-domains:
110
+
items:
111
+
- description: LCX power domain
112
+
- description: LMX power domain
113
+
power-domain-names:
114
+
items:
115
+
- const: lcx
116
+
- const: lmx
117
+
118
+
- if:
119
+
properties:
120
+
compatible:
121
+
enum:
122
+
- qcom,sm8350-cdsp-pas
123
+
- qcom,sm8450-cdsp-pas
124
+
then:
125
+
properties:
126
+
power-domains:
127
+
items:
128
+
- description: CX power domain
129
+
- description: MXC power domain
130
+
power-domain-names:
131
+
items:
132
+
- const: cx
133
+
- const: mxc
134
+
135
+
unevaluatedProperties: false
136
+
137
+
examples:
138
+
- |
139
+
#include <dt-bindings/clock/qcom,rpmh.h>
140
+
#include <dt-bindings/interrupt-controller/irq.h>
141
+
#include <dt-bindings/mailbox/qcom-ipcc.h>
142
+
#include <dt-bindings/power/qcom-rpmpd.h>
143
+
144
+
remoteproc@30000000 {
145
+
compatible = "qcom,sm8450-adsp-pas";
146
+
reg = <0x030000000 0x100>;
147
+
148
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
149
+
clock-names = "xo";
150
+
151
+
firmware-name = "qcom/sm8450/adsp.mbn";
152
+
153
+
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
154
+
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
155
+
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
156
+
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
157
+
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
158
+
interrupt-names = "wdog", "fatal", "ready",
159
+
"handover", "stop-ack";
160
+
161
+
memory-region = <&adsp_mem>;
162
+
163
+
power-domains = <&rpmhpd SM8450_LCX>,
164
+
<&rpmhpd SM8450_LMX>;
165
+
power-domain-names = "lcx", "lmx";
166
+
167
+
qcom,qmp = <&aoss_qmp>;
168
+
qcom,smem-states = <&smp2p_adsp_out 0>;
169
+
qcom,smem-state-names = "stop";
170
+
171
+
glink-edge {
172
+
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
173
+
IPCC_MPROC_SIGNAL_GLINK_QMP
174
+
IRQ_TYPE_EDGE_RISING>;
175
+
mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
176
+
177
+
label = "lpass";
178
+
qcom,remote-pid = <2>;
179
+
180
+
/* ... */
181
+
};
182
+
};
+178
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
+178
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8550 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware
14
+
on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sm8550-adsp-pas
20
+
- qcom,sm8550-cdsp-pas
21
+
- qcom,sm8550-mpss-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
qcom,qmp:
35
+
$ref: /schemas/types.yaml#/definitions/phandle
36
+
description: Reference to the AOSS side-channel message RAM.
37
+
38
+
smd-edge: false
39
+
40
+
firmware-name:
41
+
$ref: /schemas/types.yaml#/definitions/string-array
42
+
items:
43
+
- description: Firmware name of the Hexagon core
44
+
- description: Firmware name of the Hexagon Devicetree
45
+
46
+
memory-region:
47
+
minItems: 2
48
+
items:
49
+
- description: Memory region for main Firmware authentication
50
+
- description: Memory region for Devicetree Firmware authentication
51
+
- description: DSM Memory region
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
57
+
allOf:
58
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
59
+
- if:
60
+
properties:
61
+
compatible:
62
+
enum:
63
+
- qcom,sm8550-adsp-pas
64
+
- qcom,sm8550-cdsp-pas
65
+
then:
66
+
properties:
67
+
interrupts:
68
+
maxItems: 5
69
+
interrupt-names:
70
+
maxItems: 5
71
+
memory-region:
72
+
maxItems: 2
73
+
else:
74
+
properties:
75
+
interrupts:
76
+
minItems: 6
77
+
interrupt-names:
78
+
minItems: 6
79
+
memory-region:
80
+
minItems: 3
81
+
82
+
- if:
83
+
properties:
84
+
compatible:
85
+
enum:
86
+
- qcom,sm8550-adsp-pas
87
+
then:
88
+
properties:
89
+
power-domains:
90
+
items:
91
+
- description: LCX power domain
92
+
- description: LMX power domain
93
+
power-domain-names:
94
+
items:
95
+
- const: lcx
96
+
- const: lmx
97
+
98
+
- if:
99
+
properties:
100
+
compatible:
101
+
enum:
102
+
- qcom,sm8550-mpss-pas
103
+
then:
104
+
properties:
105
+
power-domains:
106
+
items:
107
+
- description: CX power domain
108
+
- description: MSS power domain
109
+
power-domain-names:
110
+
items:
111
+
- const: cx
112
+
- const: mss
113
+
- if:
114
+
properties:
115
+
compatible:
116
+
enum:
117
+
- qcom,sm8550-cdsp-pas
118
+
then:
119
+
properties:
120
+
power-domains:
121
+
items:
122
+
- description: CX power domain
123
+
- description: MXC power domain
124
+
- description: NSP power domain
125
+
power-domain-names:
126
+
items:
127
+
- const: cx
128
+
- const: mxc
129
+
- const: nsp
130
+
131
+
unevaluatedProperties: false
132
+
133
+
examples:
134
+
- |
135
+
#include <dt-bindings/clock/qcom,rpmh.h>
136
+
#include <dt-bindings/interrupt-controller/irq.h>
137
+
#include <dt-bindings/mailbox/qcom-ipcc.h>
138
+
139
+
remoteproc@30000000 {
140
+
compatible = "qcom,sm8550-adsp-pas";
141
+
reg = <0x030000000 0x100>;
142
+
143
+
clocks = <&rpmhcc RPMH_CXO_CLK>;
144
+
clock-names = "xo";
145
+
146
+
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
147
+
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
148
+
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
149
+
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
150
+
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
151
+
interrupt-names = "wdog", "fatal", "ready",
152
+
"handover", "stop-ack";
153
+
154
+
memory-region = <&adsp_mem>, <&dtb_adsp_mem>;
155
+
156
+
firmware-name = "qcom/sm8550/adsp.mbn",
157
+
"qcom/sm8550/adsp_dtb.mbn";
158
+
159
+
power-domains = <&rpmhpd_sm8550_lcx>,
160
+
<&rpmhpd_sm8550_lmx>;
161
+
power-domain-names = "lcx", "lmx";
162
+
163
+
qcom,qmp = <&aoss_qmp>;
164
+
qcom,smem-states = <&smp2p_adsp_out 0>;
165
+
qcom,smem-state-names = "stop";
166
+
167
+
glink-edge {
168
+
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
169
+
IPCC_MPROC_SIGNAL_GLINK_QMP
170
+
IRQ_TYPE_EDGE_RISING>;
171
+
mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
172
+
173
+
label = "lpass";
174
+
qcom,remote-pid = <2>;
175
+
176
+
/* ... */
177
+
};
178
+
};
-177
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt
-177
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt
···
1
-
Qualcomm WCNSS Peripheral Image Loader
2
-
3
-
This document defines the binding for a component that loads and boots firmware
4
-
on the Qualcomm WCNSS core.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be one of:
10
-
"qcom,riva-pil",
11
-
"qcom,pronto-v1-pil",
12
-
"qcom,pronto-v2-pil"
13
-
14
-
- reg:
15
-
Usage: required
16
-
Value type: <prop-encoded-array>
17
-
Definition: must specify the base address and size of the CCU, DXE and
18
-
PMU register blocks
19
-
20
-
- reg-names:
21
-
Usage: required
22
-
Value type: <stringlist>
23
-
Definition: must be "ccu", "dxe", "pmu"
24
-
25
-
- interrupts-extended:
26
-
Usage: required
27
-
Value type: <prop-encoded-array>
28
-
Definition: must list the watchdog and fatal IRQs and may specify the
29
-
ready, handover and stop-ack IRQs
30
-
31
-
- interrupt-names:
32
-
Usage: required
33
-
Value type: <stringlist>
34
-
Definition: should be "wdog", "fatal", optionally followed by "ready",
35
-
"handover", "stop-ack"
36
-
37
-
- firmware-name:
38
-
Usage: optional
39
-
Value type: <string>
40
-
Definition: must list the relative firmware image path for the
41
-
WCNSS core. Defaults to "wcnss.mdt".
42
-
43
-
- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil)
44
-
- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil)
45
-
- vddpx-supply:
46
-
Usage: required
47
-
Value type: <phandle>
48
-
Definition: reference to the regulators to be held on behalf of the
49
-
booting of the WCNSS core
50
-
51
-
- power-domains:
52
-
Usage: required (for qcom,pronto-v1/2-pil)
53
-
Value type: <phandle>
54
-
Definition: reference to the power domains to be held on behalf of the
55
-
booting of the WCNSS core
56
-
57
-
- power-domain-names:
58
-
Usage: required (for qcom,pronto-v1/2-pil)
59
-
Value type: <stringlist>
60
-
Definition: must be "cx", "mx"
61
-
62
-
- qcom,smem-states:
63
-
Usage: optional
64
-
Value type: <prop-encoded-array>
65
-
Definition: reference to the SMEM state used to indicate to WCNSS that
66
-
it should shut down
67
-
68
-
- qcom,smem-state-names:
69
-
Usage: optional
70
-
Value type: <stringlist>
71
-
Definition: should be "stop"
72
-
73
-
- memory-region:
74
-
Usage: required
75
-
Value type: <prop-encoded-array>
76
-
Definition: reference to reserved-memory node for the remote processor
77
-
see ../reserved-memory/reserved-memory.txt
78
-
79
-
= SUBNODES
80
-
A required subnode of the WCNSS PIL is used to describe the attached rf module
81
-
and its resource dependencies. It is described by the following properties:
82
-
83
-
- compatible:
84
-
Usage: required
85
-
Value type: <string>
86
-
Definition: must be one of:
87
-
"qcom,wcn3620",
88
-
"qcom,wcn3660",
89
-
"qcom,wcn3660b",
90
-
"qcom,wcn3680"
91
-
92
-
- clocks:
93
-
Usage: required
94
-
Value type: <prop-encoded-array>
95
-
Definition: should specify the xo clock and optionally the rf clock
96
-
97
-
- clock-names:
98
-
Usage: required
99
-
Value type: <stringlist>
100
-
Definition: should be "xo", optionally followed by "rf"
101
-
102
-
- vddxo-supply:
103
-
- vddrfa-supply:
104
-
- vddpa-supply:
105
-
- vdddig-supply:
106
-
Usage: required
107
-
Value type: <phandle>
108
-
Definition: reference to the regulators to be held on behalf of the
109
-
booting of the WCNSS core
110
-
111
-
112
-
The wcnss node can also have an subnode named "smd-edge" that describes the SMD
113
-
edge, channels and devices related to the WCNSS.
114
-
See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge.
115
-
116
-
= EXAMPLE
117
-
The following example describes the resources needed to boot control the WCNSS,
118
-
with attached WCN3680, as it is commonly found on MSM8974 boards.
119
-
120
-
pronto@fb204000 {
121
-
compatible = "qcom,pronto-v2-pil";
122
-
reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
123
-
reg-names = "ccu", "dxe", "pmu";
124
-
125
-
interrupts-extended = <&intc 0 149 1>,
126
-
<&wcnss_smp2p_slave 0 0>,
127
-
<&wcnss_smp2p_slave 1 0>,
128
-
<&wcnss_smp2p_slave 2 0>,
129
-
<&wcnss_smp2p_slave 3 0>;
130
-
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
131
-
132
-
power-domains = <&rpmpd MSM8974_VDDCX>, <&rpmpd MSM8974_VDDMX>;
133
-
power-domain-names = "cx", "mx";
134
-
135
-
vddpx-supply = <&pm8941_s3>;
136
-
137
-
qcom,smem-states = <&wcnss_smp2p_out 0>;
138
-
qcom,smem-state-names = "stop";
139
-
140
-
memory-region = <&wcnss_region>;
141
-
142
-
pinctrl-names = "default";
143
-
pinctrl-0 = <&wcnss_pin_a>;
144
-
145
-
iris {
146
-
compatible = "qcom,wcn3680";
147
-
148
-
clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>;
149
-
clock-names = "xo", "rf";
150
-
151
-
vddxo-supply = <&pm8941_l6>;
152
-
vddrfa-supply = <&pm8941_l11>;
153
-
vddpa-supply = <&pm8941_l19>;
154
-
vdddig-supply = <&pm8941_s3>;
155
-
};
156
-
157
-
smd-edge {
158
-
interrupts = <0 142 1>;
159
-
160
-
qcom,ipc = <&apcs 8 17>;
161
-
qcom,smd-edge = <6>;
162
-
qcom,remote-pid = <4>;
163
-
164
-
label = "pronto";
165
-
166
-
wcnss {
167
-
compatible = "qcom,wcnss";
168
-
qcom,smd-channels = "WCNSS_CTRL";
169
-
170
-
qcom,mmio = <&pronto>;
171
-
172
-
bt {
173
-
compatible = "qcom,wcnss-bt";
174
-
};
175
-
};
176
-
};
177
-
};
+294
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml
+294
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm WCNSS Peripheral Image Loader
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
12
+
description:
13
+
This document defines the binding for a component that loads and boots
14
+
firmware on the Qualcomm WCNSS core.
15
+
16
+
properties:
17
+
compatible:
18
+
description:
19
+
Append "qcom,pronto" if the device is actually pronto, and not riva
20
+
oneOf:
21
+
- items:
22
+
- enum:
23
+
- qcom,pronto-v1-pil
24
+
- qcom,pronto-v2-pil
25
+
- qcom,pronto-v3-pil
26
+
- const: qcom,pronto
27
+
- const: qcom,riva-pil
28
+
29
+
reg:
30
+
maxItems: 3
31
+
description:
32
+
The base address and size of the CCU, DXE and PMU register blocks
33
+
34
+
reg-names:
35
+
items:
36
+
- const: ccu
37
+
- const: dxe
38
+
- const: pmu
39
+
40
+
interrupts:
41
+
minItems: 2
42
+
maxItems: 5
43
+
44
+
interrupt-names:
45
+
minItems: 2
46
+
items:
47
+
- const: wdog
48
+
- const: fatal
49
+
- const: ready
50
+
- const: handover
51
+
- const: stop-ack
52
+
53
+
firmware-name:
54
+
$ref: /schemas/types.yaml#/definitions/string
55
+
description:
56
+
Relative firmware image path for the WCNSS core. Defaults to
57
+
"wcnss.mdt".
58
+
59
+
vddpx-supply:
60
+
description:
61
+
PX regulator to be held on behalf of the booting of the WCNSS core
62
+
63
+
vddmx-supply:
64
+
description:
65
+
MX regulator to be held on behalf of the booting of the WCNSS core.
66
+
67
+
vddcx-supply:
68
+
description:
69
+
CX regulator to be held on behalf of the booting of the WCNSS core.
70
+
71
+
power-domains:
72
+
maxItems: 2
73
+
74
+
power-domain-names:
75
+
items:
76
+
- const: cx
77
+
- const: mx
78
+
79
+
qcom,smem-states:
80
+
$ref: /schemas/types.yaml#/definitions/phandle-array
81
+
description:
82
+
States used by the AP to signal the WCNSS core that it should shutdown
83
+
items:
84
+
- description: Stop the modem
85
+
86
+
qcom,smem-state-names:
87
+
description: The names of the state bits used for SMP2P output
88
+
items:
89
+
- const: stop
90
+
91
+
memory-region:
92
+
maxItems: 1
93
+
description: reserved-memory for the WCNSS core
94
+
95
+
smd-edge:
96
+
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
97
+
description:
98
+
Qualcomm Shared Memory subnode which represents communication edge,
99
+
channels and devices related to the ADSP.
100
+
101
+
iris:
102
+
type: object
103
+
description:
104
+
The iris subnode of the WCNSS PIL is used to describe the attached RF module
105
+
and its resource dependencies.
106
+
107
+
properties:
108
+
compatible:
109
+
enum:
110
+
- qcom,wcn3620
111
+
- qcom,wcn3660
112
+
- qcom,wcn3660b
113
+
- qcom,wcn3680
114
+
115
+
clocks:
116
+
minItems: 1
117
+
items:
118
+
- description: XO clock
119
+
- description: RF clock
120
+
121
+
clock-names:
122
+
minItems: 1
123
+
items:
124
+
- const: xo
125
+
- const: rf
126
+
127
+
vddxo-supply:
128
+
description:
129
+
Reference to the regulator to be held on behalf of the booting WCNSS
130
+
core
131
+
132
+
vddrfa-supply:
133
+
description:
134
+
Reference to the regulator to be held on behalf of the booting WCNSS
135
+
core
136
+
137
+
vddpa-supply:
138
+
description:
139
+
Reference to the regulator to be held on behalf of the booting WCNSS
140
+
core
141
+
142
+
vdddig-supply:
143
+
description:
144
+
Reference to the regulator to be held on behalf of the booting WCNSS
145
+
core
146
+
147
+
required:
148
+
- compatible
149
+
- clocks
150
+
- clock-names
151
+
- vddxo-supply
152
+
- vddrfa-supply
153
+
- vddpa-supply
154
+
- vdddig-supply
155
+
156
+
additionalProperties: false
157
+
158
+
required:
159
+
- compatible
160
+
- reg
161
+
- reg-names
162
+
- interrupts
163
+
- interrupt-names
164
+
- iris
165
+
- vddpx-supply
166
+
- memory-region
167
+
- smd-edge
168
+
169
+
additionalProperties: false
170
+
171
+
allOf:
172
+
- if:
173
+
properties:
174
+
compatible:
175
+
contains:
176
+
const: qcom,riva-pil
177
+
then:
178
+
required:
179
+
- vddcx-supply
180
+
- vddmx-supply
181
+
182
+
- if:
183
+
properties:
184
+
compatible:
185
+
contains:
186
+
enum:
187
+
- qcom,pronto-v1-pil
188
+
- qcom,pronto-v2-pil
189
+
then:
190
+
properties:
191
+
vddmx-supply:
192
+
deprecated: true
193
+
description: Deprecated for qcom,pronto-v1/2-pil
194
+
195
+
vddcx-supply:
196
+
deprecated: true
197
+
description: Deprecated for qcom,pronto-v1/2-pil
198
+
199
+
oneOf:
200
+
- required:
201
+
- power-domains
202
+
- power-domain-names
203
+
- required:
204
+
- vddmx-supply
205
+
- vddcx-supply
206
+
207
+
- if:
208
+
properties:
209
+
compatible:
210
+
contains:
211
+
enum:
212
+
- qcom,pronto-v3-pil
213
+
then:
214
+
properties:
215
+
vddmx-supply: false
216
+
vddcx-supply: false
217
+
218
+
required:
219
+
- power-domains
220
+
- power-domain-names
221
+
222
+
examples:
223
+
- |
224
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
225
+
#include <dt-bindings/clock/qcom,rpmcc.h>
226
+
#include <dt-bindings/power/qcom-rpmpd.h>
227
+
pronto@a21b000 {
228
+
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
229
+
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
230
+
reg-names = "ccu", "dxe", "pmu";
231
+
232
+
interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
233
+
<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
234
+
<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
235
+
<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
236
+
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
237
+
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
238
+
239
+
power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>;
240
+
power-domain-names = "cx", "mx";
241
+
242
+
vddpx-supply = <&pm8916_l7>;
243
+
244
+
qcom,smem-states = <&wcnss_smp2p_out 0>;
245
+
qcom,smem-state-names = "stop";
246
+
247
+
memory-region = <&wcnss_region>;
248
+
249
+
pinctrl-names = "default";
250
+
pinctrl-0 = <&wcnss_pin_a>;
251
+
252
+
iris {
253
+
compatible = "qcom,wcn3620";
254
+
vddxo-supply = <&pm8916_l7>;
255
+
vddrfa-supply = <&pm8916_s3>;
256
+
vddpa-supply = <&pm8916_l9>;
257
+
vdddig-supply = <&pm8916_l5>;
258
+
259
+
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
260
+
clock-names = "xo";
261
+
};
262
+
263
+
smd-edge {
264
+
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
265
+
266
+
qcom,ipc = <&apcs 8 17>;
267
+
qcom,smd-edge = <6>;
268
+
qcom,remote-pid = <4>;
269
+
270
+
label = "pronto";
271
+
272
+
wcnss_ctrl: wcnss {
273
+
compatible = "qcom,wcnss";
274
+
qcom,smd-channels = "WCNSS_CTRL";
275
+
276
+
qcom,mmio = <&pronto>;
277
+
278
+
bluetooth {
279
+
compatible = "qcom,wcnss-bt";
280
+
};
281
+
282
+
wifi {
283
+
compatible = "qcom,wcnss-wlan";
284
+
285
+
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
286
+
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
287
+
interrupt-names = "tx", "rx";
288
+
289
+
qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
290
+
qcom,smem-state-names = "tx-enable", "tx-rings-empty";
291
+
};
292
+
};
293
+
};
294
+
};
+3
Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
+3
Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
···
31
31
properties:
32
32
compatible:
33
33
enum:
34
+
- ti,am62a-c7xv-dsp
34
35
- ti,j721e-c66-dsp
35
36
- ti,j721e-c71-dsp
36
37
- ti,j721s2-c71-dsp
37
38
description:
39
+
Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs
38
40
Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
39
41
Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
40
42
Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs
···
111
109
properties:
112
110
compatible:
113
111
enum:
112
+
- ti,am62a-c7xv-dsp
114
113
- ti,j721e-c71-dsp
115
114
- ti,j721s2-c71-dsp
116
115
then:
+60
Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml
+60
Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Common TI PRU Consumer Binding
8
+
9
+
maintainers:
10
+
- Suman Anna <s-anna@ti.com>
11
+
12
+
description: |
13
+
A PRU application/consumer/user node typically uses one or more PRU device
14
+
nodes to implement a PRU application/functionality. Each application/client
15
+
node would need a reference to at least a PRU node, and optionally define
16
+
some properties needed for hardware/firmware configuration. The below
17
+
properties are a list of common properties supported by the PRU remoteproc
18
+
infrastructure.
19
+
20
+
The application nodes shall define their own bindings like regular platform
21
+
devices, so below are in addition to each node's bindings.
22
+
23
+
properties:
24
+
ti,prus:
25
+
$ref: /schemas/types.yaml#/definitions/phandle-array
26
+
description: phandles to the PRU, RTU or Tx_PRU nodes used
27
+
minItems: 1
28
+
maxItems: 6
29
+
items:
30
+
maxItems: 1
31
+
32
+
firmware-name:
33
+
$ref: /schemas/types.yaml#/definitions/string-array
34
+
minItems: 1
35
+
maxItems: 6
36
+
description: |
37
+
firmwares for the PRU cores, the default firmware for the core from
38
+
the PRU node will be used if not provided. The firmware names should
39
+
correspond to the PRU cores listed in the 'ti,prus' property
40
+
41
+
ti,pruss-gp-mux-sel:
42
+
$ref: /schemas/types.yaml#/definitions/uint32-array
43
+
minItems: 1
44
+
maxItems: 6
45
+
items:
46
+
enum: [0, 1, 2, 3, 4]
47
+
description: |
48
+
array of values for the GP_MUX_SEL under PRUSS_GPCFG register for a PRU.
49
+
This selects the internal muxing scheme for the PRU instance. Values
50
+
should correspond to the PRU cores listed in the 'ti,prus' property. The
51
+
GP_MUX_SEL setting is a per-slice setting (one setting for PRU0, RTU0,
52
+
and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
53
+
same slice in the associative array. If the array size is smaller than
54
+
the size of 'ti,prus' property, the default out-of-reset value (0) for the
55
+
PRU core is used.
56
+
57
+
required:
58
+
- ti,prus
59
+
60
+
additionalProperties: true
+1
drivers/remoteproc/mtk_scp.c
+1
drivers/remoteproc/mtk_scp.c
+16
-16
drivers/remoteproc/mtk_scp_ipi.c
+16
-16
drivers/remoteproc/mtk_scp_ipi.c
···
6
6
#include <linux/clk.h>
7
7
#include <linux/err.h>
8
8
#include <linux/io.h>
9
+
#include <linux/iopoll.h>
9
10
#include <linux/kernel.h>
10
11
#include <linux/module.h>
11
12
#include <linux/platform_device.h>
13
+
#include <linux/time64.h>
12
14
#include <linux/remoteproc/mtk_scp.h>
13
15
14
16
#include "mtk_common.h"
17
+
18
+
#define SCP_TIMEOUT_US (2000 * USEC_PER_MSEC)
15
19
16
20
/**
17
21
* scp_ipi_register() - register an ipi function
···
160
156
unsigned int wait)
161
157
{
162
158
struct mtk_share_obj __iomem *send_obj = scp->send_buf;
163
-
unsigned long timeout;
159
+
u32 val;
164
160
int ret;
165
161
166
162
if (WARN_ON(id <= SCP_IPI_INIT) || WARN_ON(id >= SCP_IPI_MAX) ||
···
168
164
WARN_ON(len > sizeof(send_obj->share_buf)) || WARN_ON(!buf))
169
165
return -EINVAL;
170
166
171
-
mutex_lock(&scp->send_lock);
172
-
173
167
ret = clk_prepare_enable(scp->clk);
174
168
if (ret) {
175
169
dev_err(scp->dev, "failed to enable clock\n");
176
-
goto unlock_mutex;
170
+
return ret;
177
171
}
178
172
173
+
mutex_lock(&scp->send_lock);
174
+
179
175
/* Wait until SCP receives the last command */
180
-
timeout = jiffies + msecs_to_jiffies(2000);
181
-
do {
182
-
if (time_after(jiffies, timeout)) {
183
-
dev_err(scp->dev, "%s: IPI timeout!\n", __func__);
184
-
ret = -ETIMEDOUT;
185
-
goto clock_disable;
186
-
}
187
-
} while (readl(scp->reg_base + scp->data->host_to_scp_reg));
176
+
ret = readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_reg,
177
+
val, !val, 0, SCP_TIMEOUT_US);
178
+
if (ret) {
179
+
dev_err(scp->dev, "%s: IPI timeout!\n", __func__);
180
+
goto unlock_mutex;
181
+
}
188
182
189
183
scp_memcpy_aligned(send_obj->share_buf, buf, len);
190
184
···
196
194
197
195
if (wait) {
198
196
/* wait for SCP's ACK */
199
-
timeout = msecs_to_jiffies(wait);
200
197
ret = wait_event_timeout(scp->ack_wq,
201
198
scp->ipi_id_ack[id],
202
-
timeout);
199
+
msecs_to_jiffies(wait));
203
200
scp->ipi_id_ack[id] = false;
204
201
if (WARN(!ret, "scp ipi %d ack time out !", id))
205
202
ret = -EIO;
···
206
205
ret = 0;
207
206
}
208
207
209
-
clock_disable:
210
-
clk_disable_unprepare(scp->clk);
211
208
unlock_mutex:
212
209
mutex_unlock(&scp->send_lock);
210
+
clk_disable_unprepare(scp->clk);
213
211
214
212
return ret;
215
213
}
+225
-5
drivers/remoteproc/pru_rproc.c
+225
-5
drivers/remoteproc/pru_rproc.c
···
2
2
/*
3
3
* PRU-ICSS remoteproc driver for various TI SoCs
4
4
*
5
-
* Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/
5
+
* Copyright (C) 2014-2022 Texas Instruments Incorporated - https://www.ti.com/
6
6
*
7
7
* Author(s):
8
8
* Suman Anna <s-anna@ti.com>
9
9
* Andrew F. Davis <afd@ti.com>
10
10
* Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
11
+
* Puranjay Mohan <p-mohan@ti.com>
12
+
* Md Danish Anwar <danishanwar@ti.com>
11
13
*/
12
14
13
15
#include <linux/bitops.h>
···
18
16
#include <linux/module.h>
19
17
#include <linux/of_device.h>
20
18
#include <linux/of_irq.h>
19
+
#include <linux/remoteproc/pruss.h>
21
20
#include <linux/pruss_driver.h>
22
21
#include <linux/remoteproc.h>
23
22
···
114
111
* @rproc: remoteproc pointer for this PRU core
115
112
* @data: PRU core specific data
116
113
* @mem_regions: data for each of the PRU memory regions
114
+
* @client_np: client device node
115
+
* @lock: mutex to protect client usage
117
116
* @fw_name: name of firmware image used during loading
118
117
* @mapped_irq: virtual interrupt numbers of created fw specific mapping
119
118
* @pru_interrupt_map: pointer to interrupt mapping description (firmware)
120
119
* @pru_interrupt_map_sz: pru_interrupt_map size
120
+
* @rmw_lock: lock for read, modify, write operations on registers
121
121
* @dbg_single_step: debug state variable to set PRU into single step mode
122
122
* @dbg_continuous: debug state variable to restore PRU execution mode
123
123
* @evt_count: number of mapped events
···
132
126
struct rproc *rproc;
133
127
const struct pru_private_data *data;
134
128
struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
129
+
struct device_node *client_np;
130
+
struct mutex lock;
135
131
const char *fw_name;
136
132
unsigned int *mapped_irq;
137
133
struct pru_irq_rsc *pru_interrupt_map;
138
134
size_t pru_interrupt_map_sz;
135
+
spinlock_t rmw_lock;
139
136
u32 dbg_single_step;
140
137
u32 dbg_continuous;
141
138
u8 evt_count;
···
154
145
{
155
146
writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
156
147
}
148
+
149
+
static inline
150
+
void pru_control_set_reg(struct pru_rproc *pru, unsigned int reg,
151
+
u32 mask, u32 set)
152
+
{
153
+
u32 val;
154
+
unsigned long flags;
155
+
156
+
spin_lock_irqsave(&pru->rmw_lock, flags);
157
+
158
+
val = pru_control_read_reg(pru, reg);
159
+
val &= ~mask;
160
+
val |= (set & mask);
161
+
pru_control_write_reg(pru, reg, val);
162
+
163
+
spin_unlock_irqrestore(&pru->rmw_lock, flags);
164
+
}
165
+
166
+
/**
167
+
* pru_rproc_set_firmware() - set firmware for a PRU core
168
+
* @rproc: the rproc instance of the PRU
169
+
* @fw_name: the new firmware name, or NULL if default is desired
170
+
*
171
+
* Return: 0 on success, or errno in error case.
172
+
*/
173
+
static int pru_rproc_set_firmware(struct rproc *rproc, const char *fw_name)
174
+
{
175
+
struct pru_rproc *pru = rproc->priv;
176
+
177
+
if (!fw_name)
178
+
fw_name = pru->fw_name;
179
+
180
+
return rproc_set_firmware(rproc, fw_name);
181
+
}
182
+
183
+
static struct rproc *__pru_rproc_get(struct device_node *np, int index)
184
+
{
185
+
struct rproc *rproc;
186
+
phandle rproc_phandle;
187
+
int ret;
188
+
189
+
ret = of_property_read_u32_index(np, "ti,prus", index, &rproc_phandle);
190
+
if (ret)
191
+
return ERR_PTR(ret);
192
+
193
+
rproc = rproc_get_by_phandle(rproc_phandle);
194
+
if (!rproc) {
195
+
ret = -EPROBE_DEFER;
196
+
return ERR_PTR(ret);
197
+
}
198
+
199
+
/* make sure it is PRU rproc */
200
+
if (!is_pru_rproc(rproc->dev.parent)) {
201
+
rproc_put(rproc);
202
+
return ERR_PTR(-ENODEV);
203
+
}
204
+
205
+
return rproc;
206
+
}
207
+
208
+
/**
209
+
* pru_rproc_get() - get the PRU rproc instance from a device node
210
+
* @np: the user/client device node
211
+
* @index: index to use for the ti,prus property
212
+
* @pru_id: optional pointer to return the PRU remoteproc processor id
213
+
*
214
+
* This function looks through a client device node's "ti,prus" property at
215
+
* index @index and returns the rproc handle for a valid PRU remote processor if
216
+
* found. The function allows only one user to own the PRU rproc resource at a
217
+
* time. Caller must call pru_rproc_put() when done with using the rproc, not
218
+
* required if the function returns a failure.
219
+
*
220
+
* When optional @pru_id pointer is passed the PRU remoteproc processor id is
221
+
* returned.
222
+
*
223
+
* Return: rproc handle on success, and an ERR_PTR on failure using one
224
+
* of the following error values
225
+
* -ENODEV if device is not found
226
+
* -EBUSY if PRU is already acquired by anyone
227
+
* -EPROBE_DEFER is PRU device is not probed yet
228
+
*/
229
+
struct rproc *pru_rproc_get(struct device_node *np, int index,
230
+
enum pruss_pru_id *pru_id)
231
+
{
232
+
struct rproc *rproc;
233
+
struct pru_rproc *pru;
234
+
struct device *dev;
235
+
const char *fw_name;
236
+
int ret;
237
+
238
+
rproc = __pru_rproc_get(np, index);
239
+
if (IS_ERR(rproc))
240
+
return rproc;
241
+
242
+
pru = rproc->priv;
243
+
dev = &rproc->dev;
244
+
245
+
mutex_lock(&pru->lock);
246
+
247
+
if (pru->client_np) {
248
+
mutex_unlock(&pru->lock);
249
+
ret = -EBUSY;
250
+
goto err_no_rproc_handle;
251
+
}
252
+
253
+
pru->client_np = np;
254
+
rproc->sysfs_read_only = true;
255
+
256
+
mutex_unlock(&pru->lock);
257
+
258
+
if (pru_id)
259
+
*pru_id = pru->id;
260
+
261
+
ret = of_property_read_string_index(np, "firmware-name", index,
262
+
&fw_name);
263
+
if (!ret) {
264
+
ret = pru_rproc_set_firmware(rproc, fw_name);
265
+
if (ret) {
266
+
dev_err(dev, "failed to set firmware: %d\n", ret);
267
+
goto err;
268
+
}
269
+
}
270
+
271
+
return rproc;
272
+
273
+
err_no_rproc_handle:
274
+
rproc_put(rproc);
275
+
return ERR_PTR(ret);
276
+
277
+
err:
278
+
pru_rproc_put(rproc);
279
+
return ERR_PTR(ret);
280
+
}
281
+
EXPORT_SYMBOL_GPL(pru_rproc_get);
282
+
283
+
/**
284
+
* pru_rproc_put() - release the PRU rproc resource
285
+
* @rproc: the rproc resource to release
286
+
*
287
+
* Releases the PRU rproc resource and makes it available to other
288
+
* users.
289
+
*/
290
+
void pru_rproc_put(struct rproc *rproc)
291
+
{
292
+
struct pru_rproc *pru;
293
+
294
+
if (IS_ERR_OR_NULL(rproc) || !is_pru_rproc(rproc->dev.parent))
295
+
return;
296
+
297
+
pru = rproc->priv;
298
+
299
+
pru_rproc_set_firmware(rproc, NULL);
300
+
301
+
mutex_lock(&pru->lock);
302
+
303
+
if (!pru->client_np) {
304
+
mutex_unlock(&pru->lock);
305
+
return;
306
+
}
307
+
308
+
pru->client_np = NULL;
309
+
rproc->sysfs_read_only = false;
310
+
mutex_unlock(&pru->lock);
311
+
312
+
rproc_put(rproc);
313
+
}
314
+
EXPORT_SYMBOL_GPL(pru_rproc_put);
315
+
316
+
/**
317
+
* pru_rproc_set_ctable() - set the constant table index for the PRU
318
+
* @rproc: the rproc instance of the PRU
319
+
* @c: constant table index to set
320
+
* @addr: physical address to set it to
321
+
*
322
+
* Return: 0 on success, or errno in error case.
323
+
*/
324
+
int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr)
325
+
{
326
+
struct pru_rproc *pru = rproc->priv;
327
+
unsigned int reg;
328
+
u32 mask, set;
329
+
u16 idx;
330
+
u16 idx_mask;
331
+
332
+
if (IS_ERR_OR_NULL(rproc))
333
+
return -EINVAL;
334
+
335
+
if (!rproc->dev.parent || !is_pru_rproc(rproc->dev.parent))
336
+
return -ENODEV;
337
+
338
+
/* pointer is 16 bit and index is 8-bit so mask out the rest */
339
+
idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF;
340
+
341
+
/* ctable uses bit 8 and upwards only */
342
+
idx = (addr >> 8) & idx_mask;
343
+
344
+
/* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */
345
+
reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1);
346
+
mask = idx_mask << (16 * (c & 1));
347
+
set = idx << (16 * (c & 1));
348
+
349
+
pru_control_set_reg(pru, reg, mask, set);
350
+
351
+
return 0;
352
+
}
353
+
EXPORT_SYMBOL_GPL(pru_rproc_set_ctable);
157
354
158
355
static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg)
159
356
{
···
653
438
dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0];
654
439
dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1];
655
440
/* PRU1 has its local RAM addresses reversed */
656
-
if (pru->id == 1)
441
+
if (pru->id == PRUSS_PRU1)
657
442
swap(dram0, dram1);
658
443
shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2];
659
444
···
962
747
case RTU0_IRAM_ADDR_MASK:
963
748
fallthrough;
964
749
case PRU0_IRAM_ADDR_MASK:
965
-
pru->id = 0;
750
+
pru->id = PRUSS_PRU0;
966
751
break;
967
752
case TX_PRU1_IRAM_ADDR_MASK:
968
753
fallthrough;
969
754
case RTU1_IRAM_ADDR_MASK:
970
755
fallthrough;
971
756
case PRU1_IRAM_ADDR_MASK:
972
-
pru->id = 1;
757
+
pru->id = PRUSS_PRU1;
973
758
break;
974
759
default:
975
760
ret = -EINVAL;
···
1031
816
pru->pruss = platform_get_drvdata(ppdev);
1032
817
pru->rproc = rproc;
1033
818
pru->fw_name = fw_name;
819
+
pru->client_np = NULL;
820
+
spin_lock_init(&pru->rmw_lock);
821
+
mutex_init(&pru->lock);
1034
822
1035
823
for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
1036
824
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
···
1122
904
1123
905
static struct platform_driver pru_rproc_driver = {
1124
906
.driver = {
1125
-
.name = "pru-rproc",
907
+
.name = PRU_RPROC_DRVNAME,
1126
908
.of_match_table = pru_rproc_match,
1127
909
.suppress_bind_attrs = true,
1128
910
},
···
1134
916
MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
1135
917
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
1136
918
MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
919
+
MODULE_AUTHOR("Puranjay Mohan <p-mohan@ti.com>");
920
+
MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>");
1137
921
MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver");
1138
922
MODULE_LICENSE("GPL v2");
+12
-7
drivers/remoteproc/qcom_common.c
+12
-7
drivers/remoteproc/qcom_common.c
···
101
101
}
102
102
}
103
103
104
-
static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsystem *subsystem)
104
+
static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsystem *subsystem,
105
+
void (*rproc_dumpfn_t)(struct rproc *rproc, struct rproc_dump_segment *segment,
106
+
void *dest, size_t offset, size_t size))
105
107
{
106
108
struct minidump_region __iomem *ptr;
107
109
struct minidump_region region;
···
125
123
126
124
for (i = 0; i < seg_cnt; i++) {
127
125
memcpy_fromio(®ion, ptr + i, sizeof(region));
128
-
if (region.valid == MD_REGION_VALID) {
129
-
name = kstrdup(region.name, GFP_KERNEL);
126
+
if (le32_to_cpu(region.valid) == MD_REGION_VALID) {
127
+
name = kstrndup(region.name, MAX_REGION_NAME_LENGTH - 1, GFP_KERNEL);
130
128
if (!name) {
131
129
iounmap(ptr);
132
130
return -ENOMEM;
133
131
}
134
132
da = le64_to_cpu(region.address);
135
-
size = le32_to_cpu(region.size);
136
-
rproc_coredump_add_custom_segment(rproc, da, size, NULL, name);
133
+
size = le64_to_cpu(region.size);
134
+
rproc_coredump_add_custom_segment(rproc, da, size, rproc_dumpfn_t, name);
137
135
}
138
136
}
139
137
···
141
139
return 0;
142
140
}
143
141
144
-
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id)
142
+
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id,
143
+
void (*rproc_dumpfn_t)(struct rproc *rproc,
144
+
struct rproc_dump_segment *segment, void *dest, size_t offset,
145
+
size_t size))
145
146
{
146
147
int ret;
147
148
struct minidump_subsystem *subsystem;
···
174
169
return;
175
170
}
176
171
177
-
ret = qcom_add_minidump_segments(rproc, subsystem);
172
+
ret = qcom_add_minidump_segments(rproc, subsystem, rproc_dumpfn_t);
178
173
if (ret) {
179
174
dev_err(&rproc->dev, "Failed with error: %d while adding minidump entries\n", ret);
180
175
goto clean_minidump;
+4
-1
drivers/remoteproc/qcom_common.h
+4
-1
drivers/remoteproc/qcom_common.h
···
34
34
struct qcom_ssr_subsystem *info;
35
35
};
36
36
37
-
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id);
37
+
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id,
38
+
void (*rproc_dumpfn_t)(struct rproc *rproc,
39
+
struct rproc_dump_segment *segment, void *dest, size_t offset,
40
+
size_t size));
38
41
39
42
void qcom_add_glink_subdev(struct rproc *rproc, struct qcom_rproc_glink *glink,
40
43
const char *ssr_name);
+2
-2
drivers/remoteproc/qcom_q6v5.c
+2
-2
drivers/remoteproc/qcom_q6v5.c
···
205
205
206
206
q6v5->running = false;
207
207
208
-
/* Don't perform SMP2P dance if sysmon already shut down the remote */
209
-
if (qcom_sysmon_shutdown_acked(sysmon))
208
+
/* Don't perform SMP2P dance if remote isn't running */
209
+
if (q6v5->rproc->state != RPROC_RUNNING || qcom_sysmon_shutdown_acked(sysmon))
210
210
return 0;
211
211
212
212
qcom_smem_state_update_bits(q6v5->state,
+121
-4
drivers/remoteproc/qcom_q6v5_adsp.c
+121
-4
drivers/remoteproc/qcom_q6v5_adsp.c
···
9
9
#include <linux/firmware.h>
10
10
#include <linux/interrupt.h>
11
11
#include <linux/io.h>
12
+
#include <linux/iommu.h>
12
13
#include <linux/iopoll.h>
13
14
#include <linux/kernel.h>
14
15
#include <linux/mfd/syscon.h>
···
49
48
#define LPASS_PWR_ON_REG 0x10
50
49
#define LPASS_HALTREQ_REG 0x0
51
50
51
+
#define SID_MASK_DEFAULT 0xF
52
+
52
53
#define QDSP6SS_XO_CBCR 0x38
53
54
#define QDSP6SS_CORE_CBCR 0x20
54
55
#define QDSP6SS_SLEEP_CBCR 0x3c
55
56
56
57
#define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3
58
+
59
+
#define LPASS_BOOT_CORE_START BIT(0)
60
+
#define LPASS_BOOT_CMD_START BIT(0)
61
+
#define LPASS_EFUSE_Q6SS_EVB_SEL 0x0
57
62
58
63
struct adsp_pil_data {
59
64
int crash_reason_smem;
···
69
62
const char *sysmon_name;
70
63
int ssctl_id;
71
64
bool is_wpss;
65
+
bool has_iommu;
72
66
bool auto_boot;
73
67
74
68
const char **clk_ids;
···
90
82
struct clk_bulk_data *clks;
91
83
92
84
void __iomem *qdsp6ss_base;
85
+
void __iomem *lpass_efuse;
93
86
94
87
struct reset_control *pdc_sync_reset;
95
88
struct reset_control *restart;
···
108
99
phys_addr_t mem_reloc;
109
100
void *mem_region;
110
101
size_t mem_size;
102
+
bool has_iommu;
111
103
112
104
struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX];
113
105
size_t proxy_pd_count;
···
335
325
return 0;
336
326
}
337
327
328
+
static void adsp_unmap_carveout(struct rproc *rproc)
329
+
{
330
+
struct qcom_adsp *adsp = rproc->priv;
331
+
332
+
if (adsp->has_iommu)
333
+
iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size);
334
+
}
335
+
336
+
static int adsp_map_carveout(struct rproc *rproc)
337
+
{
338
+
struct qcom_adsp *adsp = rproc->priv;
339
+
struct of_phandle_args args;
340
+
long long sid;
341
+
unsigned long iova;
342
+
int ret;
343
+
344
+
if (!adsp->has_iommu)
345
+
return 0;
346
+
347
+
if (!rproc->domain)
348
+
return -EINVAL;
349
+
350
+
ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);
351
+
if (ret < 0)
352
+
return ret;
353
+
354
+
sid = args.args[0] & SID_MASK_DEFAULT;
355
+
356
+
/* Add SID configuration for ADSP Firmware to SMMU */
357
+
iova = adsp->mem_phys | (sid << 32);
358
+
359
+
ret = iommu_map(rproc->domain, iova, adsp->mem_phys,
360
+
adsp->mem_size, IOMMU_READ | IOMMU_WRITE,
361
+
GFP_KERNEL);
362
+
if (ret) {
363
+
dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
364
+
return ret;
365
+
}
366
+
367
+
return 0;
368
+
}
369
+
338
370
static int adsp_start(struct rproc *rproc)
339
371
{
340
372
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
···
387
335
if (ret)
388
336
return ret;
389
337
338
+
ret = adsp_map_carveout(rproc);
339
+
if (ret) {
340
+
dev_err(adsp->dev, "ADSP smmu mapping failed\n");
341
+
goto disable_irqs;
342
+
}
343
+
390
344
ret = clk_prepare_enable(adsp->xo);
391
345
if (ret)
392
-
goto disable_irqs;
346
+
goto adsp_smmu_unmap;
393
347
394
348
ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds,
395
349
adsp->proxy_pd_count);
···
420
362
/* Program boot address */
421
363
writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
422
364
365
+
if (adsp->lpass_efuse)
366
+
writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
367
+
423
368
/* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
424
-
writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
369
+
writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
425
370
426
371
/* Trigger boot FSM to start QDSP6 */
427
-
writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
372
+
writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
428
373
429
374
/* Wait for core to come out of reset */
430
375
ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
···
451
390
qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
452
391
disable_xo_clk:
453
392
clk_disable_unprepare(adsp->xo);
393
+
adsp_smmu_unmap:
394
+
adsp_unmap_carveout(rproc);
454
395
disable_irqs:
455
396
qcom_q6v5_unprepare(&adsp->q6v5);
456
397
···
481
418
if (ret)
482
419
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
483
420
421
+
adsp_unmap_carveout(rproc);
422
+
484
423
handover = qcom_q6v5_unprepare(&adsp->q6v5);
485
424
if (handover)
486
425
qcom_adsp_pil_handover(&adsp->q6v5);
···
502
437
return adsp->mem_region + offset;
503
438
}
504
439
440
+
static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw)
441
+
{
442
+
struct qcom_adsp *adsp = rproc->priv;
443
+
int ret;
444
+
445
+
ret = qcom_register_dump_segments(rproc, fw);
446
+
if (ret) {
447
+
dev_err(&rproc->dev, "Error in registering dump segments\n");
448
+
return ret;
449
+
}
450
+
451
+
if (adsp->has_iommu) {
452
+
ret = rproc_elf_load_rsc_table(rproc, fw);
453
+
if (ret) {
454
+
dev_err(&rproc->dev, "Error in loading resource table\n");
455
+
return ret;
456
+
}
457
+
}
458
+
return 0;
459
+
}
460
+
505
461
static unsigned long adsp_panic(struct rproc *rproc)
506
462
{
507
463
struct qcom_adsp *adsp = rproc->priv;
···
534
448
.start = adsp_start,
535
449
.stop = adsp_stop,
536
450
.da_to_va = adsp_da_to_va,
537
-
.parse_fw = qcom_register_dump_segments,
451
+
.parse_fw = adsp_parse_firmware,
538
452
.load = adsp_load,
539
453
.panic = adsp_panic,
540
454
};
···
593
507
static int adsp_init_mmio(struct qcom_adsp *adsp,
594
508
struct platform_device *pdev)
595
509
{
510
+
struct resource *efuse_region;
596
511
struct device_node *syscon;
597
512
int ret;
598
513
···
603
516
return PTR_ERR(adsp->qdsp6ss_base);
604
517
}
605
518
519
+
efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1);
520
+
if (!efuse_region) {
521
+
adsp->lpass_efuse = NULL;
522
+
dev_dbg(adsp->dev, "failed to get efuse memory region\n");
523
+
} else {
524
+
adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);
525
+
if (IS_ERR(adsp->lpass_efuse)) {
526
+
dev_err(adsp->dev, "failed to map efuse registers\n");
527
+
return PTR_ERR(adsp->lpass_efuse);
528
+
}
529
+
}
606
530
syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
607
531
if (!syscon) {
608
532
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
···
693
595
}
694
596
695
597
rproc->auto_boot = desc->auto_boot;
598
+
rproc->has_iommu = desc->has_iommu;
696
599
rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
697
600
698
601
adsp = (struct qcom_adsp *)rproc->priv;
699
602
adsp->dev = &pdev->dev;
700
603
adsp->rproc = rproc;
701
604
adsp->info_name = desc->sysmon_name;
605
+
adsp->has_iommu = desc->has_iommu;
606
+
702
607
platform_set_drvdata(pdev, adsp);
703
608
704
609
if (desc->is_wpss)
···
797
696
},
798
697
};
799
698
699
+
static const struct adsp_pil_data adsp_sc7280_resource_init = {
700
+
.crash_reason_smem = 423,
701
+
.firmware_name = "adsp.pbn",
702
+
.load_state = "adsp",
703
+
.ssr_name = "lpass",
704
+
.sysmon_name = "adsp",
705
+
.ssctl_id = 0x14,
706
+
.has_iommu = true,
707
+
.auto_boot = true,
708
+
.clk_ids = (const char*[]) {
709
+
"gcc_cfg_noc_lpass", NULL
710
+
},
711
+
.num_clks = 1,
712
+
};
713
+
800
714
static const struct adsp_pil_data cdsp_resource_init = {
801
715
.crash_reason_smem = 601,
802
716
.firmware_name = "cdsp.mdt",
···
850
734
851
735
static const struct of_device_id adsp_of_match[] = {
852
736
{ .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
737
+
{ .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
853
738
{ .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },
854
739
{ .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
855
740
{ },
+194
-65
drivers/remoteproc/qcom_q6v5_mss.c
+194
-65
drivers/remoteproc/qcom_q6v5_mss.c
···
10
10
#include <linux/clk.h>
11
11
#include <linux/delay.h>
12
12
#include <linux/devcoredump.h>
13
-
#include <linux/dma-map-ops.h>
14
13
#include <linux/dma-mapping.h>
15
14
#include <linux/interrupt.h>
16
15
#include <linux/kernel.h>
···
17
18
#include <linux/module.h>
18
19
#include <linux/of_address.h>
19
20
#include <linux/of_device.h>
21
+
#include <linux/of_reserved_mem.h>
20
22
#include <linux/platform_device.h>
21
23
#include <linux/pm_domain.h>
22
24
#include <linux/pm_runtime.h>
···
39
39
#define MPSS_CRASH_REASON_SMEM 421
40
40
41
41
#define MBA_LOG_SIZE SZ_4K
42
+
43
+
#define MPSS_PAS_ID 5
42
44
43
45
/* RMB Status Register Values */
44
46
#define RMB_PBL_SUCCESS 0x1
···
112
110
#define Q6SS_CLAMP_IO BIT(20)
113
111
#define QDSS_BHS_ON BIT(21)
114
112
#define QDSS_LDO_BYP BIT(22)
113
+
114
+
/* QDSP6v55 parameters */
115
+
#define QDSP6V55_MEM_BITS GENMASK(16, 8)
115
116
116
117
/* QDSP6v56 parameters */
117
118
#define QDSP6v56_LDO_BYP BIT(25)
···
216
211
size_t mba_size;
217
212
size_t dp_size;
218
213
214
+
phys_addr_t mdata_phys;
215
+
size_t mdata_size;
216
+
219
217
phys_addr_t mpss_phys;
220
218
phys_addr_t mpss_reloc;
221
219
size_t mpss_size;
···
242
234
};
243
235
244
236
enum {
237
+
MSS_MSM8909,
245
238
MSS_MSM8916,
239
+
MSS_MSM8953,
246
240
MSS_MSM8974,
247
241
MSS_MSM8996,
248
242
MSS_MSM8998,
···
697
687
return ret;
698
688
}
699
689
goto pbl_wait;
700
-
} else if (qproc->version == MSS_MSM8996 ||
690
+
} else if (qproc->version == MSS_MSM8909 ||
691
+
qproc->version == MSS_MSM8953 ||
692
+
qproc->version == MSS_MSM8996 ||
701
693
qproc->version == MSS_MSM8998) {
702
-
int mem_pwr_ctl;
703
694
704
-
/* Override the ACC value if required */
705
-
writel(QDSP6SS_ACC_OVERRIDE_VAL,
706
-
qproc->reg_base + QDSP6SS_STRAP_ACC);
695
+
if (qproc->version != MSS_MSM8909 &&
696
+
qproc->version != MSS_MSM8953)
697
+
/* Override the ACC value if required */
698
+
writel(QDSP6SS_ACC_OVERRIDE_VAL,
699
+
qproc->reg_base + QDSP6SS_STRAP_ACC);
707
700
708
701
/* Assert resets, stop core */
709
702
val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
···
738
725
val |= QDSP6v56_LDO_BYP;
739
726
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
740
727
741
-
/* Deassert QDSP6 compiler memory clamp */
742
-
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
743
-
val &= ~QDSP6v56_CLAMP_QMC_MEM;
744
-
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
728
+
if (qproc->version != MSS_MSM8909) {
729
+
int mem_pwr_ctl;
745
730
746
-
/* Deassert memory peripheral sleep and L2 memory standby */
747
-
val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
748
-
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
731
+
/* Deassert QDSP6 compiler memory clamp */
732
+
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
733
+
val &= ~QDSP6v56_CLAMP_QMC_MEM;
734
+
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
749
735
750
-
/* Turn on L1, L2, ETB and JU memories 1 at a time */
751
-
if (qproc->version == MSS_MSM8996) {
752
-
mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
753
-
i = 19;
736
+
/* Deassert memory peripheral sleep and L2 memory standby */
737
+
val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
738
+
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
739
+
740
+
/* Turn on L1, L2, ETB and JU memories 1 at a time */
741
+
if (qproc->version == MSS_MSM8953 ||
742
+
qproc->version == MSS_MSM8996) {
743
+
mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
744
+
i = 19;
745
+
} else {
746
+
/* MSS_MSM8998 */
747
+
mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
748
+
i = 28;
749
+
}
750
+
val = readl(qproc->reg_base + mem_pwr_ctl);
751
+
for (; i >= 0; i--) {
752
+
val |= BIT(i);
753
+
writel(val, qproc->reg_base + mem_pwr_ctl);
754
+
/*
755
+
* Read back value to ensure the write is done then
756
+
* wait for 1us for both memory peripheral and data
757
+
* array to turn on.
758
+
*/
759
+
val |= readl(qproc->reg_base + mem_pwr_ctl);
760
+
udelay(1);
761
+
}
754
762
} else {
755
-
/* MSS_MSM8998 */
756
-
mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
757
-
i = 28;
763
+
/* Turn on memories */
764
+
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
765
+
val |= Q6SS_SLP_RET_N | Q6SS_L2DATA_STBY_N |
766
+
Q6SS_ETB_SLP_NRET_N | QDSP6V55_MEM_BITS;
767
+
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
768
+
769
+
/* Turn on L2 banks 1 at a time */
770
+
for (i = 0; i <= 7; i++) {
771
+
val |= BIT(i);
772
+
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
773
+
}
758
774
}
759
-
val = readl(qproc->reg_base + mem_pwr_ctl);
760
-
for (; i >= 0; i--) {
761
-
val |= BIT(i);
762
-
writel(val, qproc->reg_base + mem_pwr_ctl);
763
-
/*
764
-
* Read back value to ensure the write is done then
765
-
* wait for 1us for both memory peripheral and data
766
-
* array to turn on.
767
-
*/
768
-
val |= readl(qproc->reg_base + mem_pwr_ctl);
769
-
udelay(1);
770
-
}
775
+
771
776
/* Remove word line clamp */
772
777
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
773
778
val &= ~QDSP6v56_CLAMP_WL;
···
964
933
static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw,
965
934
const char *fw_name)
966
935
{
967
-
unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS | DMA_ATTR_NO_KERNEL_MAPPING;
968
-
unsigned long flags = VM_DMA_COHERENT | VM_FLUSH_RESET_PERMS;
969
-
struct page **pages;
970
-
struct page *page;
936
+
unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
971
937
dma_addr_t phys;
972
938
void *metadata;
973
939
int mdata_perm;
974
940
int xferop_ret;
975
941
size_t size;
976
-
void *vaddr;
977
-
int count;
942
+
void *ptr;
978
943
int ret;
979
-
int i;
980
944
981
945
metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev);
982
946
if (IS_ERR(metadata))
983
947
return PTR_ERR(metadata);
984
948
985
-
page = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
986
-
if (!page) {
987
-
kfree(metadata);
988
-
dev_err(qproc->dev, "failed to allocate mdt buffer\n");
989
-
return -ENOMEM;
949
+
if (qproc->mdata_phys) {
950
+
if (size > qproc->mdata_size) {
951
+
ret = -EINVAL;
952
+
dev_err(qproc->dev, "metadata size outside memory range\n");
953
+
goto free_metadata;
954
+
}
955
+
956
+
phys = qproc->mdata_phys;
957
+
ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC);
958
+
if (!ptr) {
959
+
ret = -EBUSY;
960
+
dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
961
+
&qproc->mdata_phys, size);
962
+
goto free_metadata;
963
+
}
964
+
} else {
965
+
ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
966
+
if (!ptr) {
967
+
ret = -ENOMEM;
968
+
dev_err(qproc->dev, "failed to allocate mdt buffer\n");
969
+
goto free_metadata;
970
+
}
990
971
}
991
972
992
-
count = PAGE_ALIGN(size) >> PAGE_SHIFT;
993
-
pages = kmalloc_array(count, sizeof(struct page *), GFP_KERNEL);
994
-
if (!pages) {
995
-
ret = -ENOMEM;
996
-
goto free_dma_attrs;
997
-
}
973
+
memcpy(ptr, metadata, size);
998
974
999
-
for (i = 0; i < count; i++)
1000
-
pages[i] = nth_page(page, i);
1001
-
1002
-
vaddr = vmap(pages, count, flags, pgprot_dmacoherent(PAGE_KERNEL));
1003
-
kfree(pages);
1004
-
if (!vaddr) {
1005
-
dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", &phys, size);
1006
-
ret = -EBUSY;
1007
-
goto free_dma_attrs;
1008
-
}
1009
-
1010
-
memcpy(vaddr, metadata, size);
1011
-
1012
-
vunmap(vaddr);
975
+
if (qproc->mdata_phys)
976
+
memunmap(ptr);
1013
977
1014
978
/* Hypervisor mapping to access metadata by modem */
1015
979
mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
···
1034
1008
"mdt buffer not reclaimed system may become unstable\n");
1035
1009
1036
1010
free_dma_attrs:
1037
-
dma_free_attrs(qproc->dev, size, page, phys, dma_attrs);
1011
+
if (!qproc->mdata_phys)
1012
+
dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
1013
+
free_metadata:
1038
1014
kfree(metadata);
1039
1015
1040
1016
return ret < 0 ? ret : 0;
···
1369
1341
1370
1342
if (phdr->p_paddr + phdr->p_memsz > max_addr)
1371
1343
max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1344
+
}
1345
+
1346
+
if (qproc->version == MSS_MSM8953) {
1347
+
ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size);
1348
+
if (ret) {
1349
+
dev_err(qproc->dev,
1350
+
"setting up mpss memory failed: %d\n", ret);
1351
+
goto release_firmware;
1352
+
}
1372
1353
}
1373
1354
1374
1355
/*
···
1873
1836
static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1874
1837
{
1875
1838
struct device_node *child;
1839
+
struct reserved_mem *rmem;
1876
1840
struct device_node *node;
1877
1841
struct resource r;
1878
1842
int ret;
···
1919
1881
1920
1882
qproc->mpss_phys = qproc->mpss_reloc = r.start;
1921
1883
qproc->mpss_size = resource_size(&r);
1884
+
1885
+
if (!child) {
1886
+
node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2);
1887
+
} else {
1888
+
child = of_get_child_by_name(qproc->dev->of_node, "metadata");
1889
+
node = of_parse_phandle(child, "memory-region", 0);
1890
+
of_node_put(child);
1891
+
}
1892
+
1893
+
if (!node)
1894
+
return 0;
1895
+
1896
+
rmem = of_reserved_mem_lookup(node);
1897
+
if (!rmem) {
1898
+
dev_err(qproc->dev, "unable to resolve metadata region\n");
1899
+
return -EINVAL;
1900
+
}
1901
+
1902
+
qproc->mdata_phys = rmem->base;
1903
+
qproc->mdata_size = rmem->size;
1922
1904
1923
1905
return 0;
1924
1906
}
···
2298
2240
.version = MSS_MSM8996,
2299
2241
};
2300
2242
2243
+
static const struct rproc_hexagon_res msm8909_mss = {
2244
+
.hexagon_mba_image = "mba.mbn",
2245
+
.proxy_supply = (struct qcom_mss_reg_res[]) {
2246
+
{
2247
+
.supply = "pll",
2248
+
.uA = 100000,
2249
+
},
2250
+
{}
2251
+
},
2252
+
.proxy_clk_names = (char*[]){
2253
+
"xo",
2254
+
NULL
2255
+
},
2256
+
.active_clk_names = (char*[]){
2257
+
"iface",
2258
+
"bus",
2259
+
"mem",
2260
+
NULL
2261
+
},
2262
+
.proxy_pd_names = (char*[]){
2263
+
"mx",
2264
+
"cx",
2265
+
NULL
2266
+
},
2267
+
.need_mem_protection = false,
2268
+
.has_alt_reset = false,
2269
+
.has_mba_logs = false,
2270
+
.has_spare_reg = false,
2271
+
.has_qaccept_regs = false,
2272
+
.has_ext_cntl_regs = false,
2273
+
.has_vq6 = false,
2274
+
.version = MSS_MSM8909,
2275
+
};
2276
+
2301
2277
static const struct rproc_hexagon_res msm8916_mss = {
2302
2278
.hexagon_mba_image = "mba.mbn",
2303
2279
.proxy_supply = (struct qcom_mss_reg_res[]) {
···
2375
2283
.has_ext_cntl_regs = false,
2376
2284
.has_vq6 = false,
2377
2285
.version = MSS_MSM8916,
2286
+
};
2287
+
2288
+
static const struct rproc_hexagon_res msm8953_mss = {
2289
+
.hexagon_mba_image = "mba.mbn",
2290
+
.proxy_supply = (struct qcom_mss_reg_res[]) {
2291
+
{
2292
+
.supply = "pll",
2293
+
.uA = 100000,
2294
+
},
2295
+
{}
2296
+
},
2297
+
.proxy_clk_names = (char*[]){
2298
+
"xo",
2299
+
NULL
2300
+
},
2301
+
.active_clk_names = (char*[]){
2302
+
"iface",
2303
+
"bus",
2304
+
"mem",
2305
+
NULL
2306
+
},
2307
+
.proxy_pd_names = (char*[]) {
2308
+
"cx",
2309
+
"mx",
2310
+
"mss",
2311
+
NULL
2312
+
},
2313
+
.need_mem_protection = false,
2314
+
.has_alt_reset = false,
2315
+
.has_mba_logs = false,
2316
+
.has_spare_reg = false,
2317
+
.has_qaccept_regs = false,
2318
+
.has_ext_cntl_regs = false,
2319
+
.has_vq6 = false,
2320
+
.version = MSS_MSM8953,
2378
2321
};
2379
2322
2380
2323
static const struct rproc_hexagon_res msm8974_mss = {
···
2467
2340
2468
2341
static const struct of_device_id q6v5_of_match[] = {
2469
2342
{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2343
+
{ .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss},
2470
2344
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2345
+
{ .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss},
2471
2346
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2472
2347
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2473
2348
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
+286
-50
drivers/remoteproc/qcom_q6v5_pas.c
+286
-50
drivers/remoteproc/qcom_q6v5_pas.c
···
35
35
struct adsp_data {
36
36
int crash_reason_smem;
37
37
const char *firmware_name;
38
+
const char *dtb_firmware_name;
38
39
int pas_id;
40
+
int dtb_pas_id;
39
41
unsigned int minidump_id;
40
-
bool has_aggre2_clk;
41
42
bool auto_boot;
42
43
bool decrypt_shutdown;
43
44
···
48
47
const char *ssr_name;
49
48
const char *sysmon_name;
50
49
int ssctl_id;
50
+
51
+
int region_assign_idx;
51
52
};
52
53
53
54
struct qcom_adsp {
···
68
65
69
66
int proxy_pd_count;
70
67
68
+
const char *dtb_firmware_name;
71
69
int pas_id;
70
+
int dtb_pas_id;
72
71
unsigned int minidump_id;
73
72
int crash_reason_smem;
74
-
bool has_aggre2_clk;
75
73
bool decrypt_shutdown;
76
74
const char *info_name;
75
+
76
+
const struct firmware *firmware;
77
+
const struct firmware *dtb_firmware;
77
78
78
79
struct completion start_done;
79
80
struct completion stop_done;
80
81
81
82
phys_addr_t mem_phys;
83
+
phys_addr_t dtb_mem_phys;
82
84
phys_addr_t mem_reloc;
85
+
phys_addr_t dtb_mem_reloc;
86
+
phys_addr_t region_assign_phys;
83
87
void *mem_region;
88
+
void *dtb_mem_region;
84
89
size_t mem_size;
90
+
size_t dtb_mem_size;
91
+
size_t region_assign_size;
92
+
93
+
int region_assign_idx;
94
+
int region_assign_perms;
85
95
86
96
struct qcom_rproc_glink glink_subdev;
87
97
struct qcom_rproc_subdev smd_subdev;
···
102
86
struct qcom_sysmon *sysmon;
103
87
104
88
struct qcom_scm_pas_metadata pas_metadata;
89
+
struct qcom_scm_pas_metadata dtb_pas_metadata;
105
90
};
91
+
92
+
void adsp_segment_dump(struct rproc *rproc, struct rproc_dump_segment *segment,
93
+
void *dest, size_t offset, size_t size)
94
+
{
95
+
struct qcom_adsp *adsp = rproc->priv;
96
+
int total_offset;
97
+
98
+
total_offset = segment->da + segment->offset + offset - adsp->mem_phys;
99
+
if (total_offset < 0 || total_offset + size > adsp->mem_size) {
100
+
dev_err(adsp->dev,
101
+
"invalid copy request for segment %pad with offset %zu and size %zu)\n",
102
+
&segment->da, offset, size);
103
+
memset(dest, 0xff, size);
104
+
return;
105
+
}
106
+
107
+
memcpy_fromio(dest, adsp->mem_region + total_offset, size);
108
+
}
106
109
107
110
static void adsp_minidump(struct rproc *rproc)
108
111
{
···
130
95
if (rproc->dump_conf == RPROC_COREDUMP_DISABLED)
131
96
return;
132
97
133
-
qcom_minidump(rproc, adsp->minidump_id);
98
+
qcom_minidump(rproc, adsp->minidump_id, adsp_segment_dump);
134
99
}
135
100
136
101
static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds,
···
195
160
* here.
196
161
*/
197
162
qcom_scm_pas_metadata_release(&adsp->pas_metadata);
163
+
if (adsp->dtb_pas_id)
164
+
qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata);
198
165
199
166
return 0;
200
167
}
···
206
169
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
207
170
int ret;
208
171
209
-
ret = qcom_mdt_pas_init(adsp->dev, fw, rproc->firmware, adsp->pas_id,
210
-
adsp->mem_phys, &adsp->pas_metadata);
211
-
if (ret)
212
-
return ret;
172
+
/* Store firmware handle to be used in adsp_start() */
173
+
adsp->firmware = fw;
213
174
214
-
ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, adsp->pas_id,
215
-
adsp->mem_region, adsp->mem_phys, adsp->mem_size,
216
-
&adsp->mem_reloc);
217
-
if (ret)
218
-
return ret;
175
+
if (adsp->dtb_pas_id) {
176
+
ret = request_firmware(&adsp->dtb_firmware, adsp->dtb_firmware_name, adsp->dev);
177
+
if (ret) {
178
+
dev_err(adsp->dev, "request_firmware failed for %s: %d\n",
179
+
adsp->dtb_firmware_name, ret);
180
+
return ret;
181
+
}
219
182
220
-
qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
183
+
ret = qcom_mdt_pas_init(adsp->dev, adsp->dtb_firmware, adsp->dtb_firmware_name,
184
+
adsp->dtb_pas_id, adsp->dtb_mem_phys,
185
+
&adsp->dtb_pas_metadata);
186
+
if (ret)
187
+
goto release_dtb_firmware;
188
+
189
+
ret = qcom_mdt_load_no_init(adsp->dev, adsp->dtb_firmware, adsp->dtb_firmware_name,
190
+
adsp->dtb_pas_id, adsp->dtb_mem_region,
191
+
adsp->dtb_mem_phys, adsp->dtb_mem_size,
192
+
&adsp->dtb_mem_reloc);
193
+
if (ret)
194
+
goto release_dtb_metadata;
195
+
}
221
196
222
197
return 0;
198
+
199
+
release_dtb_metadata:
200
+
qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata);
201
+
202
+
release_dtb_firmware:
203
+
release_firmware(adsp->dtb_firmware);
204
+
205
+
return ret;
223
206
}
224
207
225
208
static int adsp_start(struct rproc *rproc)
···
275
218
goto disable_cx_supply;
276
219
}
277
220
221
+
if (adsp->dtb_pas_id) {
222
+
ret = qcom_scm_pas_auth_and_reset(adsp->dtb_pas_id);
223
+
if (ret) {
224
+
dev_err(adsp->dev,
225
+
"failed to authenticate dtb image and release reset\n");
226
+
goto disable_px_supply;
227
+
}
228
+
}
229
+
230
+
ret = qcom_mdt_pas_init(adsp->dev, adsp->firmware, rproc->firmware, adsp->pas_id,
231
+
adsp->mem_phys, &adsp->pas_metadata);
232
+
if (ret)
233
+
goto disable_px_supply;
234
+
235
+
ret = qcom_mdt_load_no_init(adsp->dev, adsp->firmware, rproc->firmware, adsp->pas_id,
236
+
adsp->mem_region, adsp->mem_phys, adsp->mem_size,
237
+
&adsp->mem_reloc);
238
+
if (ret)
239
+
goto release_pas_metadata;
240
+
241
+
qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
242
+
278
243
ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
279
244
if (ret) {
280
245
dev_err(adsp->dev,
281
246
"failed to authenticate image and release reset\n");
282
-
goto disable_px_supply;
247
+
goto release_pas_metadata;
283
248
}
284
249
285
250
ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
286
251
if (ret == -ETIMEDOUT) {
287
252
dev_err(adsp->dev, "start timed out\n");
288
253
qcom_scm_pas_shutdown(adsp->pas_id);
289
-
goto disable_px_supply;
254
+
goto release_pas_metadata;
290
255
}
291
256
292
257
qcom_scm_pas_metadata_release(&adsp->pas_metadata);
258
+
if (adsp->dtb_pas_id)
259
+
qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata);
260
+
261
+
/* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */
262
+
adsp->firmware = NULL;
293
263
294
264
return 0;
295
265
266
+
release_pas_metadata:
267
+
qcom_scm_pas_metadata_release(&adsp->pas_metadata);
268
+
if (adsp->dtb_pas_id)
269
+
qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata);
296
270
disable_px_supply:
297
271
if (adsp->px_supply)
298
272
regulator_disable(adsp->px_supply);
···
338
250
adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
339
251
disable_irqs:
340
252
qcom_q6v5_unprepare(&adsp->q6v5);
253
+
254
+
/* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */
255
+
adsp->firmware = NULL;
341
256
342
257
return ret;
343
258
}
···
374
283
375
284
if (ret)
376
285
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
286
+
287
+
if (adsp->dtb_pas_id) {
288
+
ret = qcom_scm_pas_shutdown(adsp->dtb_pas_id);
289
+
if (ret)
290
+
dev_err(adsp->dev, "failed to shutdown dtb: %d\n", ret);
291
+
}
377
292
378
293
handover = qcom_q6v5_unprepare(&adsp->q6v5);
379
294
if (handover)
···
442
345
return ret;
443
346
}
444
347
445
-
if (adsp->has_aggre2_clk) {
446
-
adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
447
-
if (IS_ERR(adsp->aggre2_clk)) {
448
-
ret = PTR_ERR(adsp->aggre2_clk);
449
-
if (ret != -EPROBE_DEFER)
450
-
dev_err(adsp->dev,
451
-
"failed to get aggre2 clock");
452
-
return ret;
453
-
}
348
+
adsp->aggre2_clk = devm_clk_get_optional(adsp->dev, "aggre2");
349
+
if (IS_ERR(adsp->aggre2_clk)) {
350
+
ret = PTR_ERR(adsp->aggre2_clk);
351
+
if (ret != -EPROBE_DEFER)
352
+
dev_err(adsp->dev,
353
+
"failed to get aggre2 clock");
354
+
return ret;
454
355
}
455
356
456
357
return 0;
···
557
462
return -EBUSY;
558
463
}
559
464
465
+
if (!adsp->dtb_pas_id)
466
+
return 0;
467
+
468
+
node = of_parse_phandle(adsp->dev->of_node, "memory-region", 1);
469
+
if (!node) {
470
+
dev_err(adsp->dev, "no dtb memory-region specified\n");
471
+
return -EINVAL;
472
+
}
473
+
474
+
ret = of_address_to_resource(node, 0, &r);
475
+
if (ret)
476
+
return ret;
477
+
478
+
adsp->dtb_mem_phys = adsp->dtb_mem_reloc = r.start;
479
+
adsp->dtb_mem_size = resource_size(&r);
480
+
adsp->dtb_mem_region = devm_ioremap_wc(adsp->dev, adsp->dtb_mem_phys, adsp->dtb_mem_size);
481
+
if (!adsp->dtb_mem_region) {
482
+
dev_err(adsp->dev, "unable to map dtb memory region: %pa+%zx\n",
483
+
&r.start, adsp->dtb_mem_size);
484
+
return -EBUSY;
485
+
}
486
+
560
487
return 0;
488
+
}
489
+
490
+
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
491
+
{
492
+
struct qcom_scm_vmperm perm;
493
+
struct device_node *node;
494
+
struct resource r;
495
+
int ret;
496
+
497
+
if (!adsp->region_assign_idx)
498
+
return 0;
499
+
500
+
node = of_parse_phandle(adsp->dev->of_node, "memory-region", adsp->region_assign_idx);
501
+
if (!node) {
502
+
dev_err(adsp->dev, "missing shareable memory-region\n");
503
+
return -EINVAL;
504
+
}
505
+
506
+
ret = of_address_to_resource(node, 0, &r);
507
+
if (ret)
508
+
return ret;
509
+
510
+
perm.vmid = QCOM_SCM_VMID_MSS_MSA;
511
+
perm.perm = QCOM_SCM_PERM_RW;
512
+
513
+
adsp->region_assign_phys = r.start;
514
+
adsp->region_assign_size = resource_size(&r);
515
+
adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
516
+
517
+
ret = qcom_scm_assign_mem(adsp->region_assign_phys,
518
+
adsp->region_assign_size,
519
+
&adsp->region_assign_perms,
520
+
&perm, 1);
521
+
if (ret < 0) {
522
+
dev_err(adsp->dev, "assign memory failed\n");
523
+
return ret;
524
+
}
525
+
526
+
return 0;
527
+
}
528
+
529
+
static void adsp_unassign_memory_region(struct qcom_adsp *adsp)
530
+
{
531
+
struct qcom_scm_vmperm perm;
532
+
int ret;
533
+
534
+
if (!adsp->region_assign_idx)
535
+
return;
536
+
537
+
perm.vmid = QCOM_SCM_VMID_HLOS;
538
+
perm.perm = QCOM_SCM_PERM_RW;
539
+
540
+
ret = qcom_scm_assign_mem(adsp->region_assign_phys,
541
+
adsp->region_assign_size,
542
+
&adsp->region_assign_perms,
543
+
&perm, 1);
544
+
if (ret < 0)
545
+
dev_err(adsp->dev, "unassign memory failed\n");
561
546
}
562
547
563
548
static int adsp_probe(struct platform_device *pdev)
···
645
470
const struct adsp_data *desc;
646
471
struct qcom_adsp *adsp;
647
472
struct rproc *rproc;
648
-
const char *fw_name;
473
+
const char *fw_name, *dtb_fw_name = NULL;
649
474
const struct rproc_ops *ops = &adsp_ops;
650
475
int ret;
651
476
···
661
486
&fw_name);
662
487
if (ret < 0 && ret != -EINVAL)
663
488
return ret;
489
+
490
+
if (desc->dtb_firmware_name) {
491
+
dtb_fw_name = desc->dtb_firmware_name;
492
+
ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", 1,
493
+
&dtb_fw_name);
494
+
if (ret < 0 && ret != -EINVAL)
495
+
return ret;
496
+
}
664
497
665
498
if (desc->minidump_id)
666
499
ops = &adsp_minidump_ops;
···
688
505
adsp->rproc = rproc;
689
506
adsp->minidump_id = desc->minidump_id;
690
507
adsp->pas_id = desc->pas_id;
691
-
adsp->has_aggre2_clk = desc->has_aggre2_clk;
692
508
adsp->info_name = desc->sysmon_name;
693
509
adsp->decrypt_shutdown = desc->decrypt_shutdown;
510
+
adsp->region_assign_idx = desc->region_assign_idx;
511
+
if (dtb_fw_name) {
512
+
adsp->dtb_firmware_name = dtb_fw_name;
513
+
adsp->dtb_pas_id = desc->dtb_pas_id;
514
+
}
694
515
platform_set_drvdata(pdev, adsp);
695
516
696
517
ret = device_init_wakeup(adsp->dev, true);
···
702
515
goto free_rproc;
703
516
704
517
ret = adsp_alloc_memory_region(adsp);
518
+
if (ret)
519
+
goto free_rproc;
520
+
521
+
ret = adsp_assign_memory_region(adsp);
705
522
if (ret)
706
523
goto free_rproc;
707
524
···
730
539
731
540
qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
732
541
qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
733
-
qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
734
542
adsp->sysmon = qcom_add_sysmon_subdev(rproc,
735
543
desc->sysmon_name,
736
544
desc->ssctl_id);
···
738
548
goto detach_proxy_pds;
739
549
}
740
550
551
+
qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
741
552
ret = rproc_add(rproc);
742
553
if (ret)
743
554
goto detach_proxy_pds;
···
761
570
rproc_del(adsp->rproc);
762
571
763
572
qcom_q6v5_deinit(&adsp->q6v5);
573
+
adsp_unassign_memory_region(adsp);
764
574
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
765
575
qcom_remove_sysmon_subdev(adsp->sysmon);
766
576
qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
···
777
585
.crash_reason_smem = 423,
778
586
.firmware_name = "adsp.mdt",
779
587
.pas_id = 1,
780
-
.has_aggre2_clk = false,
781
588
.auto_boot = true,
782
589
.ssr_name = "lpass",
783
590
.sysmon_name = "adsp",
···
787
596
.crash_reason_smem = 423,
788
597
.firmware_name = "adsp.mdt",
789
598
.pas_id = 1,
790
-
.has_aggre2_clk = false,
791
599
.auto_boot = true,
792
600
.load_state = "adsp",
793
601
.ssr_name = "lpass",
···
798
608
.crash_reason_smem = 423,
799
609
.firmware_name = "adsp.mdt",
800
610
.pas_id = 1,
801
-
.has_aggre2_clk = false,
802
611
.auto_boot = true,
803
612
.proxy_pd_names = (char*[]){
804
613
"lcx",
···
814
625
.crash_reason_smem = 423,
815
626
.firmware_name = "adsp.mdt",
816
627
.pas_id = 1,
817
-
.has_aggre2_clk = false,
818
628
.auto_boot = true,
819
629
.proxy_pd_names = (char*[]){
820
630
"cx",
···
829
641
.crash_reason_smem = 423,
830
642
.firmware_name = "adsp.mdt",
831
643
.pas_id = 1,
832
-
.has_aggre2_clk = false,
833
644
.auto_boot = true,
834
645
.proxy_pd_names = (char*[]){
835
646
"lcx",
···
845
658
.crash_reason_smem = 423,
846
659
.firmware_name = "adsp.mdt",
847
660
.pas_id = 1,
848
-
.has_aggre2_clk = false,
849
661
.auto_boot = true,
850
662
.proxy_pd_names = (char*[]){
851
663
"lcx",
···
861
675
.crash_reason_smem = 423,
862
676
.firmware_name = "adsp.mdt",
863
677
.pas_id = 1,
864
-
.has_aggre2_clk = false,
865
678
.auto_boot = true,
866
679
.proxy_pd_names = (char*[]){
867
680
"cx",
···
875
690
.crash_reason_smem = 601,
876
691
.firmware_name = "cdsp.mdt",
877
692
.pas_id = 18,
878
-
.has_aggre2_clk = false,
879
693
.auto_boot = true,
880
694
.ssr_name = "cdsp",
881
695
.sysmon_name = "cdsp",
···
885
701
.crash_reason_smem = 601,
886
702
.firmware_name = "cdsp.mdt",
887
703
.pas_id = 18,
888
-
.has_aggre2_clk = false,
889
704
.auto_boot = true,
890
705
.load_state = "cdsp",
891
706
.ssr_name = "cdsp",
···
896
713
.crash_reason_smem = 601,
897
714
.firmware_name = "cdsp.mdt",
898
715
.pas_id = 18,
899
-
.has_aggre2_clk = false,
900
716
.auto_boot = true,
901
717
.proxy_pd_names = (char*[]){
902
718
"cx",
···
912
730
.crash_reason_smem = 601,
913
731
.firmware_name = "cdsp.mdt",
914
732
.pas_id = 18,
915
-
.has_aggre2_clk = false,
916
733
.auto_boot = true,
917
734
.proxy_pd_names = (char*[]){
918
735
"cx",
···
927
746
.crash_reason_smem = 601,
928
747
.firmware_name = "cdsp.mdt",
929
748
.pas_id = 18,
930
-
.has_aggre2_clk = false,
931
749
.auto_boot = true,
932
750
.proxy_pd_names = (char*[]){
933
751
"cx",
···
942
762
.crash_reason_smem = 601,
943
763
.firmware_name = "cdsp.mdt",
944
764
.pas_id = 18,
945
-
.has_aggre2_clk = false,
946
765
.auto_boot = true,
947
766
.proxy_pd_names = (char*[]){
948
767
"nsp",
···
956
777
.crash_reason_smem = 633,
957
778
.firmware_name = "cdsp.mdt",
958
779
.pas_id = 30,
959
-
.has_aggre2_clk = false,
960
780
.auto_boot = true,
961
781
.proxy_pd_names = (char*[]){
962
782
"nsp",
···
970
792
.crash_reason_smem = 601,
971
793
.firmware_name = "cdsp.mdt",
972
794
.pas_id = 18,
973
-
.has_aggre2_clk = false,
974
795
.auto_boot = true,
975
796
.proxy_pd_names = (char*[]){
976
797
"cx",
···
987
810
.firmware_name = "modem.mdt",
988
811
.pas_id = 4,
989
812
.minidump_id = 3,
990
-
.has_aggre2_clk = false,
991
813
.auto_boot = false,
992
814
.proxy_pd_names = (char*[]){
993
815
"cx",
···
1003
827
.crash_reason_smem = 421,
1004
828
.firmware_name = "modem.mdt",
1005
829
.pas_id = 4,
1006
-
.has_aggre2_clk = false,
1007
830
.auto_boot = false,
1008
831
.proxy_pd_names = (char*[]){
1009
832
"cx",
···
1018
843
.crash_reason_smem = 424,
1019
844
.firmware_name = "slpi.mdt",
1020
845
.pas_id = 12,
1021
-
.has_aggre2_clk = true,
1022
846
.auto_boot = true,
1023
847
.proxy_pd_names = (char*[]){
1024
848
"ssc_cx",
···
1032
858
.crash_reason_smem = 424,
1033
859
.firmware_name = "slpi.mdt",
1034
860
.pas_id = 12,
1035
-
.has_aggre2_clk = false,
1036
861
.auto_boot = true,
1037
862
.proxy_pd_names = (char*[]){
1038
863
"lcx",
···
1048
875
.crash_reason_smem = 424,
1049
876
.firmware_name = "slpi.mdt",
1050
877
.pas_id = 12,
1051
-
.has_aggre2_clk = false,
1052
878
.auto_boot = true,
1053
879
.proxy_pd_names = (char*[]){
1054
880
"lcx",
···
1064
892
.crash_reason_smem = 424,
1065
893
.firmware_name = "slpi.mdt",
1066
894
.pas_id = 12,
1067
-
.has_aggre2_clk = false,
1068
895
.auto_boot = true,
1069
896
.proxy_pd_names = (char*[]){
1070
897
"lcx",
···
1090
919
.crash_reason_smem = 421,
1091
920
.firmware_name = "modem.mdt",
1092
921
.pas_id = 4,
1093
-
.has_aggre2_clk = false,
1094
922
.auto_boot = true,
1095
923
.proxy_pd_names = (char*[]){
1096
924
"cx",
···
1106
936
.firmware_name = "modem.mdt",
1107
937
.pas_id = 4,
1108
938
.minidump_id = 3,
1109
-
.has_aggre2_clk = false,
1110
939
.auto_boot = false,
1111
940
.decrypt_shutdown = true,
1112
941
.proxy_pd_names = (char*[]){
···
1119
950
.ssctl_id = 0x12,
1120
951
};
1121
952
953
+
static const struct adsp_data sm8550_adsp_resource = {
954
+
.crash_reason_smem = 423,
955
+
.firmware_name = "adsp.mdt",
956
+
.dtb_firmware_name = "adsp_dtb.mdt",
957
+
.pas_id = 1,
958
+
.dtb_pas_id = 0x24,
959
+
.minidump_id = 5,
960
+
.auto_boot = true,
961
+
.proxy_pd_names = (char*[]){
962
+
"lcx",
963
+
"lmx",
964
+
NULL
965
+
},
966
+
.load_state = "adsp",
967
+
.ssr_name = "lpass",
968
+
.sysmon_name = "adsp",
969
+
.ssctl_id = 0x14,
970
+
};
971
+
972
+
static const struct adsp_data sm8550_cdsp_resource = {
973
+
.crash_reason_smem = 601,
974
+
.firmware_name = "cdsp.mdt",
975
+
.dtb_firmware_name = "cdsp_dtb.mdt",
976
+
.pas_id = 18,
977
+
.dtb_pas_id = 0x25,
978
+
.minidump_id = 7,
979
+
.auto_boot = true,
980
+
.proxy_pd_names = (char*[]){
981
+
"cx",
982
+
"mxc",
983
+
"nsp",
984
+
NULL
985
+
},
986
+
.load_state = "cdsp",
987
+
.ssr_name = "cdsp",
988
+
.sysmon_name = "cdsp",
989
+
.ssctl_id = 0x17,
990
+
};
991
+
992
+
static const struct adsp_data sm8550_mpss_resource = {
993
+
.crash_reason_smem = 421,
994
+
.firmware_name = "modem.mdt",
995
+
.dtb_firmware_name = "modem_dtb.mdt",
996
+
.pas_id = 4,
997
+
.dtb_pas_id = 0x26,
998
+
.minidump_id = 3,
999
+
.auto_boot = false,
1000
+
.decrypt_shutdown = true,
1001
+
.proxy_pd_names = (char*[]){
1002
+
"cx",
1003
+
"mss",
1004
+
NULL
1005
+
},
1006
+
.load_state = "modem",
1007
+
.ssr_name = "mpss",
1008
+
.sysmon_name = "modem",
1009
+
.ssctl_id = 0x12,
1010
+
.region_assign_idx = 2,
1011
+
};
1012
+
1122
1013
static const struct of_device_id adsp_of_match[] = {
1123
1014
{ .compatible = "qcom,msm8226-adsp-pil", .data = &adsp_resource_init},
1015
+
{ .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource},
1124
1016
{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
1125
1017
{ .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource},
1126
1018
{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
···
1202
972
{ .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init},
1203
973
{ .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init},
1204
974
{ .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource},
975
+
{ .compatible = "qcom,sm6115-adsp-pas", .data = &adsp_resource_init},
976
+
{ .compatible = "qcom,sm6115-cdsp-pas", .data = &cdsp_resource_init},
977
+
{ .compatible = "qcom,sm6115-mpss-pas", .data = &sc8180x_mpss_resource},
1205
978
{ .compatible = "qcom,sm6350-adsp-pas", .data = &sm6350_adsp_resource},
1206
979
{ .compatible = "qcom,sm6350-cdsp-pas", .data = &sm6350_cdsp_resource},
1207
980
{ .compatible = "qcom,sm6350-mpss-pas", .data = &mpss_resource_init},
···
1223
990
{ .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource},
1224
991
{ .compatible = "qcom,sm8450-slpi-pas", .data = &sm8350_slpi_resource},
1225
992
{ .compatible = "qcom,sm8450-mpss-pas", .data = &sm8450_mpss_resource},
993
+
{ .compatible = "qcom,sm8550-adsp-pas", .data = &sm8550_adsp_resource},
994
+
{ .compatible = "qcom,sm8550-cdsp-pas", .data = &sm8550_cdsp_resource},
995
+
{ .compatible = "qcom,sm8550-mpss-pas", .data = &sm8550_mpss_resource},
1226
996
{ },
1227
997
};
1228
998
MODULE_DEVICE_TABLE(of, adsp_of_match);
+1
-1
drivers/remoteproc/qcom_sysmon.c
+1
-1
drivers/remoteproc/qcom_sysmon.c
···
388
388
}
389
389
390
390
memset(&req, 0, sizeof(req));
391
-
strlcpy(req.subsys_name, event->subsys_name, sizeof(req.subsys_name));
391
+
strscpy(req.subsys_name, event->subsys_name, sizeof(req.subsys_name));
392
392
req.subsys_name_len = strlen(req.subsys_name);
393
393
req.event = event->ssr_event;
394
394
req.evt_driven_valid = true;
+12
drivers/remoteproc/qcom_wcnss.c
+12
drivers/remoteproc/qcom_wcnss.c
···
141
141
.num_vregs = 1,
142
142
};
143
143
144
+
static const struct wcnss_data pronto_v3_data = {
145
+
.pmu_offset = 0x1004,
146
+
.spare_offset = 0x1088,
147
+
148
+
.pd_names = { "mx", "cx" },
149
+
.vregs = (struct wcnss_vreg_info[]) {
150
+
{ "vddpx", 1800000, 1800000, 0 },
151
+
},
152
+
.num_vregs = 1,
153
+
};
154
+
144
155
static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
145
156
{
146
157
struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
···
686
675
{ .compatible = "qcom,riva-pil", &riva_data },
687
676
{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
688
677
{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
678
+
{ .compatible = "qcom,pronto-v3-pil", &pronto_v3_data },
689
679
{ },
690
680
};
691
681
MODULE_DEVICE_TABLE(of, wcnss_of_match);
-2
drivers/remoteproc/qcom_wcnss.h
-2
drivers/remoteproc/qcom_wcnss.h
+12
drivers/remoteproc/ti_k3_dsp_remoteproc.c
+12
drivers/remoteproc/ti_k3_dsp_remoteproc.c
···
870
870
{ .name = "l1dram", .dev_addr = 0xe00000 },
871
871
};
872
872
873
+
static const struct k3_dsp_mem_data c7xv_mems[] = {
874
+
{ .name = "l2sram", .dev_addr = 0x800000 },
875
+
};
876
+
873
877
static const struct k3_dsp_dev_data c66_data = {
874
878
.mems = c66_mems,
875
879
.num_mems = ARRAY_SIZE(c66_mems),
···
888
884
.uses_lreset = false,
889
885
};
890
886
887
+
static const struct k3_dsp_dev_data c7xv_data = {
888
+
.mems = c7xv_mems,
889
+
.num_mems = ARRAY_SIZE(c7xv_mems),
890
+
.boot_align_addr = SZ_2M,
891
+
.uses_lreset = false,
892
+
};
893
+
891
894
static const struct of_device_id k3_dsp_of_match[] = {
892
895
{ .compatible = "ti,j721e-c66-dsp", .data = &c66_data, },
893
896
{ .compatible = "ti,j721e-c71-dsp", .data = &c71_data, },
894
897
{ .compatible = "ti,j721s2-c71-dsp", .data = &c71_data, },
898
+
{ .compatible = "ti,am62a-c7xv-dsp", .data = &c7xv_data, },
895
899
{ /* sentinel */ },
896
900
};
897
901
MODULE_DEVICE_TABLE(of, k3_dsp_of_match);
+83
include/linux/remoteproc/pruss.h
+83
include/linux/remoteproc/pruss.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* PRU-ICSS Subsystem user interfaces
4
+
*
5
+
* Copyright (C) 2015-2022 Texas Instruments Incorporated - http://www.ti.com
6
+
* Suman Anna <s-anna@ti.com>
7
+
*/
8
+
9
+
#ifndef __LINUX_PRUSS_H
10
+
#define __LINUX_PRUSS_H
11
+
12
+
#include <linux/device.h>
13
+
#include <linux/types.h>
14
+
15
+
#define PRU_RPROC_DRVNAME "pru-rproc"
16
+
17
+
/**
18
+
* enum pruss_pru_id - PRU core identifiers
19
+
* @PRUSS_PRU0: PRU Core 0.
20
+
* @PRUSS_PRU1: PRU Core 1.
21
+
* @PRUSS_NUM_PRUS: Total number of PRU Cores available.
22
+
*
23
+
*/
24
+
25
+
enum pruss_pru_id {
26
+
PRUSS_PRU0 = 0,
27
+
PRUSS_PRU1,
28
+
PRUSS_NUM_PRUS,
29
+
};
30
+
31
+
/*
32
+
* enum pru_ctable_idx - Configurable Constant table index identifiers
33
+
*/
34
+
enum pru_ctable_idx {
35
+
PRU_C24 = 0,
36
+
PRU_C25,
37
+
PRU_C26,
38
+
PRU_C27,
39
+
PRU_C28,
40
+
PRU_C29,
41
+
PRU_C30,
42
+
PRU_C31,
43
+
};
44
+
45
+
struct device_node;
46
+
struct rproc;
47
+
48
+
#if IS_ENABLED(CONFIG_PRU_REMOTEPROC)
49
+
50
+
struct rproc *pru_rproc_get(struct device_node *np, int index,
51
+
enum pruss_pru_id *pru_id);
52
+
void pru_rproc_put(struct rproc *rproc);
53
+
int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr);
54
+
55
+
#else
56
+
57
+
static inline struct rproc *
58
+
pru_rproc_get(struct device_node *np, int index, enum pruss_pru_id *pru_id)
59
+
{
60
+
return ERR_PTR(-EOPNOTSUPP);
61
+
}
62
+
63
+
static inline void pru_rproc_put(struct rproc *rproc) { }
64
+
65
+
static inline int pru_rproc_set_ctable(struct rproc *rproc,
66
+
enum pru_ctable_idx c, u32 addr)
67
+
{
68
+
return -EOPNOTSUPP;
69
+
}
70
+
71
+
#endif /* CONFIG_PRU_REMOTEPROC */
72
+
73
+
static inline bool is_pru_rproc(struct device *dev)
74
+
{
75
+
const char *drv_name = dev_driver_string(dev);
76
+
77
+
if (strncmp(drv_name, PRU_RPROC_DRVNAME, sizeof(PRU_RPROC_DRVNAME)))
78
+
return false;
79
+
80
+
return true;
81
+
}
82
+
83
+
#endif /* __LINUX_PRUSS_H */